CN117494628A

CN117494628A - Method, device, equipment and storage medium for repairing chip time sequence

Info

Publication number: CN117494628A
Application number: CN202311544164.6A
Authority: CN
Inventors: 崔茜; 任威丽; 周发标; 刘子君
Original assignee: Shanghai Silang Technology Co ltd
Current assignee: Shanghai Silang Technology Co ltd
Priority date: 2023-11-17
Filing date: 2023-11-17
Publication date: 2024-02-02

Abstract

The invention relates to the technical field of integrated circuits and discloses a method, a device, equipment and a storage medium for repairing chip time sequences. The method comprises the following steps: in the engineering modification stage, acquiring a target chip block and a target system-on-chip; acquiring a target node in a target chip block to serve as an output port, and establishing a two-stage clock tree; connecting an output port to a clock end of a first trigger in a target system-on-chip through a two-stage clock tree, and repairing a time sequence violation between an interface of a target chip block and the target system-on-chip through the two-stage clock tree; by establishing a two-stage clock tree and repairing the timing violations based on the two-stage clock tree, the clock tree corresponding to the specific clock offset can be created, the setting of the specific clock offset can be realized, and the workload of repairing the clock offset can be reduced.

Description

Method, device, equipment and storage medium for repairing chip time sequence

Technical Field

The present invention relates to the field of integrated circuits, and in particular, to a method, an apparatus, a device, and a storage medium for repairing chip timing sequences.

Background

The engineering modification stage (Engineering Change Order, ECO) refers to that in the later design stage, the designer adjusts the circuit and standard cell layout in a small range according to the problems exposed in the static time sequence analysis and the post simulation, and performs small-scale optimization on the premise of keeping the original design layout and wiring result basically unchanged, so as to repair the residual violations (such as time sequence violations, design rule violations, physical rule violations, etc.) of the chip, thereby finally reaching the signature standard of the chip.

In Cadence Denali DDR (Double Data Rate Synchronous Dynamic Random Access Memory, double rate synchronous dynamic random access memory) architecture, in addition to conventional setup/hold time checking, clock skew between DDR data needs to be checked, and as DDR speed increases, the demand for clock skew increases.

At present, the existing method for repairing DDR data clock offset mainly adjusts the clock offset between DDR different data by optimizing the length of a clock tree, however, in the prior art, a clock tree corresponding to a specific clock offset cannot be created, setting of the specific clock offset cannot be realized, and workload for repairing the clock offset cannot be reduced.

Disclosure of Invention

The invention provides a method, a device, equipment and a storage medium for repairing chip time sequence, which can realize the creation of a clock tree corresponding to specific clock offset, realize the setting of the specific clock offset and reduce the workload of repairing the clock offset.

According to an aspect of the present invention, there is provided a method for repairing a chip timing sequence, including:

in the engineering modification stage, acquiring a target chip block and a target system-on-chip;

acquiring a target node from the target chip block to serve as an output port, and establishing a two-stage clock tree;

and connecting the output port to a clock end of a first trigger in the target system-on-chip through the two-stage clock tree, and repairing the time sequence violation between the target chip block and the interface of the target system-on-chip through the two-stage clock tree.

According to another aspect of the present invention, there is provided a repair apparatus for chip timing, including:

the target chip block acquisition module is used for acquiring a target chip block and a target system-on-chip in an engineering modification stage;

the two-stage clock tree building module is used for obtaining a target node from the target chip block to serve as an output port and building a two-stage clock tree;

and the timing violation repairing module is used for connecting the output port to the clock end of the first trigger in the target system-on-chip through the two-stage clock tree, and repairing the timing violation between the target chip block and the interface of the target system-on-chip through the two-stage clock tree.

According to another aspect of the present invention, there is provided an electronic apparatus including:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the method of repairing chip timing according to any one of the embodiments of the present invention.

According to another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to execute a method for repairing a chip timing according to any one of the embodiments of the present invention.

According to the technical scheme, the target chip block and the target system-on-chip are obtained in an engineering modification stage; then, a target node is obtained from a target chip block to be used as an output port, and a two-stage clock tree is established; finally, connecting the output port to the clock end of a first trigger in the target system-on-chip through a two-stage clock tree, and repairing the time sequence violation between the interfaces of the target chip block and the target system-on-chip through the two-stage clock tree; by establishing a two-stage clock tree and repairing the timing violations based on the two-stage clock tree, the clock tree corresponding to the specific clock offset can be created, the setting of the specific clock offset can be realized, and the workload of repairing the clock offset can be reduced.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1A is a flowchart of a method for repairing a chip timing sequence according to a first embodiment of the present invention;

FIG. 1B is a schematic diagram of a deployment of a two-level clock tree according to a first embodiment of the invention;

FIG. 1C is a schematic view of a leaf node according to a first embodiment of the present invention;

FIG. 1D is a schematic diagram of a non-leaf node provided according to a first embodiment of the present invention;

fig. 2 is a schematic structural diagram of a chip timing repair device according to a second embodiment of the present invention;

fig. 3 is a schematic structural diagram of an electronic device implementing a method for repairing chip timing according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," "target," and the like in the description and claims of the present invention and in the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Example 1

Fig. 1A is a flowchart of a method for repairing a chip timing according to an embodiment of the present invention, where the method may be applied to a case of repairing a timing problem between a chip block and an on-chip interface, and the method may be performed by a chip timing repairing device, which may be implemented in hardware and/or software, and typically, the chip timing repairing device may be configured in an electronic device, for example, a computer device or a server. As shown in fig. 1A, the method includes:

s110, in the engineering modification stage, acquiring a target chip block and a target system-on-chip.

The target Chip Block and the target System On Chip (SOC) may be a Chip Block (Block) and a System On Chip (SOC) that have a timing problem and need to be repaired by clock offset. In this embodiment, the timing violations inside the chip may be determined according to the static timing analysis result and the post-simulation result, and then the blocks and SOCs that need to be repaired by clock offset may be determined according to the timing violations, so as to be the target blocks and the target SOCs.

S120, acquiring a target node in the target chip block to serve as an output port, and establishing a two-stage clock tree.

Specifically, a node can be randomly found on a clock tree inside the target Block to be used as a target node, and the target node is used as an output port of the target Block. Then, a two-level clock tree including two-level delay clock trees (latency clock tree) may be newly created.

In this embodiment, the two delay clock trees may respectively correspond to preset clock delays, for example, the first delay clock tree may correspond to the shortest delay, and the second delay clock tree may have a set clock offset from the first delay clock tree. The shortest delay may be a minimum correction value determined according to a transition value range specified by the repair tool, or may be a preset value; the clock offset is set to a value that is preset based on historical experience, typically 300 picoseconds. The clock tree may be a binary tree and each tree node may be a clock buffer.

It should be noted that, in the engineering modification stage (Engineering Change Order, ECO), the clock tree cannot be set directly by using the cts instruction of the tool, and too much action affects other logic that has completed wiring and timing clean, only small-scale adjustment can be performed. Secondly, for the timing sequence between the Block and the SOC interface, since the common path of the single clock tree is too short, on-chip errors (on chip variation, OCV) can cause setup and hold to fail to converge at the same time, so that effective repair of the timing violation cannot be achieved.

S130, connecting the output port to a clock end of a first trigger in the target system-on-chip through the two-stage clock tree, and repairing the time sequence violation between the interface of the target chip block and the target system-on-chip through the two-stage clock tree.

The flip-flop may be a D-type flip-flop (DFF), and may perform state refresh under the effect of a clock edge.

In this embodiment, in order to increase the common path of the clock tree, the output port of the Block may be connected to the clock end of the DFF in the SOC through the two-stage clock tree; specifically, the output port of the Block is connected to the first layer delay clock tree, and then connected to the clock end of the DFF in the SOC through the second layer delay clock tree.

In this embodiment, the interface timing sequence with the Block may be satisfied by the first layer delay clock tree corresponding to the shortest delay; meanwhile, through the second layer of delay clock tree corresponding to the specific delay, the clock signals of the Block and the SOC can have specific clock offset, so that the timing violations between interfaces of the target Block and the target SOC can be repaired.

In one specific example, the deployment of a two-level clock tree may be as shown in FIG. 1B. In the prior art, a single clock tree drives a Block and an SOC at the same time, in this embodiment, the DFF clock end of the SOC is changed to the output port of the Block, and two stages of clock trees are made, so that specific clock delay can be realized while the time sequence of the Block interface is satisfied.

In an alternative implementation of this embodiment, establishing a two-stage clock tree may include:

acquiring a transition repair requirement, and acquiring the shortest delay according to the transition repair requirement;

generating a first layer delay clock tree according to the shortest delay, and generating a second layer delay clock tree according to the preset delay;

the two-stage clock tree is established based on the first-layer delay clock tree and the second-layer delay clock tree.

In this embodiment, a transition (transition) violation, that is, a max_transition value is too large, may be obtained through static timing analysis or post-simulation; then, according to the current max_transition value and a preset numerical reference range, a modifiable numerical range, namely a transition repair requirement, can be obtained; finally, the current shortest delay may be determined from the modifiable range of values, e.g., the minimum value of the modifiable range of values is taken as the shortest delay.

Specifically, when the two-stage clock tree is created, first, the first-layer delay clock tree corresponding to the shortest delay can be designed only according to the transition repair requirement, so as to have the smallest clock offset (clock skew) with the DFF inside the Block, so as to meet the interface timing sequence. Then, a second layer delay clock tree corresponding to the preset delay can be designed through compiling a script; finally, each leaf node of the first layer delay clock tree may be connected to a root node of the second layer delay clock tree to generate a two-level clock tree.

Wherein the preset delay may be 300 picoseconds. Alternatively, the predetermined delay may have a value in the range of 300 picoseconds-a, 300 picoseconds + a, a being a predetermined value. Thus, the timing between DFFs having a relatively long delay from the next stage can be satisfied while the timing between DFFs driven by the first-layer delay clock tree is satisfied.

The delay clock tree may include a root node, a plurality of non-leaf nodes, and a plurality of leaf nodes, each node being a clock buffer;

the non-leaf node comprises a first-stage clock buffer, a second-stage clock buffer and a third-stage clock buffer, each second-stage clock buffer drives two third-stage clock buffers respectively, and the root node is connected with the first-stage clock buffer.

In another alternative implementation of this embodiment, generating the first layer delay clock tree according to the shortest delay may include:

dividing a second trigger in the target chip block into a plurality of partitions based on a preset size, and respectively inserting a clock buffer into the center of each partition to serve as a leaf node;

the leaf node is used for driving a clock end of a second trigger in the partition.

In one specific example, when building a delay clock tree, leaf nodes may be designed first; specifically, as shown in fig. 1C, the DFF of the target Block is partitioned according to a lattice of a preset size, so as to divide the DFF into a plurality of cells with the same size; then, a clock buffer (clock buffer) is inserted in the center of each partition to serve as a leaf node (triangle); the clock ends of the DFFs in the partitions are driven by the clock buffer in the center of the partition.

Further, each non-leaf node is designed, and the non-leaf node can be shown in fig. 1D. Specifically, a unique first-stage clock buffer is arranged at the center point of the DFF, a second-stage clock buffer is arranged at the center point of each vertical line adjacent to the first-stage clock buffer, and two third-stage clock buffers are respectively arranged around each second-stage clock buffer; wherein each second stage clock buffer drives two third stage clock buffers, and each third stage clock buffer drives a corresponding leaf node.

Finally, designing a root node; for example, for a first layer delay clock tree, a clock buffer may be designed between the output port of the Block and the first stage clock buffer according to the transition repair requirement to serve as a root node.

In this embodiment, by reconstructing the clock tree in a small range in the ECO stage, a balanced tree meeting the specific clock offset requirement is constructed in a hierarchical manner, so that delay offset between DDR data can be reduced, repair of timing violations can be realized, and repair workload can be reduced.

Example two

Fig. 2 is a schematic structural diagram of a chip timing repair device according to a second embodiment of the present invention. As shown in fig. 2, the apparatus includes: a target chip block acquisition module 210, a two-stage clock tree establishment module 220, and a timing violation repair module 230; wherein,

a target chip block obtaining module 210, configured to obtain a target chip block and a target system-on-chip during an engineering modification stage;

a two-stage clock tree building module 220, configured to obtain a target node from the target chip block, to serve as an output port, and build a two-stage clock tree;

the timing violation repairing module 230 is configured to connect the output port to a clock end of a first trigger in the target system-on-chip through the two-stage clock tree, and repair a timing violation between the target chip block and an interface of the target system-on-chip through the two-stage clock tree.

Optionally, the two-stage clock tree building module 220 includes:

the shortest delay obtaining unit is used for obtaining the transition repair requirement and obtaining the shortest delay according to the transition repair requirement;

the delay clock tree generating unit is used for generating a first layer of delay clock tree according to the shortest delay and generating a second layer of delay clock tree according to the preset delay;

and the two-stage clock tree building unit is used for building the two-stage clock tree based on the first-layer delay clock tree and the second-layer delay clock tree.

Optionally, the delay clock tree includes a root node, a plurality of non-leaf nodes, and a plurality of leaf nodes, each node being a clock buffer;

Optionally, the delay clock tree generating unit is specifically configured to:

Optionally, the preset delay is 300 picoseconds.

The device for repairing the chip time sequence provided by the embodiment of the invention can execute the method for repairing the chip time sequence provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

Example III

Fig. 3 shows a schematic diagram of an electronic device 30 that may be used to implement an embodiment of the invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Electronic equipment may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 3, the electronic device 30 includes at least one processor 31, and a memory, such as a Read Only Memory (ROM) 32, a Random Access Memory (RAM) 33, etc., communicatively connected to the at least one processor 31, wherein the memory stores a computer program executable by the at least one processor, and the processor 31 can perform various suitable actions and processes according to the computer program stored in the Read Only Memory (ROM) 32 or the computer program loaded from the storage unit 38 into the Random Access Memory (RAM) 33. In the RAM 33, various programs and data required for the operation of the electronic device 30 may also be stored. The processor 31, the ROM 32 and the RAM 33 are connected to each other via a bus 34. An input/output (I/O) interface 35 is also connected to bus 34.

Various components in electronic device 30 are connected to I/O interface 35, including: an input unit 36 such as a keyboard, a mouse, etc.; an output unit 37 such as various types of displays, speakers, and the like; a storage unit 38 such as a magnetic disk, an optical disk, or the like; and a communication unit 39 such as a network card, modem, wireless communication transceiver, etc. The communication unit 39 allows the electronic device 30 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.

The processor 31 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 31 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 31 performs the various methods and processes described above, such as a repair method for chip timing.

In some embodiments, the method of repairing chip timing may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as the memory unit 38. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 30 via the ROM 32 and/or the communication unit 39. When the computer program is loaded into RAM 33 and executed by processor 31, one or more steps of the method of repairing chip timing described above may be performed. Alternatively, in other embodiments, the processor 31 may be configured to perform the repair method of the chip timing in any other suitable manner (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.

The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. A method for repairing a chip timing sequence, comprising:

2. The method of claim 1, wherein establishing a two-level clock tree comprises:

3. The method of claim 2, wherein the delay clock tree comprises a root node, a plurality of non-leaf nodes, and a plurality of leaf nodes, each node being a clock buffer;

4. A method according to claim 3, wherein generating a first layer delay clock tree from the shortest delay comprises:

5. The method of claim 2, wherein the predetermined delay is 300 picoseconds.

6. A chip timing repair device, comprising:

7. The apparatus of claim 6, wherein the two-stage clock tree establishment module comprises:

8. The apparatus according to claim 7, wherein the delay clock tree generating unit is specifically configured to:

9. An electronic device, the electronic device comprising:

at least one processor, and

a memory communicatively coupled to the at least one processor; wherein,

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the method of repairing chip timing of any one of claims 1-5.

10. A computer readable storage medium storing computer instructions for causing a processor to perform the method of repairing chip timing according to any one of claims 1-5.