CN117494407A

CN117494407A - Method for accelerating verification of central processing unit and computing equipment

Info

Publication number: CN117494407A
Application number: CN202311386532.9A
Authority: CN
Inventors: 肖晶; 蔡权雄; 牛昕宇
Original assignee: Shenzhen Corerain Technologies Co Ltd
Current assignee: Shenzhen Corerain Technologies Co Ltd
Priority date: 2023-10-24
Filing date: 2023-10-24
Publication date: 2024-02-02

Abstract

The application provides a method for accelerating verification of a central processing unit, which is used for verifying different scenes corresponding to different bootstrap programs, and comprises the following steps: starting a simulation program for verifying the central processing unit; detecting whether a first transfer simulation state file exists; if the first transfer simulation state file exists, recovering a corresponding simulation state from the first transfer simulation state file; the back door loads a read-only memory bootstrap program of a preset level in a mode of reading files; and executing subsequent simulation. According to the technical scheme, the debugging mode and the debugging script are added in the compiling simulation simulator, the central processing unit program is accelerated to be verified in a mode that the read-only memory is loaded on the back door, verification time can be saved while verification functions are met, and verification speed of the central processing unit is improved.

Description

Method for accelerating verification of central processing unit and computing equipment

Technical Field

The invention relates to the technical field of central processing unit verification, in particular to a method for accelerating central processing unit verification and computing equipment.

Background

Today, where technology is rapidly evolving, computer user bases are becoming enormous, and technology iterative updates support larger Central Processing Unit (CPU) requirements. With the continuous improvement of CPU performance and the continuous perfection of software ecology, key information infrastructures of relevant important industries are being developed. The new technology and the new architecture bring development opportunities for the CPU. Development and maturation of cloud computing, artificial intelligence, 5G, edge computing, blockchain, etc. will pose a significant challenge to the traditional computing requirements and create new computing technology requirements. In the fields of electronic government affairs, public service, energy, traffic, finance, water conservancy, communication and other key information infrastructures, CPU application is gradually spread in various industries. Among them, the server chip market is also rising in cloud computing and enterprise digital transformation, especially in domestic markets, where the scale of the cloud computing market will continue to increase for the next few years. Not only is the embedded CPU in the industrial control field more widely demanded, and the CPU is used as an intelligent core component and is widely applied to industrial control systems.

The CPU is an operation and control core of the computer, and is a core hardware unit for controlling and allocating all hardware resources (such as a memory and an input/output unit) of the computer and executing general operation; at the same time, the operation of all software layers in the computer system is finally mapped into the operation of the CPU through the instruction system.

CPU verification is a test method for verifying CPU performance and function. CPU authentication is mainly to ensure that the performance and function of the CPU meet expectations and can meet the needs of users. CPU verification is typically composed of two parts, hardware for simulating the physical behavior of the CPU and software for verifying the logical behavior of the CPU. Common CPU authentication methods include: performance testing, functional testing, stability testing, compatibility testing, security testing, and the like. The duration of the CPU verification depends on the goal of the CPU verification, as well as the complexity and accuracy of the verification method. If only the basic functions and performance of the CPU are verified, the verification period may take only a few hours to a few days. However, if advanced functions and performance of the CPU need to be verified, the verification period may take weeks or even months. In addition, the length of verification depends on the complexity and accuracy of the verification method, as well as the test equipment and tools used. Therefore, for the CPU verification work, how to reduce the time length required for verification is a key to improve the CPU verification work efficiency.

Therefore, a technical solution is needed that can shorten the time required for verification on the basis of achieving the verification effect.

Disclosure of Invention

The application aims to provide a method and computing equipment for accelerating CPU verification, which are used for accelerating the verification of a CPU program by adding a debugging mode and a debugging script into a compiling type simulation simulator, so that the verification function is met, the verification time is saved, and the CPU verification speed is improved.

According to an aspect of the present application, there is provided a method for accelerating CPU verification, for verifying different scenarios corresponding to different booths, the method including:

starting a simulation program for verifying the CPU;

detecting whether a first transfer simulation state file exists;

if the first transfer simulation state file exists, recovering a corresponding simulation state from the first transfer simulation state file;

the back door loads a read-only memory bootstrap program of a preset level in a mode of reading files;

and executing subsequent simulation.

According to some embodiments, initiating a simulation program for validating a CPU includes:

starting a simulation program through a compiling type simulation simulator;

a debug mode and a debug script are added to the compilation options of the compilation simulation simulator.

According to some embodiments, the debug script is configured to detect whether a first debug emulation state file exists, and apply the first debug emulation state file to restore a corresponding emulation state.

According to some embodiments, the method further comprises:

and if the first transfer simulation state file does not exist, simulating from the moment 0 to a preset time, and generating the first transfer simulation state file.

According to some embodiments, the method further comprises:

the predetermined time is determined by analyzing the completed emulation, and includes any time from the 0 th moment of the emulation to before the loading of the read-only memory boot program of the predetermined level.

According to some embodiments, the incoming parameters of the debug script include an engineering catalog, a use case name, a seed number.

According to some embodiments, the first transfer simulation state file is a file stored under the engineering catalog and corresponding to the use case name and the seed number.

According to some embodiments, the method further comprises:

and writing the read-only memory bootstrap program which is configured according to the need under different verification environments into one or more files according to actual verification requirements, and loading the read-only memory bootstrap program through a back door in a file reading mode.

According to some embodiments, the predetermined level of read-only memory boot program comprises a zeroth level of read-only memory boot program, a first level of read-only memory boot program, and/or a second level of read-only memory boot program.

According to some embodiments, the read-only memory comprises a read-only memory disposed inside the system on chip or a read-only memory disposed on a board comprising the system on chip.

According to another aspect of the present application, there is provided a computing device comprising:

a processor; and

a memory storing a computer program which, when executed by the processor, causes the processor to perform the method of any one of the preceding claims.

According to another aspect of the present application, there is provided a non-transitory computer readable storage medium having stored thereon computer readable instructions which, when executed by a processor, cause the processor to perform the method of any of the above.

According to the embodiment of the application, on the basis of recording and analyzing the completed simulation flow, the subsequent simulation is accelerated and adjusted, a debugging mode and a debugging script are added in the compiling type simulation simulator, and the CPU program is accelerated and verified in a mode that a read-only memory is loaded on a back door. And saving the first transfer simulation state file through the debugging script, loading the first transfer simulation state file in subsequent simulation to restore the corresponding verification scene, skipping the simulation operation of the corresponding stage, saving the verification time and achieving the acceleration verification effect.

According to some embodiments, the corresponding predetermined time is grasped through the recording and analysis of the completed simulation flow, and the specific skipped stage time point is determined through the setting of the predetermined time, so that the accelerated verification of the CPU is achieved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that are required to be used in the description of the embodiments will be briefly described below.

FIG. 1 illustrates a flow chart of a method for accelerating CPU verification according to an example embodiment.

FIG. 2 shows a method schematic diagram for accelerating CPU verification according to an example embodiment.

Fig. 3 shows a timing diagram for accelerating CPU verification according to an example embodiment.

FIG. 4 illustrates a block diagram of a computing device in accordance with an exemplary embodiment.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present application. One skilled in the relevant art will recognize, however, that the aspects of the application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the application.

The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, the functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first component discussed below could be termed a second component without departing from the teachings of the present application concept. As used herein, the term "and/or" includes any one of the associated listed items and all combinations of one or more.

User information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, presented data, etc.) referred to herein are both user-authorized or fully authorized information and data by parties, and the collection, use and processing of relevant data requires compliance with relevant laws and regulations and standards of the relevant country and region, and is provided with corresponding operation portals for user selection of authorization or denial.

Those skilled in the art will appreciate that the drawings are schematic representations of example embodiments, and that the modules or flows in the drawings are not necessarily required to practice the present application, and therefore, should not be taken to limit the scope of the present application.

With the continuous improvement of CPU performance and the continuous perfection of software ecology, key information infrastructures of relevant important industries are being developed. The new technology and the new architecture bring development opportunities for the CPU. Development and maturation of cloud computing, artificial intelligence, 5G, edge computing, blockchain, etc. will pose a significant challenge to the traditional computing requirements and create new computing technology requirements. In the fields of electronic government affairs, public service, energy, traffic, finance, water conservancy, communication and other key information infrastructures, CPU application is gradually spread in various industries. Among them, the server chip market is also rising in cloud computing and enterprise digital transformation, especially in domestic markets, where the scale of the cloud computing market will continue to increase for the next few years.

CPU verification is a test method for verifying CPU performance and function. CPU authentication is mainly to ensure that the performance and function of the CPU meet expectations and can meet the needs of users. CPU verification is typically composed of two parts, hardware for simulating the physical behavior of the CPU and software for verifying the logical behavior of the CPU. Common CPU authentication methods include: performance testing, functional testing, stability testing, compatibility testing, security testing, and the like.

The duration of the CPU verification depends on the goal of the CPU verification, as well as the complexity and accuracy of the verification method. If only the basic functions and performance of the CPU are verified, the verification period may take only a few hours to a few days. However, if advanced functions and performance of the CPU need to be verified, the verification period may take weeks or even months. In addition, the length of verification depends on the complexity and accuracy of the verification method, as well as the test equipment and tools used.

Therefore, for the CPU verification work, how to reduce the time length required for verification is a key to improve the CPU verification work efficiency.

For this purpose, the present application proposes a method of accelerating CPU authentication. On the basis of recording and analyzing the completed simulation flow, the subsequent simulation is accelerated and adjusted, a debugging mode and a debugging script are added in the compiling simulation simulator, and the CPU program is accelerated and verified in a mode of loading the read-only memory by a back door. And saving the first transfer simulation state file through the debugging script, loading the first transfer simulation state file in subsequent simulation to restore the corresponding verification scene, skipping the simulation operation of the corresponding stage, and saving the verification time to reach the acceleration verification effect. According to the embodiment, the corresponding preset time is mastered through the recording and analysis of the completed simulation flow, and the specific skipped stage time point is determined through the setting of the preset time, so that the accelerated verification of the CPU is realized.

Before describing embodiments of the present application, some terms or concepts related to the embodiments of the present application are explained.

Version control system (Version Control System): hereinafter VCS is abbreviated. A system records one or several file content changes for later review of a particular version revision. The version control system can be applied not only to text files of software source code, but also to version control of any type of file.

System on chip SoC (System on Chip): hereinafter, soC is abbreviated. Also referred to as a system-on-chip, it means a product that is an integrated circuit with dedicated objects, containing the complete system and having the entire contents of embedded software. It is also a technique to achieve the whole process from determining the system functions, to software/hardware partitioning, and to complete the design.

rst signal: also referred to as a reset signal, is a signal for a reset circuit. It is typically used during a boot-up of a processor or system to restore the state of the processor or system to its original state. The RST signal is typically generated by external hardware equipment or system software and communicated to the processor or system via a bus or other communication line. The RST signal typically has two states, a high level, which indicates reset, and a low level, which indicates normal operation.

Example embodiments of the present application are described below with reference to the accompanying drawings.

According to an example embodiment, referring to fig. 1, a method for accelerating CPU verification for verifying different scenarios corresponding to different booths includes:

at S101, a simulation program for verifying the CPU is started.

According to some embodiments, a VCS may be used to launch an emulation program for validating a CPU. In a VCS, a start command may be used to start a simulation program, e.g.,/simv. This command will initiate a simulation environment in which other commands for CPU verification can be entered, the simulation program will execute the corresponding commands, the simulation environment can be configured by special commands in the simulation environment, e.g./config, this command can be modified as needed, other interfaces can be set or other options can be configured.

At S103, it is detected whether a first transfer simulation state file exists.

According to some embodiments, the detection determination of whether the first save emulation state file exists may be implemented in the VCS by adding a debug mode and a debug script. A debug mode tool UCLI is added in the VCS to detect whether the first transfer emulation state file is present. The UCLI is used for detecting whether the first transfer simulation state file exists, so that codes can be conveniently managed and debugged, and the development efficiency is improved.

If the first storage simulation state file exists, S105, the corresponding simulation state is recovered from the first storage simulation state file.

According to some embodiments, if the first transferred simulation state file exists, recovering the corresponding simulation state from the first transferred simulation state file may be implemented in the VCS using a command in debug mode, e.g. loading the first transferred simulation state file in UCLI using a load command, loading the states in the simulation state file into the current simulation environment.

In S107, the back gate loads a read-only memory boot program of a predetermined level in a manner of reading a file.

According to some embodiments, a file may be loaded using a source command in a UCLI by backdoor loading a read-only memory boot program of a predetermined level in a manner to read the file using debug mode in a VCS. The UCLI is used for loading the read-only memory bootstrap program of a preset level on the back door in a file reading mode, so that codes can be conveniently managed and debugged, and development efficiency is improved.

At S109, subsequent simulation is performed.

According to some embodiments, after the debug mode in the application VCS restores the corresponding emulation state, the read-only register boot program of the reserved level is loaded through the back door, and then the corresponding program of the reserved level is run to verify the corresponding scene and program function.

Referring to fig. 2, in S201, a simulation program for verifying a CPU is started.

According to some embodiments, initiating a simulation program for validating a CPU includes: starting a simulation program through a compiling type simulation simulator; a debug mode and a debug script are added to the compilation options of the compilation simulation simulator.

According to some embodiments, the simulation program is started by adding a start command in the VCS. The "VCS" command on the VCS command line is used. The "VCS" command allows for starting a VCS emulator and selecting different options to configure the emulator according to the authentication requirements.

According to some embodiments, debug modes and debug scripts are added to the compiled options of the VCS. Adding a debug mode UCLI and a debug script in a compiling option of the VCS, wherein the debug script can be a configuration file written by TCL script language.

At S203, it is detected whether a first transfer simulation state file exists. If so, jump to S207; if not, the process proceeds to S205.

According to some embodiments, the debug mode and debug script are applied to detect whether a first save emulation state file exists. The combination of the UCLI tool and the TCL file may be used to load a plurality of commands at compile time, including commands to determine if the first transfer simulation state file exists. The code can be conveniently managed and debugged by using the option, and the development efficiency is improved.

According to some embodiments, file presence detection may also be implemented by adding a conditional function to the debug script program to determine whether the first transfer emulation state file is present.

At S205, a first stored-simulation file is generated by the debug script.

Determining the predetermined time by analyzing the completed emulation, the predetermined time including any time from a time 0 of the emulation to before loading the predetermined level of read-only memory boot program

According to some embodiments, if the first save emulation state file does not exist, then it is said to be the first time an emulation is run in the add debug mode. By analyzing the simulation model in the completed non-accelerated state, determining the time period from the 0 time of simulation to the time of loading the read-only memory boot program of the preset level, the time period can be regarded as scene unfolding time, and the optional time length in the time period can be set as preset time according to different test requirements.

According to some embodiments, the first transfer simulation state file is generated after a predetermined time by a debug mode and a debug script in the VCS. Starting a debugger under the debug mode UCLI in the VCS by using a corresponding command, and generating the first transfer simulation state file at the preset time point.

At S207, a first transfer emulation state file saved by the debug script is loaded.

According to some embodiments, when the first transferred state file exists, the corresponding simulation state may be restored from the first transferred simulation state file by loading the first transferred simulation state file saved by the debug script during operation.

According to some embodiments, specific commands may be used in the VCS to restore the corresponding simulation state from the first save simulation state file, e.g., "ucli-r-s first_dump_file" specifies the name of the first save simulation state file to be restored. The corresponding simulation state is recovered from the first transfer simulation state file by using the ' ucli-r-s ' my_first_dump_file ', and the values of various variables in the simulation program are recorded for subsequent analysis of simulation results.

According to some embodiments, after restoring the corresponding simulation state, debugging is also required by using a debugging mode and a debugging script.

The input parameters of the debugging script comprise an engineering catalog, a use case name and a seed number.

The first transfer simulation state file is a file corresponding to the use case name and the seed number stored in the engineering catalog.

According to some embodiments, the simulation state recovered by applying the first transfer simulation state file can only be the simulation state of the same use case and seed number, that is to say, the effect of recovering the simulation state can only be achieved if the use case and seed number are guaranteed to be consistent. If a plurality of use cases exist, the simulation is accelerated by the method of the invention, dump simulation state files corresponding to all running simulations are stored in the same directory, and under the situation, the corresponding stored dump simulation state file names need to be modified or the dump simulation state file stored in the last simulation is deleted, and the storage is rerun.

At S209, a read-only memory boot program of a predetermined level is loaded.

The predetermined level of read-only memory boot programs include a zeroth level read-only memory boot program, a first level read-only memory boot program, and/or a second level read-only memory boot program.

According to some embodiments, a read file is back-door loaded with a predetermined level of read-only memory boot programs including a zeroth level read-only memory boot program, a first level read-only memory boot program, and/or a second level read-only memory boot program using a debug mode in the VCS. The UCLI is used for loading the read-only memory bootstrap program of a preset level on the back door in a file reading mode, so that codes can be conveniently managed and debugged, and development efficiency is improved.

According to some embodiments, the read-only memory is initialized by means of a back gate, i.e. before the CPU is started, to verify different predetermined levels of read-only memory boot programs, i.e. different scenarios. The read-only memory program can be loaded by reading the file only by preparing the read-only memory bootstrap program codes of a preset level in advance, so that the compiling time is saved, frequent compiling and programming of the codes can be avoided, and the verification efficiency is improved.

According to some embodiments, if code debugging is performed on the first-level rom boot program and/or the second-level rom boot program, only the time when the back door loads the code of the first-level rom boot program and/or the second-level rom boot program needs to be recorded as the predetermined time, and then the acceleration verification is performed directly by using the acceleration method of the present invention.

According to some embodiments, for other different verification scenarios, only the rom boot program needs to be replaced, the same use case and the same seed number are re-simulated, and after the existence of the first transfer simulation state file is detected, the first transfer simulation state file stored before is directly loaded, so that the preset time is skipped, and the accelerated verification is performed on the CPU.

According to some embodiments, the VCS will assign an rst signal at time 0, create a waveform file, etc. usually at time 0 when the simulation starts, and often time 0 will take up much simulation time. And saving simulation time by skipping simulation from the moment 0 to the preset time period, thereby achieving the effect of accelerating the verification of the CPU.

According to some embodiments, the read-only memory comprises a read-only memory disposed inside the SoC or a read-only memory disposed on a board comprising the SoC.

As shown in fig. 3, T1: power IC provides a stable Power supply, CLKIC provides a stable reference clock; por_n is delayed by a chip global reset synchronization module for a period of time to release glb_rst_n, and cfuse and the like can be also involved before CPU is started according to different chip scenes and starting modes; t3, enabling a BOOT ROM clock; t4, releasing BOOT ROM reset; t5, waiting for CPU to start, and reading codes of the first bootrom; t6, after the Bootrom code BL0 stage is executed, starting to enter BL1; and T7, after BL1 is executed, starting to enter BL2.

According to some embodiments, as shown in fig. 3, in the illustrated timing diagram for accelerating the verification of the CPU, the acceleration method of the present invention may be applied to select the predetermined time from the time 0 to the time T5 shown in the drawing according to the test requirement, apply the loading of the debug environment and the debug script to the first transfer simulation state file, restore to the corresponding simulation state, save the simulation verification duration, and thereby achieve the effect of accelerating the verification of the CPU.

FIG. 4 illustrates a block diagram of a computing device according to an example embodiment of the present application.

As shown in fig. 4, computing device 30 includes processor 12 and memory 14. Computing device 30 may also include a bus 22, a network interface 16, and an I/O interface 18. The processor 12, memory 14, network interface 16, and I/O interface 18 may communicate with each other via a bus 22.

The processor 12 may include one or more general purpose CPUs (Central Processing Unit, processors), microprocessors, or application specific integrated circuits, etc. for executing relevant program instructions. According to some embodiments, computing device 30 may also include a high performance display adapter (GPU) 20 that accelerates processor 12.

Memory 14 may include machine-system-readable media in the form of volatile memory, such as Random Access Memory (RAM), read Only Memory (ROM), and/or cache memory. Memory 14 is used to store one or more programs including instructions as well as data. The processor 12 may read instructions stored in the memory 14 to perform the methods described above in accordance with embodiments of the present application.

Computing device 30 may also communicate with one or more networks through network interface 16. The network interface 16 may be a wireless network interface.

Bus 22 may be a bus including an address bus, a data bus, a control bus, etc. Bus 22 provides a path for exchanging information between the components.

It should be noted that, in the implementation, the computing device 30 may further include other components necessary to achieve normal operation. Furthermore, it will be understood by those skilled in the art that the above-described apparatus may include only the components necessary to implement the embodiments of the present description, and not all the components shown in the drawings.

The present application also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the above method. The computer readable storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, DVDs, CD-ROMs, micro-drives, and magneto-optical disks, ROM, RAM, EPROM, EEPROM, DRAM, VRAM, flash memory devices, magnetic or optical cards, nanosystems (including molecular memory ICs), network storage devices, cloud storage devices, or any type of media or device suitable for storing instructions and/or data.

The present application also provides a computer program product comprising a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform part or all of the steps of any one of the methods described in the method embodiments above.

It will be clear to a person skilled in the art that the solution of the present application may be implemented by means of software and/or hardware. "Unit" and "module" in this specification refer to software and/or hardware capable of performing a specific function, either alone or in combination with other components, where the hardware may be, for example, a field programmable gate array, an integrated circuit, or the like.

It should be noted that, for simplicity of description, the foregoing method embodiments are all expressed as a series of action combinations, but it should be understood by those skilled in the art that the present application is not limited by the order of actions described, as some steps may be performed in other order or simultaneously in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required in the present application.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, such as a division of units, merely a division of logic functions, and there may be additional divisions in actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some service interface, device or unit indirect coupling or communication connection, electrical or otherwise.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a memory, including several instructions for causing a computer device (which may be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the methods of the embodiments of the present application.

Exemplary embodiments of the present application are specifically illustrated and described above. It is to be understood that this application is not limited to the details of construction, arrangement or method of implementation described herein; on the contrary, the intention is to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A method for accelerating authentication of a central processing unit for authenticating different scenarios corresponding to different booths, the method comprising:

starting a simulation program for verifying the central processing unit;

detecting whether a first transfer simulation state file exists;

and executing subsequent simulation.

2. The method of claim 1, wherein initiating a simulation program for validating the central processing unit comprises:

starting a simulation program through a compiling type simulation simulator;

3. The method of claim 2, wherein the debug script is configured to detect whether a first saved emulation state file exists and to apply the first saved emulation state file to restore a corresponding emulation state.

4. The method as recited in claim 1, further comprising:

5. The method as recited in claim 4, further comprising:

6. The method of claim 2, wherein the incoming parameters of the debug script include an engineering catalog, a use case name, a seed number.

7. The method of claim 6, wherein the first stored simulation state file is a file stored under the engineering catalog corresponding to the use case name and the seed number.

8. The method as recited in claim 1, further comprising:

9. The method of claim 1, wherein the predetermined level of read-only memory boot program comprises a zeroth level read-only memory boot program, a first level read-only memory boot program, and/or a second level read-only memory boot program.

10. The method of claim 1, wherein the read-only memory comprises a read-only memory disposed within a system on chip or a read-only memory disposed on a board comprising the system on chip.

11. A computing device, comprising:

a processor; and

a memory storing a computer program which, when executed by the processor, causes the processor to perform the method of any one of claims 1-10.