CN117493114A

CN117493114A - Exception handling method and device, processor and electronic equipment

Info

Publication number: CN117493114A
Application number: CN202311492436.2A
Authority: CN
Inventors: 王银峰; 刘勇鹏; 舒奕棋; 田鹏
Original assignee: Phytium Technology Co Ltd
Current assignee: Phytium Technology Co Ltd
Priority date: 2023-11-09
Filing date: 2023-11-09
Publication date: 2024-02-02

Abstract

The application discloses an exception handling method, an exception handling device, a processor and electronic equipment, which are applied to the processor; the exception handling method comprises the following steps: when a target exception is triggered in the process of executing a program flow, performing exception handling on the target exception based on target firmware; performing exception handling on the target exception again based on an exception vector table of kernel space in the processor; and after the exception processing is completed in the kernel space, returning to a target fault point to continue executing the program flow, wherein the target fault point is a break point when the target exception is triggered in the program flow. According to the embodiment of the application, two modes of processing the exception are integrated, specific processing procedures are realized based on the firmware and the exception vector table in the kernel space respectively aiming at the actual occurrence of one exception or one interrupt of hardware, and the superiority of exception processing in a processor is obviously improved.

Description

Exception handling method and device, processor and electronic equipment

Technical Field

The present invention relates to the field of chips, and in particular, to a processor technology in the field of chips, and more particularly, to an exception handling method, an exception handling device, a processor, and an electronic device.

Background

The exception handling mechanism of a processor is an important component of its architecture that allows the processor to take appropriate action when a particular exception condition is encountered. The mechanism can ensure the stable operation of the system and can also improve the flexibility and the reliability of the processor.

At present, the large multiprocessor realizes exception handling based on an exception vector table in a kernel space. For example, after triggering an exception in the program flow, jumping to the exception vector table, executing the exception handling function in the exception vector table to implement exception handling, and finally returning to the fault point to continue executing the program flow.

However, exception vector tables are typically stored in the processor's core, which can only handle exceptions in the core space. And in order to handle some specific exceptions, the universal codes of all relevant platforms need to be deployed, which is very difficult to realize. Eventually, the current exception handling mechanism in the processor is less advantageous.

Disclosure of Invention

In order to solve the technical problems, the application provides an exception handling method, an exception handling device, a processor and electronic equipment, so as to achieve the purpose of improving the superiority of a current exception handling mechanism in the processor.

In order to achieve the technical purpose, the embodiment of the application provides the following technical scheme:

In a first aspect, an embodiment of the present application provides an exception handling method, applied to a processor, where the exception handling method includes:

when a target exception is triggered in the process of executing a program flow, performing exception handling on the target exception based on target firmware;

performing exception handling on the target exception again based on an exception vector table of kernel space in the processor;

and after the exception processing is completed in the kernel space, returning to a target fault point to continue executing the program flow, wherein the target fault point is a break point when the target exception is triggered in the program flow.

In a second aspect, an embodiment of the present application provides an exception handling apparatus, applied to a processor, including:

the first exception handling module is used for performing exception handling on the target exception based on target firmware when the target exception is triggered in the process of executing the program flow;

the second exception handling module is used for performing exception handling on the target exception again based on an exception vector table of the kernel space in the processor;

and the exception return module is used for returning to a target fault point to continue executing the program flow after the exception processing is completed in the kernel space, wherein the target fault point is a break point in the program flow when the target exception is triggered.

In a third aspect, embodiments of the present application provide a processor configured to perform the exception handling method according to the first aspect.

In a fourth aspect, embodiments of the present application provide an electronic device, including: the processor of the third aspect.

In a fifth aspect, embodiments of the present application provide a computer readable storage medium, where a computer program is stored, where the computer program is executed by a processor to implement the exception handling method according to the first aspect.

In a sixth aspect, embodiments of the present application provide a computer program product or computer program, the computer program product comprising a computer program stored in a computer readable storage medium; a processor of the computer device reads the computer program from the computer readable storage medium, the processor implementing the steps of the exception handling method according to the first aspect when the processor executes the computer program.

According to the exception handling method, when the target exception is triggered in the process of executing the program flow, first, the first exception handling is performed in the form of firmware, compared with the operation in the kernel space, the exception handling is safer in the firmware layer, the operability of the firmware is higher, and the exception handling logic can be flexibly adjusted. Then, the target exception is again exception-processed based on the exception vector table of the kernel space in the processor. And the secondary processing of the exception is realized by multiplexing the exception vector table in the kernel space. The safety and the flexibility are ensured, and the final effect of the whole exception handling flow can be improved. Finally, after the exception handling is completed in the kernel space, returning to the interrupt point when the target exception is triggered to continue to execute the program flow, and completing the exception handling flow. According to the embodiment of the application, two modes of processing the exception are integrated, specific processing procedures are realized based on the firmware and the exception vector table in the kernel space respectively aiming at the actual occurrence of one exception or one interrupt of hardware, and the superiority of exception processing in a processor is obviously improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings may be obtained according to the provided drawings without inventive effort to a person skilled in the art.

FIG. 1 is a flow chart of an exception handling method according to an embodiment of the present application;

FIG. 2 is a flow chart of the offset calculation provided by one embodiment of the present application;

FIG. 3 is a schematic diagram of a processing procedure for target exceptions triggered by user space according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a processing procedure for kernel-space triggered target exceptions according to one embodiment of the present application;

FIG. 5 is a block diagram of an exception handling apparatus according to one embodiment of the present application;

fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

Unless otherwise defined, technical or scientific terms used in the embodiments of the present application should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs. The terms "first," "second," and the like, as used in this embodiment, do not denote any order, quantity, or importance, but rather are used to avoid intermixing of components.

Throughout the specification, unless the context requires otherwise, the word "plurality" means "at least two", and the word "comprising" is to be construed as open, inclusive meaning, i.e. as "comprising, but not limited to. In the description of the present specification, the terms "one embodiment," "some embodiments," "example embodiments," "examples," "particular examples," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present application. The schematic representations of the above terms do not necessarily refer to the same embodiment or example.

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

SUMMARY

As previously described, the exception handling mechanism of a processor typically relies on an exception vector table in kernel space. The abnormal vector table can be understood as a section of fixed memory address space, and after an abnormality occurs, the abnormal vector table is jumped into, and then the abnormal processing is carried out by means of the abnormal vector table.

At present, the abnormal vector table is mature and stable, and is used for carrying out abnormal processing, so that the realization is relatively simple. However, the exception vector table is subject to some restrictions in kernel space, so that the superiority of the exception handling mechanism that implements exception handling with the exception vector table is not apparent. For example, the kernel space is limited in terms of operating system security, and flexibility and operability are poor.

In order to solve the problems found by the research of the inventor, the inventor proposes that when an exception occurs, the firmware is preferentially used for carrying out one-time exception handling, then the exception handling is carried out again by multiplexing the exception vector table in the kernel space, and the superiority of the exception handling in the processor can be obviously improved by integrating two ways of exception handling.

Based on the above-described conception, the present inventors have provided an abnormality processing method, and an abnormality processing method provided in the embodiment of the present application will be exemplarily described below with reference to the accompanying drawings.

Exemplary method

Taking the application to a processor as an example, the embodiment of the application provides an exception handling method, which includes:

step S101: when the target exception is triggered in the process of executing the program flow, the target exception is processed based on the target firmware.

In this step, program flow (program flow) refers to a control flow when a program is executed in a processor. It describes the execution order and conditional branching of instructions, determining the path of travel and logic of the program. Which may also be referred to as a program execution flow. During execution of the program stream, a failure triggers a corresponding exception, thereby interrupting execution of the program stream. The target anomalies may be specified certain fault-triggered anomalies. These faults may be, but are not limited to, illegal instructions, instruction misaligned accesses, UCE in memory faults (Uncorrectable Error, uncorrectable faults), etc. Accordingly, these failure-triggered target exceptions may be synchronous external aborts (Synchronous External Abort, SEA), system error interrupts (System Error Interrupt, SEI), etc.

The target firmware is a functional module in the processor for exception handling in the form of firmware (firmware). Notably, the target firmware is distinguished from the kernel-space exception vector table, which has the characteristics of firmware, is more operable, and can flexibly adjust exception handling logic. When the processor triggers an exception during the program flow execution process, the pre-stored target firmware is preferentially utilized for carrying out exception processing, wherein the exception processing comprises fault diagnosis, fault repair, and panic execution. It will be appreciated that the processor uses hardware to record fault information in the event of a fault or triggering exception. In the process of processing the exception by utilizing the target firmware, fault information in hardware can be read to realize exception processing.

Step S102: and carrying out exception processing on the target exception again based on an exception vector table of the kernel space in the processor.

In the step, the target exception is processed by using an exception vector table in the kernel space. The kernel space of the processor and the exception vector table of the kernel space are not described in detail herein. The exception vector table is used when the kernel space processes exception. Specifically, the abnormal vector table may be understood as a section of specific memory address space, and when an abnormality occurs, the abnormal vector table jumps to the corresponding memory address space in the abnormal vector table to perform the abnormality processing. The target abnormality may be processed by using an existing abnormality vector table, but is not limited thereto.

Step S103: after the exception handling of the kernel space is completed, returning to the target fault point to continue executing program flow.

In this step, the target fault point is a break point when the target abnormality is triggered in the program flow. It will be appreciated that after a fault, an interrupt is typically made. After the failover, execution continues from the point of interruption. Specifically, the interrupt point may be the address of the next PC currently executing, i.e., the next instruction to be executed, but is not limited thereto. In the present embodiment, step S101 and step S102 are two different processing methods for the same exception. That is, for an exception or an interrupt of hardware that is actually triggered during the system operation, two different processing methods are adopted to process the exception/interrupt respectively.

In the embodiment of the application, when the target exception is triggered in the process of executing the program flow, first, the first exception processing is performed in the form of firmware, and compared with the operation performed in the kernel space, the exception processing is safer in the firmware layer, the operability of the firmware is higher, and the exception processing logic can be flexibly adjusted. Then, the target exception is again exception-processed based on the exception vector table of the kernel space in the processor. And the secondary processing of the exception is realized by multiplexing the exception vector table in the kernel space. The safety and the flexibility are ensured, and the final effect of the whole exception handling flow can be improved. Finally, after the exception handling is completed in the kernel space, returning to the interrupt point when the target exception is triggered to continue to execute the program flow, and completing the exception handling flow. According to the embodiment of the application, two modes of processing the exception are integrated, specific processing procedures are realized based on the firmware and the exception vector table in the kernel space respectively aiming at the actual occurrence of one exception or one interrupt of hardware, and the superiority of exception processing in a processor is obviously improved.

In some embodiments, when a target exception is triggered during execution of a program flow, exception handling of the target exception based on target firmware includes:

When triggering a target abnormality in the process of executing the program flow, switching the abnormality level of the target abnormality to a target abnormality level; the target exception level is an exception level for exception handling in a processor in a firmware manner;

and performing exception handling on the target exception based on the target firmware corresponding to the target exception level.

It should be noted that, regarding the Exception triggered in the processor, an Exception Level (EL) is generally divided to achieve the security and reliability of the processor. Wherein the exception levels define different privilege levels, each privilege level having different access rights and capabilities. For example, the anomaly level can be divided into four different levels in the current ARM architecture, namely EL0, EL1, EL2, EL3. Where EL0 is the lowest privilege level for executing a generic application. EL1 is a high privilege level for executing an operating system kernel. EL2 is used for virtualization support, allowing virtualization software (e.g., virtual machine monitor) to run at this level. EL3 is the highest privilege level for security monitoring and trusted execution environments. It will be appreciated that the processor may divide the exception level of the triggered target exception according to the failure that triggered the exception. Then, the abnormality level of the target abnormality may be switched to the target abnormality level by switching the abnormality level. For example, during execution of an application in the user space, an EL0 level exception will be triggered when UCE occurs. Then, by switching the abnormality level, the abnormality level of the abnormality can be switched to the EL3 level. Correspondingly, the anomaly is the target anomaly, and EL3 is the target anomaly level.

In the present embodiment, the exception of the target exception level is not directly implemented by using the exception vector table in the kernel space, but is implemented in the form of firmware preferentially. That is, the target firmware for realizing the abnormality processing may be set in advance corresponding to the target abnormality level, and when the abnormality of the target abnormality level is triggered, the abnormality processing is realized by the target firmware preferentially. In some embodiments, the target anomaly level is not EL1/EL2, but may be EL3. To ensure a smooth switch to EL3, the EA (External Abort) bit field of SCR (security configuration register, secure Configuration Register) under EL3 may be kept at 1, i.e. scr_el3.ea is at 1. At this time, regardless of the level of exception at which the current program is executing, all SEA and SEI eventually get trapped in EL3, thereby ensuring that the target firmware handles the target exception preferentially. Naturally, if the abnormality level of the target abnormality triggered by the fault is directly classified as the target abnormality level, the target abnormality level may be maintained. It can also be considered to switch from the target exception level to the present exception level.

In the present embodiment, when the target abnormality is not an abnormality level at which abnormality processing is performed by the firmware, it is possible to ensure that abnormality processing is realized by preferentially using the target firmware by switching the abnormality level.

In some embodiments, exception handling of the target exception again based on an exception vector table of kernel space in the processor includes:

determining an entry address of a target exception handling function; the target exception handling function is an exception handling function used for handling target exceptions in an exception vector table in kernel space;

storing the entry address of the target exception handling function to a target register under the target exception level;

and executing a target exception handling function in the kernel space based on the entry address in the target register, and performing exception handling on the target exception.

It should be noted that the exception vector table contains a plurality of exception handling functions that can handle different exceptions. When the exception handling is implemented using an exception vector table, the exception handling is typically implemented using an exception handling function in the exception vector table. It will be appreciated that different exception handling functions are used to handle different exceptions. Therefore, in the process of performing the exception handling on the target exception by the exception vector table, it is necessary to determine an exception handling function for handling the target exception, that is, a target exception handling function. And further, the exception handling of the target exception is realized by means of the target exception handling function.

In the processor, each exception handling function has an entry address through which a jump to the corresponding exception handling function can be made. In this embodiment, after the target abnormality is preferentially handled by the target firmware, the target abnormality is subjected to abnormality handling by the target abnormality handling function for implementation. It is necessary to store the entry address of the target exception handling function in a target register of a target exception level, which is a register for storing the return address of the function at the target exception level, after the target exception handling function is determined. In this embodiment, the function return address is the entry address of the target exception handling function. After the target firmware is used for processing the target exception, the jump is carried out according to the function return address in the target register, so that the jump is carried out to the target exception processing function in the kernel space, and the exception processing is realized. Specifically, the target register may be an abnormal link address register (Exception Link Register, abbreviated ELR).

In this embodiment, after the exception handling is implemented by the target firmware, the entry address in the target register is used to jump to the kernel space, so that the exception handling of the target exception is implemented by the target exception handling function.

In order to ensure that critical system states and data are not lost when the kernel space processes an exception and ensure that the state before the exception occurs can be correctly recovered after the exception processing is completed, in some embodiments of the present application, a target exception processing function is executed in the kernel space based on an entry address in a target register, and before the exception processing is performed on the target exception, the method further includes:

and storing the abnormal state information of the target abnormality into a corresponding register of the kernel space.

It should be noted that the abnormal state information is information indicating a target abnormality or a failure triggering the target abnormality. Specifically, the abnormal state information may be error information related to the abnormality or fault stored in the related register after the triggering target abnormality.

It will be appreciated that in the case where the target anomaly level is EL3, SCR_EL3.EA may be changed to 0 in order to enable subsequent target anomalies to be routed to kernel space. But this method can perform exception handling only once. After the target exception is triggered subsequently, since the operating system has no authority to modify the value of scr_el3, exception handling in kernel space will only be enabled. Therefore, the present embodiment injects the target exception into the EL2/EL1 of the operating system by software, that is, it is possible to always keep the firmware to preferentially process the target exception, and then smoothly jump to the kernel space. After the exception state information is stored in the corresponding register of the kernel space, the exception state information can be regarded as that the target exception occurs in the kernel space, and at this time, the exception processing can be smoothly performed on the target exception in the kernel space.

In this embodiment, by storing the abnormal state information in the corresponding register in the kernel space, it is possible to ensure that the critical system state and data are not lost when the kernel space processes the abnormality, and to ensure that the state before the occurrence of the abnormality can be correctly recovered after the completion of the abnormality processing, and to directly return to the failure point from the kernel space.

In some embodiments, storing exception state information for a target exception to a corresponding register in kernel space includes:

copying the value of each register for recording abnormal state information under the target abnormal level to a corresponding register in the kernel space;

and adjusting the value of the target bit domain in the corresponding register of the kernel space based on the exception type and the exception source information of the target exception.

It should be noted that registers in the processor for recording exception status information include, but are not limited to: status registers (Exception Syndrome Register, ESR for short), exception link address registers, program pointer status registers (Saved Program Status Register, SPSR for short), error address registers (Fault Address Register, FAR for short), and the like. It will be appreciated that the aforementioned registers are provided at each level of exception. For example, esr_el1, elr_el1, spsr_el1, far_el1 are provided below EL1. ESR_EL3, ELR_EL3, SPSR_EL3, FAR_EL3 are provided below EL3. Registers with the same function under different exception levels are corresponding registers. In some embodiments, the kernel space corresponds to an anomaly level comprising EL1, EL2, and the target anomaly level is EL3. During the exception handling of the target exception with the target firmware, registers such as esr_el3, elr_el3, spsr_el3, far_el3, etc. will record exception status information. When copying the abnormal state information into the corresponding registers of the kernel space, esr_el3 is copied to esr_el1, elr_el3 is copied to elr_el1, and so on.

Notably, since kernel space corresponds to both anomaly levels of EL1 and EL2. In considering which exception level registers are copied information, it may be considered whether ARM64 server enabled virtualized extension (VHE), if so, to registers under EL2, or else to registers under EL 1.

In addition, the relevant bit fields need to be modified during or after copying, taking into account the differences between the corresponding registers at different exception levels. The target bit field is the bit field with the difference in the corresponding register. Specifically, when considering the target bit-domain and how to adjust the target bit-domain, it is necessary to ensure that the kernel space after adjustment is as if the target exception has actually occurred. Therefore, specific adjustment needs to be achieved based on the abnormality type and abnormality source information of the target abnormality. The exception types include synchronous exceptions and asynchronous exceptions, among others. The abnormality source information includes an initial abnormality level divided when the target abnormality is triggered, that is, an abnormality level before the target abnormality is subjected to abnormality level switching. For example, in a scenario in which the value of each register at the EL3 level is copied to the corresponding register at the EL2 level, when esr_el3.Ec error type is 0x25, it indicates that the abnormality type is a synchronization abnormality. At this time, if spsr_el3.m [3:0] = 0x9 is true, the abnormality source information may indicate that the abnormality is from EL1h, thereby setting esr_el2.ec=0x25. If spsr_el3.m [3:0] = 0x8 holds, the abnormality source information may indicate that the abnormality is from EL1t, thereby setting esr_el2.ec=0x25. If neither SPSR_EL3.M [3:0] = 0x9 nor SPSR_EL3.M [3:0] = 0x8 is true, the anomaly source information may indicate that the anomaly is from EL0t, thereby setting SPSR_EL3.M [3:0] = 0x9. When esr_el3.Ec error type is 0x2f, it indicates that the exception type is an asynchronous exception. At this time, if spsr_el3.m [3:0] = 0x9 is true, the abnormality source information may indicate that the abnormality is from EL1h, thereby setting spsr_el3.m [3:0] = 0x9. If SPSR_EL3.M [3:0] = 0x8 is true, then the anomaly source information may indicate that the anomaly is from EL1t, thereby setting SPSR_EL3.M [3:0] = 0x9. If neither SPSR_EL3.M [3:0] = 0x9 nor SPSR_EL3.M [3:0] = 0x8 is true, the anomaly source information may indicate that the anomaly is from EL0t, thereby setting SPSR_EL3.M [3:0] = 0x9.

In this embodiment, when copying the relevant information to the corresponding registers in the kernel space, some bit fields of the relevant registers are adjusted based on the difference information between the corresponding registers, so that errors possibly caused by copying the relevant information only can be avoided.

In some embodiments, determining the entry address of the target exception handling function includes:

determining the offset of the target exception handling function based on the exception type and the exception source information of the target exception;

the entry address of the target exception handling function is determined based on the base address and the offset of the exception vector table in kernel space.

It should be noted that the exception types include synchronous exceptions and asynchronous exceptions. The abnormality source information includes an initial abnormality level divided when the target abnormality is triggered, that is, an abnormality level before the target abnormality is subjected to abnormality level switching. It will be appreciated that the base address of the exception vector table is its starting address, and that there are different offsets to the base address of the entry address of the different exception handling functions within it. Thus, to determine the entry address of the target exception handling function, the offset of the entry address of the target exception handling function relative to the base address may be determined first. In determining the offset, it is necessary to use the abnormality type and abnormality source information of the target abnormality. The offset may be obtained after determining the anomaly type of the target anomaly, the initial anomaly level of the target anomaly. As shown in fig. 2, in the case where the target abnormality level is EL3, the process of determining the offset of the target abnormality processing function includes:

Starting:

step S201: and determining whether the target abnormality is synchronous abnormality, if so, starting a synchronous abnormality flow, and if not, starting an asynchronous abnormality flow. Specifically, whether the error type of esr_el3.Ec is 0x2f is determined, if so, an asynchronous exception, such as SEI, is indicated; otherwise, a synchronization exception, such as SEA, is detected.

Step S202: judging whether spsr_el3.m [3:0] = 0x9 is true, if yes, indicating that the abnormality is from EL1h, and executing step S203; if not, go to step S204.

Step S203: the offset of the target exception handling function is set to 0x200, i.e., the entry address of the el1h_64_sync synchronization exception. Of course, the offset of the target exception handling function may also be considered as an offset of the exception vector table.

Step S204: judging whether SPSR_EL3.M [3:0] = 0x8 is true, if yes, indicating that the abnormality is from EL1t, and executing step S205; if not, go to step S206.

Step S205: the offset of the target exception handling function is set to 0x00, i.e., the entry address of the el1t_64_sync synchronization exception. Likewise, the offset of the target exception handling function may also be considered as the offset of the exception vector table.

Step S206: the exception is from EL0h, and the offset of the target exception handling function is set to 0x400, i.e., the entry address of the el0h_64_sync sync exception.

Step S207: judging whether SPSR_EL3.M [3:0] = 0x9 is true, if yes, indicating that the abnormality is from EL1h, and executing step S208; if not, step S209 is performed.

Step S208: the offset of the target exception handling function is set to 0x380, the entry address of the el1h_64_error asynchronous exception. Of course, the offset of the target exception handling function may also be considered as an offset of the exception vector table.

Step S209: judging whether SPSR_EL3.M [3:0] = 0x8 is true, if so, indicating that the abnormality is from EL1t, and executing step S210; if not, step S211 is performed.

Step S210: the offset of the target exception handling function is set to 0x180, the entry address of the el1t_64_error asynchronous exception. Likewise, the offset of the target exception handling function may also be considered as the offset of the exception vector table.

Step S211: the exception is from EL0h, and the offset of the target exception handling function is set to 0x580, the entry address of the el0h_64_error asynchronous exception.

And (5) ending.

In this embodiment, based on the anomaly type and anomaly source information of the target anomaly, the offset of the target anomaly handling function can be accurately determined, and then the entry address of the target anomaly handling function can be obtained by combining the base address of the anomaly vector table.

In some implementations, executing a target exception handling function in kernel space based on an entry address in a target register, exception handling a target exception, includes:

executing an exception return instruction, jumping to kernel space and executing a target exception handling function according to the entry address;

notifying the kernel thread of an exception event;

reading the exception record information in the shared memory by using the kernel thread, and performing exception handling on the target exception based on the restoration condition of the target exception;

the abnormal record information in the shared memory is record information generated in the process that the target firmware carries out abnormal processing on the target abnormality.

It should be noted that, the exception return instruction is an ERET instruction in the processor, which is not described in detail herein. Since the entry address of the target exception handling function has already been stored to the target register at the target exception level. Thus, by executing the ERET instruction, it is possible to jump to kernel space based on the entry address of the target exception handling function in the target register, and execute the target exception handling function.

It will be appreciated that when exception handling is performed in kernel space, a particular exception handling process will be implemented using kernel threads. In this embodiment, to call a kernel thread, it is necessary to notify an exception event to the kernel thread. Since the target exception has been handled once by the target firmware, the target exception may have been repaired or otherwise. To simplify exception handling in kernel threads. In the process of processing the target exception by using the kernel thread, record information generated in the process of processing the target exception by the target firmware can be read first. And then determine the repair situation of the target abnormality based on the information. And finally, carrying out targeted exception handling on the target exception based on the restoration condition of the target exception. For example, if the repair situation indicates that the target anomaly has been repaired. At this time, when the target exception is handled in the kernel thread, the operating system is notified of the relevant log. If the repair case indicates that the target exception is not repaired, but is of a type that can be repaired in kernel space. At this time, when the exception handling is performed on the target exception in the kernel thread, the target exception may be repaired by means of isolation, page remapping, and the like. If the repair situation indicates that the target abnormality is not repaired, the target abnormality belongs to an unrepairable type. At this time, when the target exception is handled in the kernel thread, the kernel Panic may be directly processed.

In this embodiment, in the process of performing exception processing on the target exception by using the kernel thread, the record information generated in the process of performing exception processing on the target exception by using the target firmware may be referred to, and on this basis, targeted processing is performed on the target exception, so that the exception processing in the kernel thread may be simplified.

To avoid the influence caused by the abnormal level switching, before the abnormal level of the target abnormality is switched to the target abnormal level, the method further includes:

performing a protected field operation;

before executing the exception return instruction, jumping to kernel space and executing the target exception handling function according to the entry address, the method further comprises:

and performing a recovery field operation.

It should be noted that, the switching of the abnormal level may cause the values of some registers in the processor to change, so that in order to ensure that the state before the switching of the abnormal level can be restored, the effect caused by the switching of the abnormal level is avoided, and a protection field operation needs to be performed before the switching of the abnormal level, so that the values of registers that may be affected need to be stored. The restoration field operation is performed after the relevant operation processing, and the values of the respective registers are restored. Among the registers that may be affected are, but are not limited to, general purpose registers X0-X29, LR (Link Register) registers, and SP (Stack Pointer) registers.

In the present embodiment, the site protection operation and the site restoration operation are performed before and after the abnormal level switching, respectively, so that the influence caused by the abnormal level switching can be avoided.

To ensure that the program flow can continue smoothly after the exception handling is completed, the method further includes, before executing the target exception handling function according to the entry address:

performing a protected field operation;

after performing exception handling on the target exception based on the restoration condition of the target exception, the method further comprises the following steps:

and performing a recovery field operation.

It should be noted that the present embodiment protects and recovers the field operation similarly to the previous embodiment. The difference is that the present embodiment is to avoid the influence caused by the exception handling process. It will be appreciated that exception handlers need to maintain state information about the thread or process currently executing, including program counters, register values, stack pointers, etc. The purpose of this is to prevent the exception handling process from damaging the site, ensuring that the execution site can be correctly restored after the exception handling is completed. The protection site can also prevent errors or anomalies in the process of exception handling from being propagated to other parts, and the stability of the system is maintained. By resuming field operation, the operating system can resume the saved thread state information to a state before the occurrence of the exception, so that the program can continue to execute from the place where the exception occurred. Specifically, in this embodiment, the protection field operation is executed, so that the switching and push protection processes of the user stack sp_el0 and the kernel stack sp_el1 of the application program can be implemented. The user stack sp_el0 may be restored from the kernel stack by performing a restore live operation.

In this embodiment, the site protection operation and the site restoration operation are executed before and after the exception processing, respectively, so that the influence caused by the exception processing process can be avoided.

In some implementations, the target exception is an exception triggered in user space of the processor or an exception triggered in kernel space.

It should be noted that the kernel space and the user space in the processor are not described in detail here. In this embodiment, no matter in which space in the kernel space or the user space an exception is triggered, the triggered exception may be processed by two ways of processing the exception, so as to improve the superiority of exception processing in the processor.

The exception handling method provided in the present application is described below with specific examples. Assuming UCE in a memory failure in user space, the triggered target anomaly is an EL0 level anomaly, and the target anomaly level is EL3. As shown in fig. 3, when a segment of UCE fault address is accessed at time t1, if the Normal memory attribute is used as the attribute of the address, the hardware is triggered to generate a synchronization exception, which may be specifically referred to as SEA; if the address is a device attribute, the hardware is triggered to generate an asynchronous exception, which may be SEI in particular.

Since the firmware fixedly configures the EA bit field of SCR_EL3 to be 1, EL3 is trapped regardless of the level of exception at which the current program is executing. Here, since the EL0 is trapped into the EL3, the values of the general registers X0 to X29, LR, and sp_el0 register need to be stored for the subsequent use for fault recovery due to the occurrence of abnormal level switching.

After the field protection before the abnormal level switching is completed, an abnormal processing function provided by the target firmware is entered, and fault diagnosis is performed by inquiring information of a fault record register and abnormal/interrupt information provided by hardware. If the fault address can be repaired, the fault address is repaired, and meanwhile, the fault is recorded into a piece of shared memory, so that the fault record inquiry of the subsequent kernel thread is facilitated.

When the abnormal level switch occurs, fault/abnormal error states are recorded in SPSR_EL3, ELR_EL3, ESR_EL3 and FAR_EL3 registers, so that when faults are reported to an operating system/kernel space, the fault record information needs to be transmitted to the operating system to ensure that the faults can normally return, and a mechanism of step-by-step reporting is followed by fault layering processing adopted by firmware priority. Specifically, the values of the spsr_el3, elr_el3, esr_el3, and far_el3 registers are copied to the spsr_el2/1, elr_el2/1, esr_el2/1, and far_el2/1, where the contents of some of the bit fields need to be modified appropriately, and reference may be made to the adjustment of the target bit field in the above embodiment, which is not repeated here.

EL2/1 exception vector table configuration is performed. The vector base address register (Vector Base Address Register, VBAR for short) under EL2, i.e., vbar_el2, is read. The entry address (absolute address) of the target exception handling function is calculated using the base address plus the offset of the exception vector table and then assigned to elr_el3. The target exception handling function is an exception handling function capable of handling the exception in the exception vector table. The offset of the abnormal vector table may be obtained in the manner shown in fig. 2, and will not be described here.

The values of the general registers X0-X29, LR and SP_EL0 registers are restored. Then executing ERET, the program will jump to the kernel exception vector table specified by elr_el3 to execute the target exception handling function. I.e. SEA or SEI processing functions. Here, a protection field operation is required, and a switching and push protection procedure of the application user stack sp_el0 and the kernel stack sp_el1 is shown in fig. 3. And will not be described in detail herein. It will be appreciated that other kernel threads may be notified of the sea_notify event or the sei_notify event when exception handling is performed in kernel space. And then reading a fault record generated by firmware repair to realize specific fault processing/exception handling. Specifically, the kernel thread for fault handling can read the type of the exception and the severity level of the exception from the fault record, if the type is Fatal deadly, the kernel Panic can be directly repaired, if the type is a recovery type, a kernel repairing mechanism (such as isolation and page remapping) can be called for repairing, if the type is a Corrected type, no repairing is needed, and only the log informs the operating system. After the exception handling is finished, the site needs to be restored, namely the user stack SP_EL0 can be restored from the kernel stack. It is noted that for the Recoverable and the Corrected type errors, after the user stack SP_EL0 is restored, the user stack is returned to the interruption point of the program stream according to the address recorded by ELR_EL2/1 for further execution.

It will be appreciated that each sequence number and arrow in fig. 3 indicates an execution order of the exception handling method, but implementing the exception handling method provided in the present application is not limited to one execution order provided in fig. 3.

In the embodiment, during the process of processing the firmware with priority, the software is used for injecting the exception into the operating system/kernel space, so that the existing exception vector table of the operating system is fully utilized for reporting, recovering and processing the fault. The security, the reliability, the implementation flexibility and the layering processing idea are fully ensured.

In the case of kernel space triggering exception, a specific implementation of the exception handling method provided in the present application is shown in fig. 4. The whole process is basically similar to the process shown in fig. 3, but the switching process of the user state stack and the kernel state stack is absent, and the processing functions corresponding to the exception vector table are inconsistent, and otherwise, there are no essential differences, and the same points are described in relation to fig. 3, and are not repeated here.

Exemplary apparatus

Some embodiments of the present application further provide an exception handling apparatus, applied to a processor, as shown in fig. 5, including:

The first exception handling module 51 is configured to perform exception handling on a target exception based on the target firmware when the target exception is triggered during execution of the program flow;

the second exception handling module 52 is configured to perform exception handling on the target exception again based on an exception vector table in kernel space in the processor;

and the exception return module 53 is configured to return to a target fault point to continue executing the program flow after the kernel space completes exception processing, where the target fault point is a break point in the program flow when the target exception is triggered.

In some implementations, the first exception handling module 51 includes:

an abnormal level switching unit for switching the abnormal level of the target abnormality to the target abnormal level when the target abnormality is triggered in the process of executing the program flow; the target exception level is an exception level for exception handling in a processor in a firmware manner;

the first exception handling unit is used for performing exception handling on the target exception based on the target firmware corresponding to the target exception level.

In some implementations, the second exception handling module 52 includes:

an entry address determination unit configured to determine an entry address of a target exception handling function; the target exception handling function is an exception handling function used for handling target exceptions in an exception vector table in kernel space;

An entry address storage unit for storing an entry address of a target exception handling function to a target register under a target exception level;

and the second exception handling unit is used for executing a target exception handling function in the kernel space based on the entry address in the target register and performing exception handling on the target exception.

In some embodiments, the apparatus further comprises:

and the abnormal information storage module is used for storing the abnormal state information of the target abnormality into a corresponding register in the kernel space.

In some embodiments, the anomaly information storage module is specifically configured to:

In some embodiments, the entry address determining unit is specifically configured to:

In some embodiments, the second exception handling unit is specifically configured to:

notifying the kernel thread of an exception event;

In some embodiments, the apparatus further comprises:

the first field protection module is used for executing protection field operation before switching the abnormal level of the target abnormality to the target abnormal level;

the first field recovery module is used for executing recovery field operation before executing the exception return instruction, jumping to the kernel space and executing the target exception handling function according to the entry address.

In some embodiments, the apparatus further comprises:

the second field protection module is used for executing the protection field operation before executing the target exception handling function according to the entry address;

and the second field recovery module is used for executing recovery field operation after carrying out exception handling on the target exception based on the repair condition of the target exception.

The exception handling apparatus provided in the embodiment of the present application is the same as the exception handling method provided in the above embodiment of the present application. Technical details not described in detail in this embodiment may be referred to the specific processing content of the exception handling method provided in the foregoing embodiment of the present application, and will not be described herein.

Exemplary processor and electronic device

Another embodiment of the present application also proposes a processor configured to perform the steps in the exception handling method according to various embodiments of the present application described in the above embodiments of the present application.

Another embodiment of the present application further provides an electronic device, including the processor in the foregoing embodiment. Referring to fig. 6, an exemplary embodiment of the present application further provides an electronic device, including: a memory storing a computer program, and a processor that executes steps in the exception handling method according to various embodiments of the present application described in the above embodiments of the present application.

The internal architecture of the electronic device may be as shown in fig. 6, the electronic device comprising a processor, a memory, a network interface and input means connected by a system bus. Wherein the processor of the electronic device is configured to provide computing and control capabilities. The memory of the electronic device includes a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface of the electronic device is used for communicating with an external terminal through a network connection. The computer program, when executed by a processor, performs the steps in the abnormality processing method according to various embodiments of the present application described in the above embodiments of the present application.

The processor may include a host processor, and may also include a baseband chip, modem, and the like.

The memory stores programs for executing the technical scheme of the invention, and can also store an operating system and other key services. In particular, the program may include program code including computer-operating instructions. More specifically, the memory may include read-only memory (ROM), other types of static storage devices that may store static information and instructions, random access memory (random access memory, RAM), other types of dynamic storage devices that may store information and instructions, disk storage, flash, and the like.

The processor may be a general-purpose processor, such as a general-purpose Central Processing Unit (CPU), microprocessor, etc., or may be an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of programs in accordance with aspects of the present invention. But may also be a Digital Signal Processor (DSP), application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components.

The input device may include means for receiving data and information entered by a user, such as a keyboard, mouse, camera, scanner, light pen, voice input device, touch screen, pedometer or gravity sensor, etc.

The output device may include means, such as a display screen, printer, speakers, etc., that allow information to be output to the user.

The communication interface may include means, such as any transceiver, for communicating with other devices or communication networks, such as ethernet, radio Access Network (RAN), wireless Local Area Network (WLAN), etc.

The processor executes the program stored in the memory and invokes other devices, which may be used to implement the steps of any of the exception handling methods provided in the embodiments of the present application.

The electronic equipment can also comprise a display component and a voice component, wherein the display component can be a liquid crystal display screen or an electronic ink display screen, an input device of the electronic equipment can be a touch layer covered on the display component, can also be a key, a track ball or a touch pad arranged on a shell of the electronic equipment, and can also be an external keyboard, a touch pad or a mouse and the like.

It will be appreciated by those skilled in the art that the structure shown in fig. 6 is merely a block diagram of a portion of the structure associated with the present application and is not limiting of the electronic device to which the present application is applied, and that a particular electronic device may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.

Exemplary computer program product and storage Medium

In addition to the methods and apparatus described above, the exception handling methods provided by embodiments of the present application may also be a computer program product comprising computer program instructions which, when executed by a processor, cause the processor to perform the steps in the exception handling methods according to various embodiments of the present application described in the section "exemplary methods" above.

The computer program product may write program code for performing the operations of embodiments of the present application in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server.

Further, the present application embodiment also provides a computer-readable storage medium having stored thereon a computer program that is executed by a processor to perform the steps in the abnormality processing method according to various embodiments of the present application described in the above-described "exemplary method" section of the present application.

Those skilled in the art will appreciate that implementing all or part of the above described embodiments may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.

The technical features of the above embodiments may be combined in any manner, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, all of the combinations of the technical features should be considered as being within the scope of the present disclosure as long as there is no contradiction between them.

The above embodiments represent only a few embodiments of the present application, which are described in more detail and detail, but are not to be construed as limiting the scope of the solutions provided by the embodiments of the present application. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims

1. An exception handling method, applied to a processor, comprising:

2. The method of claim 1, wherein when a target exception is triggered during execution of a program flow, exception handling of the target exception based on target firmware comprises:

when triggering a target abnormality in the process of executing a program flow, switching the abnormality level of the target abnormality to a target abnormality level; the target exception level is an exception level for exception handling in the processor in a firmware manner;

3. The method of claim 2, wherein exception handling the target exception again based on an exception vector table for kernel space in the processor comprises:

determining an entry address of a target exception handling function; the target exception handling function is an exception handling function used for handling the target exception in an exception vector table in the kernel space;

Storing an entry address of the target exception handling function to a target register under the target exception level;

and executing the target exception handling function in the kernel space based on the entry address in the target register, and performing exception handling on the target exception.

4. The method of claim 3, wherein, based on the entry address in the target register, prior to executing the target exception handling function in the kernel space to exception-handle the target exception, the method further comprises:

5. The method of claim 4, wherein storing the exception state information of the target exception to the corresponding register of the kernel space comprises:

copying the value of each register used for recording abnormal state information under the target abnormal level into a corresponding register of the kernel space;

and adjusting the value of the target bit field in the corresponding register of the kernel space based on the exception type and the exception source information of the target exception.

6. A method according to claim 3, wherein determining the entry address of the target exception handling function comprises:

determining the offset of a target exception handling function based on the exception type and the exception source information of the target exception;

and determining the entry address of the target exception handling function based on the base address of the exception vector table in the kernel space and the offset.

7. The method of claim 3, wherein executing the target exception handling function in the kernel space based on the entry address in the target register, exception handling the target exception, comprises:

executing an exception return instruction, jumping to the kernel space and executing the target exception handling function according to the entry address;

notifying the kernel thread of an exception event;

reading exception record information in a shared memory by using the kernel thread, and performing exception handling on the target exception based on the restoration condition of the target exception;

8. The method of claim 7, wherein prior to switching the anomaly level of the target anomaly to the target anomaly level, the method further comprises:

performing a protected field operation;

before executing the exception return instruction, jumping to the kernel space and executing the target exception handling function according to the entry address, the method further comprises:

and performing a recovery field operation.

9. The method of claim 7, wherein prior to executing the target exception handling function according to the entry address, the method further comprises:

performing a protected field operation;

after performing exception handling on the target exception based on the restoration condition of the target exception, the method further comprises:

and performing a recovery field operation.

10. The method of claim 1, wherein the target exception is an exception triggered in a user space of the processor or an exception triggered in the kernel space.

11. An exception handling apparatus for use with a processor, the exception handling apparatus comprising:

12. The apparatus of claim 11, wherein the first exception handling module comprises:

an exception level switching unit, configured to switch an exception level of a target exception to a target exception level when the target exception is triggered during execution of a program flow; the target exception level is an exception level for exception handling in the processor in a firmware manner;

13. The apparatus of claim 12, wherein the second exception handling module comprises:

an entry address determination unit configured to determine an entry address of a target exception handling function; the target exception handling function is an exception handling function used for handling the target exception in an exception vector table in the kernel space;

An entry address storage unit configured to store an entry address of the target exception handling function to a target register under the target exception level;

and the second exception handling unit is used for executing the target exception handling function in the kernel space based on the entry address in the target register and performing exception handling on the target exception.

14. The apparatus of claim 13, wherein the apparatus further comprises:

and the abnormal information storage module is used for storing the abnormal state information of the target abnormality into a corresponding register of the kernel space.

15. The apparatus of claim 14, wherein the anomaly information storage module is specifically configured to:

16. The apparatus according to claim 13, wherein the entry address determination unit is specifically configured to:

17. A processor configured to perform the exception handling method of any one of claims 1 to 10.

18. An electronic device, comprising: the processor of claim 17.

19. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the exception handling method according to any one of claims 1 to 10.