CN117493011A - Backtracking method and system of multi-core processor, storage medium and electronic equipment - Google Patents

Backtracking method and system of multi-core processor, storage medium and electronic equipment Download PDF

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Publication number
CN117493011A
CN117493011A CN202311526721.1A CN202311526721A CN117493011A CN 117493011 A CN117493011 A CN 117493011A CN 202311526721 A CN202311526721 A CN 202311526721A CN 117493011 A CN117493011 A CN 117493011A
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Prior art keywords
processor
context information
memory
address space
core
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Chinese (zh)
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李平
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Chengdu Xinsheng Integrated Circuit Co ltd
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Chengdu Xinsheng Integrated Circuit Co ltd
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Priority to CN202311526721.1A priority Critical patent/CN117493011A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application provides a backtracking method of a multi-core processor, which comprises the following steps: if the processor cores in the hanging state are detected, mapping the context information of all the processor cores to a target address space; generating a storage snapshot according to the context information and storing the storage snapshot into a nonvolatile memory; the storage snapshot is used to perform stack trace back of the processor. When the processor core is in a hanging state, the context information of the processor core is mapped to a target address space, so that a storage snapshot is generated, and trace back and memory analysis of the processor core are conducted according to the storage snapshot to determine an abnormal processor core. The method and the device can save the context information of the processor core in any scene, and avoid influencing the reading and the brushing of the register context in the context information when the interrupt priority is lower. The application also provides a backtracking system of the multi-core processor, a storage medium and electronic equipment, and the backtracking system has the beneficial effects.

Description

Backtracking method and system of multi-core processor, storage medium and electronic equipment
Technical Field
The present disclosure relates to the field of chip technologies, and in particular, to a backtracking method, a system, a storage medium, and an electronic device for a multi-core processor.
Background
Currently, when a core is hooked in a CPU (Central Processing Unit ), a register context of the hooked processor core cannot be acquired sometimes, so that stack backtracking is difficult. For example, when a processor core is suspended, an IPI (Inter-Processor Interrupt) interrupt is sent to the suspended processor core by other active processor cores to save its runtime register context before the interrupt occurs, facilitating other active processor cores to read and brush down. However, if the processor core is hung up in the interrupt state, because the processor core cannot support interrupt nesting or the IPI interrupt priority is not high enough, the IPI interrupt will fail, the register context of the processor core cannot be obtained, and effective backtracking cannot be performed.
Disclosure of Invention
The invention aims to provide a backtracking method, a backtracking system, a storage medium and electronic equipment of a multi-core processor, which can ensure that complete execution site information of all processor cores can be obtained when a multi-core processor system is hung up under any condition by mapping context information of all processor cores to a target address space.
In order to solve the technical problems, the application provides a backtracking method of a multi-core processor, which comprises the following specific technical scheme:
if the processor cores in the hanging state are detected, mapping the context information of all the processor cores to a target address space;
generating a storage snapshot according to the context information and storing the storage snapshot into a nonvolatile memory; the storage snapshot is used to perform stack trace back of the processor.
Optionally, before mapping the context information of all the processor cores to the target address space, the method further includes:
and if the heartbeat count of the target processor core is detected to be unchanged beyond the set time length, determining that the target processor core is in the hanging state.
Wherein after the determining that the target processor core is in the hung state, further comprises:
determining location information of the target processor core;
the mapping of the context information of all processor cores to the target address space includes:
determining a processor core in an active state according to the position information;
the context information of the target processor core is mapped to the target address space by any of the active processor cores.
Optionally, a hardware control logic module is arranged; after the determining that the target processor core is in the hung state, further comprising:
determining location information of the target processor core;
the mapping of the context information of all processor cores to the target address space includes:
determining a processor core in an active state according to the position information;
and taking over the hardware control logic module by any processor core in an active state to realize the mapping of the context information of the target processor core to the target address space.
Optionally, if the context information includes register context information, the mapping the context information of all processor cores to the target address space includes:
mapping register context information for all processor cores to a register address space;
if the context information comprises register context information and memory context information; the mapping of the context information of all processor cores to the target address space includes:
register context information of all processor cores is mapped to a register address space, and memory context information of processor cores including private memory is mapped to a memory address space.
Optionally, mapping the memory context information of the processor core including the private memory to the memory address space includes:
setting a remapping shared memory area according to the address space of the private memory;
and remapping the memory context information of the private memory to the remapped shared memory area.
Optionally, after generating the storage snapshot according to the context information and saving the storage snapshot to the nonvolatile memory, the method further includes:
analyzing the storage snapshot, and acquiring the execution direction of the program counting registers of all the processor cores and the stack direction conditions of the stack pointer registers;
and carrying out stack backtracking and memory analysis of all the processor cores according to the execution direction and the stack direction conditions so as to locate the abnormal processor core.
The application also provides a backtracking system of the multi-core processor, which comprises:
the information mapping module is used for mapping the context information of all the processor cores to a target address space if the processor cores in the hanging state are detected;
the information storage module is used for generating a storage snapshot according to the context information and storing the storage snapshot into a nonvolatile memory; the storage snapshot is used to perform stack trace back of the processor.
The present application also provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method as described above.
The application also provides an electronic device comprising a memory in which a computer program is stored and a processor which when calling the computer program in the memory implements the steps of the method as described above.
The application provides a backtracking method of a multi-core processor, which comprises the following specific technical scheme: if the processor cores in the hanging state are detected, mapping the context information of all the processor cores to a target address space; generating a storage snapshot according to the context information and storing the storage snapshot into a nonvolatile memory; the storage snapshot is used to perform stack trace back of the processor.
When the processor core is in a hanging state, the context information of the processor core is mapped to a target address space, so that a storage snapshot is generated, and trace back and memory analysis of the processor core are carried out according to the storage snapshot to determine an abnormal processor core. When context information is mapped, the register context information is used to perform stack trace back of the processor. The method and the device can save the context information of the processor core in any scene, and avoid influencing the reading and the brushing of the context information when the interrupt priority is lower. On the basis, the method and the device can also support the storage of the memory execution context state of each processor core in the scene that the processor is provided with the private memory, reduce the occupation of logic resources and reduce the cost.
The application further provides a backtracking system, a storage medium and electronic equipment of the multi-core processor, which have the beneficial effects and are not repeated here.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings may be obtained according to the provided drawings without inventive effort to a person skilled in the art.
FIG. 1 is a flowchart of a backtracking method of a first multi-core processor according to an embodiment of the present application;
FIG. 2 is a flowchart of a trace-back method of a second multi-core processor according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of mapping internal resources of a multi-core processor according to an embodiment of the present disclosure;
FIG. 4 is a flowchart of a trace-back method of a third multi-core processor according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram illustrating a backtracking procedure of a multi-core processor according to an embodiment of the present disclosure;
FIG. 6 is a flowchart of a trace-back method of a fourth multi-core processor according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram of a trace-back system of a multi-core processor according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Referring to fig. 1, fig. 1 is a flowchart of a backtracking method of a multi-core processor according to an embodiment of the present application, where the method includes:
s101: if the processor cores in the hanging state are detected, mapping the context information of all the processor cores to a target address space;
s102: generating a storage snapshot according to the context information and storing the storage snapshot into a nonvolatile memory; the storage snapshot is used to perform stack trace back of the processor.
The embodiments of the present application are not limited as to how to detect whether a processor core is in a hung state. In one possible approach, it may be detected whether the processor core is in a hung state based on a heartbeat mechanism. Generally, each processor core is responsible for updating its own heartbeat count and checking for heartbeat count changes of other cores to determine whether any processor core is stuck in the current multi-core system.
After confirming that the processor cores are in the hanging state, mapping the context information of all the processor cores to a target address space, wherein the context information is mainly register context information, and for part of the processor cores with private memories, the memory context information can be contained. The target address space may be set by a person skilled in the art, and is not limited herein, and may be disposed in a memory on a main board of the processor system, for example, the memory may be an off-chip cache chip on a solid state disk. It should be noted that, in this embodiment, after the processor cores are in the hanging state, the states of the processor cores are not distinguished, and context information of all the processor cores is mapped to the target address space in a unified manner.
The present embodiment is not limited in how context information of all processor cores is mapped to the target address space.
Referring to fig. 2, fig. 2 is a flowchart of a backtracking method of a second multi-core processor according to an embodiment of the present application, which includes the following steps:
after determining that the target processor core is in the hanging state, determining the position information of the target processor core, determining the processor core in the active state according to the position information, and finally mapping the context information of the target processor core into a target address space by any one of the processor cores in the active state. It should be noted that the target processor core may be a processor core in a suspended state, or may be all processor cores, that is, a processor core including a processor in a suspended state and a processor core in an active state. The processor cores except the position information are in an active state, and the active processor cores are different from the processor cores in the hanging state, namely the processor cores still updating the heartbeat count. That is, the processor in any active state maps the context information of the processor cores in the suspended state to the target address space, and the other processor cores in the active state can perform the mapping of the self-context information by themselves. The location information is used to determine the location of the processor core in the suspended state, and may be information that may be used to indicate the location, such as a name, an identifier, etc. of the processor core in the suspended state, so as to directly process the context information of the processor core in the suspended state.
No matter what mapping mode is adopted, as long as the context information of all the processor cores can be mapped to the target address space, the technical effect of the embodiment is not affected.
After the context information of all the processor cores is mapped to the target address space, a storage snapshot can be generated according to the context information and stored in the nonvolatile memory. The nonvolatile memory to be used is not limited and may be set by one skilled in the art. The formed memory snapshot may be used to obtain the execution direction of the PC registers and the stack direction of the SP registers for all processor cores. The PC register is a program counter in the ARM for storing the address of the next instruction to be executed. During program execution, the value of the PC register will change continuously, pointing to the address of the next instruction to be executed. When the program is executed, the value of the PC register points to the end address of the program. The SP register is a stack pointer register in the ARM for storing the address of the current stack top. During program execution, the stack is an important data structure for storing temporary variables, function call return addresses and other data, and the value of the SP register changes along with the change of the stack. Thus, the exception processor core can be located by storing the exception trace back of the snapshot execution processor core.
In other embodiments of the present application, when the context information of the processor is specifically mapped, different mapping manners may be adopted according to the specific content of the context information:
if the context information includes register context information, mapping the register context information of all processor cores to a register address space;
if the context information includes register context information and memory context information, mapping the register context information of all processor cores to a register address space, and mapping the memory context information of the processor cores including the private memory to a memory address space.
When the processor cores are in the hanging state, the embodiment of the application maps the context information of all the processor cores to the target address space, so that the storage snapshot is generated, and the backtracking and the memory analysis of the processor cores are carried out according to the storage snapshot to determine the abnormal processor cores. In mapping context information, register context information in the context information is used to perform stack trace back of the processor. The method and the device can save the context information of the processor core in any scene, and avoid influencing the reading and the brushing of the context information when the interrupt priority is lower. On the basis, the method and the device can also support the storage of the memory execution context state of each processor core in the scene that the processor is provided with the private memory, reduce the occupation of logic resources and reduce the cost.
It can be seen that, the context information at least includes register context information, and part of the processor cores include private memories, so that in order to ensure the trace-back effect of the subsequent process, for the processor cores including the private memories in the suspended state, the corresponding memory context information is also required to be directly mapped to the memory address space.
In order to better demonstrate the mapping process of the context information, refer to fig. 3, fig. 3 is a schematic diagram of mapping internal resources of a multi-Core processor provided in the embodiment of the present application, in fig. 3, core0 and Core1 … … Core N respectively represent processor Core0 and processor Core1 … … processor Core N, cpu reg context is register context information of a corresponding processor Core, CPU Registers Address Space is a processor register address space as one of target address spaces, CPU Memory Address Space is a processor memory address space as one of target address spaces, cpu reg bank is a register bank of a processor, and Inner Mem is a private memory of the processor Core, where the processor cores shown in fig. 3 all include the private memory, and in practical application, there is a situation that the processor Core does not include the private memory. For private memory, it is mapped to the memory address space of the processor. In both the processor register address space and the processor memory address space, mapped addresses of context information in each processor core, i.e., register addresses and memory addresses, are recorded.
On the basis of the above embodiments, since the previous embodiment performs all mapping on the context information of the processor cores, it is easy to think that the larger the processor cores, the larger the data amount of the mapping required, the more resources are required for mapping, i.e. the more gates are required, the greater the cost and power consumption thereof will be.
In order to reduce the cost and power consumption required by the mapping process, since the operating environment of each processor core is composed of its respective register context and a section of memory space associated therewith, the memory space is within which code and data are executed. While the processor system typically includes execution logic, control logic, state-related logic, and the like, to effect management of the processor system.
As a more preferred implementation manner, referring to fig. 4, fig. 4 is a flowchart of a backtracking method of a third multi-core processor provided in the embodiment of the present application, and the process includes:
s401: after determining that the target processor core is in the hanging state, determining the position information of the target processor core;
s402: determining a processor core in an active state according to the position information;
s403: taking over, by any of the processor cores in an active state, a hardware control logic module, mapping context information of the processor core in a suspended state to the target address space;
s404: generating a storage snapshot according to the context information and storing the storage snapshot into a nonvolatile memory; the storage snapshot is used to perform stack trace back of the processor.
In this embodiment, a hardware control logic module may be set, after determining that the target processor core is in a hanging state, determining location information of the target processor core, determining a processor core in an active state according to the location information, and then taking over the hardware control logic module by any one of the processor cores in the active state to implement mapping from context information of the target processor core to a target address space. The target processor core may be only the processor core in the suspended state, or may be all the processor cores.
The hardware control logic may be a multiplexer or decoder or the like for controlling the context information of the processor core to perform the mapping. This ensures that context information for the processor core in the suspended state can be obtained in any scenario, while reducing the resources that are occupied in mapping the context information. The hardware control logic module is mainly used for mapping the context information of the processor core in the hanging state to the target address space. For the remaining active processor cores, the context information of the active processor cores can be mapped to the target address space in the same manner as the hardware control logic module, or the context information of each active processor core can be automatically mapped to the target address space.
Here, it is not limited how to determine the processor core in the active state, and the location information of the target processor core may be determined first, and then the processor core in the active state may be determined according to the location information.
In this embodiment, the target address space is divided into a register address space and a memory address space, which are used to store the register context information and the memory context information of the processor core in the suspended state, respectively.
After any processor core in an active state takes over the hardware control logic module, the hardware control logic module is utilized to map the register context of the processor core in a hanging state to a register group, and the register context is transferred to a global memory area. Similarly, if there are multiple processor cores in the suspended state, the register context information of the suspended processor cores can be mapped to the register group in sequence, then stored to the global memory, and after all the register context information of the processors are stored to the global memory, the register context information is uniformly brushed to the nonvolatile memory, so that the register bank mechanism is realized. The register set is a place in the processor for temporarily storing data, and is used for storing data to be processed or processed data, and the time for the processor to access the data in the register set is shorter than the time for accessing the memory.
Therefore, the embodiment realizes unified mapping of the context information by using the hardware logic control module, thereby greatly reducing the resource occupation during the mapping and storage of the context information and reducing the cost. For processor cores that do not contain private memory, when they are in the suspended state, any processor core in the active state may take over the hardware logic control module to map the context information of all processor cores in the suspended state. For a processor core including a private memory, when mapping a register context, a hardware control logic module may be utilized to remap memory context information of the private memory to a remapped shared memory area, where the process is typically performed by the processor core in the same active state. The mapping process of the register context information and the memory context information does not conflict with each other, and the mapping process can be executed successively or synchronously.
Referring to fig. 5, fig. 5 is a schematic diagram of a trace-back process of the multi-Core processor provided in the embodiment of the present application, in fig. 5, core0 and Core1 … … Core N respectively represent processor Core0 and processor Core1 … … processor Core N, and cpu reg context is register context information of the corresponding processor Core, cpu Reg BankControl refers to a register set control module, which may be regarded as the above-mentioned hardware logic control module, busMatrix is a bus matrix, and cpu reg bank is a register set (register bank) of the processor. As can be seen from FIG. 5, when any processor core is on hold, the hardware control logic module may be taken over by the processor core in any of the active states to control the register set to map the register context of the processor core in the on hold state to the register set. When a plurality of processor cores are hung, the register context of the hung processor cores is mapped to a register group cpu reg bank below in fig. 5 in sequence, then the register group cpu reg bank is transferred to a global memory area, and finally the register context is uniformly brushed to a nonvolatile memory.
If the processor core includes a private memory, the hardware control logic module may also be used to map the memory context information of the processor core in the suspended state to the memory address space. Similarly, if there are multiple processor cores in the suspended state, the memory context information of the suspended processor cores can be mapped to the remapped shared memory area in sequence and then stored to the global memory, so that the memory bank mechanism is realized.
Specifically, when the memory context information of the private memory is stored, the remapped shared memory area may be set according to the address space of the private memory, and then the memory context information of the private memory may be remapped to the remapped shared memory area. Here, it is not limited how to implement the remapping of the private memory, and the private memory of the processor core in the suspended state may be remapped into the remapped shared memory area through the MUX selector.
In addition, since the more mapping resources are required when more processor cores are present, the more gates are required when the circuit design is implemented, the cost and power consumption will increase. At the same time, with the full mapping mechanism, the resources of each processor core will map onto different address spaces, which results in an asymmetric view of the address space of each processor core.
In order to solve the problem, in the processor, a remapping shared memory area and a global memory area are respectively constructed, and respective symmetrical address spaces of the remapping shared memory area and the global memory area can be set according to the private memory address space of the processor core so as to realize the address space symmetry of each processor core. If the register space of the BANK is the register space of 0 xMMMM-0 xNNNN of all cores, the register environments of different processor cores can be switched only by changing the BANK control register value. If the address space of the remapping shared memory area is set to be the memory address space of 0 xSSSS-0 xTTTT of all the processor cores, the private memory space of different processor cores can be mapped only by controlling the remapping shared memory area. It can be seen that the address space of all processor cores is relatively consistent. Assuming that the address of the private memory in each processor core is set to 0x0000-0x8000, the address of the remapped shared memory is set to 0x10000-0x18000, and the address of the global shared memory is set to start from 0x 50000. Through the bank mechanism, the addresses accessed are the same from the perspective of each processor core.
Referring to fig. 6, fig. 6 is a flowchart of a backtracking method of a fourth multi-core processor according to an embodiment of the present application, which may include the following steps:
s601: when detecting that the heartbeat count of the target processor core exceeds a set time period and is unchanged, determining that the target processor core is in a hanging state;
s602: if the processor cores in the hanging state are detected, mapping the context information of all the processor cores to a target address space;
s603: generating a storage snapshot according to the context information and storing the storage snapshot into a nonvolatile memory; the storage snapshot is used to perform stack trace back of the processor.
In this embodiment, if it is detected that the heartbeat count of the target processor core exceeds the set duration and is unchanged, it is determined that the target processor core is in a hanging state, and at this time, the location information of the target processor core may also be determined. The embodiment further describes how to detect whether the processor core is in a hanging state, ensures that the running state of the processor core can be accurately detected, ensures that the processor can trace back in time when the processor core is hung, and reduces adverse effects caused by the hanging of the processor core. This embodiment can be combined with the above embodiments to form a new embodiment, and a description thereof will not be repeated here.
Based on the above embodiments, in one possible implementation manner, after the storage snapshot is generated, the storage snapshot may be parsed, the execution direction of the program count registers and the stack direction of the stack pointer registers of all the processor cores are obtained, and then the stack trace back and the memory parsing of all the processor cores are performed according to the execution direction and the stack direction conditions, so as to locate the abnormal processor core. The user can locate the abnormal processor core in the processor according to the generated storage snapshot, so that the abnormal can be quickly located, and the fault processing efficiency is improved.
The following describes a trace-back system of a multi-core processor provided in the embodiments of the present application, where the trace-back system described below and the trace-back method of the multi-core processor described above may be referred to correspondingly with each other.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a trace-back system of a multi-core processor provided in an embodiment of the present application, and the present application further provides a trace-back system of a multi-core processor, where the specific scheme is as follows:
the information mapping module is used for mapping the context information of all the processor cores to a target address space if the processor cores in the hanging state are detected;
the information storage module is used for generating a storage snapshot according to the context information and storing the storage snapshot into a nonvolatile memory; the storage snapshot is used to perform stack trace back of the processor.
Based on the above embodiment, as a preferred embodiment, further comprising:
and the hanging detection module is used for determining that the target processor core is in the hanging state if the heartbeat count of the target processor core is detected to be unchanged beyond the set duration.
Based on the above embodiment, as a preferred embodiment, further comprising:
a location information determining module configured to determine location information of the target processor core;
correspondingly, the information mapping module comprises:
a first information mapping unit, configured to determine a processor core in an active state according to the location information; the context information of the target processor core is mapped to the target address space by any of the active processor cores.
Based on the above embodiment, as a preferred embodiment, further comprising:
the control logic setting module is used for setting a hardware control logic module;
a location information determining module for determining location information of the target processor core
Correspondingly, the information mapping module comprises:
a second information mapping unit, configured to determine a processor core in an active state according to the location information; and taking over the hardware control logic module by any processor core in an active state to realize the mapping of the context information of the target processor core to the target address space.
Based on the above embodiment, as a preferred embodiment, if the context information includes register context information, the information mapping module includes:
a first mapping unit for mapping register context information of all processor cores to a register address space;
if the context information includes register context and memory context information, the information mapping module includes:
and the second mapping unit is used for mapping the register context information of all the processor cores to a register address space, and mapping the target address space comprising the register address space and/or the memory context information of the processor cores containing the private memory to or to a memory address space.
Based on the above embodiments, as a preferred embodiment, the second mapping unit includes:
the remapping unit is used for setting a remapping shared memory area according to the address space of the private memory; and remapping the private memory to a remapped shared memory area.
Based on the above embodiment, as a preferred embodiment, further comprising:
the backtracking module is used for analyzing the storage snapshot and acquiring the execution direction of the program counting registers of all the processor cores and the stack direction condition of the stack pointer register; and carrying out stack backtracking and memory analysis of all the processor cores according to the execution direction and the stack direction conditions, and positioning the abnormal processor cores.
The present application also provides a computer-readable storage medium having stored thereon a computer program which, when executed, implements the steps provided by the above embodiments. The storage medium may include: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a Flash, a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The application also provides an electronic device, which may include a memory and a processor, where the memory stores a computer program, and the processor may implement the steps provided in the foregoing embodiments when calling the computer program in the memory. Of course the electronic device may also include various network interfaces, power supplies, etc. Specific forms of the electronic device include, but are not limited to, a computer, a mobile terminal, a portable mobile storage device, a solid state disk, and the like.
In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. The system provided by the embodiment is relatively simple to describe as it corresponds to the method provided by the embodiment, and the relevant points are referred to in the description of the method section.
Specific examples are set forth herein to illustrate the principles and embodiments of the present application, and the description of the examples above is only intended to assist in understanding the methods of the present application and their core ideas. It should be noted that it would be obvious to those skilled in the art that various improvements and modifications can be made to the present application without departing from the principles of the present application, and such improvements and modifications fall within the scope of the claims of the present application.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Claims (10)

1. A trace-back method for a multi-core processor, comprising:
if the processor cores in the hanging state are detected, mapping the context information of all the processor cores to a target address space;
generating a storage snapshot according to the context information and storing the storage snapshot into a nonvolatile memory; the storage snapshot is used to perform stack trace back of the processor.
2. The backtracking method of claim 1, wherein before mapping context information for all processor cores to the target address space, further comprising:
and if the heartbeat count of the target processor core is detected to be unchanged beyond the set time length, determining that the target processor core is in the hanging state.
3. The backtracking method of claim 2, wherein after the determining that the target processor core is in the lived state, further comprising:
determining location information of the target processor core;
the mapping of the context information of all processor cores to the target address space includes:
determining a processor core in an active state according to the position information;
the context information of the target processor core is mapped to the target address space by any of the active processor cores.
4. The backtracking method of claim 2, wherein a hardware control logic module is provided; after the determining that the target processor core is in the hung state, further comprising:
determining location information of the target processor core;
the mapping of the context information of all processor cores to the target address space includes:
determining a processor core in an active state according to the position information;
and taking over the hardware control logic module by any processor core in an active state to realize the mapping of the context information of the target processor core to the target address space.
5. The backtracking method of claim 1, wherein if the context information includes register context information, the mapping the context information of all processor cores to a target address space includes:
mapping register context information for all processor cores to a register address space;
if the context information comprises register context information and memory context information; the mapping of the context information of all processor cores to the target address space includes:
register context information of all processor cores is mapped to a register address space, and memory context information of processor cores including private memory is mapped to a memory address space.
6. The backtracking method of claim 5, wherein mapping memory context information of a processor core including private memory to a memory address space comprises:
setting a remapping shared memory area according to the address space of the private memory;
and remapping the memory context information of the private memory to the remapped shared memory area.
7. The backtracking method of any of claims 1-6, further comprising, after generating a storage snapshot based on the context information and saving the storage snapshot to a non-volatile memory:
analyzing the storage snapshot, and acquiring the execution direction of the program counting registers of all the processor cores and the stack direction conditions of the stack pointer registers;
and carrying out stack backtracking and memory analysis of all the processor cores according to the execution direction and the stack direction conditions so as to locate the abnormal processor core.
8. A trace-back system for a multi-core processor, comprising:
the information mapping module is used for mapping the context information of all the processor cores to a target address space if the processor cores in the hanging state are detected;
the information storage module is used for generating a storage snapshot according to the context information and storing the storage snapshot into a nonvolatile memory; the storage snapshot is used to perform stack trace back of the processor.
9. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the backtracking method of a multicore processor according to any of claims 1-7.
10. An electronic device comprising a memory and a processor, the memory having a computer program stored therein, the processor implementing the steps of the trace-back method of the multi-core processor of any one of claims 1-7 when the computer program in the memory is invoked by the processor.
CN202311526721.1A 2023-11-15 2023-11-15 Backtracking method and system of multi-core processor, storage medium and electronic equipment Pending CN117493011A (en)

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