CN117492844B

CN117492844B - Register renaming method, device and storage medium

Info

Publication number: CN117492844B
Application number: CN202311844258.5A
Authority: CN
Inventors: 郇丹丹; 李祖松
Original assignee: Beijing Micro Core Technology Co ltd
Current assignee: Beijing Micro Core Technology Co ltd
Priority date: 2023-12-29
Filing date: 2023-12-29
Publication date: 2024-03-29
Anticipated expiration: 2043-12-29
Also published as: CN117492844A

Abstract

The invention provides a register renaming method, a register renaming device and a storage medium, and relates to the technical field of data processing. The method comprises the following steps: identifying a target instruction of a register, and determining a logic register related to the target instruction, wherein the logic register comprises a logic source register and a logic destination register; querying a renaming table in any period based on the number of the logic source register to determine a first physical register corresponding to the logic source register; based on the number of the logic destination register, searching an idle register number table in any period to determine a second physical register corresponding to the logic destination register, wherein the idle register number table is used for recording the number and the corresponding state of the idle register; the second physical register is renamed to the first physical register. The performance and the main frequency of the out-of-order processor are improved, and the power consumption and the area of the out-of-order processor are reduced.

Description

Register renaming method, device and storage medium

Technical Field

The present invention relates to the field of data processing technologies, and in particular, to a register renaming method, a device and a storage medium.

Background

The processor execution mode is divided into two types, sequential execution and out-of-order execution. The sequentially executed processors are generally used for low-power-consumption processors, and are affected by Read After Write (RAW) conflicts, so that a certain resource waste is caused, and in order to avoid waiting caused by sequential execution, the execution efficiency of the processors is improved through out-of-order execution.

However, for out-of-order processors, a false correlation of Write After Read (WAR) and Write After Write (Write After Write, WAW) may occur, resulting in either a Read-to-error data of the predecessor instruction or a later Write-back of the predecessor instruction, resulting in an error in the end result. In order to avoid errors in out-of-order execution, elimination of inter-instruction dependencies is achieved by renaming the logical registers.

Because the register renaming needs to be subjected to correlation check, renaming list item allocation and the like, the conventional register renaming method generally needs to be completed in a single period from the aspect of performance, the clock frequency of a processor is greatly influenced, and the record maintenance of the renaming relation also has a great influence on the power consumption and the area of the processor.

Disclosure of Invention

The present invention aims to solve at least one of the technical problems in the related art to some extent.

Therefore, a first object of the present invention is to propose a register renaming method to achieve performance improvement of an out-of-order processor.

A second object of the present invention is to propose a register renaming device.

A third object of the present invention is to propose another register renaming device.

A fourth object of the present invention is to propose an electronic device.

A fifth object of the present invention is to propose a non-transitory computer readable storage medium.

A sixth object of the invention is to propose a computer programme product.

To achieve the above object, an embodiment of a first aspect of the present invention provides a register renaming method, including:

identifying a target instruction of a register, and determining a logic register related to the target instruction, wherein the logic register comprises a logic source register and a logic destination register;

querying a renaming table in any period based on the number of the logic source register to determine a first physical register corresponding to the logic source register, wherein the renaming table is used for maintaining a mapping relation between the logic source register and the first physical register;

Based on the number of the logic destination register, searching an idle register number table in any period to determine a second physical register corresponding to the logic destination register, wherein the idle register number table is used for recording the number and the corresponding state of the idle register;

the second physical register is renamed to the first physical register.

To achieve the above object, an embodiment of a second aspect of the present invention provides a register renaming apparatus, including:

the device comprises an identification module, a logic register and a logic register, wherein the identification module is used for identifying a target instruction of a register and determining a logic register related to the target instruction, and the logic register comprises a logic source register and a logic destination register;

the first query module is used for querying a renaming table in any period based on the number of the logic source register to determine a first physical register corresponding to the logic source register, wherein the renaming table is used for maintaining the mapping relation between the logic source register and the first physical register;

the second query module is used for querying an idle register numbering table in any period based on the number of the logic destination register so as to determine a second physical register corresponding to the logic destination register, wherein the idle register numbering table is used for recording the number and the corresponding state of the idle register;

And the renaming module is used for renaming the second physical register into the first physical register.

To achieve the above object, an embodiment of a third aspect of the present invention provides another register renaming apparatus, including a memory, a transceiver, and a processor:

a memory for storing a computer program; a transceiver for transceiving data under control of the processor; a processor for reading the computer program in the memory and performing the following operations:

The second physical register is renamed to the first physical register.

To achieve the above object, an embodiment of a fourth aspect of the present invention provides an electronic device, including: a processor; a memory for storing executable instructions of the processor; wherein the processor is configured to execute the instruction to implement a register renaming method as proposed by the embodiment of the first aspect of the present invention.

To achieve the above object, an embodiment of a fifth aspect of the present invention proposes a computer readable storage medium, which when executed by a processor of an electronic device, enables the electronic device to perform a register renaming method as proposed by the embodiment of the first aspect of the present invention.

To achieve the above object, an embodiment of a sixth aspect of the present invention provides a computer program product, which when executed by an instruction processor in the computer program product, performs a register renaming method according to the embodiment of the first aspect of the present invention.

The invention at least has the following beneficial effects:

the invention identifies a target instruction of a register and determines a logic register related to the target instruction, wherein the logic register comprises a logic source register and a logic destination register; querying a renaming table in any period based on the number of the logic source register to determine a first physical register corresponding to the logic source register, wherein the renaming table is used for maintaining the mapping relation between the logic source register and the first physical register; based on the number of the logic destination register, searching an idle register number table in any period to determine a second physical register corresponding to the logic destination register, wherein the idle register number table is used for recording the number and the corresponding state of the idle register; the second physical register is renamed to the first physical register. Based on the renaming table and the idle register numbering table, renaming from the logic register to the physical register related to the target instruction is realized, and only the renaming table and the idle register numbering table are maintained, so that the performance and the main frequency of the out-of-order processor are improved, and the power consumption and the area of the out-of-order processor are reduced.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The foregoing and/or additional aspects and advantages of the invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a flowchart illustrating a register renaming method according to an embodiment of the invention;

FIG. 2 is a flowchart illustrating another register renaming method according to an embodiment of the invention;

FIG. 3 is a diagram illustrating an idle register numbering table according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a register renaming apparatus according to an embodiment of the invention.

Detailed Description

Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.

The register renaming method and device according to the embodiment of the invention are described below with reference to the accompanying drawings.

Fig. 1 is a flowchart of a register renaming method according to an embodiment of the invention.

In an out-of-order processor, decoded instructions are first register renamed (Register Renaming) and allocated to different Dispatch queues according to the type of operation. Register renaming is a key technique for out-of-order execution in an out-of-order processor dynamic pipeline. The out-of-order processor achieves elimination of dependencies among instructions by renaming logical registers. Register renaming techniques eliminate register read-write correlations (WARs) and write-write correlations (WAWs) between instructions, increase the number of instructions that an out-of-order processor can schedule in parallel, and accomplish out-of-order scheduling, and ensure field accuracy when an exception occurs to instruction execution or an instruction speculation error is transferred to cancel a subsequent instruction.

Register renaming needs to be checked in a correlation manner, renaming entries are allocated, and the like, and generally needs to be completed in a single cycle from the aspect of performance, so that the clock frequency of a processor is greatly influenced by register renaming, and the power consumption and the area of the processor are also greatly influenced by record maintenance of a renaming relation.

In view of this problem, an embodiment of the present invention provides a register renaming method to achieve performance improvement of an out-of-order processor, as shown in fig. 1, the method includes the following steps:

step 101, identifying a target instruction of a register, and determining a logic register related to the target instruction, wherein the logic register comprises a logic source register and a logic destination register.

In the embodiment of the present invention, the target instruction is a register Move instruction (Move) of the processor, which is a data transfer instruction for transferring data in one register to another register, and the Move instruction actually does not need to be calculated, but causes data dependency and delay.

Optionally, in the case that the data transfer instruction of the register performs instruction execution, a target instruction, that is, a Move instruction, in the data transfer instruction is identified. The execution in the Move instruction is that the data of the source register (rs) is copied into the destination register (rd), the corresponding instruction comprises the identifiers of the source register (rs) and the destination register, namely, under the condition of acquiring the Move instruction, the corresponding source register and the destination register can be determined, in the embodiment of the invention, the logical register is renamed into the physical register, so that the logical register corresponding to the Move instruction is firstly determined, and the logical register comprises the logical source register and the logical destination register.

Step 102, based on the number of the logic source register, a renaming table is queried in any period to determine a first physical register corresponding to the logic source register, wherein the renaming table is used for maintaining a mapping relationship between the logic source register and the first physical register.

Optionally, the renaming table includes a correspondence between the logical source register and the first physical register, and in the case of determining the number of the logical source register, the corresponding first physical register can be determined by looking up the renaming table.

In the embodiment of the invention, for any period, the update of read data is performed on any period based on the write data of the corresponding previous period, so that the update of the renaming table is realized.

Step 103, based on the number of the logic destination register, querying an idle register number table in any period to determine a second physical register corresponding to the logic destination register, wherein the idle register number table is used for recording the number and the corresponding state of the idle register.

Optionally, the free register number table includes the number and the corresponding state of the free register, and in the case of determining the number of the logical destination register, the corresponding available second physical register can be determined by looking up the free register number table.

Alternatively, in the case of renaming a logical source register, if a logical destination register is also present, a second physical register in an idle state needs to be assigned to the logical destination register.

In the embodiment of the present invention, the second physical register in the idle state needs to be read from the idle register number table, and the number of available second physical registers that can be given in the idle register number table is fixed, and in the case that the second physical register is used, the second physical register needs to be released through the retired instruction, so as to obtain the idle second physical register for reuse.

Step 104 renaming the second physical register to the first physical register.

Optionally, under the condition that the register renaming checks that the data transmission instruction transmitted from the decoding is the target instruction, renaming the second physical register related to the target instruction as the first physical register, namely directly renaming the second physical register corresponding to the logic target register in the target instruction as the first physical register corresponding to the logic source register, thereby reducing the renaming process flow and reducing the power consumption and the area of the out-of-order processor.

In this embodiment, a target instruction of a register is identified, and a logic register related to the target instruction is determined, where the logic register includes a logic source register and a logic destination register; querying a renaming table in any period based on the number of the logic source register to determine a first physical register corresponding to the logic source register, wherein the renaming table is used for maintaining the mapping relation between the logic source register and the first physical register; based on the number of the logic destination register, searching an idle register number table in any period to determine a second physical register corresponding to the logic destination register, wherein the idle register number table is used for recording the number and the corresponding state of the idle register; the second physical register is renamed to the first physical register. Based on the renaming table and the idle register numbering table, renaming from the logic register to the physical register related to the target instruction is realized, and only the renaming table and the idle register numbering table are maintained, so that the performance and the main frequency of the out-of-order processor are improved, and the power consumption and the area of the out-of-order processor are reduced.

In order to clearly illustrate the above embodiment, another register renaming method is provided in this embodiment, and fig. 2 is a flowchart of another register renaming method provided in this embodiment of the invention.

As shown in fig. 2, the method may include the steps of:

in step 201, an instruction execution identification target instruction is executed based on a data transfer instruction of a register.

In the embodiment of the invention, the target instruction is a register Move instruction (Move) of the processor, and in a RISC-V (Reduced Instruction Set Computer-Five, fifth generation reduced instruction set) instruction manual, an instruction set architecture (Instruction Set Architecture, ISA) instruction corresponding to the Move pseudo instruction is addi rd, rs, 0. The Move instruction performs copying the data of the source register (rs) into the destination register (rd).

In response to fetching and decoding the data transfer instruction from the instruction cache, marking a target instruction in the data transfer instruction.

In the embodiment of the invention, a data transmission instruction is taken out from an instruction cache, sent to a decoding unit for decoding (Decode), and meanwhile, the Move instruction is identified based on an ISA instruction corresponding to the Move pseudo instruction, and the identified Move instruction is marked, namely, each addi rd, rs, 0 is added with a tag of ismove=true.

In step 202, a logical register associated with a target instruction is determined, wherein the logical register includes a logical source register and a logical destination register.

The Move instruction includes the identifiers of the source register and the destination register, that is, the corresponding source register and destination register can be determined when the Move instruction is acquired.

Taking all 5 instructions processed in one cycle as Move instructions, there is data dependence such as WAW/RAW between them as an example.

0addi r2, r1, 0 // r1 ->r2

1addi r4, r3, 0 // r3 ->r4

2addi r5, r4, 0 // r4 ->r5

3addi r5, r1, 0 // r1 ->r5

4addi r1, r5, 0 // r5 ->r1

Then for the 0 th Move instruction, the corresponding logical source register is r1, and the corresponding logical destination register is r2; for the 1 st Move instruction, the corresponding logic source register is r3, and the corresponding logic destination register is r4; for the 2 nd Move instruction, the corresponding logic source register is r4, and the corresponding logic destination register is r5; for the 3 rd Move instruction, the corresponding logic source register is r1, and the corresponding logic destination register is r5; for the 4 th Move instruction, the corresponding logical source register is r5, and the corresponding logical destination register is r1.

Step 203, based on the number of the logical source registers, a renaming table is queried in any period to determine a first physical register corresponding to the logical source registers, wherein the renaming table is used for maintaining a mapping relationship between the logical source registers and the first physical registers.

In the embodiment of the present invention, the number of the logical register numbers is 32, and the renaming table includes 32 registers with a width of the first physical register numbers (i.e. physical register file addresses), for example, 384 first physical registers, where the first physical register numbers are 9 bits, and each represents the first physical register numbers corresponding to the 32 logical registers. The rename table records the most recently allocated first physical register number for each logical register.

Optionally, the first physical register includes a fixed point physical register and a floating point physical register, and the renaming table includes a first renaming table corresponding to the fixed point physical register and a second renaming table corresponding to the floating point physical register. That is, for the case where the fixed point physical register file and the floating point physical register file are separate, the fixed point physical register and the floating point register each have a set of rename tables.

Further, depending on the instruction extension, the renaming table may record more contents (e.g., renaming states of a condition register file, a vector register file, etc.).

Optionally, the renaming table includes a set of read ports and a set of write ports, wherein the read ports are used for outputting renaming table read data and the write ports are used for updating the renaming table.

The read port is a group of synchronous read interfaces, when the read port is used, history renaming list read data of the previous period of any period are read, wherein the history renaming list read data comprise history read addresses and history keeping signals, the history read addresses are determined through logic register assignment of target instructions, and the history keeping signals are determined according to blocking conditions of corresponding pipeline stages.

The read address is assigned in the decoding stage, and the hold signal is assigned according to the blocking condition of the corresponding pipeline stage.

For example, in the t+1 cycle, the corresponding rename table read data (history read address and history hold signal) is output correspondingly according to the history rename table read data of the T cycle.

Optionally, the historical read address is updated based on the value of the historical holding signal to obtain the target read address in any period.

Responding to the history keeping signal as a preset value, and taking the history read address as a target read address; and in response to the history holding signal not being a preset value, updating the history read address to the latest read address as the target read address.

As a possible implementation manner, the history holding signal is a preset value, for example, 1, so that the read data will remain unchanged, and the history read address is taken as the target read address; otherwise the read data will be updated according to the latest read address.

Optionally, determining a target holding signal according to the blocking condition of the corresponding flow level of any period; the rename table read data is composed of a target read address and a target hold signal.

Further, the mapping relation corresponding to renaming is updated to the renaming table.

In the embodiment of the invention, the write port is a group of write interfaces, and according to the renaming or Reorder Buffer (ROB) rollback state, updating of the renaming table is completed according to the renaming information of the new instruction and the rollback information of the ROB. For example, write data for the T cycle may be updated to read data for the T+1 cycle.

An entry instruction requires processing of both the source and destination registers when performing register renaming. For the logic source register, searching the renaming table based on the number of the logic source register, and determining the corresponding first physical register number.

Step 204, based on the number of the logical destination register, a free register number table is queried in any period to determine a second physical register corresponding to the logical destination register, wherein the free register number table is used for recording the number and the corresponding state of the free register.

Optionally, in the case where there is a logical source register in the target instruction, there is also a logical destination register, for which a second physical register in an idle state needs to be specified.

In the embodiment of the present invention, a free register number table (FreeList) is a queue, and is composed of an allocation Pointer (Tail Pointer), a release Pointer (Head Pointer), and a queue store. The numbers of all physical registers in the idle state are stored in the idle register number table.

The number of bits in each entry of the free register number table is the width of the second physical register number (i.e., the physical register file address), e.g., 384 second physical registers, and the second physical register number is 9 bits. As shown in fig. 3, the state of the second physical register is recorded (e.g., 0 indicates invalid, 1 indicates valid), whether the record is allocated (e.g., 0 indicates unallocated, 1 indicates allocated), and whether the data is written back (e.g., 0 indicates unwritten, 1 indicates written back).

Wherein, at initialization, the free register number table contains all available physical registers. Initially, the logical destination register a (a is a positive integer) will be mapped to the second physical register a, so the free register number table contains a total of 352 free physical register numbers from 32 to 383 in the initial state.

When renaming, the free register number table may present up to R second physical register numbers for use, where R is the number of instructions that are renamed per beat simultaneously. When the second physical register is released (ROB commits instructions or rolls back), the free register number table may enter at most C free physical register numbers per beat, where C is the number of instructions retired at the same time per beat.

In an embodiment of the invention, the free register numbering table comprises two release methods, used in the absence of a reference counting function and in the presence of a reference counting function, respectively. For the case where there is no reference count, when a ROB rollback occurs, the free registers released in the free register number table must be the ones that were just allocated before and the same number of new physical registers that need to be allocated in the rollback instruction. In this case, the storage of the free register number table does not need to be rewritten, but only the dequeue pointer (head pointer) needs to be rolled back forward. For the case of reference count, the number of physical registers rolled back is not necessarily the same as the number of released physical registers of the idle register numbering table, and release is performed according to the physical registers actually released, due to the presence of the repeated reference (the reference count of one physical register is not required to be allocated through the idle register numbering table).

Furthermore, the fixed-point physical register supports multiple references, when the reference counting function exists, the register renaming needs to maintain an access counter, the idle register numbering table and the resequencing queue submit the count of the modification counter, the counter update triggers the idle register numbering table update, and the register renaming reads the idle register from the idle register numbering table.

Recording the referenced times of the fixed point physical register; based on the number of references, a plurality of logical destination registers are mapped to the same second physical register.

In order to reduce the complexity of implementing the circuit, embodiments of the present invention set a limit on a counter (ref counter), and preset an upper limit on the counter to determine an upper limit on the number of times that is referenced. And the limit counter cannot handle ref counter++ requests to the same physical register twice and more in one cycle.

For example, if the upper limit of the design counter is 2-bit, one physical register is referenced 3 times at most, and the upper limit of the number of times is referenced 3.

When the number of the counters exceeds the upper limit or the counters process ref counter++ requests for two or more times of the same physical register in one period, the conflict Move instruction is directly executed as a common instruction, and the Move instructions which are eliminated and are not eliminated are distinguished.

The reference count table functions to record the number of references to each physical register, with three modules, allocate (increase the number of references), de-allocate (decrease the number of references), and release the physical registers to the reference count table.

In the presence of a reference count function, renaming allocates and releases each physical register to the reference count table. When the reference count value of one physical register becomes 0, the corresponding physical register is released into the reference count table to wait for the next allocation.

In step 205, the second physical register is renamed as the first physical register.

When register renaming (Rename) checks that the isMove tag passed from the decode is valid, the second physical register is replaced with the first physical register.

In the implementation of the present invention, the first physical register is a physical source register (psrc) and the second physical register is a physical destination register (pdst).

In order to implement Move instruction Elimination (Move eliimation), the physical register pdst corresponding to the logical destination register dst in the Move dst, src instruction is directly renamed to the physical source register psrc corresponding to the logical source register src. The Move instruction after processing does not need to reenter subsequent flow water levels such as an emission part, an execution part and the like.

The primary role of the renaming pipeline stage is to update the physical register information of the instruction, including the psrc, second physical register pdest, and old_pdest (old target physical register number). The psrc and old_pdest are derived from rename tables. When an instruction needs to allocate a new physical register, such as a fixed point instruction needs to write to a register file, a target register is a non-zero register, and a floating point instruction needs to write to the register file, pdest is derived from the allocation result of FreeList. Because of the inter-instruction dependencies, for instructions renamed in the same beat, the register renaming Rename module needs to be responsible for bypassing the physical register number between them, i.e., if instruction 1 needs to use the result of instruction 0, the corresponding source operand of instruction 1 needs to be sourced from the destination register of instruction 0.

Further, the data transmission instruction includes an immediate load instruction and an immediate instruction pair, and the base address of the immediate instruction is replaced by an immediate, so that the immediate is stored in the first physical register and in the immediate field, wherein the immediate is a preset value.

As a possible implementation, to be able to store a larger immediate in the first physical register, the immediate is a 20-bit number, and the immediate load instruction is to shift a preset 20-bit immediate left by 12 bits and zero the lower 12 bits to a 32-bit number, which is written back into the first physical register.

In the embodiment of the invention, the base address of the fetch instruction is replaced by the immediate, the immediate is stored in the psrc and immediate fields, the immediate load instruction and the fetch instruction pair are optimized, and the operand bypass function is realized.

Optionally, in response to identifying the no-op instruction, the no-op instruction is marked as a move elimination instruction.

In the embodiment of the present invention, the instruction with the logic destination register dst=0 and the logic source register src=the logic destination register dst is identified as a no-operation instruction (nop instruction), that is, the instruction does not have any influence on the processor state or the memory state.

When the nop instruction is decoded, the nop instruction is identified, marked as unnecessary to allocate pdst (physical destination register) and tagged with a tag that is a Move instruction, namely: rfWen=false =and iso & move=true, pdst is not required to be allocated to nop instructions when a register is renamed, and moving instructions are directly made to eliminate eliminomatedmove=true, after the dispatch is carried out, execution pipeline stages such as subsequent emission, functional components and the like are not required to be carried out, and only a re-sequencing queue is required to be carried out.

In the embodiment of the present invention, when the logical destination register dst=0, the logical destination register dst of the Move a0, a0 instruction is also set to 0. The instruction of the logic destination register dst=0 & & isMove is specially processed, marked as a moving instruction is eliminated, and only enters a re-sequencing queue after being dispatched.

In the embodiment of the present invention, the data transmission instruction includes an instruction with a logical source register of 0, where the instruction with a logical source register src=0 is used to clear the value of the register, and the logical destination register dst of the instruction may be mapped to a preset target physical register, and in the embodiment of the present invention, the target physical register is a number 0 second physical register.

As another embodiment, a specRAT is a logical register to physical register mapping of speculative execution states. an archRAT is a certain correct logical to physical register mapping.

In the initial state, the specRAT is the same as the archRAT, as shown in table 1:

TABLE 1

The free physical register number table is shown in table 2:

TABLE 2

The access counter ref counter (binary) is shown in table 3:

TABLE 3 Table 3

The physical register file physical reg file is shown in table 4:

TABLE 4 Table 4

The logical register file arch file is shown in table 5:

TABLE 5

Searching a special RAT to obtain a physical source register corresponding to a logical source register (src); searching an idle physical destination register in an idle register number table, distributing the idle physical destination register to a logical destination register (dst), and writing the mapping relation from the newly mapped logical register to the physical register into a specRAT; the physical register corresponding to the special rat before finding dst is searched again and recorded as an old destination physical register (old_pdst), and this register is released when the instruction is submitted, and furthermore, the RoqIdx number (re-sequence number) needs to be added to the instruction in the internal operation table (uop), and through this number, synchronization is performed with Roq (Reorder Queue) during flushing and redirection (redirect).

For the case of WAW/RAW/Move Elimination three types requiring transfer (bypass) of physical register numbers, a transfer enable signal is generated at a register renaming pipeline stage, and the pipeline stage is allocated to modify data.

The register renames each cycle to process the submission of C instructions, and when the instructions are submitted, the old_pdst is released, and the physical register corresponding to the logical register is written into the archRAT.

The method comprises the following specific steps of:

1. the corresponding psrc for src is obtained (at this stage, it is determined whether or not the move instruction elimination of the given instruction can be handled).

a. The calculation transfer bypass matrix is shown in Table 6:

TABLE 6

bypass matrix representation:

the 2 nd instruction has RAW correlation with the 1 st instruction, and the relevant register is a register r4;

the 4 th instruction has RAW correlation with the 2 nd instruction, and the relevant register is a register r5;

the 4 th instruction has RAW correlation with the 3 rd instruction, and the relevant register is a register r5;

the 3 rd and 2 nd instruction have WAW correlation and the associated register is register r5.

b. Comparing each psrc with all the previous psrcs, and judging whether the referenced times corresponding to each psrc reach the maximum value or not, so that the situation that the moving instruction elimination cannot be carried out because the psrc is repeated or the referenced times are insufficient can be obtained.

c. The bypass of the psrc is performed first to determine whether there is a repetition of the psrc that results in a repetition of pdst (because one cycle ref counter is at most +1), and thus the move instruction cannot be eliminated. If the pdst=psrc can be directly given by an instruction other than the instruction 3, the obtained pdst is p7, p10, p8, p1 (FreeList), and p2 in this order. However, because of the RAW relationship between instruction 2 and instruction 1, the pdst of instruction 1 needs to be transferred (bypass) to the psrc of instruction 2, so that it needs to be determined again whether there is a repetition of the psrc. Therefore, starting from the first instruction in the program, whether or not (psrc 0- > pdst0- > psrc1- > pdst1- > are) motion eliimation can be performed is judged in series, pdst of the instruction is correctly given in one period, operation of ref counter [ pdst ] ++ is completed, and then FreeList is updated.

d. From the aspects of performance and implementation complexity, the invention judges whether to do Move animation (me) according to the following judgment rule that Move animation instruction can be eliminated:

if there is a RAW relationship between the instruction i and the instruction j preceding it (i.e. i.psrc=j.pdst needs to be updated), then it is considered that the instruction i cannot perform Move elination, and the src_bypass [ i-1] is used to represent a row of bit vectors bit vec in the left sub-table of the table.

Ii, using src vec to access the special RAT, comparing the obtained src vec, and obtaining a lower triangular matrix, wherein the lower triangular matrix is represented by using the src_cmp [ i-1 ].

Iii, accessing the ref counter by using the psc vec to obtain an isMax vector, wherein isMax [ i ] indicates whether the ref counter corresponding to the psc corresponding to the instruction i reaches the maximum value or not. The maximum number of instructions that can be renamed per beat of the processor is denoted as RenameWidth.

meEnable = isMove[i]&!(src_bypass[i-1].orR | psrc_cmp[i-1].orR | isMax[i]), 1<= i&&i<RenameWidth；

meEnable = isMove[i]&!isMax[i], i == 0

src_bypass is shown in Table 7:

TABLE 7

The psrc_cmp is shown in table 8:

TABLE 8

isMax is shown in table 9:

TABLE 9

/>

The internal operation table uop is shown in table 10:

table 10

2. Ref counter++ for all pdst.

3. At the Rename pipeline stage, pdst is updated, and psrc and old_pdst need to be updated at the Dispatch pipeline stage. The above two RAW+WAW tables are passed to Dispatch.

4. Update specRAT, etc.

5. After the Rename is updated:

a. the specRAT (dst- > pdst) is shown in table 11:

TABLE 11

b. ref counter is shown in table 12:

table 12

c. FreeList is shown in table 13:

TABLE 13

Further, dispatch places Move instructions into a reorder queue (Roq) as they are processed, and no longer passed to later pipeline stages. The uops are updated according to the pass information, and the updated uops are shown in table 14:

TABLE 14

The dispatch also writes a new entry (entry) in Roq.

Further, consider the case where the following 5 instructions are committed Roq:

1. assuming that Roq submits 5 instructions in a period, from the standpoint of implementation complexity, the instructions requiring that the old_pdst repeat does not exist are also submitted, so that whether or not the old_pdst repeat exists is required to judge that a plurality of instructions can be submitted;

2. updating ref counter and FreeList;

a. ref counter corresponding to old_pdst of ref counter- -as shown in Table 15:

TABLE 15

b. Updating FreeList according to ref counter, and reclaiming the ref counter to be 0 to FreeList is shown in table 16:

table 16

3. Update archRAT (same as specRAT);

4. the following checks were made:

a. instructions 2-4 are general instructions, and move the data in the reg file to obtain a new reg file as shown in table 17:

TABLE 17

b. The arch reg file is obtained according to the front and back archrats, and compared with the instruction execution result, wherein the new archRAT is shown in table 18:

TABLE 18

new arch reg file is shown in table 19:

TABLE 19

The execution result of the register Move instruction elimination of the present invention is the same as the 5 Move instructions illustrated in the sequential execution step 202.

Further, if an exception-induced refresh occurs, then:

specRAT = archRAT；

The FreeList and ref counter recover, the FreeList pointer is directly reset (the 32 registers which are not in the FreeList are occupied registers), the occupied register ref counter=1 in the FreeList, and the other registers ref counter=0;

RoqIdx = 0。

further, if redirection caused by transfer cancellation or the like occurs, then:

FreeList and ref counter: rollback a given number of steps;

the specRAT updates the specRAT [ dst ] = old_pdst according to dst, old_pdst in the instruction of the rollback;

RoqIdx = redirected RoqIdx.

And finally, identifying whether an idle operation instruction exists or not, and carrying out corresponding processing.

In this embodiment, the instruction execution identification target instruction based on the data transfer instruction of the register; determining a logic register related to a target instruction, wherein the logic register comprises a logic source register and a logic destination register; querying a renaming table in any period based on the number of the logic source register to determine a first physical register corresponding to the logic source register, wherein the renaming table is used for maintaining the mapping relation between the logic source register and the first physical register; based on the number of the logic destination register, searching an idle register number table in any period to determine a second physical register corresponding to the logic destination register, wherein the idle register number table is used for recording the number and the corresponding state of the idle register; the second physical register is renamed to the first physical register. Based on the renaming table and the idle register numbering table, renaming from the logic register to the physical register related to the target instruction is realized, and only the renaming table and the idle register numbering table are maintained, so that the performance and the main frequency of the out-of-order processor are improved, and the power consumption and the area of the out-of-order processor are reduced.

In order to implement the above embodiment, the present invention further proposes a register renaming device.

Fig. 4 is a schematic structural diagram of a register renaming device according to an embodiment of the invention.

As shown in fig. 4, the register renaming apparatus 400 includes: an identification module 401, a first query module 402, a second query module 403, and a renaming module 404.

An identification module 401, configured to identify a target instruction of a register, and determine a logic register related to the target instruction, where the logic register includes a logic source register and a logic destination register;

a first query module 402, configured to query a renaming table in any period based on the number of the logical source registers, to determine a first physical register corresponding to the logical source registers, where the renaming table is used to maintain a mapping relationship between the logical source registers and the first physical registers;

a second query module 403, configured to query an idle register number table in any cycle based on the number of the logical destination register, to determine a second physical register corresponding to the logical destination register, where the idle register number table is used to record the number and the corresponding state of the idle register;

renaming module 404 is configured to rename the second physical register to the first physical register.

Further, in one possible implementation of the embodiment of the present invention, the renaming table includes a set of read ports and a set of write ports, where the read ports are used to output renaming table read data and the write ports are used to update the renaming table.

The first query module 402 is further configured to:

reading history renaming list read data of the previous period of any period, wherein the history renaming list read data comprises a history read address and a history keeping signal, the history read address is determined through logic register assignment of a target instruction, and the history keeping signal is determined according to the blocking condition of a corresponding pipeline stage;

updating the history read address based on the value of the history holding signal to obtain a target read address of any period;

determining a target holding signal according to the blocking condition of the corresponding flow level in any period;

the rename table read data is composed of a target read address and a target hold signal.

Responding to the history keeping signal as a preset value, and taking the history read address as a target read address;

and in response to the history holding signal not being a preset value, updating the history read address to the latest read address as the target read address.

And updating the mapping relation corresponding to renaming into a renaming table.

Further, in one possible implementation manner of the embodiment of the present invention, the first physical register includes a fixed-point physical register and a floating-point physical register, and the renaming table includes a first renaming table corresponding to the fixed-point physical register and a second renaming table corresponding to the floating-point physical register.

The fixed point physical register supports multiple references, the apparatus further being for:

recording the referenced times of the fixed point physical register;

multiple logical source registers are mapped to the same first physical register based on the number of times referenced.

The upper limit of the counter is preset to determine the upper limit of the number of times that is referenced.

Further, in a possible implementation manner of the embodiment of the present invention, the identifying module 401 is further configured to:

instruction execution of the register-based data transfer instruction identifies a target instruction.

The data transmission instruction comprises an immediate loading instruction and an immediate instruction pair, and the base address of the immediate instruction is replaced by an immediate, so that the immediate is stored in a first physical register and an immediate field, wherein the immediate is a preset value.

Further, in a possible implementation manner of the embodiment of the present invention, the data transmission instruction includes a no-operation instruction, and the apparatus is further configured to:

In response to identifying the no-op instruction, the no-op instruction is marked as a move elimination instruction.

And identifying the instruction with the logic destination register being 0 and the logic source register being the logic destination register as a non-operation instruction.

The data transmission instruction comprises an instruction with a logic source register of 0, and the logic destination register is mapped to a preset target physical register.

It should be noted that the foregoing explanation of the embodiment of the register renaming method is also applicable to the register renaming device of this embodiment, and will not be repeated herein.

In the embodiment of the invention, a target instruction of a register is identified, and a logic register related to the target instruction is determined, wherein the logic register comprises a logic source register and a logic destination register; querying a renaming table in any period based on the number of the logic source register to determine a first physical register corresponding to the logic source register, wherein the renaming table is used for maintaining the mapping relation between the logic source register and the first physical register; based on the number of the logic destination register, searching an idle register number table in any period to determine a second physical register corresponding to the logic destination register, wherein the idle register number table is used for recording the number and the corresponding state of the idle register; the second physical register is renamed to the first physical register. Based on the renaming table and the idle register numbering table, renaming from the logic register to the physical register related to the target instruction is realized, and only the renaming table and the idle register numbering table are maintained, so that the performance and the main frequency of the out-of-order processor are improved, and the power consumption and the area of the out-of-order processor are reduced.

In order to implement the above embodiment, the present invention further proposes another register renaming device, including a memory, a transceiver, and a processor:

a memory for storing a computer program; a transceiver for transceiving data under the control of the processor; a processor for reading the computer program in the memory and performing the following operations:

querying a renaming table in any period based on the number of the logic source register to determine a first physical register corresponding to the logic source register, wherein the renaming table is used for maintaining the mapping relation between the logic source register and the first physical register;

the second physical register is renamed to the first physical register.

In order to achieve the above embodiment, the present invention further provides an electronic device, including: a processor, and a memory for storing instructions executable by the processor.

Wherein the processor is configured to execute the instructions to implement the register renaming method described above.

To achieve the above embodiments, the present invention also proposes a non-transitory computer-readable storage medium, which when executed by a processor of an electronic device, enables the electronic device to perform the above-described register renaming method.

To achieve the above embodiments, the present invention also proposes a computer program product which, when executed by an instruction processor in the computer program product, performs the above-mentioned register renaming method.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and additional implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order from that shown or discussed, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present invention.

Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.

It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. As with the other embodiments, if implemented in hardware, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.

Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and where the program, when executed, includes one or a combination of the steps of the method embodiments.

In addition, each functional unit in the embodiments of the present invention may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product.

The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like. While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.

Claims

1. A method of register renaming, comprising the steps of:

Renaming the second physical register to the first physical register;

the renaming table comprises a group of reading ports and a group of writing ports, wherein the reading ports are used for outputting renaming table reading data, and the writing ports are used for updating the renaming table;

the read port is used for outputting rename table read data, and comprises:

reading history rename table read data of the previous cycle of any cycle, wherein the history rename table read data comprises a history read address and a history holding signal, the history read address is determined through logic register assignment of the target instruction, and the history holding signal is determined according to the blocking condition of a corresponding pipeline stage;

updating the history read address based on the value of the history holding signal to obtain the target read address of any period;

determining a target holding signal according to the blocking condition of the corresponding flow level of any period;

and the target read address and the target holding signal form the rename table read data.

2. The method of claim 1, wherein updating the history read address based on the value of the history retention signal to obtain the target read address of the any cycle comprises:

Responding to the history maintaining signal as a preset value, and taking the history read address as the target read address;

and in response to the history holding signal not being the preset value, updating the history read address to the latest read address as the target read address.

3. The method of claim 1, wherein the write port is configured to update the rename table, comprising:

and updating the mapping relation corresponding to the rename into the rename table.

4. The method of claim 1, wherein the first physical registers comprise fixed point physical registers and floating point physical registers, and wherein the rename table comprises a first rename table corresponding to fixed point physical registers and a second rename table corresponding to floating point physical registers.

5. The method of claim 4, wherein the fixed point physical register supports multiple references, the method further comprising:

recording the referenced times of the fixed point physical register;

based on the number of references, a plurality of logical source registers are mapped to the same first physical register.

6. The method of claim 5, wherein the method further comprises:

The upper limit of the counter is preset to determine the upper limit of the referenced times.

7. The method of claim 1, wherein the identifying the target instruction of the register comprises:

instruction execution of a register-based data transfer instruction identifies the target instruction.

8. The method of claim 7, wherein instruction execution of the register-based data transfer instruction identifies the target instruction, comprising:

in response to fetching and decoding the data transfer instruction from the instruction cache, marking the target instruction in the data transfer instruction.

9. The method of claim 8, wherein the data transfer instruction includes an immediate load instruction and fetch instruction pair therein, the method further comprising:

and replacing the base address of the fetch instruction with an immediate, so that the immediate is stored in the first physical register and an immediate field, wherein the immediate is a preset value.

10. The method of claim 8, wherein the data transfer instruction comprises a no-op instruction, the method further comprising:

11. The method of claim 10, wherein an instruction for which the logical destination register is 0 and the logical source register is a logical destination register is identified as the no-op instruction.

12. The method of claim 8, wherein the data transfer instruction includes an instruction with a logical source register of 0, the method further comprising:

and mapping the logic destination register to a preset target physical register.

13. A register renaming apparatus, comprising:

A renaming module for renaming the second physical register to the first physical register;

the read port is used for outputting rename table read data, and comprises:

14. A register renaming apparatus comprising a memory, a transceiver, and a processor:

renaming the second physical register to the first physical register;

The read port is used for outputting rename table read data, and comprises:

15. A computer readable storage medium, characterized in that instructions in the storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the method of any one of claims 1 to 12.