CN117492349A

CN117492349A - Time-to-digital converter, digital readout circuit and electronic device

Info

Publication number: CN117492349A
Application number: CN202311695472.9A
Authority: CN
Inventors: 吴华强; 郭欣颖; 潘思宁; 姚鹏; 卫松涛; 伍冬; 揭路; 高滨; 钱鹤
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2023-12-11
Filing date: 2023-12-11
Publication date: 2024-02-02

Abstract

The disclosure provides a time-to-digital converter, a digital readout circuit and an electronic device, wherein the time-to-digital converter comprises a first quantization unit, a second quantization unit and an output unit, wherein the first quantization unit is configured to perform first quantization on an input delay signal to obtain a first quantization result and a time residual signal; the second quantization unit is configured to perform second quantization on the time residual signal to obtain a second quantization result; the output unit is configured to obtain a target quantization result corresponding to the delay signal according to a first quantization result and a second quantization result, wherein the first quantization corresponds to an upper portion of the target quantization result and the second quantization corresponds to a lower portion of the target quantization result except for the upper portion. The time-to-digital converter, the digital readout circuit and the electronic device can avoid all time signals from being converted into digital signals through low-order quantization by a two-stage quantization structure, and reduce the power consumption of time-to-digital conversion.

Description

Time-to-digital converter, digital readout circuit and electronic device

Technical Field

Embodiments of the present disclosure relate to a time-to-digital converter, a digital readout circuit, and an electronic device.

Background

The rise of artificial intelligence based on the neural network makes the memristor-based integrated architecture of memory calculation obtain a great deal of attention, and the combination of memory weight and direct calculation is realized by using a large-scale cross array, so that the method has great advantages in high calculation power and high energy efficiency.

Disclosure of Invention

Some embodiments of the present disclosure provide a time-to-digital converter, the time-to-digital converter comprising: a first quantization unit configured to perform a first quantization on the input delayed signal to obtain a first quantization result and a time residual signal; a second quantization unit configured to perform a second quantization on the temporal residual signal to obtain a second quantization result; and an output unit configured to obtain a target quantization result corresponding to the delay signal according to the first quantization result and the second quantization result, wherein the first quantization corresponds to an upper portion of the target quantization result, and the second quantization corresponds to a lower portion of the target quantization result except for the upper portion.

For example, in a time-to-digital converter provided in some embodiments of the present disclosure, the first quantization unit is further configured to count the input delay signal using a first clock count signal to perform the first quantization.

For example, a time-to-digital converter provided in some embodiments of the present disclosure further includes: a first counter configured to provide the first clock count signal.

For example, in a time-to-digital converter provided by some embodiments of the present disclosure, the delay signal is acquired based on a first time pulse and a second time pulse, wherein the second time pulse has a delay relative to the first time pulse waveform; the first quantization unit includes: a count quantization subunit configured to count according to the first time pulse, the second time pulse, and based on the first clock count signal to obtain the first quantization result; a residual generation subunit configured to acquire an unquantized portion of the delay pulse that is not included in the first quantization based on the delay pulse and the count value, and output the unquantized portion as the time residual signal.

For example, in a time-to-digital converter provided in some embodiments of the present disclosure, the delay signal is a delay pulse signal acquired based on the first time pulse and the second time pulse, and the count quantization subunit includes: a count value acquisition unit configured to acquire a first count value from a first rising edge of the first clock count signal within the delayed pulse signal, and correspondingly acquire a second count value from a first rising edge of the first clock count signal after the delayed pulse signal; a first subtractor configured to obtain the first quantization result using the first count value and the second count value.

For example, in a time-to-digital converter provided in some embodiments of the present disclosure, the second quantization unit includes: a sample-and-hold subunit configured to sample the temporal residual signal to obtain a residual signal to be quantized; and the quantization subunit is configured to quantize the residual signal to be quantized to obtain the second quantization result.

For example, in a time-to-digital converter provided by some embodiments of the present disclosure, the sample-and-hold subunit includes: at least one capacitive digital-to-analog converter (CDAC) configured to convert the temporal residual signal to obtain a residual signal to be quantized as a voltage signal; a current mirror unit connected to the at least one CDAC and configured to control the at least one CDAC to perform a passive integration operation according to a time residual signal to obtain the voltage signal; wherein the quantization subunit comprises an analog-to-digital converter configured to convert the voltage signal to obtain the second quantization result.

For example, in a time-to-digital converter provided in some embodiments of the present disclosure, the at least one CDAC includes two CDACs connected in parallel between the current mirror unit and the quantization subunit, and the sample-and-hold subunit further includes two switches respectively disposed between the two CDACs and the current mirror unit, wherein the two CDACs and the two switches respectively form two second quantization channels capable of alternately operating.

For example, in a time-to-digital converter provided by some embodiments of the present disclosure, the sample-and-hold subunit includes: at least one time signal amplifying unit configured to amplify the time residual signal to obtain a residual signal to be quantized; at least one current mirror unit connected to the time signal amplifying unit and configured to control an operation of the time signal amplifying unit according to the time residual signal; wherein the quantization subunit is further configured to convert the residual signal to be quantized using a second clock count signal to obtain a second quantization result.

For example, in a time-to-digital converter provided in some embodiments of the present disclosure, the at least one time signal amplifying unit is two time signal amplifying units; the at least one current mirror unit is two current mirror units which are correspondingly connected in series with the two time signal amplifying units; the sample-hold subunit further comprises two switches respectively connected between the first quantization unit and the two current mirror units, wherein the two switches, the two current mirror units and the two time signal amplifying units respectively correspondingly form two second quantization channels capable of alternately working.

For example, in a time-to-digital converter provided in some embodiments of the present disclosure, the quantization subunit includes a second subtractor, and the second subtractor is configured to perform subtraction on a third count value and a fourth count value obtained by counting the residual signal to be quantized using the second clock count signal to obtain the second quantization result.

For example, in a time to digital converter provided in some embodiments of the present disclosure, the quantization subunit includes a second counter configured to count according to the second clock count signal to obtain the third count value and the fourth count value.

For example, in one time-to-digital converter provided by some embodiments of the present disclosure, the at least one current mirror unit is configured to provide a first detection current for a first charge-discharge operation and a second detection current for a second charge-discharge operation; the time signal amplifying unit includes: a working capacitor electrically connected to the current mirror unit to perform the first charge and discharge operation or the second charge and discharge operation; a comparing subunit electrically connected with the working capacitor and the reference voltage and configured to compare the voltage of the detected polar plate in the working capacitor with the reference voltage; a control subunit configured to control a current mirror unit to operate, by the comparing subunit, to cause the first charge-discharge operation to charge the detected plate in the working capacitor from the reference voltage to a first voltage with the first detection current in a first period of time determined by the time residual signal, to cause the second charge-discharge operation to discharge the detected plate in the working capacitor from the first voltage to the reference voltage with the second detection current in a second period of time, and to obtain the residual signal to be quantized using a ratio between the second period of time and the first period of time.

Some embodiments of the present disclosure also provide a digital readout circuit comprising a plurality of the time-to-digital converters of any one of the above embodiments.

Some embodiments of the present disclosure also provide an electronic device including a delay computation array; the digital readout circuit according to any one of the above embodiments, wherein the delay calculation array includes a plurality of output ports, and the plurality of time-to-digital converters are respectively and correspondingly connected to the plurality of output ports.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

FIG. 1A is a schematic diagram of an exemplary delay buffer unit;

FIG. 1B is a schematic diagram of another exemplary delay buffer unit;

FIG. 2 is a schematic diagram of an exemplary delay computation array;

FIG. 3 is a schematic diagram of an exemplary computing device;

FIG. 4A is a schematic diagram of a time-to-digital converter according to at least one embodiment of the present disclosure;

fig. 4B is a schematic structural diagram of a first quantization unit according to at least one embodiment of the present disclosure;

Fig. 4C is a schematic structural diagram of a second quantization unit according to at least one embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a time-to-digital converter according to at least one embodiment of the present disclosure;

FIG. 6 is a timing diagram illustrating operation of the time to digital converter of FIG. 5 in accordance with at least one embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a time-to-digital converter according to at least one embodiment of the present disclosure;

FIG. 8 is a timing diagram illustrating operation of the time to digital converter of FIG. 7 according to at least one embodiment of the present disclosure;

FIG. 9 is a schematic diagram illustrating a process of time amplifying and counting by a second quantization unit of the time-to-digital converter shown in FIG. 7 according to at least one embodiment of the present disclosure; and

fig. 10 is a schematic structural diagram of a digital readout circuit according to at least one embodiment of the present disclosure.

Detailed Description

For a better understanding of the technical solutions of the present disclosure, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings, and the specific embodiments and the accompanying drawings described herein are only for explaining the present disclosure and not limiting the disclosed embodiments, and the embodiments of the present disclosure and the features of the embodiments may be combined with each other without conflict.

For convenience of description, only parts related to the embodiments of the present disclosure are shown in the drawings, and parts unrelated to the embodiments of the present disclosure are not shown in the drawings. Each unit, module referred to in the embodiments of the present disclosure may correspond to only one physical structure, may be composed of a plurality of physical structures, or may be integrated into one physical structure. In the absence of conflict, the functions noted in the flowcharts and block diagrams of the disclosed embodiments may occur out of the order noted in the figures.

The architecture, functionality, and operation of possible implementations of systems, apparatuses, devices, methods according to various embodiments of the present disclosure are shown in the flowcharts and block diagrams of the disclosed embodiments. Each block in the flowchart or block diagrams may represent a unit, module, segment, or code, which comprises executable instructions for implementing the specified functions. Moreover, each block or combination of blocks in the block diagrams and flowchart illustrations can be implemented by hardware-based systems that perform the specified functions, or by combinations of hardware and computer instructions.

Detailed descriptions of known functions and known parts (elements) may be omitted for the sake of clarity and conciseness in the following description of the embodiments of the present disclosure. When any part (element) of an embodiment of the present disclosure appears in more than one drawing, the part (element) is denoted by the same or similar reference numeral in each drawing.

The memristor is a novel information processing device, has the function of memory computation fusion, and can realize computation operation in situ on stored data, so that huge expenditure of data movement is eliminated. In addition, the memristor can directly perform operation on an analog domain (for example, the memristor can complete multiplication operation based on ohm's law and addition operation based on kirchhoff's current law), so that matrix vector multiplication operation is realized in one step, and digital-to-analog conversion cost is not needed in the operation process. In recent years, memristor-based memory integration has made significant progress. However, since the power supply support of the terminal device is limited, memristor-based integrated storage devices are required to have not only higher precision of computation but also lower energy consumption and higher energy efficiency. Therefore, the memristor memory integrated design is improved in the aspects of array structure, peripheral circuit design and the like.

One improvement is a time domain quantization method, which transfers the output result to the time domain to increase the output range, so as to more simply and efficiently distinguish different output states, etc., but the output of the time domain quantization has a nonlinear problem.

Thus, a delay buffer unit comprising memristors and a delay calculation array formed by the delay buffer unit are provided, and matrix calculation integrated with memory can be realized by using the delay calculation array. When the delay buffer unit is operated, the transmission delay of the delay buffer unit can be changed according to whether the memristor is used, and the transmission delay of the delay buffer unit can be changed by controlling the resistance value change of the memristor, so that the dynamic regulation and control of the delay buffer unit are realized, and the delay can be flexibly and efficiently regulated and controlled according to actual demands.

FIG. 1A illustrates a schematic diagram of an exemplary delay buffer unit; fig. 1B shows a schematic diagram of another exemplary delay buffer unit. The circuit configuration of the delay buffer unit is described in detail below with reference to fig. 1A and 1B.

As shown in fig. 1A and 1B, the delay buffer unit 10 includes a first-stage inverter P1, a second-stage inverter P2, and a delay adjustment subunit 11.

For example, the input terminal of the first-stage inverter P1 serves as the input terminal INT of the delay buffer unit 10. The input signal of the delay buffer unit may be received from the input terminal of the first stage inverter P1, and the input signal may be, for example, a rising edge trigger signal (as shown in fig. 1A) or a falling edge trigger signal (as shown in fig. 1B). For example, the first stage inverter P1 includes two transistors T1 and T2, where T1 is, for example, an NMOS transistor, T2 is, for example, a PMOS transistor, and gate terminals of the transistors T1 and T2 may be used as input terminals, that is, the input terminal INT of the delay buffer unit 10 to receive an input signal. For example, when the input signal is at a high level, the transistor T1 is turned on, the transistor T2 is turned off, and when the input signal is at a low level, the transistor T1 is turned off, and the transistor T2 is turned on. The drain terminals of the transistors T1 and T2 are electrically connected to each other and serve as the output terminal of the first-stage inverter P1, and the source terminal of the transistor T1 or T2 may be connected to the ground terminal or the power source terminal or may serve as the first terminal of the first-stage inverter P1.

For example, the input terminal of the second-stage inverter P2 is connected to the output terminal of the first-stage inverter P1, and the output terminal of the second-stage inverter P2 serves as the output terminal OUT of the delay buffer unit 10. The circuit structure of the second-stage inverter P2 is similar to that of the first-stage inverter P1, and will not be described here again. It should be noted that the circuit structures of the first-stage inverter P1 and the second-stage inverter P2 may be realized in other structures.

For example, the output signal of the delay buffer unit 10, which corresponds to the input signal and has a certain delay with respect to the input signal, may be output from the output terminal of the second-stage inverter P2, the delay being composed of the transmission delays of the first-stage inverter P1 and the second-stage inverter P2. For example, as shown in fig. 1A, when the input signal received from the input terminal INT of the delay buffer unit 10 is a rising edge trigger signal, the output signal outputted from the output terminal OUT of the delay buffer unit 10 has a certain delay t with respect to the rising edge trigger signal (the rising edge trigger signal and the output signal are respectively represented by gray lines and black lines at the output terminal OUT in fig. 1A). For example, as shown in fig. 1B, when the input signal received from the input terminal INT of the delay buffer unit 10 is a falling edge trigger signal, the output signal outputted from the output terminal OUT of the delay buffer unit 10 has a certain delay t with respect to the falling edge trigger signal (the falling edge trigger signal and the output signal are respectively represented by gray lines and black lines at the output terminal OUT in fig. 1B).

For example, the delay adjustment subunit 11 is connected between the first end of the first-stage inverter P1 and the first operating voltage end 1, and the delay adjustment subunit 11 comprises a memristor (here, a Resistive Random Access Memory (RRAM) is exemplified), and the delay adjustment subunit 11 is configured to control the transmission delay of the first-stage inverter P1 using the memristor RRAM according to the first control signal. For example, the first control signal is provided by the first control terminal NWL and is used to control whether the delay adjustment subunit 11 uses the memristor RRAM to adjust the transmission delay of the first-stage inverter P1, thereby adjusting the delay difference (delay t) between the output signal and the input signal of the delay buffer unit 10.

For example, delay adjustment subunit 11 further includes a control switch, which may be an N-type transistor or a P-type transistor, which is not limited by the present disclosure. The control switch, here exemplified by an N-type transistor (NM 1), comprises a first pole, a second pole and a control pole, which may be, for example, the source, drain and gate of the N-type transistor, respectively. The control switch NM1 has a control electrode connected to the first control terminal NWL, and the control switch NM1 receives a first control signal from the first control terminal NWL and turns on or off the first electrode and the second electrode of the control switch NM1 according to the first control signal. For example, a first pole of the control switch NM1 is electrically connected to a first terminal of the first-stage inverter P1, a second pole of the control switch NM1 is electrically connected to the first operation voltage terminal 1, the first-stage inverter P1 is connected to the first operation voltage terminal 1 when the control switch NM1 is turned on, and the first-stage inverter P1 is disconnected from the first operation voltage terminal 1 when the control switch NM1 is turned off. The control switch NM1 may be an N-type transistor (as shown in fig. 1A) or a P-type transistor.

For example, the memristor RRAM in the delay adjustment subunit 11 includes a first terminal electrically connected to the first pole of the control switch NM1 and the first terminal of the first-stage inverter P1, and a second terminal. The second terminal of the memristor RRAM and the second terminal of the control switch NM1 may be connected to the same or different operation voltage terminal, for example. Here, the connection of the second terminal of the memristor RRAM to the same operation voltage terminal indicates that both voltage signals obtained from the same (or different) operation voltage terminal are the same, and the connection of the second terminal of the memristor RRAM to the different operation voltage terminal indicates that both voltage signals obtained from the different operation voltage terminals, respectively, are different.

For example, in one example, the second terminal of the memristor RRAM is electrically connected to the first operating voltage terminal 1 (as shown in fig. 1B), that is, the second terminal of the memristor RRAM is connected to the first operating voltage terminal together with the second terminal of the control switch NM1, and the first operating voltage terminal 1 may be, for example, a power supply terminal (as shown in fig. 1B) or a ground terminal. For example, in another example, as shown in fig. 1A, a second terminal of the memristor RRAM is electrically connected to a second operating voltage terminal 2, a second terminal of the control switch NM1 is electrically connected to a first operating voltage terminal 1, and voltage signals provided by the first operating voltage terminal 1 and the second operating voltage terminal 2 are different. For example, in yet another example, the second terminal of the memristor RRAM is electrically connected to the first operating voltage terminal 1, the second terminal of the control switch NM1 is electrically connected to the second operating voltage terminal 2, and the first operating voltage terminal 1 and the second operating voltage terminal 2 are different.

For example, the delay adjustment subunit 11 is connected to a first terminal of the first-stage inverter P1, for example, to a source terminal of the first-stage inverter P1. For example, as shown in fig. 1A, the delay adjustment subunit 11 is connected between the NMOS transistor T1 in the first-stage inverter P1 and the first operating voltage terminal 1. For example, in the delay adjustment subunit 11 shown in fig. 1A, a first pole (e.g., drain) of the control switch NM1 is connected to a source of the NMOS transistor T1 in the first-stage inverter P1, and a first end of the memristor RRAM is connected to a source of the NMOS transistor T1 in the first-stage inverter P1. For example, as shown in fig. 1B, the delay adjustment subunit 11 is connected between the PMOS transistor T2 in the first-stage inverter P1 and the first operating voltage terminal 1. For example, in the delay adjustment subunit 11 shown in fig. 1B, a first pole (e.g., a source) of the control switch NM1 is connected to a source of the PMOS transistor T2 in the first-stage inverter P1, and a first end of the memristor RRAM is connected to a source of the PMOS transistor T2 in the first-stage inverter P1.

FIG. 2 is a schematic diagram of an exemplary delay computation array; as shown in fig. 2, the delay calculation array 100 includes delay buffer units 10 of 2M rows and N columns (only 4 rows and 2 columns are shown as an example in the figure).

For example, N delay buffer units 10 in each row are connected in series with each other to form one row of delay chains 20, and each two adjacent rows of delay chains 20 constitute one delay processing combination 30. The difference in the delays of two delay buffer units 10 on the same column in each delay processing combination 30 may correspond to a signed weight element, e.g., by configuring the resistance values of memristors in the two delay buffer units 10, the difference in the delays of the two delay buffer units 10 may be made to represent a positive, negative, or zero weight element. That is, two delay buffer units 10 on the same column in each delay processing combination 30 may be used as a differential unit, and the delay of each differential unit may be used to represent a weight element of a positive value, a negative value, or a zero value.

For example, the two rows of delay chains 20 in each delay processing combination 30 receive the same input signal, e.g., the input signal is received through the input of the first delay buffer 10 in each of the two rows of delay chains 20. The input signal may be used to control the mode of operation of the delay computation array 100. For example, the input signal may control whether the delay computing array 100 is in the first mode of operation or the second mode of operation. When the input signal remains at a normally low level (or a normally high level), the delay-computing array 100 is in the first mode of operation; when the input signal is a rising edge trigger signal (or a falling edge trigger signal), the delay computing array 100 is in the second mode of operation.

In the first operation mode, the input signal is, for example, low level, and at this time, a set operation, a reset operation, or the like may be performed on the memristor RRAM. In the second mode of operation, the input signal is input to an edge signal, at which time a calculation operation or a calibration read operation may be performed on the delay calculation array 100, e.g., the delay calculation result or the delay read result is obtained from the output of the delay chain.

For example, the outputs of the two-row delay chains 20 in each delay processing combination 30 output the cumulative delays of the plurality of delay buffer units 10 of the two rows, respectively. For example, as shown in fig. 2, the first row delay chain 20 in the first delay processing combination 30 outputs the cumulative delay t_dlp <0> of the N delay buffer units 10 of the first row from the output terminal DLP <0>, and the second row delay chain 20 outputs the cumulative delay t_dln <0> of the N delay buffer units 10 of the second row from the output terminal DLN <0>.

For example, in one example, when a calculation operation is performed on delay calculation array 100, the difference Δt=t_dlp <0> -t_dln <0> between the cumulative delays of the two rows of delay chains in delay processing combination 30, i.e., output terminal DLP <0> and output terminal DLN <0> output two time signals having the same waveform but having Δt delay.

FIG. 3 is a schematic diagram of an exemplary computing device. For example, the computing device 200 shown in fig. 3 includes a delay computing array 100 and a Time-to-Digital Converter (TDC) for converting a delay signal into a digital signal, including a delay charge conversion module 40 and an analog-to-digital conversion module 50. The delay calculation array 100 includes a plurality of delay processing combinations 30, each delay processing combination 30 including two rows of delay chains 20 that perform differential operations, 3 delay processing combinations 30_a, 30_b, and 30_c being shown as an example in fig. 3. Each delay charge conversion module (TQC) 40 is connected to the output of one delay processing combination 30 of the delay computational array 100. For example, the delay charge conversion module tqc_a is connected to the delay processing combination 30_a, the delay charge conversion module tqc_b is connected to the delay processing combination 30_b, and the delay charge conversion module tqc_b is connected to the delay processing combination 30_b, so as to respectively convert the delay amounts of the output signals of the two rows of delay chains 20 in the corresponding delay processing combination 30 into voltage output signals.

For example, the delayed charge conversion module (TQC) 40 includes a current mirror, current mirror control logic 41, and a capacitive digital to analog converter (CDAC) and corresponding digitally controlled switches. The current mirror is used to provide a current source, for example, to output a stable, controllable operating current.

For example, during the operation of the TQC 40, the delayed charge conversion module 40 employs low power consumption current mirror control logic 41 to ensure timely startup of the current mirror, so that the CDAC is controlled by the current mirror to perform passive integration, thereby quantifying the delay difference output by the delay processing combination 30. When the CDAC performs passive integration, the capacitor in the CDAC performs sampling first and then performs charge distribution, for example, when the capacitor bottom plate voltage is reset to the common mode voltage VCM during sampling, when the charge distribution is performed, according to the comparison result of the comparator, the voltage of the capacitor bottom plate at the end with smaller voltage is switched to the reference voltage VRP, and the voltage of the capacitor bottom plate at the end with larger voltage is switched to the reference voltage VRN.

The time-to-digital converter TDC described above employs a combination of a time-to-charge converter (TQC) and a charge-to-digital converter (QDC). TQC uses digital logic to control the current mirror to passively integrate the capacitance in the CDAC in QDC, followed by quantization by SAR (successive approximation register, successive approximation) ADC (analog to digital converter) to get the final result. Such a circuit configuration can realize lower power consumption, but there is room for improvement. Firstly, when the offset of the chip is large, the accuracy of the calculation result can be ensured by simple digital domain calibration, but the dynamic range loss is increased, and an offset calibration circuit is additionally added; secondly, the hardware cost increases exponentially along with the increase of the dynamic range and the bit number of the circuit, so that the cost of large-scale calculation is increased; finally, the TDC layout is difficult to route due to the limitation of array spacing.

Fig. 4A is a schematic structural diagram of a time-to-digital converter according to at least one embodiment of the present disclosure.

At least one embodiment of the present disclosure provides a time-to-digital converter 300, as shown in fig. 4A, the time-to-digital converter 300 includes a first quantization unit 301, a second quantization unit 302, and an output unit 303, wherein the first quantization unit 301 is configured to perform a first quantization on an input delayed signal to obtain a first quantization result and a time residual signal; a second quantization unit 302 configured to perform a second quantization on the time residual signal to obtain a second quantization result; and an output unit 303 configured to obtain a target quantization result corresponding to the delay signal according to a first quantization result and a second quantization result, wherein the first quantization corresponds to an upper portion of the target quantization result, and the second quantization corresponds to a lower portion of the target quantization result except for the upper portion. An example of this embodiment may be referred to fig. 10, which will be described below.

In the above-described embodiments of the present disclosure, the high-order part and the low-order part of the target quantization result are obtained by performing two kinds of quantization, respectively, which can reduce the additional hardware overhead required for the TDC with an increase in the dynamic range of the circuit.

The obtained target quantized result is stored in a digitized manner, the first quantization results in a high-order part, e.g., M bits, corresponding to the target quantized result, and the second quantization results in a low-order part, e.g., N bits, corresponding to the target quantized result except for the high-order part, whereby the target quantized result has m+n bits in total. For example, during operation, the high-order part of the first quantization is stored in a first register, and the low-order part of the second quantization is added to the high-order part to obtain the target quantization result, which is then stored in the first register, or in another register. These registers are provided, for example, in the output unit 303.

For example, the first quantization unit 301 is further configured to count the input delay signal using the first clock count signal to perform the first quantization. For example, the time-to-digital converter of at least one embodiment of the present disclosure further includes a first counter configured to provide the first clock count signal described above.

In the above embodiment of the present disclosure, the first quantization unit 301 uses the counter to perform coarse counting, so that the dynamic range can be larger, and the offset calibration of the whole circuit can be directly performed in the digital domain, thereby not only ensuring the accuracy of the calculation result, but also not compressing the quantized dynamic range. If the dynamic range is required to be increased, the number of bits of the first clock counter is only required to be increased, and the number of registers is only required to be increased, so that the hardware overhead of the device is smaller along with the increase of the quantization range.

In at least one example, if there is a mismatch in the circuit that causes a deviation, it has little effect on the compression of the dynamic range, calibrated by the digital domain. For example, the output unit 303 may also have a function of digital calibration.

Examples of the first quantization unit and the second quantization unit in the present disclosure are described below according to some specific embodiments.

Fig. 4B is a schematic structural diagram of a first quantization unit according to at least one embodiment of the present disclosure.

In the example shown in fig. 4B, the first quantization unit 301 includes a count quantization subunit 3011 and a residual generation subunit tres_ge, wherein the count quantization subunit 3011 is configured to count according to the first time pulse, the second time pulse, and based on the first clock count signal to obtain a first quantization result; the residual generation subunit tres_ge is configured to acquire an unquantized portion of the delay pulse that is not included in the first quantization based on the delay pulse and the count value, and output the unquantized portion as a temporal residual signal.

The input signal of the time-to-digital converter of this embodiment is a delayed signal P, wherein the delayed signal P is acquired based on a first time pulse and a second time pulse, wherein the second time pulse has a delay with respect to the first time pulse waveform. For example, the first time pulse and the second time pulse may be the output signal of the output terminal DLN <0> and the output signal of the output terminal DLN <0> respectively when the input signals are the same as shown in fig. 2 by the delay processing combination 30, or any two other time signals with the same waveforms but a certain delay, for example, the difference between rising edges of two output pulses pulses T, pulse _b of the differential line can obtain the input pulse pulsesof the TDC.

As shown in fig. 4B, the first time pulse, the second time pulse, and the first clock count signal are input to the first quantization unit 301 to be counted to obtain a first quantization result.

For example, the first clock count signal is a periodic time pulse signal, and the count signal is counted by multiplying the number of periods elapsed by the length (time) of each period. For example, the residual generating subunit tres_ge may be implemented by a DFF (D type flip-flop), that is, an input is a pulse signal, an adopted clock is a clock of the first counter, the DFF outputs a delayed pulse signal, and then exclusive-or-operates the delayed pulse signal and the input signal, thereby generating a time residual signal.

For example, the delay signal P is a delay pulse signal acquired based on the first time pulse and the second time pulse. As further shown in fig. 4B, in at least one example, the count quantization subunit 3011 includes a count value obtaining unit 3012 and a first subtractor SUB, where the count value obtaining unit 3012 is configured to obtain a first count value from a first rising edge (or a first falling edge) of a first clock count signal within the delayed pulse signal, and correspondingly obtain a second count value from a first rising edge (or a first falling edge) of the first clock count signal after the delayed pulse signal; the first subtractor SUB is configured to obtain a first quantization result using the first count value and the second count value.

For example, the count quantization subunit 3011 further includes a first counter C, and the first clock count signal is used to drive the first counter C, that is, the first counter C counts using the clock pulse signal of the first clock count signal. Embodiments of the present disclosure are not limited to a specific implementation form of the first counter C. For example, the first counter C is a global counter that may be shared by a plurality of count quantization subunits.

In the above process, the first counter C is used to count the first time pulse and the second time pulse, the first value is a first digital code corresponding to a first rising edge of the first counter C after a first rising edge of the first time pulse, and the second count value is a second digital code corresponding to a first rising edge of the first counter C after a first rising edge of the second time pulse; the first value may be a digital code corresponding to the first rising edge of the first clock count signal in the duration of the delay signal P in the first counter C, and the second value may be a digital code corresponding to the first rising edge of the first clock count signal after the duration of the delay signal P ends in the first counter C, and the two digital codes are input to the subtractor SUB, and the first value is subtracted from the second value to obtain a first quantized (coarse quantized) result.

In at least one embodiment of the present disclosure, the first counter C may sleep when not in use, and the register of the first counter C may employ a Set-Reset Latch (Set-Reset) structure to reduce power consumption, and read the digital code output by the first counter C at a falling edge of the first clock count signal to improve accuracy of the result.

In the disclosed embodiment, the first rising edge of the first clock count signal within the delay signal P does not normally coincide with the rising edge of the delay signal P, nor does the first rising edge of the first clock count signal outside the delay signal P normally coincide with the falling edge of the delay signal P, and therefore residual portions are generated that cannot be quantized by the first quantization unit, and these residual portions are quantized by the second quantization unit.

Fig. 4C is a schematic structural diagram of a second quantization unit according to at least one embodiment of the present disclosure.

In the example shown in fig. 4C, the second quantization unit 302 includes a sample-and-hold subunit 3021 and a quantization subunit 3022. The sample-and-hold subunit 3021 is configured to sample the time residual signal to obtain a residual signal to be quantized; the quantization subunit 3022 is configured to quantize the residual signal to be quantized to obtain a second quantization result.

In the present disclosure, two ways of implementing the second quantization unit will be exemplarily described below, but embodiments of the present disclosure are not limited to these two ways.

For example, in one example of the second quantization unit of at least one embodiment of the present disclosure, the sample-and-hold subunit 3021 includes at least one CDAC and a current mirror unit, where the CDAC is configured to convert the time residual signal to obtain a residual signal to be quantized as a voltage signal; the current mirror unit is connected to the CDAC and is configured to control the CDAC to perform a passive integration operation according to the time residual signal to obtain a voltage signal. The quantization subunit 3021 includes an analog-to-digital converter (ADC) configured to convert the voltage signal to obtain a second quantization result.

For example, the at least one CDAC includes two CDACs connected in parallel between the current mirror unit and the quantization subunit, and the sample-and-hold subunit further includes two switches respectively disposed between the two CDACs and the current mirror unit, wherein the two CDACs and the two switches respectively form two second quantization channels capable of alternately operating correspondingly.

FIG. 5 is a schematic diagram of a time-to-digital converter according to at least one embodiment of the present disclosure; fig. 6 is a timing diagram illustrating the operation of the time-to-digital converter shown in fig. 5.

A first exemplary implementation of the second quantization unit in an embodiment of the present disclosure is described below with reference to fig. 5 and 6.

In fig. 5, a first counter C, a first subtractor SUB, and a residual generation subunit tres_ge comprised by the first quantization unit are exemplarily shown.

As shown in fig. 5 and 6, in the figure, "keep" represents a periodic signal, for example, an input signal received by a delay chain in the delay calculation array shown in fig. 2, pulse_t is a first time pulse, pulse_b is a second time pulse, P represents a delay signal P in fig. 5 and is obtained by a phase difference between the first time pulse and the second time pulse, clk represents a clock signal and drives a first clock count signal of a first counter C; vx represents the integrated voltage signal obtained by passive integration.

As shown in fig. 6, the first clock count signal clk and the clock delay signal P are compared, a first count value is obtained at a first rising edge (upward arrow on the left) where the first clock count signal clk overlaps with the delay signal P, a second count value is obtained at a first rising edge (upward arrow on the left) where the first clock count signal clk and the delay signal P follow, and a coarse quantization result is obtained from the first count value and the second count value, and these two count values are stored in a register (e.g., a global register, not shown in the figure). Thus, the two inputs of the subtractor SUB are a first count value and a second count value, respectively, corresponding to the rising and falling edges of the delay signal P.

After the coarse quantization of the first quantization operation, the pulse_a that is not quantized and the pulse_b that is not quantized outside the signal in the delay signal P are obtained by a certain digital logic, i.e., the residual error generating subunit tres_ge.

As shown in fig. 6, the rising edge of pulse_a is aligned with the rising edge of clock delay signal P, and the falling edge of pulse_a is aligned with the upward arrow on the left side; the rising edge of pulse_b is aligned with the falling edge of clock delay signal P, and the falling edge of pulse_b is aligned with the upward arrow on the right.

Fig. 5 shows m rows of first quantization units and second quantization units (only 3 rows are drawn as an example in the figure). The second quantization unit comprises, for each row, a time-to-charge converter (TQC) (tqc_ A, TQC _ B, TQC _c is included as an example in the figure), at least one set of differential CDACs, and an analog-to-digital converter (ADC). TQC includes current mirrors (e.g., for implementing current sources/sinks) and control switches SP/SN for them. For example, analog-to-digital converters (ADCs) are common to multiple outputs (rows), e.g., the ADC is an N-bit (N-bit) synchronous SAR ADC.

The example here illustrates two sets of differential CDACs connected to TQC through switches CH1 and CH2, respectively, and connected to ADC through switches conv_1_a, conv_1_B, conv_1_C, and conv_2 (conv_ 2_A, conv_2_B, and conv_2_C, respectively.

For each row, after the time residual signal is sent to the second quantization unit, the TQC controls the current mirror to passively integrate the CDAC through the switches SP and SN, so as to sample, and realize time-charge conversion. Where TQC converts time to voltage Vx by pulling/discharging the current to charge/discharge the capacitor in the CDAC and can adjust the magnitude of the integrated current to adjust the inter-stage gain. The integration directions of pulse_a and pulse_b in TQC are opposite, so that a subtraction operation of the pulse time length (represented by the rising and falling of the voltage Vx in fig. 6) is achieved.

In the above example, for example, when the calculation result time length of the calculation array is smaller than the width of the first stage counter clock, the entire pulse width is pulse_a, and there is no pulse_b integration stage. The quantization is started after the TQC sampling, and because the sampling time is long, a double-channel time interleaving mode is adopted, namely, the output of each differential row corresponds to two groups of differential CDACs, and one group of CDACs is quantized while the other group of CDACs is sampled, so that the throughput rate can be improved.

For example, during the second quantization, the result of each comparator comparison determines whether the capacitive bottom plate switches from the common mode voltage VCM to the reference voltage VRP or the reference voltage VRN.

For example, pulse_a and pulse_b are respectively connected to the control switches SP/SN in the current mirror to respectively control the on-times of the control switches SP/SN. The pulse width of pulses pulsa and pulsb determines the time of integration on the CDAC.

Firstly, a first channel (a channel where a switch CH1 is positioned) is in a sampling state (CH1=1, CH2=0), a capacitive top plate of the first channel is connected to a VCM through current integration, and TQC is in a full parallel state; after the TQC quantization process is completed, the integrated voltage on the capacitor is quantized by the ADC, thereby obtaining a fine quantized digital output (i.e., the second quantization result). The integrated voltage of the first channel is quantized sequentially between a plurality of differential lines by the ADC.

Then, while the integrated voltage adopted by the first channel is quantized by the ADC, the second channel (the channel where the switch CH2 is positioned) is in a sampling state (CH1=0, CH2=1), the capacitance top plate of the second channel is connected to the common-mode voltage VCM through current integration, and TQC is in a fully parallel state; after the TQC quantization process is completed, the integrated voltage on the capacitor is quantized by the ADC, thereby obtaining a fine quantized digital output (i.e., the second quantization result). The sampling process and the quantization process are alternately performed in this way, so that the throughput rate of the system is improved.

For example, as described above, multiple rows of corresponding TQCs may alternately share one SAR ADC serial quantization to reduce area overhead.

The above example of at least one embodiment of the present disclosure may be implemented by a time-to-charge converter with passive integration and a time-to-data converter with low power consumption (e.g., SAR ADC) in combination, and the pipeline architecture improves throughput, compared to performing the time-to-charge conversion with passive integration directly on the delayed signal without coarse quantization, the embodiment of the present disclosure may use more CDACs with multiple bits, which may also be more convenient to wire in a limited layout space, thereby reducing parasitic capacitance and improving computation power and energy efficiency. For example, in at least one example, the second stage performs residual amplification and sampling by digital logic control of the TQCs of the fully differential dual channel while coarse counting, and realizes different inter-stage gains by adjusting the current magnitude, and the multiple TQCs perform quantization of the low-order segment in series by the SAR ADC after parallel sampling.

For example, in another example of the second quantization unit of at least one embodiment of the present disclosure, the sample-and-hold subunit 3021 comprises at least one time signal amplification unit configured to amplify a time residual signal to obtain a residual signal to be quantized, and at least one current mirror unit; the current mirror unit is connected with the time signal amplifying unit and is configured to control an operation of the time signal amplifying unit according to the time residual signal. In this example, the quantization subunit 3022 is further configured to convert the residual signal to be quantized using the second clock count signal to obtain a second quantization result.

For example, the at least one time signal amplifying unit is two time signal amplifying units; the at least one current mirror unit is two current mirror units which are correspondingly connected in series with the two time signal amplifying units; the sample-and-hold subunit further comprises two switches respectively connected between the first quantization unit and the two current mirror units, wherein the two switches, the two current mirror units and the two time signal amplifying units respectively correspondingly form two second quantization channels capable of alternately working.

For example, the at least one current mirror unit is configured to provide a first detection current for a first charge-discharge operation and a second detection current for a second charge-discharge operation. The time signal amplifying unit comprises a working capacitor, a comparing subunit and a control subunit.

The working capacitor is electrically connected with the current mirror unit to perform the first charge-discharge operation or the second charge-discharge operation. The comparing subunit is electrically connected with the working capacitor and the reference voltage and is configured to compare the voltage of the detected polar plate in the working capacitor with the reference voltage; the control subunit is configured to control the current mirror unit to operate, by the comparison subunit, to cause the first charge-discharge operation to charge the detected plate in the working capacitor from the reference voltage to the first voltage with the first detection current for a first period of time determined by the time residual signal, to cause the second charge-discharge operation to discharge the detected plate in the working capacitor from the first voltage to the reference voltage with the second detection current for a second period of time, and to obtain the residual signal to be quantized using a ratio between the second period of time and the first period of time.

For example, the quantization subunit 3022 includes a second subtractor sub_2, and the second subtractor sub_2 is configured to perform subtraction on a third count value and a fourth count value obtained by counting the residual signal to be quantized using the second clock count signal to obtain the second quantization result. For example, the quantization subunit includes a second counter configured to count according to the second clock count signal to obtain a third count value and a fourth count value. I.e. the second counter is driven by a second clock count signal for counting. For example, the quantization subunit 3022 may further include a count value obtaining unit that obtains third count values and fourth count values corresponding to a first edge (for example, a rising edge) and a second edge (for example, a falling edge) of the residual signal to be quantized.

For example, in at least one example, the first clock count signal used by the first quantization unit and the second clock count signal used by the second quantization unit are the same clock count signal. Further, in at least one example, the first counter used by the first quantization unit and the second counter used by the second quantization unit are the same counter, e.g. a global counter, thereby providing a timing signal.

Fig. 7 is a schematic structural diagram of a time-to-digital converter according to at least one embodiment of the present disclosure, and fig. 8 is a timing diagram illustrating the operation of the time-to-digital converter shown in fig. 7.

In fig. 7, a first counter C, a first subtractor SUB, and a residual generation subunit tres_ge comprised by the first quantization unit are also exemplarily shown.

A second implementation of the second quantization unit in the embodiments of the present disclosure is described below with reference to fig. 7 and 8.

In fig. 7 and 8, the meanings of keep, pulse_ T, pulse _ B, p, clk, pulseA, pulseB, etc. and how the first quantization is implemented are the same as in fig. 5 and 6, and are not repeated for the sake of brevity.

In fig. 8, CH1 and CH2 represent the states of the switch CH1 and the switch CH2, respectively, for example, ch1=1 (ch2=1) represents that the switch CH1 (CH 2) is closed, and ch1=0 (ch2=0) represents that the switch CH1 (CH 2) is open; conv_1, conv_2 represent the state of the switches conv_1 and conv_2, respectively, for example conv_1=1 (conv_2=1) represents that the switch conv_1 (conv_2) is closed, conv_1=0 (conv_2=0) represents that the switch conv_1 (conv_2) is open; vx1 and Vx2 represent the integrated voltage signals corresponding to the operating capacitances in the quantized channels, respectively, with out_comp being the result of the comparator output.

Fig. 7 shows m rows of first quantization units and second quantization units (only 3 rows are drawn as an example in the figure). For each row, two current mirror units are respectively connected with the first quantization unit through a switch CH1 and a switch CH2, and two time signal amplifying units are correspondingly connected with the two current mirror units.

As shown in fig. 7, each time signal amplifying unit includes an operating capacitor and a comparator (one comparator is shared by a plurality of second quantizing units in the drawing), the operating capacitor of one time signal amplifying unit is connected to the comparator through a switch conv_1 (shown as conv_1_a, conv_1_B, conv_1_C in the drawing as an example), and the operating capacitor of the other time signal amplifying unit is connected to the comparator as a comparing unit through a switch conv_2 (shown as conv_2_A, conv_2_B, conv_2_C in the drawing as an example).

In the illustrated example, the comparator is shared by a plurality of rows, the non-inverting (+) input of the comparator is used for receiving an input voltage, the inverting (-) input of the comparator is used for receiving a common mode Voltage (VCM) as a reference voltage for the comparator, and the output of the comparator is connected to the second subtractor sub_2. The second subtractor sub_2 is controlled by the output of the comparator and implements the second quantization by a counter. In another example, other fixed voltages (e.g., ground) may also be employed as the reference voltage input to the inverting (-) input of the comparator.

As shown in fig. 8, in the first period of the input signal (key), coarse quantization (first quantization) is performed. After coarse quantization, in the first stage PH1, the current mirror is controlled by the switch SP (or SN) to passively integrate the time residual signals (pulse pulseA and pulse pulseB in the figure) through the working capacitor, the integrated current is I1 provided by the current mirror (e.g. in the form of a first current source), i.e. the working capacitor is subjected to a first charge-discharge operation, and the voltage of the non-grounded electrode plate in the working capacitor is adjusted, e.g. the voltage of the non-grounded electrode plate in the working capacitor is increased, e.g. from a common mode voltage VCM is increased, so that the time signal is converted into a voltage signal (Vx 1 and Vx2 in the figure). In the first charge-discharge operation, the operation capacitor is charged for a period of time corresponding to the pulse pulseA, and the operation capacitor is discharged for a period of time corresponding to the pulse pulseB.

As shown in fig. 8, in the second stage PH2, the current mirror performs a second charge-discharge operation on the capacitor with a smaller integration current I2 through the switch SN (or SP) and the control logic SN (SP) opposite to that in PH1, wherein if the voltage of the non-grounded plate in the working capacitor is higher than the common mode voltage VCM, the working capacitor is discharged, otherwise the working capacitor is charged, the second charge-discharge time counts the start time and the end time through the counter to obtain a third count value and a fourth count value, and performs a subtraction operation on the fourth count value and the third count value in combination with the second subtractor, thereby performing a second quantization.

Here the current I2 is provided by a current mirror (e.g. in the form of a second current source), i2=i1/x, where x is the scaling factor of the current scaling, and since the current I2 is smaller than the current I1, the scaling factor x is larger than 1, e.g. may be larger than 10. Based on conservation of charge, the voltage of the non-grounded plate of the working capacitor is raised from the common mode voltage VCM to a certain voltage and then lowered from this voltage to the common mode voltage VCM, and then the amount of charge involved in the charging process is comparable to the amount of charge involved in the discharging process, which is equal to the product of the current magnitude and the charging or discharging time.

The gain of the time amplifier can be adjusted by adjusting the proportionality coefficient x, the voltage of the non-grounded polar plate of the working capacitor is compared with the VCM in the discharging process, and the charging and discharging are stopped when the voltage of the non-grounded polar plate of the working capacitor is equal to the VCM. Since I2 is smaller than I1, the capacitor discharges at a slower rate than the charge, and thus takes longer to discharge than the charge, so that time amplification is performed by time-to-charge-to-time conversion, and the amplified time signal serves as a residual signal to be quantized.

Fig. 9 is a schematic diagram illustrating a process of time amplifying and counting by the second quantization unit of the time-to-digital converter shown in fig. 7 according to at least one embodiment of the present disclosure.

For example, as shown in fig. 9, in the first stage PH1, the switch SP is closed, the switch SN is opened, the capacitor is charged by the current I1 provided by the current mirror, and the voltage (capacitor voltage) of the non-grounded plate (upper plate in the figure) of the working capacitor is increased from the common mode voltage VCM to vcm+vres, so as to complete the sampling process; in the second phase PH2, the switch SP is opened and the switch SN is closed, the working capacitor is discharged by the current I2 provided by the current mirror, and the capacitor voltage is reduced to the common mode voltage VCM. The comparator compares the capacitance voltage reduction process with the common-mode voltage VCM, so as to perform conversion to obtain a residual signal to be quantized out_comp, combines the residual signal to be quantized out_comp with, for example, a global counter, obtains two count values corresponding to rising edges and falling edges of the residual signal to be quantized out_comp through the global counter, and provides the two count values to the second subtracter sub_2 to subtract the two count values to obtain an amplified second quantization result. Then dividing the amplified second quantized result by the scaling factor x to obtain the required second quantized result.

As shown in fig. 8, the second counter used for the second quantization and the first counter used for the first quantization are the same counter, so that the second clock count signal and the first clock count signal are the same, thereby reducing the additional hardware overhead in the circuit and adopting a smaller layout area.

In the example shown in fig. 8, the comparator circuit can be shared by a plurality of time signal amplifying units corresponding to TQCs, so that the additional hardware cost in the circuit is further reduced, and a smaller layout area is adopted.

In this example, the sampling process and the quantization process may also be alternately performed through two channels, thereby improving the throughput of the system.

For example, when the first channel (the channel where the switch CH1 is located) is in a sampling state, the working capacitor of the first channel integrates through the current I1 (ch1=1, ch2=0), the sampling process is completed, the discharging process is completed through the current I2 integration to obtain a residual signal to be quantized, then the residual signal to be quantized is counted through the global counter, and a second subtracter is used to obtain a fine quantized digital output (i.e. a second quantized result); the integrated voltage of the first channel is quantized among a plurality of differential lines in sequence, and meanwhile, the second channel (the channel where the switch CH2 is located) is in a full parallel sampling state.

The fine quantization scheme of the second example described above employs a time domain amplification technique, i.e., time-charge-time amplification, and the amplified time signal is quantized for the low-order segment with a counter (e.g., a globally shared counter), and coarse quantization and fine quantization may be performed in a pipelined manner.

In addition to integrating and discharging with the working capacitor, in the fine quantization scheme of the second example, in comparison with the fine quantization scheme of the previous example, in order to implement time interleaving, the current mirror circuit also needs to adopt a dual-channel structure, i.e., the switches CH1 and CH2 are alternately turned on in two stages to sample and quantize the residual error; also, the ADC circuit is omitted by quantization using a counter and a subtractor, so that the fine quantization scheme in the second example requires less additional hardware overhead for the increase of the dynamic range and consumes less power.

The quantization method of the TDC based on coarse-fine quantization according to at least one embodiment of the present disclosure can increase the sampling rate. In contrast to the scheme in which coarse counting is not used to directly perform sampling quantization, the number of bits required is higher, and the hardware overhead increases almost exponentially with the increase of the dynamic range and the number of bits, at least one embodiment of the present disclosure, because the coarse quantization part is a counter, the quantifiable range of the coarse quantization part is exponentially related to the number of bits of the counter, that is, the additional hardware overhead required for the increase of the dynamic range is smaller, and the layout complexity of the fine quantization part can be reduced, so that the power consumption and the area can be reduced, and the calculation force, the energy efficiency and the calculation force density can be improved, for example, in one exemplary scheme, the previous simulated power consumption can be compressed to 2/3 of the scheme in which the coarse counting is not used before, and the layout area can be compressed to 1/2 of the previous scheme. At least one embodiment of the present disclosure avoids all time signals from being converted into digital signals through low-order quantization by a two-stage quantization structure, and reduces power consumption of time-to-digital conversion.

At least one embodiment of the present disclosure also provides a digital readout circuit comprising a plurality of time-to-digital converters as in any one of the above embodiments.

As shown IN fig. 10, the digital readout circuit is a block diagram of an m+n-bit time-to-digital converter readout circuit based on coarse-fine quantization, the input signal in_p (e.g., the first behavior in_1) may be, for example, pulse_t and pulse_b shown IN fig. 6 or fig. 8, the first STAGE1 includes a subtractor and a residual generation module, and the global synchronization counter and the subtractor are used to perform coarse quantization on the input signal in_p (e.g., the first behavior in_1) to obtain a first quantized result of M-bits (M-bits), and the residual generation module generates a residual signal according to a portion of the input signal in_p that is not included by the first quantization; the second STAGE2 includes a sample-and-hold amplifier and a fine quantization unit, wherein the sample-and-hold amplifier is configured to sample and store a residual signal output from the first STAGE1, and then perform a second quantization on the residual signal by the fine quantization unit to obtain a second quantization result of N-bits (N-bits), and the first quantization result and the second quantization result are output to a digital calibration and output register, so that the output result can be calibrated and stored to obtain a quantization result of m+n bits, where the first quantization result of M bits is the upper M bits of the obtained quantization result and the second quantization result of N bits is the lower N bits of the obtained quantization result.

As shown in fig. 10, the subtractor (coarse quantization) may be, for example, the first subtractor described in any one of the above embodiments; the residual generating module may be, for example, the residual generating subunit tres_ge according to any of the above embodiments, and the output of the residual generating module may be, for example, pulse pulseA and pulse pulseB as shown in fig. 6 or 8; the sample-and-hold amplifier may be, for example, a sample-and-hold subunit as described in any of the above embodiments, and the fine quantization unit may be, for example, a quantization subunit as described in any of the above embodiments.

The whole digital readout circuit further comprises a common-mode voltage module, a bias generation module and a reference voltage module, wherein the bias generation module is configured to generate a bias current, for example, to provide the bias current for the current mirror, the reference voltage module and the common-mode voltage module are configured to generate voltages used by the second quantization unit, for example, the reference voltage provides voltages VRP and VRN as shown in fig. 3, and the common-mode voltage provides voltage VCM as shown in fig. 3 or fig. 6 or fig. 8.

The disclosure further provides an electronic device, which includes a delay calculation array and the digital readout circuit according to any one of the above embodiments, wherein the delay calculation array includes a plurality of output ports, and is correspondingly connected to the plurality of time-to-digital converters respectively. The delay computation array may be, for example, of the structure shown in fig. 2.

The electronic device may be, for example, a processor or any other product or component that includes the processor in combination with the processor. For another example, the electronic device may be a server device or a terminal device, and for example, the terminal device may be a mobile phone, a notebook computer, or the like.

It is to be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, however, the present disclosure is not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the disclosure, and are also considered to be within the scope of the disclosure.

For the purposes of this disclosure, the following points are also noted:

(1) The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

(2) In the drawings for describing embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced for clarity, i.e., the drawings are not drawn to actual scale.

(3) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.

The foregoing is merely specific embodiments of the disclosure, but the scope of the disclosure is not limited thereto, and the scope of the disclosure should be determined by the claims.

Claims

1. A time to digital converter comprising:

a first quantization unit configured to perform a first quantization on the input delayed signal to obtain a first quantization result and a time residual signal;

a second quantization unit configured to perform a second quantization on the temporal residual signal to obtain a second quantization result;

and an output unit configured to obtain a target quantization result corresponding to the delay signal according to the first quantization result and the second quantization result, wherein the first quantization corresponds to an upper portion of the target quantization result, and the second quantization corresponds to a lower portion of the target quantization result except for the upper portion.

2. The time-to-digital converter of claim 1, wherein the first quantization unit is further configured to count the input delay signal using a first clock count signal to perform the first quantization.

3. The time-to-digital converter of claim 2, further comprising:

A first counter configured to provide the first clock count signal.

4. The time-to-digital converter of claim 2, wherein the delay signal is acquired based on a first time pulse and a second time pulse, wherein the second time pulse has a delay relative to the first time pulse waveform;

the first quantization unit includes:

a count quantization subunit configured to count according to the first time pulse, the second time pulse, and based on the first clock count signal to obtain the first quantization result;

a residual generation subunit configured to acquire an unquantized portion of the delay pulse that is not included in the first quantization based on the delay pulse and the count value, and output the unquantized portion as the time residual signal.

5. The time-to-digital converter of claim 4, wherein the delay signal is a delay pulse signal acquired based on the first time pulse and the second time pulse, the count quantization subunit comprising:

a count value acquisition unit configured to acquire a first count value from a first rising edge of the first clock count signal within the delayed pulse signal, and correspondingly acquire a second count value from a first rising edge of the first clock count signal after the delayed pulse signal;

A first subtractor configured to obtain the first quantization result using the first count value and the second count value.

6. The time-to-digital converter of any of claims 1-5, wherein the second quantization unit comprises:

a sample-and-hold subunit configured to sample the temporal residual signal to obtain a residual signal to be quantized;

and the quantization subunit is configured to quantize the residual signal to be quantized to obtain the second quantization result.

7. The time-to-digital converter of claim 6, wherein the sample-and-hold subunit comprises:

at least one capacitive digital-to-analog converter configured to convert the time residual signal to obtain a residual signal to be quantized as a voltage signal;

a current mirror unit connected to the at least one capacitive digital-to-analog converter and configured to control the at least one capacitive digital-to-analog converter to perform a passive integration operation based on a time residual signal to obtain the voltage signal;

wherein the quantization subunit comprises an analog-to-digital converter configured to convert the voltage signal to obtain the second quantization result.

8. The time to digital converter of claim 7, wherein the at least one capacitive digital to analog converter comprises two capacitive digital to analog converters connected in parallel between the current mirror unit and the quantization subunit,

the sample-and-hold subunit further comprises two switches respectively arranged between the two capacitive digital-to-analog converters and the current mirror unit,

wherein, the two capacitive digital-to-analog converters and the two switches respectively form two second quantization channels which can work alternately.

9. The time-to-digital converter of claim 6, wherein the sample-and-hold subunit comprises:

at least one time signal amplifying unit configured to amplify the time residual signal to obtain a residual signal to be quantized;

at least one current mirror unit connected to the time signal amplifying unit and configured to control an operation of the time signal amplifying unit according to the time residual signal;

wherein the quantization subunit is further configured to convert the residual signal to be quantized using a second clock count signal to obtain a second quantization result.

10. The time-to-digital converter of claim 9, wherein the at least one time signal amplifying unit is two time signal amplifying units;

the at least one current mirror unit is two current mirror units which are correspondingly connected in series with the two time signal amplifying units;

the sample-and-hold subunit further comprises two switches connected between the first quantisation unit and the two current mirror units respectively,

wherein the two switches, the two current mirror units and the two time signal amplifying units respectively form two second quantization channels capable of alternately working correspondingly.

11. The time-to-digital converter of claim 9, wherein the quantization subunit comprises a second subtractor and the second subtractor is configured to subtract a third count value and a fourth count value counted on the residual signal to be quantized using the second clock count signal to obtain the second quantization result.

12. The time to digital converter of claim 10, wherein the quantization subunit comprises a second counter configured to count according to the second clock count signal to obtain the third count value and the fourth count value.

13. The time-to-digital converter of claim 9, wherein,

the at least one current mirror unit is configured to provide a first detection current for a first charge-discharge operation and a second detection current for a second charge-discharge operation;

the time signal amplifying unit includes:

a working capacitor electrically connected to the current mirror unit to perform the first charge and discharge operation or the second charge and discharge operation;

a comparing subunit electrically connected with the working capacitor and the reference voltage and configured to compare the voltage of the detected polar plate in the working capacitor with the reference voltage;

a control subunit configured to control a current mirror unit to operate, by the comparing subunit, to cause the first charge-discharge operation to charge the detected plate in the working capacitor from the reference voltage to a first voltage with the first detection current in a first period of time determined by the time residual signal, to cause the second charge-discharge operation to discharge the detected plate in the working capacitor from the first voltage to the reference voltage with the second detection current in a second period of time, and to obtain the residual signal to be quantized using a ratio between the second period of time and the first period of time.

14. A digital readout circuit comprising a plurality of time-to-digital converters as claimed in any one of claims 1 to 14.

15. An electronic device, comprising:

a delay calculation array;

the digital readout circuit of claim 14, wherein the delay computation array comprises a plurality of output ports respectively correspondingly connected to the plurality of time-to-digital converters.