CN117480617A - Semiconductor device having ferroelectric layer around channel and method for forming semiconductor device on substrate - Google Patents

Semiconductor device having ferroelectric layer around channel and method for forming semiconductor device on substrate Download PDF

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Publication number
CN117480617A
CN117480617A CN202180099203.9A CN202180099203A CN117480617A CN 117480617 A CN117480617 A CN 117480617A CN 202180099203 A CN202180099203 A CN 202180099203A CN 117480617 A CN117480617 A CN 117480617A
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stack
layer
semiconductor device
substrate
gate
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克里希纳·库马尔·布瓦尔卡
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/223—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using MOS with ferroelectric gate insulating film
    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/18—Peripheral circuit regions

Abstract

A semiconductor device is provided comprising at least a first silicon (Si) element (208A) and a second Si element (208B) on a substrate, and a ferroelectric layer (212) surrounding the first Si element and the second Si element on at least three sides, and a gate structure (214, 218, 206) arranged around the ferroelectric layer. The silicon element may be a nanowire (208A ) or laterally spaced fins (408A, 408B, 508A, 508B). Two laterally spaced fin or nanowire stacks may be separated by a ferroelectric material and possibly an additional dielectric material.

Description

Semiconductor device having ferroelectric layer around channel and method for forming semiconductor device on substrate
Technical Field
The present invention relates generally to the field of semiconductor devices; more particularly, the present invention relates to semiconductor devices and methods for forming semiconductor devices on substrates.
Background
Generally, a semiconductor device is an electronic device whose function is based on the electronic characteristics of semiconductor materials such as silicon (Si), germanium (Ge), gallium arsenide, and the like. The semiconductor device is fabricated as a single device or as an integrated circuit (integrated circuit, IC) device. Well known semiconductor devices are known as metal oxide semiconductor field effect transistors (metal oxide semiconductor field-effect transistor, MOSFETs) which include a drain terminal, a source terminal and a gate terminal. However, another well-known semiconductor device with partially improved performance, known as a fin field-effect transistor (FinFET), is selected as a multi-gate device instead of a conventional MOSFET. Such FinFET devices include two or more gate terminals that are located on two or three sides of a channel made from the source and drain terminals of the FinFET device, and therefore, the FinFET device exhibits better conduction characteristics, superior short channel behavior, lower switching times, and higher current densities than known MOSFET devices.
Currently, a gate-all-around (GAA) nano-sheet (NS)/Nanowire (NW) device has been proposed as an alternative to FinFET devices or FinFET-based complementary metal oxide semiconductor (complementary metal oxide semiconductor, CMOS) logic devices (e.g., for contemporary microprocessors, memory cells, etc.). GAA NS/NW devices are conceptually similar to FinFET devices, except that all sides of the channel have multiple gate enclosures, which improves some of the performance compared to FinFET devices. System-on-a-chip (SoC) applications of CMOS technology require co-integration of different types of devices or transistors. For example, in addition to devices for high speed and low power logic, such as core devices, high voltage I/O transistors, i.e., I/O devices, capable of operating at high supply voltages must also be implemented. However, such co-integration may present challenges due to the limited NS-NS space. A conventional method for integrating core GAA devices with Fin (Fin) I/O is designed, where Fin I/O requires an additional selective stack etch and a separate selective silicon (Si) epitaxial (epi) process. Therefore, the whole process is costly and is prone to variability problems. Yet another method for integrating a core GAA device with a partial GAA (pGAA) I/O is provided. pGAA I/O is least complex and therefore cost-effective to manufacture relative to core GAA devices. pGAA I/O fabrication follows a core process, NW/NS release etch, followed by gate oxidation. However, this approach may suffer from severe short channel effect (short channel effect, SCE) degradation due to imperfect gate control. Another method for integrating the core GAA device with the superlattice I/O is also devised. Superlattice I/O are easy to manufacture (because they are skipped from etching) relative to core GAA devices and therefore cost-effective. However, superlattice I/O presents several basic/process issues. For example, the gate oxidation process optimization for each Si/SiGe interface, pFET threshold voltage mismatch (about 100 mV) between Si and SiGe regions, and nFET compressive stress induced by the SiGe-Si layer. Thus, conventional pGAA and FinFET I/O devices have technical problems in that they are deficient in basic characteristics in terms of performance and stress when co-integrated with core devices.
Thus, in light of the above discussion, there is a need to overcome the above-described drawbacks associated with conventional methods for forming semiconductor devices on substrates (i.e., conventional methods of forming semiconductor devices on substrates).
Disclosure of Invention
The present invention seeks to provide an improved semiconductor device comprising at least a first Si element and a second Si element on a substrate. The present invention also seeks to provide an improved method for forming a semiconductor device on a substrate (i.e. an improved method of forming a semiconductor device on a substrate) comprising at least a first Si element and a second Si element on said substrate. The present invention provides a solution to the existing problems of conventional GAA and FinFET I/O devices that suffer from substantial deficiencies in performance and stress relative to commonly integrated I/O devices. It is an object of the present invention to provide a solution at least partly overcoming the problems encountered in the prior art and to provide a semiconductor device comprising at least a first Si element and a second Si element on a substrate, and an improved method for forming a semiconductor device comprising at least a first Si element and a second Si element on a substrate (i.e. an improved method of forming a semiconductor device comprising at least a first Si element and a second Si element on a substrate).
One or more of the objects of the invention are achieved by the solution provided in the attached independent claims. Advantageous implementations of the invention are further defined in the dependent claims.
In one aspect, the present invention provides a semiconductor device comprising at least a first silicon (Si) element and a second Si element on a substrate, and a ferroelectric layer surrounding the first Si element and the second Si element on at least three sides, and a gate stack arranged around the ferroelectric layer.
The disclosed semiconductor device comprises a ferroelectric layer surrounding the Si element on at least three sides, because the negative capacitance (negative capacitance, NC) improves the swing in pGAA I/O devices. Thus, although the I/O device is pGAA, NC characteristics of the semiconductor device exhibit improved performance. In addition, the disclosed semiconductor device reduces common integration challenges because integration is accomplished with conventional GAA flows, thereby rendering it cost-effective. In addition, the single gate disposed around the ferroelectric layer in the disclosed semiconductor device supports aggressive scaling of fin pitch and improves performance by reducing parasitic capacitance.
In one implementation, each of the first Si element and the second Si element is surrounded by a gate insulation layer. The at least first and second Si elements include at least two Si layers stacked on each other in a direction from the substrate, and each gate insulating layer is completely surrounded by the ferroelectric layer.
Advantageously, the ferroelectric layer surrounds the SI layer in the SI element on at least three sides to improve NC swing in the iron-pGAA I/O device. In one embodiment, the Si element may appear as a Nanowire (NW) or Nanoplatelet (NS) to obtain a better power performance index for logic applications of advanced sub-5 nm technology nodes. Vertical NW/NS GAAFET can implement high density memory cells such as static random-access memory (SRAM) (with improved read-write stability). The vertical NW/NS GAA FET may also be used as a selector device for a super-large magnetoresistive-resistive random access memory (MRAM) memory with lower power consumption values. Such cells may be fabricated by a cost-effective common integration scheme with a tri-gate FinFET or lateral NW/NS GAA FET high-performance logic platform to increase on-chip memory content. Despite the partial GAA scheme, performance may be improved due to NC characteristics. Such semiconductor devices (e.g., iron-pGAA devices) exhibit higher expected performance as a function of drive current versus applied voltage than other devices such as pGAA and superlattice devices.
In another implementation, the at least first and second Si elements are fins, each fin contacting the substrate through one side, the other side of the fin being surrounded by the ferroelectric layer.
It is advantageous to use the first Si element and the second Si element as fins, because the resulting FinFET provides better SCE, and thus channel doping is optional. This may mean that the FinFET is less affected by dopant-induced variations. Low channel doping ensures better mobility of carriers in the channel and thus higher performance. The FinFET further provides higher drive currents for a given transistor footprint (foltprint) and thus higher speed, lower leakage, lower power consumption, and no random dopant fluctuations, and thus better transistor mobility and scalability, beyond 28nm.
In another implementation, the gate stack is arranged to surround the ferroelectric layer in such a way that the gate stack partially surrounds each Si layer.
With this arrangement, the gate structure improves gate control by increasing gate-channel coupling, reducing off-state current, and reducing SCE.
In another implementation, the semiconductor device is an input/output (I/O) device.
It is advantageous to have an iron-pGAA or Fe-FinFET device as a semiconductor device for I/O applications because the I/O device operates at a relatively high supply voltage (2.5V to 1.8V) to support peripheral devices. The high supply voltage requires a thicker oxide thickness (about 4.5 nm) at larger gate lengths (100 nm to 250 nm).
In another implementation, comprising one or more semiconductor devices according to any of the preceding claims and one or more core devices, wherein the space between each semiconductor device and the core device is filled with ferroelectric material.
It is advantageous to fill all the space between each semiconductor device and the core device with ferroelectric material during the oxide formation. The ferroelectric material may be a hafnium-based oxide having a high dielectric constant (e.g., a k value above about 3.9) and ferroelectric behavior. The ferroelectric material reduces the subthreshold voltage swing of the semiconductor device below the threshold of 60 mV/decade. Thus, fefets require lower operating voltages to produce the same current density as MOSFETs and use less power, thereby increasing battery life, reducing energy costs and heating value. Furthermore, fefets exhibit lower off currents compared to MOSFETs due to their steeper sub-threshold voltage swing (e.g., <60 mV/decade).
In another aspect, the present invention provides a method for forming a semiconductor device on a substrate (i.e., a method of forming a semiconductor device on a substrate). The method comprises the following steps: providing a first stack of alternating layers of SiGe and Si on a substrate comprising at least two Si layers, said first stack being intended to form said semiconductor device; removing the SiGe layer of the first stack; applying a gate insulation layer around each Si layer of the first stack; applying a ferroelectric layer around each gate insulating layer in such a manner that two or more ferroelectric layers are in physical contact with each other; a gate stack is formed around the ferroelectric layer.
The disclosed method proposes that the semiconductor device is an I/O device. The method further includes forming a core device on the same substrate, including providing a second stack of alternating layers of SiGe and Si on the substrate, the second stack being intended to form the core device. Before applying the ferroelectric layer around the gate insulating layer in the first stack, the method comprises the steps of: removing the SiGe layer on the second stack; applying a gate insulation layer around each Si layer in the second stack; applying a mask over the first stack; forming a gate stack over the second stack; applying a mask over the second stack; the mask on the first stack is removed.
The disclosed method proposes the steps of, before removing the SiGe layer: forming a dummy gate around the first stack and the second stack; forming spacers and S/D epi on the first stack and the second stack; the dummy gate is removed from the first stack and the second stack. The method further includes the step of forming contacts to the I/O devices in a conventional manner.
It should be appreciated that all of the above implementations may be combined in various ways.
It should be noted that all devices, elements, circuits, units and modules described in this application may be implemented by software or hardware elements or any type of combination thereof. All steps performed by the various entities described in this application, as well as the functions described to be performed by the various entities, are intended to indicate that the respective entities are adapted to or for performing the respective steps and functions. Although in the following description of specific embodiments, a particular function or step performed by an external entity is not reflected in the description of a specific detailed element of the entity performing the particular step or function, it should be clear to a skilled person that the methods and functions may be implemented in corresponding hardware or software elements or any combination thereof. It will be appreciated that features of the invention are susceptible to being combined in various combinations without departing from the scope of the invention as defined by the accompanying claims.
Other aspects, advantages, features and objects of the invention will become apparent from the accompanying drawings and the detailed description of illustrative implementations explained in conjunction with the following appended claims.
Drawings
The foregoing summary, as well as the following detailed description of illustrative embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there is shown in the drawings exemplary constructions of the invention. However, the invention is not limited to the specific methods and instrumentalities disclosed herein. Moreover, those skilled in the art will appreciate that the drawings are not drawn to scale. Identical elements are denoted by the same numerals, where possible.
Embodiments of the invention will now be described, by way of example only, with reference to the following figures, in which:
FIG. 1 is a diagram of a side view of a semiconductor assembly provided by an embodiment of the present invention, the semiconductor assembly including one or more semiconductor devices (e.g., one semiconductor device) and one or more core devices (e.g., one core device);
fig. 2 is a diagram of a side view of a semiconductor device provided by an embodiment of the present invention, the semiconductor device including a substrate and a FET formed on the substrate;
FIG. 3 is a diagram of a side view of a semiconductor assembly including one or more semiconductor devices (e.g., one semiconductor device) and one or more core devices (e.g., one core device) provided by an embodiment of the present invention;
fig. 4 is a side view of a semiconductor device provided by an embodiment of the present invention, the semiconductor device including fins and sub-fins, a dielectric barrier, and a FET formed on a substrate;
fig. 5 is a side view of a semiconductor device provided by an embodiment of the present invention, the semiconductor device including fins and sub-fins, and a FET formed on a substrate;
fig. 6A to 6I collectively illustrate a method for forming a semiconductor device (i.e., a method of forming a semiconductor device) provided by an embodiment of the present invention;
Fig. 7A is a flowchart of a method for forming a semiconductor device on a substrate (i.e., a method for forming a semiconductor device on a substrate) provided by an embodiment of the present invention;
fig. 7B is a flowchart of a method for forming a core device on the same substrate (i.e., a method for forming a core device on a substrate) provided by an embodiment of the present invention;
in the drawings, the underlined numbers are used to denote items where the underlined numbers are located or items adjacent to the underlined numbers. The non-underlined numbers are associated with items identified by lines associating the non-underlined numbers with the items. When a number is not underlined and has an associated arrow, the number without the underline is used to identify the general item to which the arrow points.
Detailed Description
The following detailed description illustrates embodiments of the invention and the manner in which the embodiments may be implemented. While a few modes of carrying out the invention have been disclosed, those skilled in the art will appreciate that there may be other embodiments for carrying out or practicing the invention.
In fig. 1, a side view of a semiconductor assembly 100 provided by an embodiment of the present invention is shown, the semiconductor assembly 100 including one or more semiconductor devices (e.g., semiconductor device 102) and one or more core devices (e.g., core device 122). Referring to fig. 1, a side view of a semiconductor device 102 is shown, the semiconductor device 102 including a substrate 104 and a field effect transistor (field effect transistor, FET) 106 formed on the substrate 104. The semiconductor device 102 includes a first silicon (Si) element 108A and a second silicon element 108B. The semiconductor device 102 further includes a first gate insulating layer 110A and a second gate insulating layer 110B surrounding the first Si element 108A and the second Si element 108B, respectively. The semiconductor device 102 further includes a ferroelectric layer 112 surrounding the first gate insulating layer 110A and the second gate insulating layer 110B on all four sides. The semiconductor device 102 further includes a gate stack 114 disposed around the ferroelectric layer 112. The substrate 104 of the semiconductor device 102 is isolated from other substrates on either side by an isolating material, such as thermally grown oxide 116.
As shown in fig. 1, according to one embodiment, the first Si element 108A and the second Si element 108B include two Si layers stacked on top of each other in a direction from the substrate 104 and are completely surrounded by the ferroelectric layer 112. The first Si element 108A and the second Si element 108B, which are surrounded by the first gate insulation layer 110A and the second gate insulation layer 110B, respectively, are further jointly surrounded by the ferroelectric layer 112 to form a first arrangement, contacting the substrate 104 through one side. With the other three sides, the gate stack 114 is arranged to enclose the ferroelectric layer 112 in such a way that each Si layer is partially enclosed by the gate stack 114.
According to an embodiment of the present invention, as shown in fig. 1, the semiconductor device 102 may include a third gate insulation layer 110C for isolating two Si layers stacked on each other in the FET 106 from the substrate 104. The third gate insulation layer 110C is used to electrically isolate one or more layers or nanoplates of two Si layers stacked near the substrate 104 from the substrate 104.
The substrate 104, also referred to as a single wafer or chip, is composed of a semiconductor material such as silicon (Si) or germanium (Ge). In one embodiment, a p-type dopant may be added to the semiconductor material of the substrate 104. Thus, the substrate 104 may also be referred to as a p-type semiconductor. In general, p-type semiconductors are semiconductors in which most of the charge carriers are holes. Examples of p-type dopants are, but are not limited to, boron (B), indium (In), and the like. The substrate 104 may also have isolation characteristics. In another embodiment, the substrate 104 may have n-type doping and, thus, may be referred to as an n-type semiconductor. Generally, an n-type semiconductor is a semiconductor in which most charge carriers are electrons. Examples of n-type semiconductors are, but are not limited to, phosphorus (P), arsenic (As), antimony (Sb), and the like.
The FET 106 is a transistor that uses an electric field to control the flow of current. The FET 106 is used to apply a voltage signal to the gate stack 114 such that conductivity exists between the source and drain regions (not shown) of the FET 106, thereby controlling current flow. In one case, when the substrate 104 is a p-type semiconductor, the FET 106 formed on the substrate 104 is an N-type FET (or N-FET). In another case, when the substrate 104 is an n-type semiconductor, the FET 106 will be a P-type FET (or P-FET).
According to one embodiment, as shown in FIG. 1, FET 106 of semiconductor device 102 and FET 126 of core device 122 are fabricated as a gate-all-around (GAA) structure. Thus, the FET 106 of the semiconductor device 102 may also be referred to as FeFET pGAA NS, pFe-GAA, FE-FET I/O devices, and iron pGAA I/O devices without departing from the scope of the present invention. On the other hand, the FET 126 of the core device 122 may also be referred to as a core GAA or core device GAA.
Corresponding to the various devices such as the semiconductor device 102 and the core device 122, the semiconductor assembly 100 includes various regions of a substrate having one or more field-effect transistors (FETs) formed thereon. For example, a region of a substrate (e.g., substrate 104) has a FET 106 formed thereon, corresponding to the semiconductor device 102. Further, another region of the substrate (e.g., substrate 124) has a FET 126 formed thereon, corresponding to the core device 122. Although not shown for simplicity, FET 106 also includes source and drain regions that flank the vertical stack such that the first arrangement is configured to provide a conductive path between the source and drain regions in accordance with a voltage signal applied to gate stack 114. The source and drain regions of FET 106 are formed on the sides (e.g., left and right) of the vertical stack. The source and drain regions may be formed by n-type doping into silicon (Si) or germanium (Ge) or silicon-germanium (SiGe) semiconductor material. Thus, the source and drain regions may also be referred to as n-type semiconductors. The source and drain regions may be one or more of the FETs 106, which may be epitaxially formed on the substrate 104. In the semiconductor device 102, the third gate insulating layer 110C performs electrical insulation to maintain channel stress (or stress between the source and drain regions) that further maintains the performance (or performance-power trade-off design) of the semiconductor device 102. In this manner, semiconductor device 102 exhibits a stack of nanoplatelets to provide conduction between the source and drain regions.
The first Si element 108A and the second Si element 108B may correspond to silicon elements forming channels in the gate stack 114 to provide conduction between source and drain regions of the semiconductor device 102. According to one embodiment, as shown in fig. 1, the first Si element 108A and the second Si element 108B are represented by nanoplates forming a vertical stack in a direction from the substrate 104. The nanoplatelets increase current or narrow to limit power consumption and promote expansion and performance of the semiconductor device 102. Broadly speaking, fabrication of nanoplatelets requires sacrificial layers, selective chemical etchants, and advanced atomic scale precision deposition techniques. Such FETs 106 having nanoplatelets (e.g., first Si element 108A and second Si element 108B) may be referred to as fefets pGAA NS or pGAA FET NS.
The first gate insulating layer 110A and the second gate insulating layer 110B may correspond to gate dielectric layers on the channel, represented by the first Si element 108A and the second Si element 108B, respectively, in the FET 106. The gate dielectric layer may include an interfacial layer (interfacial layer, IL) deposited by one of a variety of suitable methods, such as atomic layer deposition (atomic layer deposition, ALD), chemical vapor deposition (chemical vapor deposition, CVD), and ozone oxidation. IL may include oxides, oxynitrides, and HfSiO. The gate dielectric layer may also include a high-k (HK) dielectric layer deposited over the IL by a suitable technique such as ALD, CVD, metal Organic CVD (MOCVD), physical vapor deposition (physical vapor deposition, PVD), thermal oxidation, combinations thereof, or other suitable technique. The HK dielectric layer may include LaO, ta2O5, Y2O3, srTiO3 (STO), baTiO3 (BTO), alO, zrO, tiO, baZrO, hfZrO, hfTaO, hfSiO, (Ba, sr) TiO3 (BST), al2O3, si3N4, hfLaO, hfSiO, laSiO, alSiO, oxynitride (SiON), or other such materials.
The third gate insulating layer 110C may also correspond to a gate dielectric layer as a buried oxide layer between the substrate 104 and the FET 106 formed on the substrate 104 of the semiconductor device 102. The third gate insulating layer 110C reduces parasitic junction capacitance of the semiconductor device 102. The reduced parasitic capacitance may enable lower delay, dynamic power consumption, thereby improving the performance of the semiconductor device 102. The third gate insulation layer 110C reduces unwanted leakage paths away from the gate stack 114, thereby reducing power consumption.
The ferroelectric layer 112 is a ferroelectric material sandwiched between the gate stack 114 and the source-drain conductive regions of the semiconductor device 102, i.e., the channels formed by the first Si element 108A and the second Si element 108B. The characteristics of ferroelectric layer 112, referred to as permanent electric field polarization, cause semiconductor device 102 to remain in its state (on or off) without any electrical bias. Thus, the channel conductance is used to detect the polarization state in the ferroelectric layer 112, so that the data read operation in the semiconductor device 102 is lossless. The FET 106 including the ferroelectric layer 112 surrounding the first gate insulating layer 110A and the second gate insulating layer 110B on all four sides may be referred to as a ferroelectric field effect transistor (ferroelectric field-effect transistor, fe-FET). Various features of such Fe-FETs may include, but are not limited to, fast switching speeds in ferroelectric materials, non-destructive readout, non-volatile memory states, and simple structures for high density integration. Hafnium zirconium oxide (hf0.5zr0.5o2) (hafnium zirconium oxide, HZO) may be used as the ferroelectric material in the ferroelectric layer 112 according to an embodiment of the present invention.
According to one embodiment, a negative capacitance (negative capacitance, NC) gate insulator in FET 106, i.e., fe-FET, may be used to reduce the subthreshold swing (subthreshold swing, SS) associated with FET 106 below the Boltzmann limit of 60mV/decade, which in turn defines a lower limit for power consumption. Accordingly, the NC gate insulator in the FET 106 having HZO can realize abrupt SS without losing the drive current.
The gate stack 114 in the FET 106 is a conductive element, to which the FET 106 is able to control the flow of current when a voltage is applied, which in turn changes the conductivity between the drain and source regions. Based on one configuration, as shown in fig. 1, the gate stack 114 in the FET 106 is arranged to surround the ferroelectric layer 112 in such a way as to completely surround the first gate insulating layer 110A and the second gate insulating layer 110B, which first gate insulating layer 110A and second gate insulating layer 110B further surround the first Si element 108A and the second Si element 108B.
Thermally grown oxide 116 is an isolation material used to isolate substrate 104 of semiconductor device 102 from other substrates of other devices, such as core device 122 (e.g., substrate 124). According to one embodiment, shallow trench isolation (shallow trench isolation, STI) technology can be used for technologies below 0.5 μm because it completely avoids bird's beak shaped features. STI is a suitable technique for increasing density requirements due to its zero oxide field encroachment, as it can form smaller isolation regions. During STI, shallow trenches are etched into a silicon substrate (e.g., substrate 124). After the underetching of the oxide pad, thermal oxide in the trench is also grown, i.e., liner oxide. The thermal oxidation process stops after the thin oxide layer is formed and the remainder of the trench fills with deposited oxide. Excess (deposited) oxide is removed by chemical mechanical planarization and finally, the nitride mask is also removed.
Referring to the core device 122 shown in fig. 1, a side view of a substrate 124 and FETs 126 formed on the substrate 124 are shown. The core device 122 includes a first Si element 128A and a second Si element 128B. The core device 122 also includes a first gate insulation layer 130A and a second gate insulation layer 130B surrounding the first Si element 128A and the second Si element 128B, respectively. The core device 122 also includes a gate stack 132 surrounding the first gate insulation layer 130A and the second gate insulation layer 130B on all four sides. The core device 122 also includes a Hard Mask (HM) layer 134 disposed around the gate stack 132. The substrate 124 of the core device 122 is isolated from other substrates (e.g., the substrate 104) of other devices (e.g., the semiconductor device 102) on either side by an isolation material (e.g., the thermally grown oxide 136).
It should be noted that the substrate 124, the first Si element 128A, the second Si element 128B, the first gate insulation layer 130A, the second gate insulation layer 130B, the gate stack 132, and the thermally grown oxide 136 of the core device 122 are similar to the substrate 104, the first Si element 108A, the second Si element 108B, the first gate insulation layer 110A, the second gate insulation layer 110B, the gate stack 114, and the thermally grown oxide 116, respectively, of the semiconductor device 102 without departing from the scope of the invention.
The HM layer 134 may be used to act as a potential etch stop for the core device 122 and to protect the core device 122 from any unwanted processing (e.g., etching). According to one embodiment, the HM layer 134 includes an oxide layer under a silicon nitride layer. According to another embodiment, the HM layer 134 may be composed of one or more layers. The HM layer 134 may then be patterned using a photolithographic process and used to form a gate stack including oxide portions, polysilicon portions, and a hard mask over the I/O well of the core device 122. According to such an embodiment, the HM layer 134 protects a portion of the polysilicon layer disposed over the I/O well of the core device 122 so that the polysilicon structure of the core device 122 may then be formed, for example, using an etching process. A hard mask is then formed and patterned, followed by an etching step to define the gate stack 114 of the core device 122.
According to one embodiment, when semiconductor assembly 100 includes one or more semiconductor devices (including semiconductor device 102) co-integrated with one or more core devices (including core device 122) and fabricated on a single substrate, there is space between these devices. Such spaces are filled with ferroelectric material. According to one embodiment, for a semiconductor assembly 100 including one or more semiconductor devices and one or more core devices, multiple STI structures may be formed in a single substrate. The STI so formed actually divides a single substrate into separate regions, or wells for one or more semiconductor devices and one or more core devices.
In fig. 2, a side view of a semiconductor device 202 provided by an embodiment of the present invention is shown, the semiconductor device 202 comprising a substrate 204 and a FET 206 formed on the substrate 204. The semiconductor device 202 includes a first Si element 208A and a second Si element 208B. The semiconductor device 202 further includes a ferroelectric layer 212 surrounding the first Si element 208A and the second Si element 208B on all four sides. The semiconductor device 202 further includes a gate stack 214 disposed around the ferroelectric layer 212. The substrate 204 of the semiconductor device 202 is isolated from other substrates by an isolating material, such as thermally grown oxide 216.
Semiconductor device 202 is similar to semiconductor device 102 except that ferroelectric layer 212 surrounds first Si element 208A and second Si element 208B on all four sides without any intervening gate insulation layer. Further, unlike the semiconductor device 102, the semiconductor device 202 does not include any insulating layer to isolate the substrate 204 from two Si layers stacked on top of each other in the FET 206.
As shown in fig. 2, according to one embodiment, the first Si element 208A and the second Si element 208B comprise two Si layers stacked on top of each other in a direction from the substrate 204 and are completely surrounded by the ferroelectric layer 212. The first Si element 208A and the second Si element 208B are jointly surrounded by the ferroelectric layer 212 to form a second arrangement, contacting the substrate 204 through one side. With the other three sides, the gate stack 214 is arranged to surround the ferroelectric layer 212 in such a way that each Si layer is partially surrounded.
According to one embodiment, as shown in fig. 2, FET 206 of semiconductor device 202 is fabricated as a GAA structure. Thus, FET 206 of semiconductor device 202 is similar to FET 106 and may also be referred to as FeFET pGAA NS, pFe-GAA, FE-FET I/O devices, and iron pGAA I/O devices without departing from the scope of the present invention.
In fig. 3, a side view of a semiconductor assembly 300 provided by an embodiment of the present invention is shown, the semiconductor assembly 300 including one or more semiconductor devices (e.g., semiconductor device 302) and one or more core devices (e.g., core device 322). Referring to fig. 3, a side view of a semiconductor device 302 is shown, the semiconductor device 302 including a substrate 304 and a FET 306 formed on the substrate 304. The semiconductor device 302 includes a first Si element 308A and a second Si element 308B. The semiconductor device 302 further includes a first gate insulating layer 310A and a second gate insulating layer 310B surrounding the first Si element 308A and the second Si element 308B, respectively. The semiconductor device 302 further includes a ferroelectric layer 312 surrounding the first gate insulating layer 310A and the second gate insulating layer 310B on all four sides. The semiconductor device 302 further includes a gate stack 314 disposed around the ferroelectric layer 312. The substrate 304 of the semiconductor device 302 is isolated from other substrates by an isolating material, such as thermally grown oxide 316.
As shown in fig. 3, according to one embodiment, the first Si element 308A and the second Si element 308B include two Si layers stacked on top of each other in a direction from the substrate 304 and are completely surrounded by the ferroelectric layer 312. The first Si element 308A and the second Si element 308B, which are surrounded by the first gate insulating layer 310A and the second gate insulating layer 310B, respectively, are further commonly surrounded by the ferroelectric layer 312 to form a third arrangement, contacting the substrate 304 through one side. With the other three sides, the gate stack 314 is arranged to enclose the ferroelectric layer 312 in such a way that each Si layer is partially enclosed by the gate stack 314.
According to an embodiment of the present invention, as shown in fig. 3, the semiconductor device 302 may include a third gate insulation layer 310C for isolating two Si layers stacked on each other in the FET 306 from the substrate 304. The third gate insulation layer 310C is used to electrically isolate one or more layers or nanowires of two Si layers stacked near the substrate 304 from the FET 306.
Referring to core device 322 shown in fig. 3, a side view of substrate 324 and FET 326 formed on substrate 324 is shown. The core device 322 includes a first Si element 328A and a second Si element 328B. The core device 322 also includes a first gate insulation layer 330A and a second gate insulation layer 330B surrounding the first Si element 328A and the second Si element 328B, respectively. The core device 322 also includes a gate stack 332 surrounding the first gate insulation layer 330A and the second gate insulation layer 330B on all four sides. The core device 322 also includes an HM layer 334 disposed around the gate stack 332. Substrate 324 of core device 322 is isolated from other substrates (e.g., substrate 304) of other devices (e.g., semiconductor device 302) on either side by an isolating material (e.g., thermally grown oxide 336).
The semiconductor device 302 is similar to the semiconductor device 102 except that the first Si element 308A and the second Si element 308B in the semiconductor device 302 are represented by nanowires (instead of nanoplatelets, e.g., as shown for the first Si element 108A and the second Si element 108B in the semiconductor device 102) forming a vertical stack in a direction from the substrate 304. The first Si element 308A and the second Si element 308B may correspond to silicon elements that form channels in the gate stack 314 to provide conduction between the source and drain regions of the semiconductor device 302. According to one embodiment, as shown in fig. 3, the first Si element 308A and the second Si element 308B are represented by nanowires that form a vertical stack in a direction from the substrate 304. Nanowires are the best choice for low power consumption requirements. The FET 306 with nanowires (e.g., first Si element 308A and second Si element 308B) may be referred to as FeFET pGAA NW or pGAA FET NW.
The substrate 304, the first Si element 308A, the second Si element 308B, the first gate insulating layer 310A, the second gate insulating layer 310B, the third gate insulating layer 310C, the gate stack 314, and the thermally grown oxide 316 of the semiconductor device 302 correspond to the substrate 104, the first Si element 108A, the second Si element 108B, the first gate insulating layer 110A, the second gate insulating layer 110B, the third gate insulating layer 110C, the gate stack 114, and the thermally grown oxide 116 of the semiconductor device 102, respectively.
Similarly, the substrate 324 of the core device 322, the first Si element 328A, the second Si element 328B, the first gate insulating layer 330A, the second gate insulating layer 330B, the third gate insulating layer 310C, the gate stack 332, the HM layer 334, and the thermally grown oxide 336 correspond to the substrate 124 of the core device 122, the first Si element 128A, the second Si element 128B, the first gate insulating layer 130A, the second gate insulating layer 130B, the third gate insulating layer 130C, the gate stack 132, the HM layer 134, and the thermally grown oxide 136, respectively.
In fig. 4, a side view of a semiconductor device 402 is shown, the semiconductor device 402 including a first Si element 408A and a second Si element 408B (as fins), sub-fins 404A and 404B (collectively referred to as substrate 404), a dielectric barrier 410, and a FET 406 formed on the substrate 404, in accordance with one embodiment of the present invention. The semiconductor device 402 includes a first Si element 408A and a second Si element 408B, interchangeably referred to as a fin. The semiconductor device 402 further includes a ferroelectric layer 412 surrounding the first Si element 408A and the second Si element 408B on three sides. The semiconductor device 402 further includes a dielectric barrier 410 between the first Si element 408A and the second Si element 408B, the dielectric barrier 410 being operable to control thickness in a fin-pitch (FP) device. The semiconductor device 402 further includes a gate stack 414 disposed around the ferroelectric layer 412. The sub-fins 404A and 404B of the semiconductor device 402 are isolated from each other and from other substrates by isolation materials (e.g., thermally grown oxides 416A, 416B, and 416C).
As shown in fig. 4, each fin, which is a first Si element 408A and a second Si element 408B, contacts the substrate 404 through one side (i.e., the bottom side) according to one embodiment. The other sides of the first Si element 408A and the second Si element 408B are surrounded by a ferroelectric layer 412. The first Si element 408A and the second Si element 408B comprise two Si layers arranged parallel to each other, which Si layers are orthogonal to the direction from the substrate 104 and are partly surrounded by the ferroelectric layer 112 to form a fourth arrangement. According to such an embodiment, FET 406 is formed as a single gate iron FinFET.
The substrate 404, the first Si element 408A, the second Si element 408B, the ferroelectric layer 412, the gate stack 414, and the thermally grown oxides 416A, 416B, and 416C of the semiconductor device 402 correspond to the substrate 104, the first Si element 108A, the second Si element 108B, the gate stack 114, and the thermally grown oxide 116, respectively, of the semiconductor device 102.
In fig. 5, a side view of a semiconductor device 502 is shown, the semiconductor device 502 including a first Si element 508A and a second Si element 508B (as fins), sub-fins 504A and 504B (collectively referred to as substrate 504), and a FET 506 formed on the substrate 504, in accordance with one embodiment of the present invention. The semiconductor device 502 includes a first Si element 508A and a second Si element 508B, interchangeably referred to as fins. The semiconductor device 502 further includes a ferroelectric layer 512 surrounding the first Si element 508A and the second Si element 508B on three sides. The semiconductor device 502 further includes a gate stack 514 disposed around the ferroelectric layer 512. The sub-fins 504A and 504B of the semiconductor device 502 are isolated from each other and from other substrates by isolation materials (e.g., thermally grown oxides 516A, 516B, and 516C).
Semiconductor device 502 is similar to semiconductor device 402 except that semiconductor device 502 does not include any dielectric barrier corresponding to dielectric barrier 410, as shown in semiconductor device 402. Note that the substrate 504, the first Si element 508A, the second Si element 508B, the ferroelectric layer 512, the gate stack 514, and the thermally grown oxides 516A, 516B, and 516C of the semiconductor device 502 correspond to the substrate 404, the first Si element 408A, the second Si element 408B, the ferroelectric layer 412, the gate stack 414, and the thermally grown oxides 416A, 416B, and 416C of the semiconductor device 402.
Embodiments of the present invention differ from conventional semiconductor devices such as finfets, superlattice FETs, and pgaafets. For example, in a conventional FinFET, fin (Fin) I/O requires an additional selective stack etch and a separate selective silicon (Si) epitaxial (epi) process. Thus, the conventional FinFET is an overall costHigher processes (due to extra mask and Fin-epi) and are prone to variability problems (due to thermal budget leading to integration problems). In conventional superlattice FETs, gate oxide process optimization problems are observed, and thus nI at each Si/SiGe interface dsat Damage. In addition, there is a pFET threshold voltage (pVt) mismatch (about 100 mV) between the Si and SiGe regions, as well as nFET compressive stress caused by the SiGe-Si layer. Thus, conventional superlattice FETs present several basic/process problems. In conventional pgaafets, gate control is not perfect, exhibiting severe SCE degradation. Thus, in a conventional pGAAFET, I dsat May be about 20% lower. Furthermore, n/p SCE degradation was observed in this pGAAFET. The semiconductor devices 102, 202, and 302 overcome the above-described drawbacks associated with conventional approaches because the semiconductor devices 102, 202, and 302 exhibit recovered SCE, n/p I dsat And cost-effective integrated streaming. In addition, semiconductor devices 402 and 502 are in addition to restored SCE and n/p I dsat In addition, scaling of fin pitch is also shown.
Fig. 6A to 6I collectively illustrate a method for forming a semiconductor device (i.e., a method of forming a semiconductor device) provided by an embodiment of the present invention. Fig. 6A-6I are described in connection with the elements of fig. 1, 2, 3, 4, and 5. Referring to fig. 6A-6I, a method 600 for fabricating a semiconductor component 602 (i.e., a method of fabricating a semiconductor component 602) is illustrated. Method 600 includes steps 601 through 617.
The method 600 collectively describes steps of forming a semiconductor assembly 602, the semiconductor assembly 602 being similar to one of the semiconductor assemblies 100 or 300, except that the devices in the semiconductor assembly 602 include two sub-stacks of Si elements without departing from the scope of the invention. The semiconductor assembly 602 includes a semiconductor device 604 that is similar to one of the semiconductor devices 102, 202, 302, 402, or 502 shown in fig. 1, 2, 3, 4, and 5, respectively, except that the semiconductor device 604 includes two stacks of Si elements.
The semiconductor assembly 602 also includes a core device 606, similar to one of the core devices 122 or 322 shown in fig. 1 and 3, respectively, except that the core device 606 includes two stacks of Si elements.
Each step of method 600 is represented in fig. 6A-6I by a dashed rectangular box for illustrative purposes only. Further, each of the semiconductor device 604 and the core device 606 is represented by a dashed rectangular box for illustrative purposes only and does not form part of a circuit.
Referring to fig. 6A, in step 601, a first stack of alternating layers of SiGe and Si on a substrate 104 comprising at least two Si layers is provided in a semiconductor device 604. The first stack includes a first Si element 604C, a first SiGe element 604A, a second Si element 604D, and a second SiGe element 604B. The first stack is intended to form a semiconductor device 604.
Similarly, a second stack of alternating layers of SiGe and Si on the substrate 124 comprising at least two Si layers is provided in the core device 606. The second stack includes a first Si element 606C, a first SiGe element 606A, a second Si element 606D, and a second SiGe element 606B. The substrate 104 and the substrate 124 are part of a single substrate of the semiconductor device 602.
According to one embodiment, as shown in fig. 6A and 1, a first stack and a second stack of nanoplatelet strips are formed, comprising alternately stacked Si nanoplatelet strips and SiGe nanoplatelet strips. According to another embodiment, as shown in fig. 3, a first stack and a second stack of nanowire strips are formed, comprising alternately stacked Si nanowire strips and SiGe nanowire strips. The SiGe nanoplatelets/nanowire strips serve as sacrificial strips and the Si nanoplatelets/nanowire strips serve as semiconductor bodies or channels for each of the pGAA FETs of the semiconductor device 604 and the core device 606. The first stack and the second stack including the SiGe and Si alternating layers on the corresponding substrates are formed by epitaxial growth.
According to one embodiment, a vertical stack of epitaxial layers of Si and SiGe is formed on the substrates 104 and 124 and may be stacked in alternating order, i.e., each epitaxial layer of Si immediately and vertically adjacent to a different epitaxial layer of SiGe. The number of epitaxial layers of Si and SiGe may vary without departing from the scope of the present invention. It should be noted that Si and SiGe have different etch rates, i.e., etch selectivity, relative to some etchants, such that a selective etch may be performed to remove one of the epitaxial layers while the other epitaxial layer remains.
Referring to fig. 6B, in step 603, a sub-stack of Si elements is formed in the semiconductor device 604 and the core device 606. More specifically, two sub-stacks of a first stack of alternating layers of SiGe and Si are formed within an area defined by the STI region formed on the substrate 104. One sub-stack of a first stack comprising alternating layers of SiGe and Si, such as first Si element 108A, first SiGe element 610A, second Si element 108B, and second SiGe element 610B, is formed within the region defined by STI regions 116A and 116B formed on substrate 104A. Other sub-stacks of the first stack including alternating layers of SiGe and Si, such as a third Si element 108C, a third SiGe element 610C, a fourth Si element 108D, and a fourth SiGe element 610D, are formed within the region defined by the STI regions 116B and 116C formed on the substrate 104B. It should be noted that the first Si element 108A and the third Si element 108C collectively correspond to the first Si element 604C (as shown in fig. 6A as an initial whole layer), and the second Si element 108B and the fourth Si element 108D collectively correspond to the second Si element 604D (as shown in fig. 6A as an initial whole layer). Similarly, it should be noted that the first SiGe element 610A and the third SiGe element 610C collectively correspond to the first SiGe element 604A (as shown in fig. 6A as an initial overall layer), and the second SiGe element 610B and the fourth SiGe element 610D collectively correspond to the second SiGe element 604B (as shown in fig. 6A as an initial overall layer). Other correspondence between the elements of fig. 6A and 6B may be established in a similar manner.
Similarly, two sub-stacks of a second stack of alternating layers of SiGe and Si are formed within the region defined by the STI region formed on the substrate 124. One sub-stack of a second stack comprising alternating layers of SiGe and Si, such as first Si element 128A, first SiGe element 614A, second Si element 128B, and second SiGe element 614B, is formed within the region defined by STI regions 136A and 136B formed on substrate 124A. Other sub-stacks of the second stack including alternating layers of SiGe and Si, such as a third Si element 128C, a third SiGe element 614C, a fourth Si element 128D, and a fourth SiGe element 614D, are formed within the region defined by STI regions 136B and 136C formed on substrate 124B.
A dummy oxide layer 608A may be formed that surrounds the two sub-stacks of the first stack from three sides. The dummy oxide layer 608A may also extend between two sub-stacks of the first stack in the semiconductor device 604. Similarly, a dummy oxide layer 612A may be formed that surrounds the two sub-stacks of the second stack from three sides. The dummy oxide layer 612A may also extend between two sub-stacks of a second stack in the core device 606. The dummy oxide layers 608A and 612A may be silicon nitride or other suitable dielectric material. The dummy oxide layers 608A and 612A may be formed of a low K dielectric material such as silicon oxynitride, silicon nitride (Si 3N 4), carbon monoxide (SiO), silicon oxycarbide (SiONC), silicon oxycarbide (SiOC), silicon nitride (SiN), vacuum, and other dielectrics or other suitable materials. The dummy oxide layers 608A and 612A may be formed by Chemical Vapor Deposition (CVD), high density plasma CVD, spin coating, sputtering, or other suitable methods.
Thereafter, a dummy gate 608B may be formed around the dummy oxide layer 608A surrounding the first stack of semiconductor elements 602. Similarly, a dummy gate 612B may be formed around the dummy oxide layer 612A of the second stack surrounding the core device 606. The dummy gates 608B and 612B may include a sacrificial polysilicon layer, a sacrificial cap layer, and a sacrificial liner layer, which are not shown for simplicity. The sacrificial cap layer and the sacrificial liner layer may be silicon oxide or other suitable dielectric material.
Referring to fig. 6C, in step 605, external and internal spacers may be formed. For simplicity, external and internal spacers, not shown here, are formed separating the gate structure, source region, and drain region from one another in the semiconductor assembly 602 and the core device 606. For example, the inner spacers are formed laterally adjacent to the sacrificial strip to be removed/refunded such that it is ensured that the edge surfaces of the refunded sacrificial strip are exposed from the inner spacers. An external spacer may be formed adjacent to the sacrificial gate structure.
The inner spacer may be formed of a high-K dielectric material, for example, having a higher dielectric constant than the outer spacer. The high-K material for the internal spacers may include one or more of silicon nitride Si3N4, silicon carbide (SiC), hafnium oxide (HfO 2), or other suitable high-K dielectric materials. In one embodiment, the K value of the inner spacer material is between about three to four times the K value of the outer spacer material. In one example, the internal spacers further include one or more air gaps adjacent to one or more of the gate structure or the source/drain regions.
The outer spacers may be formed of a low-K dielectric material, such as silicon oxynitride (SiOxNy), silicon nitride (Si 3N 4), carbon monoxide (SiO), silicon oxycarbide (SiONC), silicon oxycarbide (SiOC), vacuum, and other dielectrics or other suitable materials. The external spacers may be formed by chemical vapor deposition (chemical vapor deposition, CVD), high density plasma CVD, spin coating, sputtering, or other suitable methods.
In addition, source/drain (S/D) regions in the semiconductor component 602 and the core device 606 may be formed by an epitaxial process. An ohmic junction between the S/D region and the channel region is ensured if the edge surface of the sacrificial strip is not covered by the dielectric material of the inner spacer.
Once the spacers and S/D regions are formed, the dummy gates 608B and 612B, including the sacrificial polysilicon layer, the sacrificial cap layer, and the sacrificial liner layer, are also removed from over the semiconductor component 602 and the core device 606, respectively.
Referring to fig. 6D, in step 607, the sacrificial strips of the first stack of semiconductor devices 604, i.e., the first SiGe element 610A, the second SiGe element 610B, the third SiGe element 610C and the fourth SiGe element 610D, are removed (or backed) based on a selective etching process. Further, the first SiGe element 614A, the second SiGe element 614B, the third SiGe element 614C and the fourth SiGe element 614D of the second stack of the core device 606 are removed (or backed) based on a selective etching process.
Referring to fig. 6E, in step 609, a first gate insulating layer 110A, a second gate insulating layer 110B, a fourth gate insulating layer 110D, and a fifth gate insulating layer 110E are applied around the first Si element 108A, the second Si element 108B, the third Si element 108C, and the fourth Si element 108D, respectively, in the first stack of the semiconductor device 604. A third gate insulation layer 110C is deposited on the substrate 104A and a sixth gate insulation layer 110F is deposited on the substrate 104B. Similarly, a first gate insulating layer 130A, a second gate insulating layer 130B, a fourth gate insulating layer 130D, and a fifth gate insulating layer 130E are applied around the first Si element 128A, the second Si element 128B, the third Si element 128C, and the fourth Si element 128D, respectively, in the second stack of the core device 606. A third gate insulating layer 130C is deposited on the substrate 124A and a sixth gate insulating layer 130F is deposited on the substrate 124B. The gate insulating layer may be a single dielectric material layer, two layers formed separately from the same dielectric material, or two layers of different dielectric materials.
Referring to fig. 6F, in step 611, a first HM 616 is deposited on the first stack of semiconductor devices 604. The first HM 616 is then patterned and then etched to define the gate stack of the semiconductor device 604.
Referring to fig. 6G, in step 613, a gate stack 618 is formed over the second stack of the core device 606. The gate stack 618 may include a gate electrode and a gate dielectric, which are not shown for simplicity. The gate electrode comprises a conductive material, such as a metal or a metal compound. Suitable metal materials for the gate electrode may include ruthenium, palladium, platinum, tungsten, cobalt, nickel, and/or conductive metal oxides and other suitable P-type metal materials, and include hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), aluminides, and/or conductive metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), as well as other suitable materials for the N-type metal material. In some examples, the gate electrode may include a work function layer tuned to have a suitable work function for enhancing the performance of the core device 606. For example, suitable N-type workfunction metals include Ta, tiAl, tiAlN, taCN, other N-type workfunction metals, or combinations thereof, and suitable P-type workfunction metal materials include TiN, taN, other P-type workfunction metals, or combinations thereof. In some examples, a conductive layer, such as an aluminum layer, a copper layer, a cobalt layer, or a tungsten layer, is formed on the work function layer such that the gate electrode includes a work function layer disposed on the gate dielectric and a conductive layer disposed on the work function layer and below the gate cap, not shown for simplicity. In one example, the gate electrode may have a thickness of about 5nm to about 40nm based on design requirements.
Referring to fig. 6H, in step 615, a second HM 620 is applied on the second stack of core devices 606 and the first HM 616 is removed from the first stack of semiconductor devices 604. As with the first HM 616, the second HM 620 may be deposited, patterned, and etched to define a gate stack for the core device 606.
Referring to fig. 6I, in step 617, a ferroelectric layer 622A is applied around the first gate insulating layer 110A and the second gate insulating layer 110B of the semiconductor device 604 in such a manner that the corresponding ferroelectric layers are in physical contact with each other. The ferroelectric layer 622A is also applied adjacent to the third gate insulation layer 110C deposited on the substrate 104A. Further, another ferroelectric layer 622B is applied around the fourth gate insulating layer 110D and the fifth gate insulating layer 110E of the semiconductor device 604 in such a manner that the corresponding ferroelectric layers are in physical contact with each other. The ferroelectric layer 622B is also applied adjacent to the third gate insulation layer 110F deposited on the substrate 104B. When ferroelectric layers 622A and 622B merge for two sub-stacks in the first stack of semiconductor device 604, semiconductor device 604 appears as a partial GAA device. A gate stack 624 is disposed around ferroelectric layers 622A and 622B.
The gate stack 624 may include a gate electrode and a gate dielectric, which are not shown for simplicity. The gate electrode comprises a conductive material, such as a metal or a metal compound. Suitable metal materials for the gate electrode may include ruthenium, palladium, platinum, tungsten, cobalt, nickel, and/or conductive metal oxides and other suitable P-type metal materials, and include hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), aluminides, and/or conductive metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), as well as other suitable materials for the N-type metal material. In some examples, the gate electrode may include a work function layer tuned to have a suitable work function for enhancing the performance of the semiconductor device 604. For example, suitable N-type workfunction metals include Ta, tiAl, tiAlN, taCN, other N-type workfunction metals, or combinations thereof, and suitable P-type workfunction metal materials include TiN, taN, other P-type workfunction metals, or combinations thereof. In some examples, a conductive layer, such as an aluminum layer, a copper layer, a cobalt layer, or a tungsten layer, is formed on the work function layer such that the gate electrode includes a work function layer disposed on the gate dielectric and a conductive layer disposed on the work function layer and below the gate cap, not shown for simplicity. In one example, the gate electrode may have a thickness of about 5nm to about 40nm based on design requirements.
Thereafter, the conventional flow of contact information is followed. For example, a middle-of-line (MOL) process includes gate contact and/or source/drain contact formation. Back-end-of-line (BEOL) processes include all wafer fabrication processes after MOL, for example, forming wiring in metallization layers to interconnect individual devices.
In this manner, the method 600 provides an easy process for forming a semiconductor device, such as the semiconductor device 602.
Fig. 7A is a flowchart of a method for forming a semiconductor device on a substrate (i.e., a method for forming a semiconductor device on a substrate) provided by an embodiment of the present invention. Fig. 7A is described in conjunction with the elements of fig. 6A-6I. Referring to fig. 7A, a method 700A for forming a semiconductor device on a substrate is shown. Method 700A is performed to form semiconductor device 604. Note that semiconductor device 604 is similar to semiconductor devices 102, 202, 302, 402, and 502 shown in fig. 1, 2, 3, 4, and 5, respectively. Method 700A includes steps 702, 704, 706, 708, and 710.
The present invention provides a method 700A for forming a semiconductor device on a substrate, wherein the method 700A comprises: providing a first stack of alternating layers of SiGe and Si on a substrate comprising at least two Si layers, said first stack being intended to form a semiconductor device; removing the SiGe layer of the first stack; applying a gate insulating layer around each Si layer of the first stack; applying a ferroelectric layer around each gate insulating layer in such a manner that the ferroelectric layers are in physical contact with each other; a gate stack is formed around the ferroelectric layer.
A method 700A for forming a semiconductor device on a substrate is disclosed. Method 700A is used to form semiconductor device 604 on substrates 104A and 104B (which are part of the same substrate).
In step 702, method 700A includes providing a first stack of alternating layers of SiGe and Si on a substrate including at least two Si layers, the first stack being intended to form a semiconductor device. For example, one sub-stack of a first stack comprising alternating layers of SiGe and Si, such as first Si element 108A, first SiGe element 610A, second Si element 108B, and second SiGe element 610B, is formed within the region defined by STI regions 116A and 116B formed on substrate 104A. Other sub-stacks of the first stack including alternating layers of SiGe and Si, such as a third Si element 108C, a third SiGe element 610C, a fourth Si element 108D, and a fourth SiGe element 610D, are formed within the region defined by the STI regions 116B and 116C formed on the substrate 104B.
In step 704, method 700A includes removing the SiGe layer of the first stack. For example, the first SiGe element 610A, the second SiGe element 610B, the third SiGe element 610C, and the fourth SiGe element 610D of the first stack of the semiconductor device 604 are removed (or backed off) based on a selective etching process.
In step 706, method 700A includes applying a gate insulation layer around each Si layer of the first stack. For example, a first gate insulating layer 110A, a second gate insulating layer 110B, a fourth gate insulating layer 110D, and a fifth gate insulating layer 110E are applied around the first Si element 108A, the second Si element 108B, the third Si element 108C, and the fourth Si element 108D, respectively, in the first stack of the semiconductor device 604. A third gate insulation layer 110C is deposited on the substrate 104A and a sixth gate insulation layer 110F is deposited on the substrate 104B.
In step 708, method 700A includes applying a ferroelectric layer around each gate insulating layer in such a manner that two or more ferroelectric layers are in physical contact with each other. For example, the ferroelectric layer 622A is applied around the first gate insulating layer 110A and the second gate insulating layer 110B of the semiconductor device 604 in such a manner that the corresponding ferroelectric layers are in physical contact with each other. The ferroelectric layer 622A is also applied adjacent to the third gate insulation layer 110C deposited on the substrate 104A. Further, another ferroelectric layer 622B is applied around the fourth gate insulating layer 110D and the fifth gate insulating layer 110E of the semiconductor device 604 in such a manner that the corresponding ferroelectric layers are in physical contact with each other. The ferroelectric layer 622B is also applied adjacent to the third gate insulation layer 110F deposited on the substrate 104B. In addition to receiving control from step 706 in fig. 7A, step 708 receives control from step 740 in fig. 7B. Accordingly, ferroelectric layers 622A and 622B are applied only on the first stack of semiconductor devices 604 and not on the second stack of core devices 606, as the first stack is masked (step 740 in fig. 7B) and the second stack is masked (step 738 in fig. 7B). When ferroelectric layers 622A and 622B merge for two sub-stacks in the first stack of semiconductor device 604, semiconductor device 604 appears as a partial GAA device.
In step 710, method 700A includes forming a gate stack around the ferroelectric layer. For example, a gate stack 624 is disposed around ferroelectric layers 622A and 622B. The gate stack 624 may include a gate electrode and a gate dielectric, which are not shown for simplicity. The gate electrode comprises a conductive material, such as a metal or a metal compound. Suitable metal materials for the gate electrode may include ruthenium, palladium, platinum, tungsten, cobalt, nickel, and/or conductive metal oxides and other suitable P-type metal materials, and include hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), aluminides, and/or conductive metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), as well as other suitable materials for the N-type metal material. In some examples, the gate electrode may include a work function layer tuned to have a suitable work function for enhancing the performance of the semiconductor device 604.
Thus, method 700A achieves all the advantages and effects of semiconductor device 604.
Steps 702, 704, 706, 708, and 710 are merely illustrative, and other alternatives may be provided in which one or more steps are added, one or more steps are deleted, or one or more steps are provided in a different order without departing from the scope of the claims herein.
Fig. 7B is a flowchart of a method for forming a core device on the same substrate (i.e., a method for forming a core device on a substrate) provided by an embodiment of the present invention. Fig. 7B is described in conjunction with the elements of fig. 6A-6I. Referring to fig. 7B, a method 700B for forming core devices on the same substrate is shown. Method 700B is performed to form core device 606. Method 700B includes steps 722, 724, 726, 728, 730, 732, 734, 736, 738, and 740.
The present invention provides a method 700B for forming a core device on a substrate, wherein the method 700B comprises: providing a second stack of alternating layers of SiGe and Si on a substrate, the second stack being intended to form a core device, the method 700B comprising the steps of, prior to applying a ferroelectric layer around a gate insulating layer in the first stack: removing the SiGe layer on the first stack and the second stack; applying a gate insulating layer around each Si layer in the first stack and the second stack; applying a mask over the first stack; forming a gate stack over the second stack; applying a mask over the second stack; the mask over the first stack is removed. The method 700B further includes the steps of forming a dummy gate around the second stack, forming spacers and S/epi on the second stack, and removing the dummy gate prior to removing the SiGe layer.
A method 700B for forming core devices on the same substrate is disclosed. Method 700B is used to form core device 606 on substrate 124. The substrate 124 on which the core device 606 is formed and the substrate 104 on which the semiconductor device 604 is formed are different regions of the same substrate. Thus, the semiconductor device 604 and the core device 606 are co-integrated on a single substrate.
In step 722, method 700B includes providing a second stack of alternating layers, two sub-stacks of the second stack of alternating layers of SiGe and Si being formed within an area defined by STI regions formed on substrate 124. For example, one sub-stack of a second stack comprising alternating layers of SiGe and Si, such as first Si element 128A, first SiGe element 614A, second Si element 128B, and second SiGe element 614B, is formed within the region defined by STI regions 136A and 136B formed on substrate 124A. Other sub-stacks of the second stack including alternating layers of SiGe and Si, such as a third Si element 128C, a third SiGe element 614C, a fourth Si element 128D, and a fourth SiGe element 614D, are formed within the region defined by STI regions 136B and 136C formed on substrate 124B.
In step 724, method 700B includes forming a dummy gate around the first stack and the second stack. For example, a dummy gate 608B may be formed around the dummy oxide layer 608A surrounding the first stack of semiconductor devices 604. In addition, a dummy gate 612B may be formed around the dummy oxide layer 612A of the second stack surrounding the core device 606. The dummy gates 608B and 612B may include a sacrificial polysilicon layer, a sacrificial cap layer, and a sacrificial liner layer, which are not shown for simplicity. The sacrificial cap layer and the sacrificial liner layer may be silicon oxide or other suitable dielectric material.
In step 726, method 700B includes forming spacers and S/D epi on the first stack and the second stack. For example, external and internal spacers, not shown here for simplicity, are formed separating the gate structure, source region, and drain region from one another in the semiconductor device 604 and the core device 606. For example, the inner spacers are formed laterally adjacent to the sacrificial strip to be removed/refunded such that it is ensured that the edge surfaces of the refunded sacrificial strip are exposed from the inner spacers. The external spacers may be formed adjacent to the sacrificial gate structures (i.e., dummy gates 608B and 612B). In addition, the S/D regions in the semiconductor device 604 and the core device 606 may be formed by an epitaxial process. An ohmic junction between the S/D region and the channel region is ensured if the edge surface of the sacrificial strip is not covered by the dielectric material of the inner spacer.
In step 728, method 700B includes removing the dummy gate from the first stack and the second stack. For example, dummy gates 608B and 612B, including the sacrificial polysilicon layer, the sacrificial cap layer, and the sacrificial liner layer, are removed from semiconductor device 604 and core device 606, respectively.
In step 730, method 700B includes removing the SiGe layer on the second stack. For example, the first SiGe element 614A, the second SiGe element 614B, the third SiGe element 614C, and the fourth SiGe element 614D of the second stack of the core device 606 are removed (or backed) based on a selective etching process. It should be noted that, step 730 in fig. 7B is performed in parallel with step 704 in fig. 7A.
In step 732, method 700B includes applying a gate insulation layer around each Si layer in the second stack. For example, a first gate insulating layer 130A, a second gate insulating layer 130B, a fourth gate insulating layer 130D, and a fifth gate insulating layer 130E are applied around the first Si element 128A, the second Si element 128B, the third Si element 128C, and the fourth Si element 128D, respectively, in the second stack of the core device 606. A sixth gate insulation layer 130F is deposited on the substrate 124B for isolation. The gate insulating layer may be a single dielectric material layer, two layers formed separately from the same dielectric material, or two layers of different dielectric materials. It should be noted that, step 732 in fig. 7B is performed in parallel with step 706 in fig. 7A.
In step 734, method 700B includes applying a mask over the first stack. For example, a first HM 616 is deposited on the first stack of semiconductor devices 604. The first HM 616 is then patterned and then etched to define the gate stack of the semiconductor device 604.
In step 736, method 700B includes forming a gate stack over the second stack. For example, a gate stack 618 is formed over the second stack of the core device 606. The gate stack 618 may include a gate electrode and a gate dielectric, which are not shown for simplicity. The gate electrode comprises a conductive material, such as a metal or a metal compound.
In step 738, method 700B includes applying a mask over the second stack. For example, a second HM 620 is applied over a gate stack 618 formed over a second stack of the core device 606.
In step 740, method 700B includes removing the mask over the first stack. For example, the first HM 616 is removed from the first stack of semiconductor devices 604. Control moves to step 708 in method 700A of fig. 7A.
Thus, method 700B achieves all the advantages and effects of core device 606.
Steps 722 through 740 are merely illustrative, and other alternatives may be provided in which one or more steps are added, one or more steps are deleted, or one or more steps are provided in a different order without departing from the scope of the claims herein.
Modifications may be made to the embodiments of the invention described above without departing from the scope of the invention, as defined in the appended claims. Expressions such as "comprising," "combining," "having," "being/being" and the like, which describe and claim the present invention, are intended to be interpreted in a non-exclusive manner, i.e. to allow for items, components or elements that are not explicitly described. Reference to the singular is also to be construed to relate to the plural. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any embodiment described as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments, or to exclude features from other embodiments. The word "optionally" as used herein means "provided in some embodiments and not provided in other embodiments. It is appreciated that certain features of the invention, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable combination or as in any other described embodiment of the invention.

Claims (10)

1. A semiconductor device (102, 202, 302, 402, 502, 604), comprising:
at least a first silicon (Si) element (108A, 208A, 308A, 408A, 508A) and a second silicon element (108B, 208B, 308B, 408B, 508B, 604D) on the substrate (104, 204, 304);
a ferroelectric layer (112, 212, 312, 412, 512, 622A, 622B) surrounding the first and second Si elements on at least three sides, and a gate stack (114, 214, 314, 514, 624) arranged around the ferroelectric layer.
2. The semiconductor device (102, 202, 302, 402, 502, 604) according to claim 1, wherein each of the first and second Si elements is surrounded by a gate insulation layer (110A, 110B, 110C, 110D, 310A, 310B), wherein the at least first and second Si elements comprise at least two Si layers stacked on top of each other in a direction from the substrate, and each gate insulation layer is completely surrounded by the ferroelectric layer.
3. The semiconductor device (102, 202, 302, 402, 502, 604) of claim 1, wherein the at least first and second Si elements (408A, 408B) are fins, each fin contacting the substrate through one side, the other side of the fin being surrounded by the ferroelectric layer.
4. A semiconductor device (102, 202, 302, 402, 502, 604) according to any of the preceding claims, characterized in that the gate stack is arranged to enclose the ferroelectric layer in such a way that the gate stack partly encloses each Si layer.
5. The semiconductor device (102, 202, 302, 402, 502, 604) according to any of the preceding claims, being an input/output (I/O) device.
6. A semiconductor assembly (100, 300) comprising one or more semiconductor devices (102, 202, 302, 402, 502, 604) according to any of the preceding claims and one or more core devices (122, 322, 606), wherein the space between each semiconductor device and the core device is filled with a ferroelectric material.
7. A method (700A, 700B) of forming a semiconductor device on a substrate, comprising the steps of:
providing a first stack of alternating layers of SiGe (604A, 604B, 610A, 610B, 610C, 610D) and Si (604C, 604D, 108A, 108B, 108C, 108D) on a substrate (104, 104A) comprising at least two Si layers, the first stack being intended to form the semiconductor device (604);
removing the SiGe layer of the first stack;
Applying a gate insulation layer (110A, 110B, 110D, 110E) around each Si layer of the first stack;
applying ferroelectric layers (622A, 622B) around each gate insulating layer in such a way that two or more ferroelectric layers are in physical contact with each other;
a gate stack (624) is formed around the ferroelectric layer.
8. The method (700A, 700B) of claim 7, wherein the semiconductor device (604) is an I/O device, the method further comprising forming a core device (606) on the same substrate, comprising providing a second stack of alternating layers of SiGe (606A, 606B, 614A, 614B, 614C, 614D) and Si (606C, 606D, 128A, 128B, 128C, 128D) on the substrate (124, 124A, 124B), the second stack being intended to form the core device (606), the method (700A and 700B) comprising the steps of, prior to applying the ferroelectric layer around the gate insulation layer in the first stack:
removing the SiGe layer on the second stack;
applying a gate insulation layer (130A, 130B, 130D, 130E) around each Si layer in the second stack;
applying a mask over the first stack;
forming a gate stack (618) over the second stack;
Applying a mask over the second stack;
the mask on the first stack is removed.
9. The method (700A, 700B) according to claim 8, characterized in that it comprises, before removing the SiGe layer, the steps of:
forming a dummy gate (608B, 612B) around the first stack and the second stack;
forming spacers and S/D epi on the first stack and the second stack;
the dummy gate is removed from the first stack and the second stack.
10. The method (700A, 700B) of claim 9, further comprising the step of forming contacts with the I/O device in a conventional manner.
CN202180099203.9A 2021-06-08 2021-06-08 Semiconductor device having ferroelectric layer around channel and method for forming semiconductor device on substrate Pending CN117480617A (en)

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