CN117479775A

CN117479775A - Display panel

Info

Publication number: CN117479775A
Application number: CN202311141996.3A
Authority: CN
Inventors: 郜芳
Original assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2023-09-04
Filing date: 2023-09-04
Publication date: 2024-01-30

Abstract

The application provides a display panel, this display panel includes the display region and sets up in the lower frame district of display region one side, the display panel still includes the base plate, set up first signal line on the base plate, second signal line and virtual signal line, in lower frame district, the orthographic projection of virtual signal line on the base plate is located between the orthographic projection of first signal line on the base plate and the orthographic projection of second signal line on the base plate, the material of first signal line is different with the material of second signal line, under the condition of circular telegram, the voltage of first signal line is different with the voltage of second signal line, through inserting virtual signal line between first signal line and second signal line, and make the material of one of virtual signal line and first signal line and second signal line the same, the virtual signal line is the same with the voltage of another of first signal line and second signal line, so can destroy the condition that first signal line and second signal line take place electrochemical corrosion, thereby prevent electrochemical corrosion's production.

Description

Display panel

Technical Field

The application relates to the technical field of display, in particular to a display panel.

Background

In the field of display technology, flat panel display technologies such as liquid crystal display (liquid crystal display) technology and organic light-emitting diode (OLED) display technology have gradually replaced Cathode Ray Tube (CRT) display technologies. The OLED display panel has the advantages of self-luminescence, low driving voltage, high luminous efficiency, short response time, high definition and contrast, near 180 ° viewing angle, wide use temperature range, and capability of realizing flexible display and large-area full-color display, and is widely applied to mobile phone screens, computer displays, full-color televisions, etc., and is known in the industry as the display technology with the most development potential.

In the overlapping position of the lower frame area and the effective packaging area of the traditional OLED display panel, electrochemical corrosion of a metal circuit exists. The corrosion mechanism is as follows: the organic film layer of the effective packaging area is removed in the process, the edge of the effective packaging area has larger film layer section difference, the metal wires are all provided with the inorganic insulating layer and the inorganic packaging layer, in the back-end module process, the effective packaging area is rolled, stress is intensively released at the bottom edge of the effective packaging area, the inorganic insulating layer and the inorganic packaging layer are caused to generate cracks, water vapor enters in the subsequent reliability test process, and voltage difference exists between the metal signal wires of different materials, so that electrochemical corrosion is formed.

Therefore, it is necessary to provide a display panel to improve this defect.

Disclosure of Invention

Embodiments of the present application provide a display panel that may damage conditions under which electrochemical corrosion occurs, thereby preventing the generation of electrochemical corrosion of a metal line at a lower frame of the display panel.

The embodiment of the application provides a display panel, including the display area with set up in the lower frame district of display area one side, display panel still includes:

a substrate;

a first signal line disposed on the substrate;

a second signal line disposed on the substrate;

the virtual signal line is arranged on the substrate, and the orthographic projection of the virtual signal line on the substrate is positioned between the orthographic projection of the first signal line on the substrate and the orthographic projection of the second signal line on the substrate in the lower frame area;

wherein the first signal line is different from the second signal line in material, and in case of power-on, the first signal line is different from the second signal line in voltage, the virtual signal line is the same as one of the first signal line and the second signal line in material, and the virtual signal line is the same as the other of the first signal line and the second signal line in voltage.

According to an embodiment of the present application, the first signal line and the second signal line are arranged in different layers, the first signal line and the virtual signal line are made of the same material, the second signal line and the virtual signal line are arranged in different layers, and the second signal line is electrically connected with the virtual signal line.

According to an embodiment of the present application, the second signal line is disposed on a side, far away from the substrate, of the virtual signal line, an inorganic insulating layer is disposed between the second signal line and the virtual signal line, and the second signal line passes through the inorganic insulating layer and is overlapped with the virtual signal line.

According to an embodiment of the present application, the first signal line and the dummy signal line are disposed in the same layer.

According to an embodiment of the present application, the display panel further includes an integrated circuit chip, the integrated circuit chip is disposed in the lower frame area, the first signal line and the second signal line are disposed in different layers, the first signal line and the virtual signal line are electrically connected to the integrated circuit chip, and the second signal line and the virtual signal line are made of the same material.

According to an embodiment of the present application, the second signal line and the dummy signal line are disposed in the same layer.

According to an embodiment of the present application, the first signal line is a data signal line, and the second signal line is a power signal line.

According to an embodiment of the present application, the dummy signal line is a single-layer metal structure or a multi-layer metal structure formed by stacking at least two metal materials.

According to an embodiment of the application, the display panel includes a plurality of the virtual signal lines, and the plurality of the virtual signal lines are arranged at the same layer and at intervals side by side.

According to an embodiment of the present application, the number of virtual signal lines is greater than or equal to 4 and less than or equal to 8.

The beneficial effects of the embodiment of the application are that: the embodiment of the application provides a display panel, this display panel includes the display area and sets up in the lower frame district of display area one side, the display panel still includes the base plate, set up first signal line on the base plate, second signal line and virtual signal line, in the lower frame district, the orthographic projection of virtual signal line on the base plate is located between orthographic projection of first signal line on the base plate and orthographic projection of second signal line on the base plate, the material of first signal line is different from the material of second signal line, under the condition of circular telegram, the voltage of first signal line is different from the voltage of second signal line, through inserting virtual signal line between first signal line and second signal line, and make the material of one of virtual signal line and first signal line and second signal line the same, the virtual signal line is the same with the voltage of one of other of first signal line and second signal line, so can destroy the condition that first signal line and second signal line take place electrochemical corrosion, thereby prevent electrochemical corrosion to produce.

Drawings

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

FIG. 2 is a cross-sectional view of the display panel shown in FIG. 1 along the direction A-A';

FIG. 3 is a schematic diagram of a routing provided in an embodiment of the present application;

FIG. 4 is a cross-sectional view of the routing diagram of FIG. 3 along the direction B-B';

fig. 5 is another routing schematic provided in an embodiment of the present application.

Detailed Description

The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments that can be used to practice the present application. The directional terms mentioned in this application, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., are only referring to the directions of the attached drawings. Accordingly, directional terminology is used to describe and understand the application and is not intended to be limiting of the application. In the drawings, like elements are designated by like reference numerals.

The present application is further described below with reference to the drawings and specific examples.

Embodiments of the present application provide a display panel that can destroy conditions under which electrochemical corrosion occurs, thereby preventing the generation of electrochemical corrosion.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a display panel provided in an embodiment of the present application, where the display panel includes a display area A1 and a lower frame area A2 located at one side of the display area A1, the display area A1 is used for implementing display of a picture image, a plurality of sub-pixels (not shown in the figure) distributed in an array are disposed in the display area A1, and the lower frame area A2 is used for placing circuits and components related to implementing a picture image display function.

Referring to fig. 1 and 2, fig. 2 is a cross-sectional view of the display panel shown in fig. 1 along a direction A-A', the lower frame area A2 has a first fan-out area a21, an array test area a22, a bending area a23 and a second fan-out area a23 sequentially arranged along a direction from near to far from the display area A1, one side of the second fan-out area a24 of the display panel far from the display area A1 is electrically connected with the integrated circuit chip 11 and the circuit board 12, and the power signal line 13 extends from the display area A1 to the lower frame area A2 and is electrically connected with the circuit board 12.

The display panel has an encapsulation layer 14, the encapsulation layer 14 covers the display area A1 and a portion of the lower bezel area A2, and the area covered by the other portion of the encapsulation layer 14 except for the edge portion can be regarded as an effective encapsulation area. The organic film layers (e.g., the first planarization layer 15, the second planarization layer 16, and the pixel defining layer 17 shown in fig. 2) in the display panel are removed in the first fan-out area a21 to form an organic layer recess a, and barriers (e.g., barriers Dam1 and Dam2 in fig. 2) are formed at the edges of the effective package area to prevent the organic encapsulation material in the encapsulation layer 14 from overflowing.

In the related art, the retaining wall may cause a large level difference at the edge of the effective package region, and only the inorganic insulating layer 18 and the inorganic package layer in the package layer 14 are present above the metal film layer in the region where the organic film layer is removed in the first fan-out region a 21. In the back-end module manufacturing process, the inorganic encapsulation layer and the inorganic insulation layer 18 at the edge part of the effective encapsulation area are rolled, stress is intensively released at the bottom edge of the inorganic encapsulation layer, so that cracks appear in the inorganic encapsulation layer and the inorganic insulation layer 18, the area indicated by the dotted circles at the position b in fig. 1 and 2 is the part where the cracks are generated, and the subsequent reliability test Cheng Zhongshui steam enters the panel through the cracks. Taking the power low voltage signal line 132 and the data signal line as examples, the materials of the power low voltage signal line 132 and the data signal line are different, and under the condition of power on, because of the pressure difference between the power low voltage signal line 132 and the data signal line, after water vapor enters, the data signal line acts as an anode, and the power low voltage signal line 132 acts as a cathode, so that electrochemical corrosion is formed.

Referring to fig. 1 to 4, fig. 3 is a schematic diagram of a wiring provided in an embodiment of the present application, and fig. 4 is a cross-sectional view of the schematic diagram of the wiring shown in fig. 3 along a direction B-B', in an embodiment of the present application, a display panel includes a substrate 10, a first signal line 21, a second signal line 22, and a dummy signal line 23, where the first signal line 21, the second signal line 22, and the dummy signal line 23 are all disposed on the substrate 10, and in a lower frame area A2, an orthographic projection of the dummy signal line 23 on the substrate 10 is located between an orthographic projection of the first signal line 21 on the substrate 10 and an orthographic projection of the second signal line 22 on the substrate 10, so that a distance between the first signal line 21 and the second signal line 22 can be increased by using the dummy signal line 23, and a risk of electrochemical corrosion of the first signal line 21 and the second signal line 22 is reduced.

The first signal line 21 and the second signal line 22 are made of different materials, the dummy signal line 23 is made of the same material as one of the first signal line 21 and the second signal line 22, and in the case of energization, the first signal line 21 and the second signal line 22 are made of different voltages, and the voltage of the dummy signal line 23 is made of the same voltage as the other of the first signal line 21 and the second signal line 22, so that the first signal line 21 and the second signal line 22 can be prevented from being corroded by using the same material for the anode (i.e., the first signal line 21 or the second signal line 22) and the cathode (i.e., the dummy signal line 23) in which electrochemical corrosion occurs, and the voltage of the anode and the cathode is the same, thereby destroying the condition in which electrochemical corrosion occurs.

In some embodiments, the first signal line 21 is disposed in a different layer from the second signal line 22, the first signal line 21 is made of the same material as the dummy signal line 23, the second signal line 22 is disposed in a different layer from the dummy signal line 23, and the second signal line 22 is electrically connected to the dummy signal line 23.

In one embodiment, the second signal line 22 is disposed on a side of the dummy signal line 23 away from the substrate 10, and an inorganic insulating layer 18 is disposed between the second signal line 22 and the dummy signal line 23, where the inorganic insulating layer 18 may also be referred to as an interlayer dielectric layer, and the second signal line 22 overlaps the dummy signal line 23 through the inorganic insulating layer 18.

As shown in fig. 4, the dummy signal line 23 is disposed on the substrate 10, the second signal line 22 is disposed on a surface of the dummy signal line 23 away from the substrate 10, and the inorganic insulating layer 18 is disposed between the second signal line 22 and the dummy signal line 23 to insulate the metal film layer where the second signal line 22 is located from the metal film layer where the dummy signal line 23 is located. The inorganic insulating layer 18 is formed with a via hole 24, and the second signal line 22 is overlapped with the dummy signal line 23 through the via hole 24 on the inorganic insulating layer 18, so that the second signal line 22 and the dummy signal line 23 are electrically connected, and the voltage of the second signal line 22 is the same as the voltage of the dummy signal line 23.

Since the dummy signal line 23 is located between the first signal line 21 and the second signal line 22, electrochemical corrosion occurs between the first signal line 21 or the second signal line 22 and the dummy signal line 23, by overlapping the second signal line 22 and the dummy signal line 23 so that the voltage of the second signal line 22 is the same as the voltage of the dummy signal line 23 and the material of the first signal line 21 is the same as the material of the dummy signal line 23 so that the material of the anode (i.e., the first signal line 21) and the cathode (i.e., the dummy signal line 23) where electrochemical corrosion occurs is the same or the voltage is the same, thereby destroying the condition where electrochemical corrosion occurs, so that electrochemical corrosion between the first signal line 21 and the second signal line 22 can be avoided.

In some embodiments, the dummy signal line 23 is co-located with the first signal line 21. With this structure, the dummy signal line 23 can be formed by using the process of the first signal line 21, so that a new film structure and related processes are not added due to the addition of the dummy signal line 23.

In one embodiment, as shown in fig. 1 and 3, the first signal line 21 is a data signal line, the second signal line 22 is a power signal line 13 shown in fig. 1, and the power signal line 13 includes a power high voltage signal line 131 and a power low voltage signal line 132. In the present embodiment, the second signal line 22 is a low-voltage power signal line 132, and in other embodiments, the second signal line 22 may also be a high-voltage power signal line 131, which is not limited herein.

Specifically, as shown in fig. 1 and 3, the display panel includes a first gate insulating layer 101, a first gate metal layer 103, a second gate insulating layer 102, a second gate metal layer 104, an inorganic insulating layer 18, a first source-drain electrode metal layer 105, a second source-drain electrode metal layer 106, a first planarization layer 15, a second planarization layer 16, a pixel defining layer 17, and a cathode layer 19, which are sequentially stacked on a substrate 10, the second signal line 22 is a power low voltage signal line 132 shown in fig. 1, the first signal line 21 is a data signal line, and in the display area A1, the first signal line 21 may be provided on the first source-drain electrode metal layer 105 or the second source-drain electrode metal layer 106; in the first fan-out area a21 of the lower frame area A2, the first signal line 21 and the dummy signal line 23 are disposed on the second gate metal layer 104, and the second signal line 22 may be disposed on the first source-drain electrode metal layer 105 or the second source-drain electrode metal layer 106.

The first gate metal layer 103, the second gate metal layer 104, and the second signal line 22 are each a multi-layer metal structure formed by stacking at least two metal materials. For example, the second signal line 22 is a ti—al—ti three-layer metal structure formed by stacking two metal materials of titanium and aluminum.

The first source-drain electrode metal layer 105, the second source-drain electrode metal layer 106, the first signal line 21, and the dummy signal line 23 are all of a single-layer metal structure. For example, the first signal line 21 and the dummy signal line 23 are each a single-layer metal structure formed by deposition of metallic molybdenum.

In other embodiments, the first signal line 21 and the dummy signal line 23 may be disposed on the first gate metal layer 103; alternatively, the first signal line 21 and the dummy signal line 23 are provided in different layers, for example, the first signal line 21 is provided on the first gate metal layer 103, the dummy signal line 23 is provided on the second gate metal layer 104, or the first signal line 21 is provided on the second gate metal layer 104, and the dummy signal line 23 is provided on the first gate metal layer 103, and it is only necessary to satisfy that the dummy signal line 23 and the second signal line 22 are electrically connected.

Referring to fig. 1 and fig. 5, fig. 5 is a schematic diagram of another routing provided in the embodiment of the present application, in which a first signal line 21 and a second signal line 22 are arranged in different layers, a virtual signal line 23 and the first signal line 21 are arranged in different layers, the second signal line 22 and the virtual signal line 23 are made of the same material, the virtual signal line 23 and the first signal line 21 are electrically connected to the integrated circuit chip 11, and the integrated circuit chip 11 transmits data signals with the same voltage to the first signal line 21 and the virtual signal line 23 at the same time. Thus, the first signal line 21 and the dummy signal line 23 can be used as an anode and a cathode of the electrochemical corrosion, respectively, and the conditions for the electrochemical corrosion cannot be satisfied because the voltages of the anode and the cathode are the same, so that the electrochemical corrosion can be prevented.

In some embodiments, the dummy signal line 23 is disposed at the same layer as the second signal line 22. With this structure, the dummy signal line 23 is formed by the process of using the second signal line 22, so that a new film structure and related processes are not added due to the addition of the dummy signal line 23.

In the embodiment shown in fig. 5, the first signal line 21 is a data signal line, the second signal line 22 is a power low voltage signal line 132 shown in fig. 1, the first signal line 21 is a data signal line, and in the display area A1, the first signal line 21 may be disposed on the first source drain electrode metal layer 105 or the second source drain electrode metal layer 106; in the first fan-out area a21 of the lower frame area A2, the first signal line 21 is disposed on the first gate metal layer 103 or the second gate metal layer 104, and the second signal line 22 and the dummy signal line 23 are both disposed on the first source-drain electrode metal layer 105.

The first gate metal layer 103, the second gate metal layer 104, the second signal line 22, and the dummy signal line 23 are each a multi-layered metal structure formed by stacking at least two metal materials. For example, the second signal line 22 and the dummy signal line 23 are each a Ti-Al-Ti three-layer metal structure formed by stacking two metal materials of titanium and aluminum.

The first source-drain electrode metal layer 105, the second source-drain electrode metal layer 106, and the first signal line 21 are all of a single-layer metal structure. For example, the first signal line 21 is a single-layer metal structure formed by deposition of metallic molybdenum.

In other embodiments, the second signal line 22 and the dummy signal line 23 may be disposed on the second source-drain electrode metal layer 106; alternatively, the second signal line 22 and the dummy signal line 23 are provided in different layers, for example, the second signal line 22 is provided in the first source-drain electrode metal layer 105, the dummy signal line 23 is provided in the second source-drain electrode metal layer 106, or the second signal line 22 is provided in the second source-drain electrode metal layer 106, and the dummy signal line 23 is provided in the first source-drain electrode metal layer 105.

In some embodiments, the display panel includes a plurality of dummy signal lines 23, and the plurality of dummy signal lines 23 are arranged in a same layer and side by side at intervals. By providing a plurality of dummy signal lines 23, the distance between the first signal line 21 and the second signal line 22 can be increased, thereby reducing the risk of electrochemical corrosion of the first signal line 21 and the second signal line 22.

In some embodiments, the number of virtual signal lines 23 is greater than or equal to 4 and less than or equal to 8. If the number of the dummy signal lines 23 exceeds the range, there is insufficient space for placing the dummy signal lines 23, and thus the overall wiring arrangement of the lower frame area A2 is affected. If the number of the dummy signal lines 23 is smaller than this range, the distance between the first signal lines 21 and the second signal lines 22 becomes too small, which increases the risk of electrochemical corrosion.

In one embodiment, as shown in fig. 3 or fig. 4, the display panel has 4 dummy signal lines 23, and the 4 dummy signal lines 23 are arranged in the same layer and are arranged between the first signal line 21 and the second signal line 22 at a side-by-side interval. In other embodiments, the number of the dummy signal lines 23 is not limited to 4 in the above embodiments, but may be 5, 6, 7, 8, or the like, and only between 4 and 8 lines are required.

According to the display panel provided by the above embodiments of the present application, the embodiments of the present application further provide a display device, where the display device includes the display panel provided by any one of the above embodiments, and the display device is not limited to a display device such as a smart phone, a smart watch, a desktop computer, a notebook computer, and a television.

In summary, although the present application discloses the preferred embodiments, the preferred embodiments are not intended to limit the application, and those skilled in the art can make various modifications and alterations without departing from the spirit and scope of the application, so the scope of the application is defined by the claims.

Claims

1. A display panel, characterized by including display area and set up in the lower frame area of display area one side, display panel still includes:

a substrate;

a first signal line disposed on the substrate;

a second signal line disposed on the substrate;

2. The display panel according to claim 1, wherein the first signal line is provided in a different layer from the second signal line, the first signal line is made of the same material as the dummy signal line, the second signal line is provided in a different layer from the dummy signal line, and the second signal line is electrically connected to the dummy signal line.

3. The display panel according to claim 2, wherein the second signal line is disposed on a side of the dummy signal line away from the substrate, an inorganic insulating layer is disposed between the second signal line and the dummy signal line, and the second signal line passes through the inorganic insulating layer and overlaps the dummy signal line.

4. The display panel of claim 3, wherein the first signal line is disposed at the same layer as the dummy signal line.

5. The display panel of claim 1, further comprising an integrated circuit chip disposed in the lower bezel region, the first signal line being disposed in a different layer from the second signal line, the first signal line being disposed in a different layer from the dummy signal line, the first signal line and the dummy signal line both being electrically connected to the integrated circuit chip, the second signal line being of a same material as the dummy signal line.

6. The display panel of claim 5, wherein the second signal line is disposed at the same layer as the dummy signal line.

7. The display panel according to any one of claims 1 to 6, wherein the first signal line is a data signal line and the second signal line is a power signal line.

8. The display panel according to claim 1, wherein the dummy signal line is a single-layer metal structure or a multi-layer metal structure formed by stacking at least two metal materials.

9. The display panel of claim 1, wherein the display panel includes a plurality of the dummy signal lines, the plurality of the dummy signal lines being arranged in a same layer and spaced apart side by side.

10. The display panel of claim 9, wherein the number of virtual signal lines is greater than or equal to 4 and less than or equal to 8.