CN117478548A - Fault tolerance capability test system and method for I2C slave equipment - Google Patents
Fault tolerance capability test system and method for I2C slave equipment Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
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- H—ELECTRICITY
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- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
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Abstract
The invention provides a fault-tolerant capability test system and method of I2C slave equipment, belongs to the technical field of I2C bus communication, and fills up the gap of the prior art for testing the fault-tolerant capability of the slave; the system comprises an I2C bus, slave equipment, an unstable waveform level simulation module and a waveform slope change simulation module; the slave device is connected with an unstable waveform level simulation module through an I2C bus, and the unstable waveform level simulation module is used for replacing the host device in the I2C communication process and outputting an unstable waveform level to the slave device; the I2C bus is connected with an external power supply through a waveform slope change simulation module, and the waveform slope change simulation module is used for changing the slope of a level signal in the I2C bus; the slave device responds to the unstable waveform level and the change of the signal edge slope, and the fault tolerance of the slave device can be estimated according to the response result; the invention can uniformly and efficiently test the fault-tolerant capability of the slave equipment and ensure the application quality of the slave equipment.
Description
Technical Field
The invention belongs to the technical field of I2C bus communication, and is applied to a test process of slave equipment, in particular to a fault tolerance test system and a fault tolerance test method of I2C slave equipment.
Background
An integrated circuit bus (Inter-Integrated Circuit, IIC) is a simple, reliable, half-duplex and synchronous serial control bus, commonly referred to as an I2C bus. The I2C test is a test method for evaluating and verifying the functions and performances of the I2C slave device; which includes the contents of the test in terms of sending and receiving data, detecting communication errors, verifying timing and level requirements, etc. Through I2C test, the data sent by the host equipment can be correctly identified and processed by the slave equipment in different signal environments, and the accurate transmission and the reliable communication of the data are ensured.
In the I2C bus technology, a Clock line (SCL) and a Data line (SDA) are two basic signal lines among them. The clock line SCL is used for synchronizing data transmission of the host device and the slave device, and the host device indicates the time sequence of the data transmission by controlling clock pulses on the SCL; the data line SDA is used to transmit data between the host device and the slave device, the data being represented by the level on the SDA, and the data being transmitted and received between the host device and the slave device by controlling the level on the SDA.
In the prior art, when performing I2C communication, the following problems may be faced:
1. the levels of the clock line SCL and the data line SDA are unstable: this problem can lead to false triggers of the start signal or stop signal, which can prevent the communication from proceeding normally or exiting, resulting in data transmission errors or deadlock.
2. Clock frequency mismatch: this problem may cause errors in the communication timing between the master device and the slave device, and if the clock frequencies are different, the data cannot be correctly transmitted, and the communication process is failed.
Further, in the I2C communication, the transmission of data is performed between the rising edge and the falling edge of the clock line SCL; in the data transmission process, SCL is high level, and at the moment, the data represented by SDA is valid; when SCL is low, the SDA data is not valid. When the host device transmits data, the slave device needs to read the data on the data line SDA when the clock line SCL generates a rising edge.
The length of the rising edge affects the correct timing for reading the data from the device. If the rising edge time is too short, the slave device may not be able to read the data on the data line in time, resulting in data transmission errors or loss; if the rising edge is too long, the slave device may read the data at the wrong time, resulting in data parsing errors.
To sum up, in order to ensure that the I2C communication process is performed correctly, the slave device needs to have a certain fault tolerance to the levels of the clock line SCL and the data line SDA sent by the master device. Even if the level of the clock line SCL transmitted by the master device is unstable, the slave device should correctly recognize the rising and falling edges of the clock signal to ensure synchronization of the data. Even if the data line SDA level transmitted by the host device is unstable, the slave device should correctly recognize the signal state to ensure accurate reading and writing of data.
By identifying the state change of the I2C bus data signal, the slave device should accurately judge whether the data sent by the host device is 0 or 1, and perform corresponding operation; otherwise, the signal is touched by mistake due to the unstable level factor in the initial stage of communication, the communication process cannot be exited, and the I2C bus is always busy. At present, a systematic testing technology for the fault-tolerant capability of the slave equipment is lacking, so that the gap is necessary to be filled in time, the fault-tolerant capability of the slave equipment is uniformly and efficiently tested, and the actual application quality of the slave equipment is ensured.
Disclosure of Invention
Aiming at the current situation in the background technology, in the testing process of the I2C slave device, FPGA and DAC devices are introduced, the unstable waveform level and the waveform slope change effect are simulated, and the unstable scene of the I2C communication level signal is generated, so that the fault tolerance of the slave device to the unstable level of the clock line SCL and the data line SDA is observed and tested. The invention can test the data transmission stability and the I2C communication reliability of the slave equipment efficiently and comprehensively, and can control the communication quality of the slave equipment.
The invention adopts the following technical scheme to achieve the purpose:
the fault tolerance capability test system of the I2C slave equipment comprises an I2C bus, the slave equipment, an unstable waveform level simulation module and a waveform slope change simulation module; the slave device is connected with the unstable waveform level simulation module through the I2C bus, and the unstable waveform level simulation module is used for replacing the host device in the conventional I2C communication process and outputting an unstable waveform level to the slave device; the I2C bus is connected with an external power supply through the waveform slope change simulation module, the external power supply is used for providing power supply for the test system, and the waveform slope change simulation module is used for changing the level signal slope in the I2C bus.
Further, the unstable waveform level simulation module consists of a first FPGA unit, a first DAC unit and a second DAC unit; the first FPGA unit is loaded with a preset unstable waveform level simulation program, and the unstable waveform level simulation program is used for driving the first DAC unit and the second DAC unit to respectively generate unstable waveform levels corresponding to the clock line SCL and the data line SDA, and send the unstable waveform levels to the slave device; the slave device is configured to receive an unstable waveform level and respond; and the testers evaluate the fault tolerance of the slave equipment according to the response result.
Further, the waveform slope change simulation module comprises a pull-up resistor, a digital potentiometer and a second FPGA unit; the second FPGA unit is loaded with a preset waveform slope change simulation program, and the resistance value of the pull-up resistor is in a variable resistance state under the action of the digital potentiometer; the waveform slope change simulation program is used for changing the resistance value of the pull-up resistor by controlling the digital potentiometer, so as to change the slope of a preset waveform level signal edge transmitted on the clock line SCL or the data line SDA; the slave device is used for receiving preset waveform levels of different signal edge slopes and responding to the preset waveform levels; and the testers evaluate the fault tolerance of the slave equipment according to the response result.
The invention also provides a fault tolerance testing method of the I2C slave equipment, wherein the hardware basis of the testing method is the testing system, and the testing method comprises an unstable waveform level testing process and a waveform slope change testing process; according to the specification of the slave equipment and the I2C communication protocol, the slave equipment sequentially receives an unstable waveform level and preset waveform levels of different signal edge slopes to obtain a response result of the slave equipment and actually received data content; and then, evaluating the fault tolerance of the slave equipment according to the response result and the accuracy of the data content.
In summary, by adopting the technical scheme, the invention has the following beneficial effects:
the invention can simulate the unstable level sent by the host equipment based on the combination of the FPGA and the DAC device, and reproduce the level jitter or noise scene possibly existing in the real I2C communication process. This test scheme can more realistically simulate the level change of the master device, thereby evaluating the fault tolerance and recognition capability of the slave device for unstable levels. The slave device subjected to the unstable level test can better ensure the data transmission stability and the I2C communication reliability, and has better benefit in practical application.
The invention can dynamically simulate the magnitude of the pull-up resistor in the communication process of the I2C bus based on the combination of the FPGA and the digital potentiometer, thereby adjusting the rising edge and the falling edge slopes of the clock line SCL and the data line SDA. The test scheme can evaluate the signal edge recognition capability of the slave machine equipment for different slopes, so as to verify the stability and reliability of the slave machine in different signal environments; the slope adjustment can directly simulate different signal transmission environment conditions, and the adaptation condition of the slave machine to different signal environments is comprehensively tested.
Drawings
FIG. 1 is a schematic diagram of a structural connection framework of a test system of the present invention;
FIG. 2 is a schematic diagram of an unstable waveform level simulation module according to the present invention;
FIG. 3 is a schematic diagram of a waveform slope change simulation module according to the present invention;
FIG. 4 is a schematic overall flow chart of the test method of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
FIG. 1 shows the structural connection relation of the system, and the fault tolerance test system comprises an I2C bus, slave equipment, an unstable waveform level simulation module and a waveform slope change simulation module; the slave device is connected with an unstable waveform level simulation module through an I2C bus, and the unstable waveform level simulation module is used for replacing the host device in the conventional I2C communication process and outputting an unstable waveform level to the slave device; the I2C bus is connected with an external power supply through a waveform slope change simulation module, the external power supply is used for providing power supply for the test system, and the waveform slope change simulation module is used for changing the slope of a level signal in the I2C bus.
In this embodiment, as shown in fig. 2, the unstable waveform level analog module is composed of a first FPGA unit, a first DAC unit, and a second DAC unit, where the first FPGA unit is connected to the first DAC unit and the second DAC unit at the same time; the first DAC unit is connected to the clock line SCL and the second DAC unit is connected to the data line SDA.
The first FPGA unit is loaded with a preset unstable waveform level simulation program, and the unstable waveform level simulation program enables the unstable waveform level to have self-defined waveform shape, frequency and amplitude parameters in an FPGA programming mode, so that the unstable clock line and data line levels are simulated.
The unstable waveform level simulation program is used for driving the first DAC unit and the second DAC unit, respectively generating unstable waveform levels corresponding to the clock line SCL and the data line SDA, and sending the unstable waveform levels to the slave equipment; the slave device is used for receiving the unstable waveform level and responding; and the tester observes the communication behavior of the slave equipment according to the response result and judges whether the data information is correctly read, so that the fault tolerance of the slave equipment is evaluated.
Example 2
Based on embodiment 1, the related content of the waveform slope change simulation module is specifically described in this embodiment, and reference may be made to fig. 1 and 3.
As shown in fig. 3, the waveform slope change simulation modules are 2 in number and are respectively connected to the clock line SCL and the data line SDA of the I2C bus; each waveform slope change analog module comprises a pull-up resistor, a digital potentiometer and a second FPGA unit. The combination of the digital potentiometer and the pull-up resistor can be realized by adopting an external programmable resistor.
The clock line SCL or the data line SDA is connected with an external power supply through a pull-up resistor, and the pull-up resistor is connected with the second FPGA unit through a digital potentiometer.
The second FPGA unit is loaded with a preset waveform slope change simulation program, and the waveform slope change simulation program enables the duration and the length of the rising edge and/or the falling edge of the level waveform to be changed in an FPGA programming mode. The correct transmission of data and the reliability of I2C communication are ensured here by testing whether the slave device is able to correctly identify the rising and falling edges of the corresponding level.
The resistance value of the pull-up resistor is in a variable resistance state under the action of the digital potentiometer; the waveform slope change simulation program is used for changing the resistance value of the pull-up resistor by controlling the digital potentiometer, so as to change the slope of the preset waveform level signal edge transmitted on the clock line SCL or the data line SDA; the slave device is used for receiving preset waveform levels of different signal edge slopes and responding to the preset waveform levels; and the tester judges whether the slave equipment can keep synchronous with the host equipment in the actual use process according to the response result, correctly analyzes the data and meets the protocol time sequence requirement, thereby evaluating the fault tolerance of the slave equipment.
Example 3
On the basis of embodiment 1 or 2, the present embodiment provides a fault tolerance test method of an I2C slave device, where the hardware basis of the test method is the test system in embodiment 1 or 2, and the test method includes an unstable waveform level test process and a waveform slope change test process; according to the specification of the slave equipment and the I2C communication protocol, the slave equipment sequentially receives an unstable waveform level and preset waveform levels of different signal edge slopes to obtain a response result of the slave equipment and actually received data content; and then, evaluating the fault tolerance of the slave equipment according to the response result and the accuracy of the data content.
In this embodiment, the unstable waveform level test process, the overall flow can be referred to as the schematic diagram of fig. 4, specifically includes the following steps:
s11, hardware connection: connecting the first FPGA unit to a clock line SCL and a data line SDA of the I2C bus through a first DAC unit and a second DAC unit respectively;
s12, FPGA programming: using an FPGA development tool (such as a Vivado tool) to write an unstable waveform level simulation program, and controlling the output ends of the first DAC unit and/or the second DAC unit to generate an unstable waveform level; the program can be realized by calling a counter, a state machine or other logic circuits to simulate the process, and the program can be set by a person skilled in the art according to actual requirements;
s13, configuring slave equipment: accessing the slave equipment into an I2C bus, and configuring relevant configuration parameters such as address, clock frequency and the like of the slave equipment according to the specification of the slave equipment;
s14, test data transmission: transmitting the generated unstable waveform level to the slave device via the clock line SCL and/or the data line SDA; different data modes and data values can be sent according to specific test item categories, and different situations possibly occurring in actual communication are simulated;
s15, response monitoring of the slave equipment: monitoring the response condition of the slave device to the unstable waveform level by using a monitoring tool, and presenting the data content received by the slave device; the monitoring tool may use an oscilloscope, logic analyzer, or other tool to observe the level change on the I2C bus and the received data conditions from the machine device;
s16, evaluating fault tolerance: judging whether the slave equipment correctly recognizes the unstable waveform level according to the response condition and the data content accuracy of the slave equipment, and obtaining the fault tolerance assessment result of the slave equipment.
Example 4
Based on embodiments 2 and 3, this embodiment describes a waveform slope change testing procedure, and the overall flow is also shown in fig. 4, and specifically includes the following steps:
s21, hardware connection: connecting a second FPGA unit in each waveform slope change simulation module to a corresponding pull-up resistor through a digital potentiometer, and setting corresponding to a clock line SCL and a data line SDA respectively;
s22, FPGA programming: using an FPGA development tool to write a waveform slope change simulation program, and controlling a digital potentiometer to change the slope of a preset waveform level signal edge transmitted on a clock line SCL and/or a data line SDA;
s23, configuring slave equipment: accessing the slave equipment into an I2C bus, and configuring the address and clock frequency of the slave equipment according to the specification of the slave equipment;
s24, test data transmission: the method comprises the steps of fixing an unstable waveform level generated by an unstable waveform level simulation program to a preset waveform level, and transmitting the preset waveform level with changed signal edge slope to slave equipment through a clock line SCL and/or a data line SDA by a waveform slope change simulation program;
s25, response monitoring of the slave equipment: monitoring response conditions of the slave equipment to preset waveform levels of different signal edge slopes by using a monitoring tool, and presenting data content received by the slave equipment; the monitoring tool may use an oscilloscope, logic analyzer, or other tool to observe the level change on the I2C bus and the received data conditions from the machine device;
s26, evaluating fault tolerance: and judging whether the slave equipment correctly recognizes preset waveform levels of different signal edge slopes according to the response condition and the data content accuracy of the slave equipment, and obtaining the fault tolerance assessment result of the slave equipment.
Example 5
The embodiment introduces a specific test scenario, based on the unstable waveform level test procedure of embodiment 3, the steps of the scenario are as follows:
step1: selecting an Xilinx Spartan-6 FPGA development board; the slave equipment is an EEPROM chip; the DAC chip is AD5621; the clock frequency is set to 100kHz; the slave device address is 0x50; the clock frequency of the FPGA is 50MHz;
step2: the FPGA development board is connected with the DAC chip in a combined mode, and then is connected with a clock line SCL and a data line SDA of the slave equipment, so that the slave equipment can be used for simulating the host equipment to send unstable level;
step3: writing VHDL codes to control the output voltage of the DAC chip by using Xilinx ISE software; the analog host device transmits an unstable level by modifying input data of the DAC chip as needed;
step4: the FPGA development board controls the DAC chip to output unstable level, such as noise, interference and the like; the FPGA development board sends data information to the slave device, for example, writes a set of data to the EEPROM chip;
step5: monitoring level changes on the I2C bus and responses of the slave devices, an oscilloscope or logic analyzer or the like may be used; checking whether the slave device can accurately identify the data information sent by the host device, and comparing the data information with an expected result;
step6: evaluation of results: judging the identification capacity of the slave equipment to the unstable level according to the response condition of the slave equipment; if the slave device can accurately identify the data information sent by the host device, the slave device is better in data transmission and communication reliability even if the level is unstable.
Example 6
The present embodiment describes a specific test scenario, based on the waveform slope change test procedure of embodiment 4, the steps of the scenario are as follows:
step1: selecting an Xilinx Spartan-6 FPGA development board; the slave equipment is a temperature sensor; the initial setting of the pull-up resistor is 10 kilo ohms; the clock frequency is 100kHz; the slave device address is 0x48; the clock frequency of the FPGA is 50MHz;
step2: and connecting the FPGA development board with the digital potentiometer and the pull-up resistor. Adding pull-up resistors on the clock line SCL and the data line SDA, and initially setting to be 10 kiloohms; writing Verilog code to control I2C host communications; the code parameters are modified according to the requirement, so that the control of the size of the pull-up resistor is realized;
step3: changing the size of the pull-up resistor, for example, changing the pull-up resistor to 20 kilohms or 5 kilohms, and recording the value of each change; monitoring level changes on the I2C bus and responses of the slave devices, an oscilloscope or logic analyzer or the like may be used; checking whether the slave device can correctly identify the data information sent by the host device, and comparing the data information with an expected result;
step4: judging the identification capability of the slave equipment for the time change of the rising edge and the falling edge according to the response condition of the slave equipment; if the slave device can accurately identify the data information sent by the host device, even if the time of the rising edge and the falling edge are changed, the slave device has better data transmission and communication reliability.
Claims (10)
1. The fault tolerance capability test system of the I2C slave device is characterized in that: the test system comprises an I2C bus, slave equipment, an unstable waveform level simulation module and a waveform slope change simulation module; the slave device is connected with the unstable waveform level simulation module through the I2C bus, and the unstable waveform level simulation module is used for replacing the host device in the conventional I2C communication process and outputting an unstable waveform level to the slave device; the I2C bus is connected with an external power supply through the waveform slope change simulation module, the external power supply is used for providing power supply for the test system, and the waveform slope change simulation module is used for changing the level signal slope in the I2C bus.
2. The fault tolerance testing system of an I2C slave device according to claim 1, wherein: the unstable waveform level simulation module consists of a first FPGA unit, a first DAC unit and a second DAC unit, wherein the first FPGA unit is connected with the first DAC unit and the second DAC unit at the same time; the first DAC unit is connected to the clock line SCL, and the second DAC unit is connected to the data line SDA.
3. The fault tolerance testing system of the I2C slave device according to claim 2, wherein: the first FPGA unit is loaded with a preset unstable waveform level simulation program, and the unstable waveform level simulation program is used for driving the first DAC unit and the second DAC unit to respectively generate unstable waveform levels corresponding to the clock line SCL and the data line SDA, and send the unstable waveform levels to the slave device; the slave device is configured to receive an unstable waveform level and respond; and the testers evaluate the fault tolerance of the slave equipment according to the response result.
4. A fault tolerance testing system for I2C slave devices according to claim 3, wherein: the unstable waveform level simulation program enables the unstable waveform level to have self-defined waveform shape, frequency and amplitude parameters in an FPGA programming mode.
5. The fault tolerance testing system of an I2C slave device according to claim 1, wherein: the waveform slope change simulation modules are 2 in number and are respectively connected to a clock line SCL and a data line SDA of the I2C bus; each waveform slope change simulation module comprises a pull-up resistor, a digital potentiometer and a second FPGA unit; the clock line SCL or the data line SDA is connected to the external power supply through the pull-up resistor, and the pull-up resistor is connected to the second FPGA unit through the digital potentiometer.
6. The fault tolerance testing system of the I2C slave device according to claim 5, wherein: the second FPGA unit is loaded with a preset waveform slope change simulation program, and the resistance value of the pull-up resistor is in a variable resistance state under the action of the digital potentiometer; the waveform slope change simulation program is used for changing the resistance value of the pull-up resistor by controlling the digital potentiometer, so as to change the slope of a preset waveform level signal edge transmitted on the clock line SCL or the data line SDA; the slave device is used for receiving preset waveform levels of different signal edge slopes and responding to the preset waveform levels; and the testers evaluate the fault tolerance of the slave equipment according to the response result.
7. The fault tolerance testing system of the I2C slave device according to claim 6, wherein: the waveform slope change simulation program changes the duration and the length of the rising edge and/or the falling edge of the level waveform in an FPGA programming mode.
8. A fault tolerance capability test method of I2C slave equipment is characterized in that: the hardware basis of the test method is the test system of any one of claims 1 to 7, and the test method comprises an unstable waveform level test process and a waveform slope change test process; according to the specification of the slave equipment and the I2C communication protocol, the slave equipment sequentially receives an unstable waveform level and preset waveform levels of different signal edge slopes to obtain a response result of the slave equipment and actually received data content; and then, evaluating the fault tolerance of the slave equipment according to the response result and the accuracy of the data content.
9. The fault tolerance testing method for the I2C slave device according to claim 8, wherein: the unstable waveform level test process specifically comprises the following steps:
s11, hardware connection: connecting the first FPGA unit to a clock line SCL and a data line SDA of the I2C bus through a first DAC unit and a second DAC unit respectively;
s12, FPGA programming: using an FPGA development tool to write an unstable waveform level simulation program, and controlling the output ends of the first DAC unit and/or the second DAC unit to generate an unstable waveform level;
s13, configuring slave equipment: accessing the slave equipment into an I2C bus, and configuring the address and clock frequency of the slave equipment according to the specification of the slave equipment;
s14, test data transmission: transmitting the generated unstable waveform level to the slave device via the clock line SCL and/or the data line SDA;
s15, response monitoring of the slave equipment: monitoring the response condition of the slave device to the unstable waveform level by using a monitoring tool, and presenting the data content received by the slave device;
s16, evaluating fault tolerance: judging whether the slave equipment correctly recognizes the unstable waveform level according to the response condition and the data content accuracy of the slave equipment, and obtaining the fault tolerance assessment result of the slave equipment.
10. The fault tolerance testing method for the I2C slave device according to claim 8, wherein: the waveform slope change testing process specifically comprises the following steps:
s21, hardware connection: connecting a second FPGA unit in each waveform slope change simulation module to a corresponding pull-up resistor through a digital potentiometer, and setting corresponding to a clock line SCL and a data line SDA respectively;
s22, FPGA programming: using an FPGA development tool to write a waveform slope change simulation program, and controlling a digital potentiometer to change the slope of a preset waveform level signal edge transmitted on a clock line SCL and/or a data line SDA;
s23, configuring slave equipment: accessing the slave equipment into an I2C bus, and configuring the address and clock frequency of the slave equipment according to the specification of the slave equipment;
s24, test data transmission: the method comprises the steps of fixing an unstable waveform level generated by an unstable waveform level simulation program to a preset waveform level, and transmitting the preset waveform level with changed signal edge slope to slave equipment through a clock line SCL and/or a data line SDA by a waveform slope change simulation program;
s25, response monitoring of the slave equipment: monitoring response conditions of the slave equipment to preset waveform levels of different signal edge slopes by using a monitoring tool, and presenting data content received by the slave equipment;
s26, evaluating fault tolerance: and judging whether the slave equipment correctly recognizes preset waveform levels of different signal edge slopes according to the response condition and the data content accuracy of the slave equipment, and obtaining the fault tolerance assessment result of the slave equipment.
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| CN202311825407.3A CN117478548B (en) | 2023-12-28 | 2023-12-28 | Fault tolerance capability test system and method for I2C slave equipment |
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