CN117476640A - Semiconductor preparation method, semiconductor structure and chip - Google Patents

Semiconductor preparation method, semiconductor structure and chip Download PDF

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Publication number
CN117476640A
CN117476640A CN202311295787.4A CN202311295787A CN117476640A CN 117476640 A CN117476640 A CN 117476640A CN 202311295787 A CN202311295787 A CN 202311295787A CN 117476640 A CN117476640 A CN 117476640A
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transistor
substrate
layer
epitaxial structure
epitaxial
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CN117476640B (en
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吴恒
张磊
黎明
王润声
黄如
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Peking University
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Peking University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The application provides a semiconductor preparation method, a semiconductor structure and a chip. The method comprises the following steps: forming a first laminated structure and a second laminated structure on a substrate, wherein the first laminated structure is used for forming a first transistor, the second laminated structure is used for forming a second transistor, and a first sacrificial layer is formed between the first laminated structure and the substrate and between the second laminated structure and the substrate; removing a portion of the first sacrificial layer between the second stacked structure and the substrate to form a gap between the second stacked structure and the substrate; forming a BDI layer in the gap; and forming a first epitaxial structure and a second epitaxial structure of the first transistor and a third epitaxial structure of the second transistor, wherein the first epitaxial structure and the second epitaxial structure form a source electrode and/or a drain electrode of the first transistor, the third epitaxial structure forms a source electrode and/or a drain electrode of the second transistor, and the BDI layer is arranged between the third epitaxial structure and the substrate. Through the present application, both BDI layers and ESD protection are provided.

Description

Semiconductor preparation method, semiconductor structure and chip
Technical Field
The present application relates to the field of semiconductor technology, and in particular, to a semiconductor fabrication method, a semiconductor structure, and a chip.
Background
A Gate-All-Around NanoSheet (GAA NS) structured field effect transistor (Field Effect Transistor, FET), alternatively referred to as GAA-FET, is capable of carrying larger currents and maintaining smaller dimensions. GAA transistors have evolved on the basis of fin field effect transistors. Fin field effect transistors are also known as finfets. The GAA transistor reduces the supply voltage and enhances the current driving capability compared to the fin field effect transistor, thereby further improving the performance. In particular, GAA-FETs have better electrostatic properties than FinFETs.
The use of GAA transistors in large scale, even very large scale, integrated circuits may cause severe bottom parasitic channel leakage. To address this problem, a bottom dielectric isolation (Bottom Dielectric Isolation, BDI) layer is provided under the source, drain, gate, etc. regions of the GAA transistor.
In everyday use, electrostatic discharge (Electro Static Discharge, ESD) tends to interfere with the normal operation of a semiconductor device and even damage the semiconductor device. In general, a diode having a substrate as a current drain path may be prepared to achieve electrostatic protection.
However, since the BDI layer is disposed between the GAA transistor and the underlying substrate, the underlying substrate cannot serve as a bleed-off path for the electrostatic discharge current. How to protect the GAA transistor with BDI layer from ESD is a problem to be solved.
Disclosure of Invention
The present application relates to a semiconductor fabrication method, semiconductor structure and chip to provide ESD protection for GAA transistors with BDI layers.
In a first aspect, the present application provides a semiconductor fabrication method. The method comprises the following steps: forming a first laminated structure and a second laminated structure on a substrate, wherein the first laminated structure is used for forming a first transistor, the second laminated structure is used for forming a second transistor, and a first sacrificial layer is formed between the first laminated structure and the substrate and between the second laminated structure and the substrate; removing a portion of the first sacrificial layer between the second stacked structure and the substrate to form a gap between the second stacked structure and the substrate; forming a BDI layer in the gap; and forming a first epitaxial structure and a second epitaxial structure of the first transistor and a third epitaxial structure of the second transistor, wherein the first epitaxial structure and the second epitaxial structure form a source electrode and/or a drain electrode of the first transistor, the third epitaxial structure forms a source electrode and/or a drain electrode of the second transistor, and the BDI layer is arranged between the third epitaxial structure and the substrate.
In some possible embodiments, removing the portion of the first sacrificial layer between the second stacked structure and the substrate to form a gap between the second stacked structure and the substrate may include: forming a protective layer to cover the first laminated structure and the second laminated structure; removing a part of the protective layer corresponding to the second laminated structure through photoetching; and removing the part of the first sacrificial layer, which is positioned between the second laminated structure and the substrate, by wet etching to form a gap.
In some possible embodiments, the protective layer may include a linear oxide layer and an amorphous carbon layer.
In some possible embodiments, the operation of forming the BDI layer within the gap may include: forming a first isolation layer on the lower surface of the second laminated structure and the upper surface of the substrate through surface growth; a BDI layer is formed between the first isolation layer of the lower surface of the second stacked structure and the first isolation layer of the upper surface of the substrate.
In some possible embodiments, the above method may further comprise: removing a portion of the first sacrificial layer between the first stacked structure and the substrate;
a metal gate is formed at a position of the portion where the first sacrificial layer is removed, wherein the metal gate is located between the first transistor and the substrate.
In some possible embodiments, the material of the first sacrificial layer may be SiGe.
In a second aspect, the present application provides a semiconductor structure. The semiconductor structure includes a substrate, a first transistor, a second transistor, and a BDI layer. The first transistor and the second transistor are arranged on the substrate. The first transistor includes a first epitaxial structure and a second epitaxial structure. The first epitaxial structure and the second epitaxial structure constitute a source and/or a drain of the first transistor. The first epitaxial structure, the second epitaxial structure and the substrate form an electrostatic discharge path. The second transistor includes a third epitaxial structure. The third epitaxial structure constitutes the source and/or drain of the second transistor. The BDI layer is interposed between the third epitaxial structure and the substrate.
In some possible embodiments, the first epitaxial structure and the second epitaxial structure may have different conductivity types and are both in contact with the substrate.
In some possible embodiments, the first epitaxial structure may be an N-type epitaxial structure and the second epitaxial structure may be a P-type epitaxial structure; alternatively, the first epitaxial structure may be a P-type epitaxial structure and the second epitaxial structure may be an N-type epitaxial structure.
In a third aspect, the present application provides a chip. The chip comprises a semiconductor structure as described in the second aspect.
By the scheme of the application, the semiconductor structure comprises a first transistor and a second transistor. In the region corresponding to the first transistor, the first epitaxial structure, the substrate, and the second epitaxial structure of the first transistor constitute an electrostatic discharge path capable of bleeding off the ESD current, thereby providing ESD protection for the semiconductor structure.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic layout of a semiconductor structure provided in an embodiment of the present application.
Fig. 2 is a cross-sectional view of a semiconductor structure provided in an embodiment of the present application.
Fig. 3 is a flow chart of a semiconductor manufacturing method provided in an embodiment of the present application.
Fig. 4A to 4M are schematic views of respective steps of a semiconductor manufacturing method provided in an embodiment of the present application.
Reference numerals illustrate:
g: a gate; NS: a nanosheet; 100: a first transistor; 101: a first epitaxial structure; 102: a second epitaxial structure; 110: a first laminated structure; 111: a Si layer; 112: a SiGe layer; 200: a second transistor; 201: a third epitaxial structure; 210: a second laminated structure; s: a substrate; 3: a BDI layer; 5: a second isolation layer; 6: a metal; 7: a first oxide layer; 8: a first sacrificial layer; 9: a metal gate; 12: positive photoresist; 13: a second oxide layer; 14: a dummy gate; 15: a nitride layer; 16: an amorphous carbon layer; 17: a first isolation layer; 18: and a third isolation layer.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same reference numerals in different drawings may refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application.
The embodiment of the application provides a semiconductor structure. Fig. 1 is a schematic layout of a semiconductor structure provided in an embodiment of the present application. As shown in fig. 1, the semiconductor structure includes a first transistor 100 and a second transistor 200.
The first transistor 100 is used for ESD protection. The first transistor may be referred to as an ESD transistor or an ESD device. The region where the first transistor 100 is located is shown by the dashed box identified by 100 in the figure. The first transistor 100 includes a gate structure G and a nano-sheet (NS).
The second transistor 200 is used to perform normal transistor functions, e.g., switching, amplifying, etc. The region where the second transistor 200 is located is shown by the dashed box identified in figure 200. The second transistor 200 includes a gate structure G and a nano-sheet NS.
In an embodiment, the first transistor 100 and/or the second transistor 200 may be GAA transistors. For example, the first transistor 100 and/or the second transistor 200 may be nanoflake field effect transistors. For example, the first transistor 100 and/or the second transistor 200 may be nanowire field effect transistors. Of course, the first transistor 100 and/or the second transistor 200 may be other types of transistors, which are not specifically limited in the embodiments of the present application.
In the semiconductor structure, the number of the first transistors 100 may be one or more, and the number of the second transistors 200 may be one or more. In an embodiment, the number of second transistors 200 may be much greater than the number of first transistors 100. For example, the number of second transistors 200 may be an order of magnitude greater than the number of first transistors 100. In an embodiment, the size of the first transistor 100 may be larger than the size of the second transistor 200. For example, the area occupied by the first transistor 100 may be much larger than the area occupied by the second transistor 200.
The first transistor 100 may implement electrostatic discharge in case that a preset condition is satisfied. In one embodiment, the preset condition may be related to a supply voltage (e.g., VDD). In an example, the first transistor 100 may implement electrostatic discharge in the case where the voltage applied across the first transistor 100 exceeds a power supply voltage of 1.1 times or 1.2 times.
Fig. 2 is a cross-sectional view of a semiconductor structure provided in an embodiment of the present application. The cross-sectional view for the first transistor 100 is taken along the A1-A1 'direction and the B1-B1' direction, respectively. The cross-sectional views for the second transistor 200 are taken along the A2-A2 'direction and the B2-B2' direction, respectively.
As shown in fig. 2, the semiconductor structure of the embodiment of the present application may include a substrate S, a first transistor 100, a second transistor 200, and a BDI layer 3. The first transistor 100 and the second transistor 200 are arranged on a substrate S.
The first transistor 100 includes a first epitaxial structure 101 and a second epitaxial structure 102. A metal 6 is provided on the first epitaxial structure 101 and the second epitaxial structure 102. The metal 6 forms a metal contact with the first epitaxial structure 101 and the second epitaxial structure 102, respectively. The metal 6 passes through the second isolation layer 5 and the first oxide layer 7. The second transistor 200 comprises a third epitaxial structure 201. A metal 6 is provided on the third epitaxial structure 201. The metal 6 makes a metal contact with the third epitaxial structure 201. The metal 6 passes through the second isolation layer 5 and the first oxide layer 7.
The BDI layer 3 is disposed between the second transistor 200 and the substrate S. In one embodiment, the BDI layer 3 may be made of a low dielectric (low-K) material. For example, BDI layer 3 may be SiO 2 Or a dielectric film made of other materials.
Either of the first epitaxial structure 101 and the second epitaxial structure 102 constitutes a source and/or a drain of the first transistor 100. For example, the first epitaxial structure 101 may constitute a source and a drain, and the second epitaxial structure 102 may constitute a source and a drain. The first epitaxial structure 101, the substrate S, and the second epitaxial structure 102 constitute an electrostatic discharge path. In an embodiment, the first epitaxial structure 101 may be an N-type epitaxial structure and the second epitaxial structure 102 may be a P-type epitaxial structure. ESD current may flow from the first epitaxial structure 101 through the substrate S to the second epitaxial structure 102. In one embodiment, the first epitaxial structure may be a P-type epitaxial structure and the second epitaxial structure 102 may be an N-type epitaxial structure. ESD current may flow from the second epitaxial structure 102 to the first epitaxial structure 101 through the substrate S.
The third epitaxial structure 201 constitutes the source and/or drain of the second transistor 200. The third epitaxial structure 201 may have the same conductivity type as the first epitaxial structure 101 or the second epitaxial structure 102. In an embodiment, the third epitaxial structure 201 may be an N-type epitaxial structure. In an embodiment, the third epitaxial structure 201 may be a P-type epitaxial structure.
In an embodiment, the metal gate 9 may be formed in the first transistor 100. A high dielectric material and/or an isolation layer may be provided between the metal gate 9 and the substrate S. In one example, a high dielectric material may be employed such as hafnium oxide. In an embodiment, a portion of the metal gate 9 (e.g., the lowermost metal gate 9 in the first transistor 100 in fig. 2) may be at substantially the same height as the BDI layer 3 at the second transistor 200.
In the embodiment of the application, the semiconductor structure can be applied to semiconductor devices such as memories, processors and the like. In particular, the semiconductor structure described above may be used to implement a chip. In other words, the semiconductor structure of embodiments of the present application may be included in a packaged chip.
The embodiment of the application also provides a semiconductor preparation method. The method is used for preparing the semiconductor structure in the embodiment of the application. Fig. 3 is a flow chart of a semiconductor manufacturing method provided in an embodiment of the present application. As shown in fig. 3, the semiconductor manufacturing method of the embodiment of the present application includes steps S310 to S340.
In step S310, a first stacked structure and a second stacked structure are formed on a substrate.
In this step, a substrate may be provided, a first sacrificial layer is formed on the substrate, and a first laminated structure and a second laminated structure are formed on the first sacrificial layer. The first stacked structure is used to form a first transistor. The second stacked structure is used to form a second transistor.
In one embodiment, the substrate may be made of various materials. For example, the first substrate may be a silicon substrate, a germanium substrate. At this time, the first substrate may be a substrate formed of a silicon wafer, a germanium wafer, or the like. For another example, the first substrate may be a silicon-on-insulator (SOI) substrate. In this case, the first substrate may be a substrate obtained by processing a silicon wafer.
In an embodiment, the first transistor and the second transistor formed over the first substrate may be different in size, number, position, and the like. For example, the size of the first transistor may be larger than the size of the second transistor. For example, the number of first transistors may be less than the number of second transistors. For example, the first transistor may be located adjacent to or remote from the second transistor.
In step S320, a portion of the first sacrificial layer located between the second stacked structure and the substrate is removed.
In this step, a portion of the first sacrificial layer between the second stacked structure and the substrate may be removed, and a portion of the first sacrificial layer between the first stacked structure and the substrate may be left. In this way, a gap is formed between the first sacrificial layer and the second stacked structure and the substrate.
In an embodiment, step S320 may include: forming a protective layer to cover the first laminated structure and the second laminated structure; removing a part of the protective layer corresponding to the second laminated structure through photoetching; and removing the part of the first sacrificial layer, which is positioned between the second laminated structure and the substrate, by wet etching to form a gap.
In one embodiment, the protective layer may include a linear oxide layer and an amorphous carbon layer. The linear oxide layer may be an oxide layer formed by atomic layer deposition (Atomatic Layer Deposition, ALD). The linear oxide layer may be formed on the first and second stacked structures. An amorphous carbon layer may be formed on the linear oxide layer.
In an embodiment, the photolithography process for removing the portion of the protective layer corresponding to the second stacked structure may be implemented by a positive photoresist or a negative photoresist.
In one embodiment, the photolithography process may use positive photoresist. Specifically, a positive photoresist is coated on the protective layer corresponding to the first transistor. Thereafter, the positive photoresist is exposed to light using a mask to pattern the positive photoresist. The portion of the positive photoresist corresponding to the first transistor is exposed and the portion corresponding to the second transistor is not exposed. The exposed portions of the positive photoresist remain and the unexposed portions are removed. The patterned positive photoresist exposes portions of the protective layer corresponding to the second transistors and portions of the protective layer corresponding to the first transistors. Next, the protective layer is etched. The portion of the protective layer corresponding to the second transistor is etched. The portion of the protective layer corresponding to the first transistor is not etched due to the protection of the positive photoresist. In this way, only the portion of the protective layer corresponding to the second transistor is removed.
In one embodiment, the photolithography process may use a negative photoresist. Specifically, a negative photoresist is coated on the protective layer corresponding to the second transistor. Thereafter, the negative photoresist is exposed to light using a mask to pattern the negative photoresist. The portion of the negative photoresist corresponding to the second transistor is exposed, and the portion corresponding to the first transistor is not exposed. The exposed portions of the negative photoresist are removed and the unexposed portions remain. The patterned negative photoresist exposes portions of the protective layer corresponding to the second transistors and portions of the protective layer corresponding to the first transistors. Next, the protective layer is etched. The portion of the protective layer corresponding to the second transistor is etched. The portion of the protective layer corresponding to the first transistor is not etched due to the protection of the negative photoresist. In this way, only the portion of the protective layer corresponding to the second transistor is removed.
In an embodiment, after the protective layer is removed, a portion of the first sacrificial layer between the second stacked structure and the substrate may be removed by wet etching.
In step S330, a BDI layer is formed in the gap.
In this step, a BDI layer is formed in the gap formed between the second stacked structure and the substrate. The BDI layer is a dielectric layer and separates the second transistor from the substrate. In one embodiment, the BDI layer may be formed of, for example, siO 2 Such as a low dielectric material. In one embodiment, the low dielectric material may be formed by ALD on the lower surface of the second stacked structure and the upper surface of the substrate, and eventually filling the entire gap to form the BDI layer.
In an embodiment, the first isolation layer may be formed on the lower surface of the second stacked structure and the upper surface of the substrate before the BDI layer is formed. For example, formation of SiN material on the first stacked structure, the second stacked structure, and the lower surface of the second stacked structure and the upper surface of the substrate through interfacial growth may be performed, thereby forming a first isolation layer on the lower surface of the second stacked structure and the upper surface of the substrate.
In step S340, a first epitaxial structure, a second epitaxial structure, and a third epitaxial structure are formed.
In this step, the epitaxial structures of the first transistor and the second transistor may be formed by epitaxial growth. The first epitaxial structure and the second epitaxial structure each constitute a source and/or a drain of the first transistor. The third epitaxial structure constitutes the source and/or drain of the second transistor.
It should be noted that the materials of the first epitaxial structure and the second epitaxial structure may have opposite conductivity types. Here, the conductivity type refers to conductivity with electrons or conductivity with holes. Then the conductivity type is N-type or P-type, respectively. In one embodiment, the first epitaxial structure and the second epitaxial structure are N-type and P-type, respectively. In one embodiment, the first epitaxial structure and the second epitaxial structure are P-type and N-type, respectively.
After step S340, the middle-of-line process and/or the back-end process may be continued to complete the preparation of the first transistor and the second transistor.
In an embodiment, the metal gate of the first transistor may be formed during the performance of the middle-end-of-line process and/or the back-end-of-line process. In an example, the operation of forming the metal gate of the first transistor may include: removing a portion of the first sacrificial layer between the first stacked structure and the substrate; a metal gate is formed at a position of the portion where the first sacrificial layer is removed, wherein the metal gate is located between the first transistor and the substrate. In this way, a portion of the metal gate may be formed at a position where a portion of the first sacrificial layer is removed so as to be disposed between the first transistor and the substrate. In an example, the portion of the metal gate may be at substantially the same height as the BDI layer of the second transistor. In an example, the portion of the metal gate may have substantially the same thickness as the BDI layer of the second transistor.
Hereinafter, a method for manufacturing the semiconductor structure in the embodiment of the present application is described in detail.
Fig. 4A to 4M are schematic views of respective steps of a semiconductor manufacturing method provided in an embodiment of the present application. Various steps of the fabrication method shown in fig. 4A to 4M may be used to fabricate the semiconductor structure shown in fig. 2.
In a first step, a first stacked structure 110 and a second stacked structure 210 are formed on a substrate S (see fig. 4A).
In one embodiment, the substrate S may be implemented by a silicon wafer. In an embodiment, the substrate S may be implemented as SOI. In one embodiment, the substrate S may be implemented by a Ge wafer.
In this step a layer of SiGe is formed as a first sacrificial layer 8 on the substrate S. A first laminated structure 110 and a second laminated structure 210 are formed on the first sacrificial layer 8. The first and second stacked structures 110 and 210 each include a plurality of Si layers 111 and a plurality of SiGe layers 112. The plurality of SiGe layers 112 and the plurality of Si layers 111 are staggered in the vertical direction. Adjacent two Si layers 111 are separated by a SiGe layer 112.
In an embodiment, the first sacrificial layer 8, the first stacked structure 110, and the second stacked structure 210 may be formed by epitaxial growth.
In an embodiment, the first sacrificial layer 8 may be different from the SiGe layers of the first and second stacked structures 110 and 210 in the concentration of SiGe. For example, the concentration of SiGe in the first sacrificial layer 8 may be greater than or equal to 70%, such as about 70%. The concentration of SiGe in the SiGe layers of the first and second stacked structures 110 and 210 may be about 30%. It should be noted that "concentration" in the embodiments of the present application may be a weight ratio.
In the second step, a second oxide layer 13 is formed (see fig. 4B), a dummy gate is formed on the second oxide layer 13 (see fig. 4C), and an amorphous carbon layer is formed (see fig. 4D).
Here, the first and second stacked structures 110 and 210 are etched to obtain the desired size of the nano-sheets. Thereafter, oxide isolation is formed on the substrate S by a shallow trench isolation (Shallow Strench Isolation, STI) process. The second oxide layer 13 is formed on the first and second stacked structures 110 and 210 through an ALD process. The second oxide layer 13 is formed as a linear oxide layer.
Thereafter, a polysilicon layer is formed on the second oxide layer 13 of the first and second stacked structures 110 and 210, and a nitride layer is formed on the polysilicon layer. The polysilicon layer and the nitride layer are etched by a photolithography process to obtain the dummy gate 14 composed of polysilicon and the nitride layer 15 for protecting the dummy gate 14 during etching.
Next, amorphous carbon layer 16 is deposited over first stacked structure 110 and second stacked structure 210. The amorphous carbon layer 16 covers the first and second stacked structures 110 and 210. The upper surface of the protective layer 16 may be flush with the upper surface of the nitride layer 15.
In the third step, the amorphous carbon layer 16 and the second oxide layer 13 on the second stacked structure 210 are removed (see fig. 4E), and the first sacrificial layer 8 between the second stacked structure 210 and the substrate S is removed (see fig. 4F), after which the amorphous carbon layer 16 and the second oxide layer 13 on the first stacked structure 110 are removed (see fig. 4G).
In this step, photoresist 12 is formed on amorphous carbon layer 16. The photoresist 12 on the first stacked structure 110 is exposed to light to harden the photoresist 12. Photoresist 12 on the second stacked structure 210 is removed. In this manner, the photoresist 12 is patterned. Next, the amorphous carbon layer 16 and the second oxide layer 13 on the second stacked structure 210 are removed by an etching process under the action of the patterned photoresist 12. Here, the etching process may include dry etching, wet etching.
Then, a portion of the first sacrificial layer 8 located between the second stacked structure 210 and the substrate S is removed by wet etching. In this way, a gap is formed between the second stacked structure 210 and the substrate S. Finally, the amorphous carbon layer 16 and the second oxide layer 13 on the first stacked structure 110 are removed.
In the fourth step, the first spacer 17 is formed in the gap (see fig. 4H), and the BDI layer 3 is formed (see fig. 4I).
In this step, surface growth is performed on the first stacked structure 110, the second stacked structure 210, and the substrate S to form SiN. SiN is formed on the surface of the first stacked structure 110, the surface of the second stacked structure 210, and the surface of the substrate S corresponding to the second stacked structure 210. Thus, the first isolation layer 17 is formed on the lower surface of the second stacked structure 210 and the upper surface of the substrate S.
Next, a low dielectric material is deposited at the first and second stacked structures 110 and 210. As such, the BDI layer 3 is formed between the first isolation layer 17 at the lower surface of the second stacked structure 210 and the first isolation layer 17 at the upper surface of the corresponding substrate S. Here, the deposition of the low dielectric material may be achieved using an ALD process. The low dielectric material may be deposited not only between the second stacked structure 210 and the substrate S, but also on the first stacked structure 110 and the second stacked structure 210.
In a fifth step, the excess SiN and low dielectric material are removed by an etching process, and the excess portions of the first and second stacked structures 110 and 210 are removed (see fig. 4J), followed by forming the third isolation layer 18 (see fig. 4K).
In this step, excess SiN and low dielectric material located on the first and second stacked structures 110 and 210 is first removed by anisotropic etching to expose a portion of the first stacked structure 110 and a portion of the second stacked structure 210. Thereafter, the exposed first and second stacked structures 110 and 210 are cut to remove the unnecessary portions, thereby obtaining columnar first and second stacked structures 110 and 210.
After that, the SiGe layer in the first laminated structure 110, the first sacrificial layer 8, and the SiGe layer in the second laminated structure 210 are laterally etched. SiN is deposited by an ALD process in the etched space to form a third isolation layer 18.
In a sixth step, a first epitaxial structure 101, a second epitaxial structure 102, and a third epitaxial structure 201 are formed (see fig. 4L).
In this step, the first epitaxial structure 101 and the second epitaxial structure 102 are formed at the first stacked structure 110 by epitaxial growth. The first epitaxial structure 101 is an N-type epitaxial structure. The first epitaxial structure 101 constitutes the source and/or drain of the first transistor 100. The second epitaxial structure 102 is a P-type epitaxial structure. The second epitaxial structure 102 constitutes the source and/or drain of the first transistor 100. Meanwhile, a third epitaxial structure 201 is formed at the second stacked structure 210 by epitaxial growth. The third epitaxial structure 201 is an N-type epitaxial structure. The third epitaxial structure 201 constitutes the source and/or drain of the second transistor 200. The first epitaxial structure 101, the substrate S, and the second epitaxial structure 102 may constitute an ESD path. ESD current may flow from the first epitaxial structure 101 through the substrate S to the second epitaxial structure 102.
In an alternative embodiment, the first epitaxial structure 101 and the third epitaxial structure 201 may be P-type epitaxial structures and the second epitaxial structure 102 may be N-type epitaxial structures. At this time, the first epitaxial structure 101, the substrate S, and the second epitaxial structure 102 may constitute an ESD path. ESD current may flow from the second epitaxial structure 102 to the first epitaxial structure 101 through the substrate S.
In the seventh step, the middle-stage process and the back-stage process of the first transistor 100 and the second transistor 200 are completed (see fig. 4M).
In this step, the nitride layer 15 may be removed by chemical-mechanical polishing (CMP) and the dummy gate 14 may be removed. Thereafter, a second isolation layer 5 and a first oxide layer 7 are deposited. The SiGe layer between the nanoplates is removed and a metal gate 9 is deposited. Finally, a metal is formed on the first epitaxial structure 101, the second epitaxial structure 102, and the third epitaxial structure 103 to form a metal contact.
In an embodiment, the first oxide layer 7 may be an interlayer dielectric (Interlayer Dielectric, ILD). In an embodiment, the second isolation layer 5 may be made of a material such as SiON. In an embodiment, a high dielectric material (e.g., hfO 2 ) And/or a spacer material.
The semiconductor structure of the embodiment of the application can be prepared through the above method steps. Based on this method, the photoresist is patterned through a mask, so that only the first sacrificial layer 8 corresponding to the second transistor 200 is etched, and the first sacrificial layer 8 corresponding to the first transistor 100 remains. In this way, the BDI layer 3 is formed only in the region corresponding to the second transistor 200. The first transistor 100 may constitute an ESD path, implementing ESD protection of the semiconductor structure. Furthermore, the fabrication of the first transistor 100 for ESD protection in a semiconductor structure is achieved by an additional mask, which is simpler and more convenient for both packaging and wire-making of the chip in which the semiconductor structure is located.
In the description of the present application, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In this application, the schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described herein, as well as the features of the various embodiments or examples, may be combined by those skilled in the art without contradiction.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations can be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (10)

1. A method of manufacturing a semiconductor, comprising:
forming a first laminated structure and a second laminated structure on a substrate, wherein the first laminated structure is used for forming a first transistor, the second laminated structure is used for forming a second transistor, and a first sacrificial layer is formed between the first laminated structure and the substrate and between the second laminated structure and the substrate;
removing a portion of the first sacrificial layer between the second stacked structure and the substrate to form a gap between the second stacked structure and the substrate;
forming a bottom dielectric isolation BDI layer in the gap;
forming a first epitaxial structure and a second epitaxial structure of the first transistor and a third epitaxial structure of the second transistor, wherein the first epitaxial structure and the second epitaxial structure form a source electrode and/or a drain electrode of the first transistor, the third epitaxial structure forms a source electrode and/or a drain electrode of the second transistor, and the BDI layer is arranged between the third epitaxial structure and the substrate.
2. The method of claim 1, wherein the removing the portion of the first sacrificial layer between the second stacked structure and the substrate to form a gap between the second stacked structure and the substrate comprises:
forming a protective layer to cover the first laminated structure and the second laminated structure;
removing a part of the protective layer corresponding to the second laminated structure through photoetching;
and removing the part, located between the second laminated structure and the substrate, of the first sacrificial layer by wet etching to form the gap.
3. The method of claim 2, wherein the protective layer comprises a linear oxide layer and an amorphous carbon layer.
4. The method of claim 1, wherein forming a BDI layer within the gap comprises:
forming a first isolation layer on the lower surface of the second laminated structure and the upper surface of the substrate through surface growth;
the BDI layer is formed between the first isolation layer of the lower surface of the second laminated structure and the first isolation layer of the upper surface of the substrate.
5. The method according to claim 1, wherein the method further comprises:
removing a portion of the first sacrificial layer between the first stacked structure and the substrate;
a metal gate is formed at a position of the portion where the first sacrificial layer is removed, wherein the metal gate is located between the first transistor and the substrate.
6. The method of any one of claims 1 to 5, wherein the material of the first sacrificial layer is SiGe.
7. A semiconductor structure, comprising:
a substrate;
a first transistor and a second transistor arranged on the substrate;
a bottom dielectric isolation BDI layer;
the first transistor comprises a first epitaxial structure and a second epitaxial structure, the first epitaxial structure and the second epitaxial structure form a source electrode and/or a drain electrode of the first transistor, and the first epitaxial structure, the second epitaxial structure and the substrate form an electrostatic discharge path;
wherein the second transistor comprises a third epitaxial structure, the third epitaxial structure constitutes a source and/or a drain of the second transistor, and the BDI layer is arranged between the third epitaxial structure and the substrate.
8. The semiconductor structure of claim 7, wherein the first epitaxial structure and the second epitaxial structure have different conductivity types and are each in contact with the substrate.
9. The semiconductor structure of claim 8, wherein the first epitaxial structure is an N-type epitaxial structure and the second epitaxial structure is a P-type epitaxial structure;
or the first epitaxial structure is a P-type epitaxial structure, and the second epitaxial structure is an N-type epitaxial structure.
10. A chip, characterized in that it comprises a semiconductor structure according to any of claims 7 to 9.
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