CN117476599A - Photoelectric chip interconnection packaging structure and preparation method thereof - Google Patents
Photoelectric chip interconnection packaging structure and preparation method thereof Download PDFInfo
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- CN117476599A CN117476599A CN202311415631.5A CN202311415631A CN117476599A CN 117476599 A CN117476599 A CN 117476599A CN 202311415631 A CN202311415631 A CN 202311415631A CN 117476599 A CN117476599 A CN 117476599A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 11
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- 230000005693 optoelectronics Effects 0.000 claims description 86
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
Abstract
The invention discloses a photoelectric chip interconnection packaging structure and a preparation method thereof, wherein the photoelectric chip interconnection packaging structure comprises: a package substrate provided with external solder balls; the photoelectric combination body is arranged on the packaging substrate; the photoelectric combination comprises an optical chip and an electric chip which are directly jointed in a die-to-die mode, wherein the optical chip is attached to the packaging substrate and the electric chip is electrically connected to the packaging substrate in a fan-out mode, or the electric chip is attached to the packaging substrate and the optical chip is electrically connected to the packaging substrate in a fan-out mode. In the invention, the optical chip and the electric chip are directly interconnected in a die-to-die mode through the die, a TVS (transient voltage suppressor) interposer is not needed, the advantages of low power consumption, low delay and high bandwidth efficiency are achieved, the process flow is simplified, UPH (unified power flow) is improved, the expenditure of materials, equipment, manpower and the like is reduced, the fan-out technology is adopted, the electric chip or the optical chip is rearranged and a circuit is led out, and the interconnection between different chips is realized.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to an interconnection packaging structure of a photoelectric chip and a preparation method thereof.
Background
Hybrid packaging of optoelectronic chips has become a mainstream of future development, and the main function of the optoelectronic packages is to perform interconversion of optical signals and electrical signals, or to perform operations using the optoelectronic chips.
Referring to fig. 1, a schematic structure diagram of a prior art optoelectronic chip interconnection package structure in an embodiment is shown. As shown in fig. 1, in the package structure, the package structure includes a substrate 91, an optoelectronic assembly disposed on the substrate 91, and a protective cover 92 disposed on the substrate 91 to cover the optoelectronic assembly, in the optoelectronic assembly, an optical chip 93 is flip-chip connected to a TSV (Through-Silicon-Via) interposer 95 Through a circuit layer, an electrical chip 94 is connected to the TSV interposer 95 Through a circuit layer, and the TSV interposer 95 is further connected to the substrate 91 Through a lead 96, wherein the substrate is provided with an optical window corresponding to an optical outlet of the optical chip 93. In the packaging structure, due to the adoption of the TSV intermediate plate, the whole process is complex, the cost is high, the optical chip and the electric chip are electrically connected with the TSV intermediate plate through the circuit layer, the chip mounting is difficult, the yield is low, the mass production is difficult, in addition, the supply chain is complex, and the quality control is difficult.
Disclosure of Invention
The invention aims to solve the problems of complex process, difficult quality control, high cost and the like of the conventional photoelectric chip interconnection packaging structure, and provides a photoelectric chip interconnection packaging structure and a preparation method thereof.
To achieve the above and other objects, the present invention provides an optoelectronic chip interconnection package structure, including:
a package substrate provided with external solder balls; and
the photoelectric combination body is arranged on the packaging substrate; the photoelectric combination comprises an optical chip and an electric chip which are directly jointed in a die-to-die mode, wherein the optical chip is attached to the packaging substrate and the electric chip is electrically connected to the packaging substrate in a fan-out mode, or the electric chip is attached to the packaging substrate and the optical chip is electrically connected to the packaging substrate in a fan-out mode.
As an implementation manner, in the photoelectric combination, the optical chip is mounted on a supporting board, the supporting board is arranged on the packaging substrate, the electric chip is mounted on the optical chip in a flip-chip manner, the electric chip extends outwards in a fan-out manner to form a fan-out structure, and the fan-out structure is electrically connected with the packaging substrate through an electrical connection structure.
As one embodiment, the support plate includes any one of a ceramic substrate, a glass substrate, and a silicon substrate, or any combination thereof.
In one embodiment, in the optoelectronic combination, the optical chip is disposed on the package substrate, the electrical chip is mounted on the optical chip in a flip-chip manner, the electrical chip extends outwards in a fan-out manner to form a fan-out structure, and the fan-out structure is electrically connected to the package substrate through an electrical connection structure.
In one embodiment, in the photoelectric combination, the optical chip is disposed on the packaging substrate, the electrical chip is mounted on the optical chip in a flip-chip manner, the electrical chip extends outwards in a fan-out manner to form a fan-out structure, the packaging substrate is a concave packaging substrate, metal lines are disposed on the protruding edges of the packaging substrate, and the fan-out structure of the electrical chip is electrically connected to the packaging substrate through the metal lines.
As an implementation manner, in the photoelectric combination, the electrical chip is disposed on the packaging substrate, the optical chip is attached to the electrical chip in a flip-chip manner, the optical chip extends outwards in a fan-out manner to form a fan-out structure, the fan-out structure is electrically connected to the packaging substrate through an electrical connection structure, and the packaging substrate is provided with an optical window corresponding to an optical outlet of the optical chip; or in the photoelectric combination, the electric chip is arranged on the packaging substrate, the optical chip is mounted on the electric chip in a flip-chip manner, the optical chip outwards extends in a fan-out manner to form a fan-out structure, the packaging substrate is a concave packaging substrate, a metal circuit is arranged at the protruding edge of the packaging substrate, the fan-out structure of the optical chip is electrically connected with the packaging substrate through the metal circuit, and the packaging substrate is provided with an optical window corresponding to an optical outlet of the optical chip.
As an implementation manner, the package substrate is internally provided with a heat dissipation structure penetrating through the thickness direction of the package substrate.
As an embodiment, the electrical connection structure includes an interposer, or the electrical connection structure includes conductive pillars or solder balls formed using bump technology.
As one embodiment, the package substrate includes any one of an organic substrate, a ceramic substrate, a glass substrate, and a silicon substrate, or any combination thereof.
Correspondingly, the invention also provides a preparation method of the photoelectric chip interconnection packaging structure, which comprises the following steps: manufacturing an optoelectronic combination, and manufacturing an optical chip and an electrical chip which are mutually jointed in a die-to-die mode; providing a packaging substrate provided with external solder balls, and arranging the photoelectric combination body on the packaging substrate; the implementation manner of arranging the photoelectric combination on the packaging substrate comprises the following steps: attaching the optical chip in the photoelectric combination body to the packaging substrate, and electrically connecting the electric chip to the packaging substrate in a fan-out mode; or, attaching the electric chip in the photoelectric combination body to the packaging substrate, and electrically connecting the optical chip to the packaging substrate in a fan-out mode.
As an embodiment, the step of fabricating the optoelectric complex, and fabricating the optical chip and the electrical chip bonded to each other in a die-to-die manner, includes: providing an electric chip, rewiring the surface of the electric chip and leading out a circuit in a fan-out mode; attaching the electrical chip to the optical chip in a flip-chip manner; the step of attaching the optical chip in the optoelectronic combination to the package substrate and electrically connecting the electrical chip to the package substrate in a fan-out manner includes: attaching the optical chip in the photoelectric combination to the packaging substrate; and manufacturing an electric connection structure on the packaging substrate, and electrically connecting the circuit led out by the electric chip in a fan-out mode to the packaging substrate through the electric connection structure.
As an implementation manner, the preparation method of the optoelectronic chip interconnection packaging structure further includes the steps of: and mounting the optical chip on a supporting plate, and arranging the optical chip on the packaging substrate through the supporting plate.
As an embodiment, the step of fabricating the optoelectric complex, and fabricating the optical chip and the electrical chip bonded to each other in a die-to-die manner, includes: providing an electric chip, rewiring the surface of the electric chip and leading out a circuit in a fan-out mode; attaching the electrical chip to the optical chip in a flip-chip manner; the step of attaching the optical chip in the optoelectronic combination to the package substrate and electrically connecting the electrical chip to the package substrate in a fan-out manner includes: the provided packaging substrate is a concave packaging substrate, metal circuits are manufactured on the convex edges of the packaging substrate, and the circuits led out of the electric chip in a fan-out mode are electrically connected to the packaging substrate through the metal circuits.
As an embodiment, the step of fabricating the optoelectric complex, and fabricating the optical chip and the electrical chip bonded to each other in a die-to-die manner, includes: providing an electrical chip, rewiring the surface of the optical chip and leading out a circuit in a fan-out mode; attaching the optical chip to the optical chip in a flip-chip manner; the step of attaching the electrical chip in the optoelectronic combination to the package substrate and electrically connecting the optical chip to the package substrate in a fan-out manner includes: the provided packaging substrate is a concave packaging substrate, metal circuits are manufactured on the convex edges of the packaging substrate, and the circuits led out of the optical chip in a fan-out mode are electrically connected with the packaging substrate through the metal circuits; a light window corresponding to the light outlet of the optical chip is arranged on the packaging substrate; or, attaching the electric chip in the photoelectric combination body to the packaging substrate; and manufacturing an electric connection structure at the edge of the packaging substrate, and electrically connecting the circuits led out by the optical chip in a fan-out mode to the packaging substrate through the electric connection structure.
As an implementation manner, the preparation method of the optoelectronic chip interconnection packaging structure further includes the steps of: and manufacturing a heat dissipation structure penetrating through the thickness direction of the packaging substrate in the packaging substrate.
The invention has the beneficial effects that: the invention discloses an interconnection packaging structure of photoelectric chips and a preparation method thereof, wherein the photoelectric chips and the electric chips are directly interconnected in a bare chip mode through bare chips, a TVS (transient voltage suppressor) intermediate plate is not needed, the method has the advantages of low power consumption, low delay and high bandwidth efficiency, the process flow is simplified, UPH (unified power head) is improved, the expenditure of materials, equipment, manpower and the like is reduced, the fan-out technology is adopted, and the electric chips or the photoelectric chips are rearranged and circuits are led out, so that the interconnection among different chips is realized.
Drawings
Fig. 1 is a schematic structural diagram of a prior art optoelectronic chip interconnection package structure in an embodiment.
Fig. 2 and fig. 3 are schematic structural diagrams of the interconnection package structure of the optoelectronic chip according to the present invention in the first embodiment.
Fig. 4 is a schematic structural diagram of an interconnection package structure of an optoelectronic chip according to a second embodiment of the present invention.
Fig. 5 is a schematic structural diagram of an interconnection package structure of an optoelectronic chip according to a variation of the second embodiment of the present invention.
Fig. 6 is a schematic structural diagram of an interconnection package structure of an optoelectronic chip according to a third embodiment of the present invention.
Fig. 7 is a schematic structural diagram of an interconnection package structure of an optoelectronic chip according to a variation of the third embodiment of the present invention.
Fig. 8 is a schematic structural diagram of an interconnection package structure of an optoelectronic chip according to a fourth embodiment of the present invention.
Fig. 9 is a schematic structural diagram of an interconnection package structure of an optoelectronic chip according to a variation of the fourth embodiment of the present invention.
Fig. 10 is a schematic structural diagram of an interconnection package structure of an optoelectronic chip according to a fifth embodiment of the present invention.
Fig. 11 is a schematic structural diagram of an interconnection package structure of an optoelectronic chip according to a variation of the fifth embodiment of the present invention.
Fig. 12 and 13 are schematic structural views of an interconnection package structure for an optoelectronic chip according to a sixth embodiment of the present invention.
Fig. 14 is a schematic structural diagram of an interconnection package structure of an optoelectronic chip according to a variation of the sixth embodiment of the present invention.
Fig. 15 to 25 are schematic structural diagrams of an interconnection package structure of an optoelectronic chip according to a second embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
For ease of description, spatially relative terms such as "under," "above," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" may include both above and below orientations.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
As to the background art, in the existing photoelectric chip interconnection packaging structure, because interconnection between the optical chip and the electric chip needs to use the TSV interposer, the whole process is complex, the cost is high, the chip mounting is difficult, the yield is low, the mass production is difficult, the quality control is difficult, and the like. In view of this, the inventor of the present invention proposes a novel optoelectronic chip interconnection package structure and a method for manufacturing the same, in which the optical chip and the electrical chip are directly interconnected by a die to a die mode, and a TVS interposer is not required, so that the present invention has the advantages of low power consumption, low delay, and high bandwidth efficiency, simplifies the process flow, improves the UPH, and reduces the expenditure of materials, equipment, manpower, etc.
The invention provides an interconnection packaging structure of photoelectric chips, which comprises: the packaging substrate and the photoelectric combination body arranged on the packaging substrate, wherein the packaging substrate is provided with external solder balls, and the photoelectric combination body further comprises an optical chip and an electric chip which are directly connected in a die-to-die mode. In the optoelectronic chip interconnection packaging structure, the optical chip needs light input and light output, and the optoelectronic combination body is arranged on the packaging substrate in different setting modes according to different modes of light input and light output. For example, in some embodiments, in the optoelectronic complex, the optical chip is mounted on the package substrate and the electrical chip is electrically connected to the package substrate in a fan-out manner. In some such embodiments, the electrical chip is mounted on the package substrate and the optical chip is electrically connected to the package substrate in a fan-out fashion.
Referring to fig. 2 and 3, a schematic structural diagram of an interconnection package structure of an optoelectronic chip according to a first embodiment of the present invention is shown. As shown in fig. 2 and 3, the optoelectronic chip interconnection package structure includes:
a package substrate 101, wherein the package substrate 101 is provided with external solder balls 102.
In some embodiments, the package substrate includes any one of or any combination of an organic substrate, a ceramic substrate, a glass substrate, and a silicon substrate, i.e., the package substrate may be an organic substrate, a ceramic substrate, a glass substrate, a silicon substrate, or the like, and the package substrate includes any two or more of an organic substrate, a ceramic substrate, a glass substrate, and a silicon substrate, for example, a combination of a ceramic substrate and an organic substrate, a combination of a silicon substrate and an organic substrate, or the like. In the embodiment shown in fig. 2 and 3, the package substrate 101 may be, for example, an organic substrate.
In some embodiments, the external solder balls may be one or more of tin, indium, titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, for example, tin solder balls, tin lead solder balls, tin silver copper solder balls, or braze balls. In the embodiment shown in fig. 2 and 3, the external solder balls 102 may be, for example, solder balls.
The photoelectric combination is arranged on the packaging substrate 101. The optoelectric combination comprises an optical chip 103 and an electric chip 104 which are directly jointed in a die-to-die mode, wherein the optical chip 103 is attached to a supporting plate 107, the supporting plate 107 is arranged on the packaging substrate 101, the electric chip 104 is attached to the optical chip 103 in a flip-chip mode, the electric chip 104 extends outwards in a fan-out mode to form a fan-out structure, and the fan-out structure is electrically connected with the packaging substrate 101 through an electric connection structure 110. The electrical connection structure 110 is electrically connected to the package substrate 101 through bumps (bumps) 111, and the electrical connection structure 110 includes an insulating layer 108 and a conductive line 109 penetrating the insulating layer 108.
For the optical chip 103, one side may serve as the light entrance LI, and the other side may serve as the light exit LO, and light is emitted in a direction facing away from the package substrate 101.
As described above, the electrical chip 104 is flip-chip mounted on the optical chip 103. In a specific implementation, the implementation in which the electrical chip 104 is flip-chip mounted on the optical chip 103 may include: rewiring fabrication of the wiring layer 105 on the electrical chip 103 using wafer level packaging and growing bumps 106 on the wiring layer 105 to form a fan-out structure; the electrical chip 104 is flip-chip mounted on the optical chip 103, the electrical chip 104 is electrically connected to the optical chip 103 through the wiring layer 105 and the bump 106, and the electrical chip 104 is electrically connected to the electrical connection 110 through the wiring layer 105 and the bump 106. In some embodiments, the material of the circuit layer may be one or more metals selected from aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver. In some embodiments, the circuit layer may be a metal pillar, and the material of the metal pillar may be one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver. The bump may be made of one or more of tin, indium, titanium, copper, aluminum, silver, palladium, gold, thallium, tin, and nickel.
Similarly, as shown in fig. 2, the fan-out structure may include a wiring layer 105 and bumps 106 on the wiring layer 105. In some embodiments, the material of the circuit layer may be one or more metals selected from aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver. In some embodiments, the circuit layer may be a metal pillar, and the material of the metal pillar may be one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver. The bump may be made of one or more of tin, indium, titanium, copper, aluminum, silver, palladium, gold, thallium, tin, and nickel.
In some embodiments, in the optoelectronic combination, the supporting board may be attached to the package substrate by dispensing or solder paste. The support plate includes any one or any combination of a ceramic substrate, a glass substrate, and a silicon substrate, that is, the support plate may be a ceramic substrate, a glass substrate, a silicon substrate, or the like, and the package substrate includes any two or more combinations of a ceramic substrate, a glass substrate, and a silicon substrate, for example, a combination of a ceramic substrate and a glass substrate, a combination of a ceramic substrate and a silicon substrate, or the like. In the embodiment shown in fig. 2 and 3, the package substrate 101 may be, for example, an organic substrate.
In some embodiments, the electrical connection structure may be, for example, an interposer, where the interposer includes any one of or any combination of an organic substrate, a ceramic substrate, a glass substrate, and a silicon substrate, that is, the interposer may be an organic substrate, a ceramic substrate, a glass substrate, or a silicon substrate, and the interposer includes any two or more of an organic substrate, a ceramic substrate, a glass substrate, and a silicon substrate, for example, a combination of a ceramic substrate and an organic substrate, or a combination of a silicon substrate and an organic substrate, and the like. In the embodiment shown in fig. 2 and 3, the electrical connection structure 110 may be, for example, an organic substrate. The conductive lines may be, for example, copper pillars, silver pillars, or other types of metal pillars. The bump may be made of one or more of tin, indium, titanium, copper, aluminum, silver, palladium, gold, thallium, tin, and nickel.
According to the photoelectric chip interconnection packaging structure in the first embodiment of the invention, the optical chip and the electric chip are directly interconnected in a die-to-die mode through the die, a TVS (transient voltage suppressor) interposer is not needed, the advantages of low power consumption, low delay and high bandwidth efficiency are achieved, the process flow is simplified, the chip packaging integration level is improved, UPH (unified power head) is improved, the expenditure of materials, equipment, manpower and the like is reduced, the electric chip adopts a fan-out technology, and the electric chip is rearranged and leads out a circuit, so that the electric connection with a packaging substrate is achieved. In addition, the backup pad adopts ceramic substrate as the carrier plate of optical chip, not only can protect the optical chip, simultaneously because ceramic substrate has lower coefficient of thermal expansion, can effectively reduce optical chip warpage, guarantee welding performance. Furthermore, the packaging substrate adopts an organic substrate, and the supporting plate adopts a ceramic substrate, so that the electric connection of the electric chip and the optical chip can be separated from the electric connection of the electric chip and the packaging substrate, and the high-precision mounting of the chip is realized.
Referring to fig. 4, a schematic structural diagram of an interconnection package structure of an optoelectronic chip according to a second embodiment of the invention is shown.
As shown in fig. 4, the optoelectronic chip interconnection package structure includes:
a package substrate 201, wherein the package substrate 201 is provided with external solder balls 202.
In some embodiments, the package substrate includes any one of or any combination of an organic substrate, a ceramic substrate, a glass substrate, and a silicon substrate, i.e., the package substrate may be an organic substrate, a ceramic substrate, a glass substrate, a silicon substrate, or the like, and the package substrate includes any two or more of an organic substrate, a ceramic substrate, a glass substrate, and a silicon substrate, for example, a combination of a ceramic substrate and an organic substrate, a combination of a silicon substrate and an organic substrate, or the like. In the embodiment shown in fig. 4, the package substrate 201 may be, for example, an organic substrate.
In some embodiments, the external solder balls may be one or more of tin, indium, titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, for example, tin solder balls, tin lead solder balls, tin silver copper solder balls, or braze balls.
The photoelectric combination is arranged on the packaging substrate 201. The optoelectric combination comprises an optical chip 203 and an electric chip 204 which are directly bonded in a die-to-die manner, wherein the electric chip 204 is mounted on the optical chip 203 in a flip-chip manner, and the optical chip 203 is mounted on a packaging substrate 201. The electrical die 204 extends outward in a fan-out fashion to form a fan-out structure that is electrically connected to the package substrate 201 through electrical connection structures 210. The electrical connection structure 210 is electrically connected to the package substrate 201 through bumps (bumps) 211, and the electrical connection structure 210 includes an insulating layer 208 and a conductive line 209 penetrating through the insulating layer 208.
For the optical chip 203, one side may be used as a light inlet, and the other side may be used as a light outlet, and light is emitted in a direction facing away from the package substrate 201.
In some embodiments, in the optoelectronic assembly, the optical chip 203 may be attached to the package substrate 201 by dispensing or by soldering flux, solder paste, or the like.
As described above, the electrical chip 204 is flip-chip mounted on the optical chip 203. In a specific implementation, the implementation in which the electrical chip 204 is flip-chip mounted on the optical chip 203 may include: rewiring on the electrical chip 204 using wafer level packaging to fabricate the wiring layer 205 and growing bumps 206 on the wiring layer 205; the electrical chip 204 is flip-chip mounted on the optical chip 203, the electrical chip 204 is electrically connected to the optical chip 203 through the wiring layer 205 and the bump 206, and the electrical chip 204 is electrically connected to the electrical connection 210 through the wiring layer 205 and the bump 206. In some embodiments, the material of the circuit layer may be one or more metals selected from aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver. In some embodiments, the circuit layer may be a metal pillar, and the material of the metal pillar may be one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver. The bump may be made of one or more of tin, indium, titanium, copper, aluminum, silver, palladium, gold, thallium, tin, and nickel.
Similarly, as shown in fig. 4, the fan-out structure may include a wiring layer 205 and bumps 206 located on the wiring layer 205. In some embodiments, the material of the circuit layer may be one or more metals selected from aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver. In some embodiments, the circuit layer may be a metal pillar, and the material of the metal pillar may be one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver. The bump may be made of one or more of tin, indium, titanium, copper, aluminum, silver, palladium, gold, thallium, tin, and nickel.
It should be noted that, in the second embodiment of the present invention, the electrical chip 204 is flip-chip mounted on the optical chip 203, wherein the electrical chip 204 is subjected to rewiring by using a wafer level package to manufacture the circuit layer 205 and the bump 206 is grown on the circuit layer 205; the electrical chip 204 is flip-chip mounted on the optical chip 203, and the electrical chip 204 is electrically connected to the optical chip 203 through a wiring layer 205 and bumps 206. However, the electrical chip is not limited to this, and other implementations of the electrical chip mounted on the optical chip in a flip-chip manner are possible, for example, please refer to fig. 5, which shows a schematic structural diagram of the interconnection package structure of the optoelectronic chip in a variation of the second embodiment of the present invention. As shown in fig. 5, bumps 206 are grown on electrical chip 204; flip-chip the electrical chip 204 onto the optical chip 203, the electrical chip 204 being electrically connected to the optical chip 203 by bumps 206, and similarly, large bumps 206 are grown on the electrical chip 204; the electrical chip 204 is flip-chip mounted on the optical chip 203, and the electrical chip 204 is electrically connected to the package substrate 201 after being electrically connected to the conductive traces 209 in the electrical connection structure 210 through the bumps 206 in the fan-out structure. In some embodiments, the bump may be made of one or more of tin, indium, titanium, copper, aluminum, silver, palladium, gold, thallium, tin, and nickel.
According to the photoelectric chip interconnection packaging structure in the second embodiment of the invention, the optical chip and the electric chip are directly interconnected in a die-to-die mode through the die, a TVS (transient voltage suppressor) interposer is not needed, the advantages of low power consumption, low delay and high bandwidth efficiency are achieved, the process flow is simplified, the chip packaging integration level is improved, UPH (unified power head) is improved, the expenditure of materials, equipment, manpower and the like is reduced, the electric chip adopts a fan-out technology, and the electric chip is rearranged and leads out a circuit, so that the electric connection with a packaging substrate is achieved.
Referring to fig. 6, a schematic structural diagram of an interconnection package structure of an optoelectronic chip according to a third embodiment of the present invention is shown.
As shown in fig. 6, the optoelectronic chip interconnection package structure includes:
the package substrate 301 is provided with external solder balls 302.
The photoelectric combination is disposed on the package substrate 301. The optoelectric combination comprises an optical chip 303 and an electric chip 304 which are directly bonded in a die-to-die manner, wherein the electric chip 304 is mounted on the optical chip 303 in a flip-chip manner, and the optical chip 303 is mounted on a package substrate 301. The electrical die 304 extends outward in a fan-out fashion to form a fan-out structure that is electrically connected to the package substrate 301 by electrical connection structures 309. Wherein the electrical connection structure 309 is electrically connected to the package substrate 301 through bumps (bumps) 311, the electrical connection structure 309 includes conductive pillars.
For the optical chip 303, one side may be used as a light inlet, and the other side may be used as a light outlet, and light is emitted in a direction facing away from the package substrate 301.
In some embodiments, in the optoelectronic combination, the optical chip 303 may be attached to the package substrate 301 by dispensing or by soldering flux, solder paste, or the like.
As described above, the electrical chip 304 is flip-chip mounted on the optical chip 303. In a specific implementation, the implementation in which the electrical chip 304 is flip-chip mounted on the optical chip 303 may include: a conductive post 305 formed on the electrical chip 304 using electroplating techniques and a bump 306 grown on the conductive post 305; the electrical chip 304 is flip-chip mounted onto the optical chip 303, and the electrical chip 304 is electrically connected to the optical chip 303 through conductive posts 305 and bumps 306. In certain embodiments, the conductive pillars may be, for example, copper pillars, silver pillars, or other types of metal pillars. The bump may be made of one or more of tin, indium, titanium, copper, aluminum, silver, palladium, gold, thallium, tin, and nickel.
Similarly, as shown in fig. 6, the fan-out structure may include an electrical connection structure 309 and a bump 311 on the electrical connection structure 309. In practical applications, the electrical connection structure 309 and the bump 311 may be fabricated in the same process as the conductive pillar 305 and the bump 306 or fabricated in different processes, which is not limited herein. In certain embodiments, the electrical connection structure may be, for example, a copper pillar, a silver pillar, or other types of metal pillars. The bump may be made of one or more of tin, indium, titanium, copper, aluminum, silver, palladium, gold, thallium, tin, and nickel.
In the third embodiment of the present invention, the electrical chip 304 is flip-chip mounted on the optical chip 303, wherein the conductive pillars 305 formed on the electrical chip 304 by bump technology and the bumps 306 are grown on the conductive pillars 305; flip-chip the electrical chip 304 onto the optical chip 303, the electrical chip 304 being electrically connected to the optical chip 303 by conductive pillars 305 and bumps 306; and the electrical die 304 extends outward in a fan-out fashion to form a fan-out structure, which may include an electrical connection structure 309 and bumps 311 on the electrical connection structure 309, the electrical connection structure 309 being electrically connected to the package substrate 301 by the bumps 311. However, the electrical chip is not limited to this, and other implementations of the electrical chip mounted on the optical chip in a flip-chip manner are possible, for example, please refer to fig. 7, which shows a schematic structural diagram of the interconnection package structure of the optoelectronic chip in a variation of the third embodiment of the present invention. As shown in fig. 7, bumps 306 are grown on the electrical chip 304; the electrical chip 304 is flipped onto the optical chip 303, the electrical chip 304 is electrically connected to the optical chip 303 by bumps 306, and similarly, large bumps 311 are grown on the electrical chip 304, the electrical chip 304 is flipped onto the optical chip 303, and the electrical chip 304 is electrically connected to the package substrate 301 by the bumps 311 in a fan-out structure. In some embodiments, the bump may be made of one or more of tin, indium, titanium, copper, aluminum, silver, palladium, gold, thallium, tin, and nickel, for example, a tin solder ball, a tin-lead solder ball, a tin-silver-copper solder ball, or a brazing ball.
According to the photoelectric chip interconnection packaging structure in the third embodiment of the invention, the optical chip and the electric chip are directly interconnected in a die-to-die mode through the die, a TVS (transient voltage suppressor) interposer is not needed, the advantages of low power consumption, low delay and high bandwidth efficiency are achieved, the process flow is simplified, the chip packaging integration level is improved, UPH (unified power head) is improved, the expenditure of materials, equipment, manpower and the like is reduced, the electric chip adopts a fan-out technology, and the electric chip is rearranged and leads out a circuit, so that the electric connection with a packaging substrate is achieved. In addition, compared with the photoelectric chip interconnection packaging structure in the second embodiment and the variation thereof, the electrical connection structure of the photoelectric chip interconnection packaging structure in the third embodiment of the invention is relatively simple, simplifies the structure and the packaging process flow, and can reduce the packaging size and the cost.
Referring to fig. 8, a schematic structural diagram of an interconnection package structure of an optoelectronic chip according to a fourth embodiment of the invention is shown.
As shown in fig. 8, the optoelectronic chip interconnection package structure includes:
a package substrate 401, wherein the package substrate 401 is provided with external solder balls 402. In this embodiment, the package substrate 401 is a concave package substrate, which has a substrate body and a convex edge, and the package substrate 401 is provided with a metal circuit 409 therein.
The photoelectric combination is arranged on the packaging substrate 401. The optoelectric combination comprises an optical chip 403 and an electrical chip 404 directly bonded in a die-to-die manner, wherein the electrical chip 404 is flip-chip mounted on the optical chip 403, and the optical chip 403 is mounted on a concave substrate body of the package substrate 401. The electrical chip 404 extends outward in a fan-out manner to form a fan-out structure, and the fan-out structure is arranged on the convex edge of the package substrate 401 and is electrically connected to the package substrate 401 through the metal wires 409.
In the fourth embodiment of the present invention, the electrical chip 404 is flip-chip mounted on the optical chip 403, wherein the electrical chip 404 is subjected to rewiring by wafer level packaging to manufacture the circuit layer 405 and the bump 406 is grown on the circuit layer 405; the electrical chip 404 is flip-chip mounted onto the optical chip 403, and the electrical chip 404 is electrically connected to the optical chip 403 through a wiring layer 405 and bumps 406. However, the electrical chip is not limited to this, and other implementations of the electrical chip mounted on the optical chip in a flip-chip manner are possible, for example, please refer to fig. 9, which shows a schematic structural diagram of the interconnection package structure of the optoelectronic chip according to the fourth embodiment of the present invention. As shown in fig. 9, bumps 406 are grown on the electrical chip 404; flip-chip the electrical chip 404 onto the optical chip 403, the electrical chip 404 being electrically connected to the optical chip 403 by bumps 406, similarly, large bumps 411 are grown on the electrical chip 404; the electrical chip 404 is flip-chip mounted on the optical chip 403, and the electrical chip 404 is electrically connected to the package substrate 401 through bumps 411. In some embodiments, the bumps may be, for example, tin solder balls, tin lead solder balls, tin silver copper solder balls, or braze balls, etc.
According to the photoelectric chip interconnection packaging structure in the fourth embodiment of the invention, the optical chip and the electric chip are directly interconnected in a die-to-die mode through the die, a TVS (transient voltage suppressor) interposer is not needed, the advantages of low power consumption, low delay and high bandwidth efficiency are achieved, the process flow is simplified, the chip packaging integration level is improved, UPH (unified power head) is improved, the expenditure of materials, equipment, manpower and the like is reduced, the electric chip adopts a fan-out technology, and the electric chip is rearranged and leads out a circuit, so that the electric connection with a packaging substrate is achieved. In addition, compared with the second embodiment and its variation in which the interposer is additionally fabricated as an intermediate structure between the electrical chip and the package substrate, in the fourth embodiment of the present invention, the package substrate employs the concave package substrate and the metal circuit is fabricated at the convex edge of the concave package substrate, so that the electrical chip can be directly electrically connected to the package substrate through the metal circuit without the intermediate structure, thereby simplifying the structure and the packaging process, and improving the dimensional accuracy.
Referring to fig. 10, a schematic structural diagram of an interconnection package structure of an optoelectronic chip according to a fifth embodiment of the invention is shown.
As shown in fig. 10, the optoelectronic chip interconnection package structure includes:
The package substrate 501 is provided with external solder balls 502. In this embodiment, the package substrate 501 is a concave package substrate, which has a substrate body and a convex edge, and the package substrate 501 is provided with a metal circuit 509 therein.
The photoelectric combination is arranged on the packaging substrate 501. The optoelectric combination comprises an optical chip 503 and an electric chip 504 directly bonded in a die-to-die manner, wherein the electric chip 504 is flip-chip mounted on the optical chip 503, and the optical chip 503 is mounted on a concave substrate body of a package substrate 501. The electrical die 504 extends outward in a fan-out fashion to form a fan-out structure that is configured to be disposed at the raised edge of the package substrate 501 and electrically connected to the package substrate 501 through the metal traces 509.
In addition, a heat dissipation structure 512 penetrating through the thickness direction of the package substrate is disposed in the package substrate 501. In some embodiments, the heat dissipating structure is a heat dissipating metal post. The heat dissipation metal column can be made of one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold and silver. For example, the heat dissipation metal posts are copper posts.
In a fourth embodiment of the present invention, the electrical chip 504 is flip-chip mounted on the optical chip 503, wherein a wafer level package is used on the electrical chip 504 to re-route the wiring layer 505 and to grow bumps 506 on the wiring layer 505; the electrical chip 504 is flip-chip mounted on the optical chip 503, and the electrical chip 504 is electrically connected to the optical chip 503 through the wiring layer 505 and the bump 506. However, the electrical chip is not limited to this, and other implementations of the electrical chip mounted on the optical chip in a flip-chip manner are possible, for example, please refer to fig. 11, which shows a schematic structural diagram of the interconnection package structure of the optoelectronic chip in a variation of the fifth embodiment of the present invention. As shown in fig. 11, bumps 506 are grown on the electrical chip 504; flip-chip the electrical chip 504 onto the optical chip 503, the electrical chip 504 being electrically connected to the optical chip 503 by bumps 506, and similarly, large bumps 511 are grown on the electrical chip 504; the electrical chip 504 is flip-chip mounted on the optical chip 503, and the electrical chip 504 is electrically connected to the package substrate 501 through bumps 511.
In the photovoltaic chip interconnection packaging structure in the fifth embodiment of the invention, the photovoltaic chips and the electrical chips are directly interconnected in a die-to-die mode through the bare chips, a TVS (transient voltage suppressor) interposer is not needed, the photovoltaic chip interconnection packaging structure has the advantages of low power consumption, low delay and high bandwidth efficiency, the process flow is simplified, the chip packaging integration level is improved, the UPH (unified power head) is improved, the expenditure of materials, equipment, manpower and the like is reduced, the electrical chips are rearranged by adopting a fan-out technology, and the electrical chips are led out to realize the electrical connection with a packaging substrate. Compared with the second embodiment and its variation, in the fifth embodiment of the present invention, the interposer is additionally fabricated as an intermediate structure between the electrical chip and the package substrate, and in the fifth embodiment of the present invention, the package substrate employs the concave package substrate and the metal circuit is fabricated at the convex edge of the concave package substrate, so that the electrical chip can be directly electrically connected to the package substrate through the metal circuit without the intermediate structure, thereby simplifying the structure and the packaging process, and improving the dimensional accuracy. In addition, compared to the fourth embodiment and the variation thereof, in the fifth embodiment of the present invention, a heat dissipation structure (e.g., a heat dissipation metal post) penetrating through the thickness direction of the package substrate is disposed in the package substrate, which is more beneficial to heat dissipation.
Referring to fig. 12, a schematic structural diagram of an interconnection package structure of an optoelectronic chip according to a sixth embodiment of the invention is shown.
As shown in fig. 12, the optoelectronic chip interconnection package structure includes:
the package substrate 601, the package substrate 601 is provided with external solder balls 602. In this embodiment, the package substrate 601 is a concave package substrate, which has a substrate body and a convex edge, and the package substrate 601 is provided with a metal circuit 609 therein.
The photoelectric combination is disposed on the package substrate 601. The optoelectric complex comprises an optical chip 603 and an electrical chip 604 directly bonded in a die-to-die manner, wherein the optical chip 603 is flip-chip mounted on the electrical chip 604, and the electrical chip 604 is mounted on the package substrate 601. The optical chip 603 extends outward in a fan-out manner to form a fan-out structure, and the fan-out structure is electrically connected to the package substrate 601 through the metal wires 609.
In addition, a heat dissipation structure 612 penetrating through the thickness direction of the package substrate is disposed in the package substrate 601.
For the optical chip 603, one side may be a light inlet and the other side may be a light outlet, and light is emitted toward the package substrate 601, and for this purpose, the package substrate 601 is provided with a light window W (see fig. 13) corresponding to the light outlet of the optical chip 603.
In some embodiments, in the optoelectronic assembly, the electrical chip 604 may be attached to the package substrate 601 by dispensing or by soldering, soldering paste, or the like.
In the sixth embodiment of the present invention, the optical chip 603 is flip-chip mounted on the electrical chip 604, wherein the optical chip 603 is subjected to rewiring by wafer level packaging to manufacture a circuit layer 605 and to grow bumps 606 on the circuit layer 605; the optical chip 603 is flip-chip mounted on the electrical chip 604, and the optical chip 603 is electrically connected to the electrical chip 604 through the wiring layer 605 and the bump 606. However, the electrical chip is not limited to this, and other implementations of flip-chip mounting on the optical chip are possible, for example, please refer to fig. 14, which shows a schematic structural diagram of the optical-electrical chip interconnection package structure according to the sixth embodiment of the present invention. As shown in fig. 14, bumps 606 are grown on the optical chip 603; flip-chip the optical chip 603 onto the electrical chip 604, the optical chip 603 being electrically connected to the electrical chip 604 by bumps 606, and similarly, large bumps 611 are grown on the optical chip 603; the optical chip 603 is flip-chip mounted on the electrical chip 604, and the optical chip 603 is electrically connected to the package substrate 601 through bumps 611.
It should be noted that, in the sixth embodiment or the variation thereof, the package substrate 601 is a concave package substrate, and metal lines are fabricated on the convex edges of the concave package substrate, so that the flipped optical chip 603 can be electrically connected to the package substrate 601 through the metal lines, but not limited thereto, in other embodiments, in the optoelectronic assembly, the electrical chip is disposed on the package substrate, the optical chip is mounted on the electrical chip in a flip-chip manner, the optical chip extends outwards in a fan-out manner to form a fan-out structure, and the fan-out structure is electrically connected to the package substrate through an electrical connection structure. Wherein, in some embodiments, the electric connection structure can comprise an adapter plate, a conductive line and a bump. In some embodiments, the electrical connection structure includes conductive pillars or solder balls formed using bump technology. The specific structure of the electrical connection structure may be referred to the related description in the foregoing embodiments, and will not be repeated herein.
According to the photoelectric chip interconnection packaging structure in the sixth embodiment of the invention, the optical chips and the electric chips are directly interconnected in a die-to-die mode through the bare chips, a TVS (transient voltage suppressor) interposer is not needed, the advantages of low power consumption, low delay and high bandwidth efficiency are achieved, the process flow is simplified, the chip packaging integration level is improved, UPH (unified power head) is improved, the expenditure of materials, equipment, manpower and the like is reduced, the optical chips are rearranged by adopting a fan-out technology, the circuits are led out, and the electric connection with a packaging substrate is achieved.
The invention further provides a preparation method of the photoelectric chip interconnection packaging structure, which comprises the following steps: manufacturing an optoelectronic combination, and manufacturing an optical chip and an electrical chip which are mutually jointed in a die-to-die mode; providing a packaging substrate provided with external solder balls, and arranging the photoelectric combination body on the packaging substrate; the implementation manner of arranging the photoelectric combination on the packaging substrate comprises the following steps: attaching the optical chip in the photoelectric combination body to the packaging substrate, and electrically connecting the electric chip to the packaging substrate in a fan-out mode; or, attaching the electric chip in the photoelectric combination body to the packaging substrate, and electrically connecting the optical chip to the packaging substrate in a fan-out mode.
In certain embodiments, the step of fabricating the optoelectric complex to fabricate the interengaged optical and electrical chips on a die-to-die basis includes:
providing an electric chip, rewiring the surface of the electric chip and leading out a circuit in a fan-out mode;
attaching the electrical chip to the optical chip in a flip-chip manner;
the step of attaching the optical chip in the optoelectronic combination to the package substrate and electrically connecting the electrical chip to the package substrate in a fan-out manner includes:
Attaching the optical chip in the photoelectric combination to the packaging substrate;
and manufacturing an electric connection structure at the edge of the packaging substrate, and electrically connecting the circuit led out by the electric chip in a fan-out mode to the packaging substrate through the electric connection structure.
Wherein, in certain embodiments, for the optical chip, the steps further comprise: and mounting the optical chip on a supporting plate, and arranging the optical chip on the packaging substrate through the supporting plate.
In certain implementations, the step of fabricating the optoelectric complex to fabricate the interengaged optical and electrical chips on a die-to-die basis includes:
providing an electric chip, rewiring the surface of the electric chip and leading out a circuit in a fan-out mode;
attaching the electrical chip to the optical chip in a flip-chip manner;
the step of attaching the optical chip in the optoelectronic combination to the package substrate and electrically connecting the electrical chip to the package substrate in a fan-out manner includes:
the provided packaging substrate is a concave packaging substrate, metal circuits are manufactured in the packaging substrate, and the circuits led out by the electric chips in a fan-out mode are electrically connected to the packaging substrate through the metal circuits.
In certain embodiments, the step of fabricating the optoelectric complex to fabricate the interengaged optical and electrical chips on a die-to-die basis includes:
providing an electrical chip, rewiring the surface of the optical chip and leading out a circuit in a fan-out mode;
attaching the optical chip to the optical chip in a flip-chip manner;
the step of attaching the electrical chip in the optoelectronic combination to the package substrate and electrically connecting the optical chip to the package substrate in a fan-out manner includes:
the provided packaging substrate is a concave packaging substrate, metal circuits are manufactured in the packaging substrate, and the circuits led out by the optical chips in a fan-out mode are electrically connected with the packaging substrate through the conductive circuits; a light window corresponding to the light outlet of the optical chip is arranged on the packaging substrate; or, attaching the electric chip in the photoelectric combination body to the packaging substrate; and manufacturing an electric connection structure at the edge of the packaging substrate, and electrically connecting the circuits led out by the optical chip in a fan-out mode to the packaging substrate through the electric connection structure.
Wherein, the method can further comprise the steps of: and manufacturing a heat dissipation structure penetrating through the thickness direction of the packaging substrate in the packaging substrate.
The following describes a method for manufacturing the optoelectronic chip interconnection structure in the first embodiment in detail with reference to fig. 15 to 25.
An optical chip 103 is provided, and a bonding pad is provided on the surface of the optical chip 103. A structure as shown in fig. 15 is formed.
Providing an electric chip 104, rewiring the surface of the electric chip 104, and leading out a line in a fan-out mode to form a line layer 105; and bumps 106 are grown on the wiring layer 105. A structure as shown in fig. 16 is formed.
Providing a packaging substrate 101, and manufacturing external solder balls 102 on the packaging substrate 101; an electrical connection structure 110 is provided, a conductive line 109 penetrating through the thickness direction of the interposer is provided in the electrical connection structure 110, and a bump 111 is provided at the bottom of the conductive line 109 to form the electrical connection structure. A structure as shown in fig. 17 is formed.
The electrical connection structure 110 shown in fig. 17 is attached to the package substrate 101 through bumps 111 and reflowed. A structure as shown in fig. 18 is formed.
The gap between the electrical connection structure 110 and the package substrate 101 is underfilled and cured using a Plasma (Plasma) rinse. A structure as shown in fig. 19 is formed.
The optical chip 103 is attached to a support plate 107, which may be, for example, a ceramic substrate, by an adhesive or the like and cured. A structure as shown in fig. 20 is formed.
The electrical chip 104 is flip-chip mounted on the optical chip 103, so that the electrical chip 104 is electrically connected to the optical chip 103 to form an optoelectronic complex. A structure as shown in fig. 21 is formed.
The photo-chip 103 and the electrical chip 104 are underfilled and cured by Plasma (Plasma) cleaning. A structure as shown in fig. 22 is formed.
Dispensing or printing flux (flux), solder paste, on the package substrate 101. A structure as shown in fig. 23 is formed.
The optoelectric combination is mounted on the package substrate 101, specifically, the optical chip 103 in the optoelectric combination is mounted on the package substrate 101 through the supporting plate 107, and the electrical chip 104 in the optoelectric combination is electrically connected to the package substrate 101 through the electrical connection structure through the circuit layer 105. A structure as shown in fig. 24 is formed.
The electrical connection structure and the electrical chip 104 are underfilled and cured using a Plasma (Plasma) clean. A structure as shown in fig. 25 is formed.
Although the present invention has been described with respect to the preferred embodiments, it is not intended to be limited thereto, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present invention by using the methods and techniques disclosed herein without departing from the spirit and scope of the present invention.
Claims (15)
1. An optoelectronic chip interconnect package structure, comprising:
a package substrate provided with external solder balls; and
the photoelectric combination body is arranged on the packaging substrate; the photoelectric combination comprises an optical chip and an electric chip which are directly jointed in a die-to-die mode, wherein the optical chip is attached to the packaging substrate and the electric chip is electrically connected to the packaging substrate in a fan-out mode, or the electric chip is attached to the packaging substrate and the optical chip is electrically connected to the packaging substrate in a fan-out mode.
2. The optoelectronic chip interconnect assembly of claim 1, wherein in the optoelectronic assembly, the optoelectronic chip is mounted on a support plate, the support plate is disposed on the package substrate, the electrical chip is flip-chip mounted on the optoelectronic chip, the electrical chip extends outward in a fan-out manner to form a fan-out structure, and the fan-out structure is electrically connected to the package substrate through an electrical connection structure.
3. The optoelectronic chip interconnect package of claim 2, wherein said support plate comprises any one or any combination of a ceramic substrate, a glass substrate, and a silicon substrate.
4. The optoelectronic chip interconnect assembly of claim 1, wherein in the optoelectronic assembly, the optical chip is disposed on the package substrate, the electrical chip is flip-chip mounted on the optical chip, the electrical chip extends outward in a fan-out manner to form a fan-out structure, and the fan-out structure is electrically connected to the package substrate through an electrical connection structure.
5. The optoelectronic chip interconnection package structure according to claim 1, wherein in the optoelectronic combination, the optical chip is disposed on the package substrate, the electrical chip is flip-chip mounted on the optical chip, the electrical chip extends outwards in a fan-out manner to form a fan-out structure, the package substrate is a concave package substrate, metal lines are disposed on the protruding edges of the package substrate, and the fan-out structure of the electrical chip is electrically connected to the package substrate through the metal lines.
6. The optoelectronic chip interconnection package structure according to claim 1, wherein in the optoelectronic combination, the electrical chip is disposed on the package substrate, the optical chip is flip-chip mounted on the electrical chip, the optical chip extends outwards in a fan-out manner to form a fan-out structure, the fan-out structure is electrically connected to the package substrate through an electrical connection structure, and the package substrate is provided with an optical window corresponding to an optical outlet of the optical chip; or in the photoelectric combination, the electric chip is arranged on the packaging substrate, the optical chip is mounted on the electric chip in a flip-chip manner, the optical chip outwards extends in a fan-out manner to form a fan-out structure, the packaging substrate is a concave packaging substrate, a metal circuit is arranged at the protruding edge of the packaging substrate, the fan-out structure of the optical chip is electrically connected with the packaging substrate through the metal circuit, and the packaging substrate is provided with an optical window corresponding to an optical outlet of the optical chip.
7. The optoelectronic chip interconnection package according to claim 5 or 6, wherein the package substrate is provided therein with a heat dissipation structure penetrating through a thickness direction of the package substrate.
8. The optoelectronic chip interconnect package assembly of claim 2, 4, or 6, wherein the electrical connection structure includes an insulating layer and conductive traces extending through the insulating layer, or wherein the electrical connection structure includes conductive pillars or solder balls formed using bump technology.
9. The optoelectronic chip interconnect package of claim 1, wherein said package substrate comprises any one or any combination of an organic substrate, a ceramic substrate, a glass substrate, and a silicon substrate.
10. The preparation method of the photoelectric chip interconnection packaging structure is characterized by comprising the following steps:
manufacturing an optoelectronic combination, and manufacturing an optical chip and an electrical chip which are mutually jointed in a die-to-die mode;
providing a packaging substrate provided with external solder balls, and arranging the photoelectric combination body on the packaging substrate;
the implementation manner of arranging the photoelectric combination on the packaging substrate comprises the following steps: attaching the optical chip in the photoelectric combination body to the packaging substrate, and electrically connecting the electric chip to the packaging substrate in a fan-out mode; or, attaching the electric chip in the photoelectric combination body to the packaging substrate, and electrically connecting the optical chip to the packaging substrate in a fan-out mode.
11. The method of fabricating an optoelectronic chip interconnect package according to claim 10, wherein said fabricating an optoelectronic complex, die-to-die fabricating an inter-bonded optical chip and electrical chip comprises:
providing an electric chip, rewiring the surface of the electric chip and leading out a circuit in a fan-out mode;
attaching the electrical chip to the optical chip in a flip-chip manner;
the step of attaching the optical chip in the optoelectronic combination to the package substrate and electrically connecting the electrical chip to the package substrate in a fan-out manner includes:
attaching the optical chip in the photoelectric combination to the packaging substrate;
and manufacturing an electric connection structure at the edge of the packaging substrate, and electrically connecting the circuit led out by the electric chip in a fan-out mode to the packaging substrate through the electric connection structure.
12. The method for manufacturing an interconnection package structure of an optoelectronic chip according to claim 11, further comprising the steps of: and mounting the optical chip on a supporting plate, and arranging the optical chip on the packaging substrate through the supporting plate.
13. The method of fabricating an optoelectronic chip interconnect package according to claim 10, wherein said fabricating an optoelectronic complex, die-to-die fabricating an inter-bonded optical chip and electrical chip comprises:
Providing an electric chip, rewiring the surface of the electric chip and leading out a circuit in a fan-out mode;
attaching the electrical chip to the optical chip in a flip-chip manner;
the step of attaching the optical chip in the optoelectronic combination to the package substrate and electrically connecting the electrical chip to the package substrate in a fan-out manner includes:
the provided packaging substrate is a concave packaging substrate, metal circuits are manufactured on the convex edges of the packaging substrate, and the circuits led out of the electric chip in a fan-out mode are electrically connected to the packaging substrate through the metal circuits.
14. The method of fabricating an optoelectronic chip interconnect package according to claim 10, wherein said fabricating an optoelectronic complex, die-to-die fabricating an inter-bonded optical chip and electrical chip comprises:
providing an electrical chip, rewiring the surface of the optical chip and leading out a circuit in a fan-out mode;
attaching the optical chip to the optical chip in a flip-chip manner;
the step of attaching the electrical chip in the optoelectronic combination to the package substrate and electrically connecting the optical chip to the package substrate in a fan-out manner includes:
The provided packaging substrate is a concave packaging substrate, metal circuits are manufactured on the convex edges of the packaging substrate, and the circuits led out of the optical chip in a fan-out mode are electrically connected with the packaging substrate through the metal circuits; a light window corresponding to the light outlet of the optical chip is arranged on the packaging substrate; or, attaching the electric chip in the photoelectric combination body to the packaging substrate; and manufacturing an electric connection structure on the packaging substrate, and electrically connecting the circuits led out by the optical chip in a fan-out mode to the packaging substrate through the electric connection structure.
15. The method for manufacturing an interconnection package structure of an optoelectronic chip according to claim 13 or 14, further comprising the steps of: and manufacturing a heat dissipation structure penetrating through the thickness direction of the packaging substrate in the packaging substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311415631.5A CN117476599A (en) | 2023-10-27 | 2023-10-27 | Photoelectric chip interconnection packaging structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311415631.5A CN117476599A (en) | 2023-10-27 | 2023-10-27 | Photoelectric chip interconnection packaging structure and preparation method thereof |
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| Publication Number | Publication Date |
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| CN117476599A true CN117476599A (en) | 2024-01-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202311415631.5A Pending CN117476599A (en) | 2023-10-27 | 2023-10-27 | Photoelectric chip interconnection packaging structure and preparation method thereof |
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| Country | Link |
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| CN (1) | CN117476599A (en) |
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