CN117476472A - Photoelectric integrated semiconductor packaging structure and preparation method thereof - Google Patents
Photoelectric integrated semiconductor packaging structure and preparation method thereof Download PDFInfo
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- CN117476472A CN117476472A CN202311373189.4A CN202311373189A CN117476472A CN 117476472 A CN117476472 A CN 117476472A CN 202311373189 A CN202311373189 A CN 202311373189A CN 117476472 A CN117476472 A CN 117476472A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 24
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 102
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- GQYHUHYESMUTHG-UHFFFAOYSA-N lithium niobate Chemical compound [Li+].[O-][Nb](=O)=O GQYHUHYESMUTHG-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/122—Basic optical elements, e.g. light-guiding paths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Optics & Photonics (AREA)
- Optical Integrated Circuits (AREA)
Abstract
The invention provides a photoelectric integrated semiconductor packaging structure and a preparation method thereof, wherein by preparing a composite functional chip, one side of the composite functional chip is provided with an electric metal wiring layer for electric transmission by combining a metal column and a rewiring layer, and the other side of the composite functional chip is provided with an optical waveguide wiring layer for optical transmission by combining an optical chip, so that the combined packaging of the optical chip and the electric chip can be realized, the photoelectric integration is realized, the packaging size is reduced, the power consumption is reduced, the reliability is improved, and the composite functional chip is suitable for high-density integrated packaging, and good photoelectric signal transmission can be realized.
Description
Technical Field
The invention belongs to the technical field of semiconductor manufacturing, and relates to a photoelectric integrated semiconductor packaging structure and a preparation method thereof.
Background
With the continued development of big data, artificial intelligence, telemedicine, internet of things, electronic commerce, 5G communications, global data traffic has exploded, lower cost, more reliable, faster and higher density circuits are the goal of integrated circuit packaging pursuits.
In a semiconductor package structure, functional chips such as ASIC (Application Specific Integrated Circuit ) chips and HBM (High Bandwidth Memory, high bandwidth memory) chips are typically disposed on RDL (Re-distribution Layer, redistribution layer) and electrically connected and signal communicated with each other through the RDL, but the electrical connection and signal communication between the functional chips are performed through the RDL, which may cause distortion of transmission signals due to the length, distribution of transmission paths, and the like.
Because light has excellent performances such as small signal attenuation, low energy consumption, high bandwidth, compatibility with CMOS and the like, the industry generally considers that the light technology is introduced into the semiconductor manufacturing process, so that the chip size, the cost and the power consumption can be reduced, and the reliability can be improved. Therefore, the functional chips can be optically coupled through optical fibers in an end-face coupling (edge coupling) mode, but with the reduction of the chip spacing, the application mode of optical fiber coupling is limited.
Therefore, it is necessary to provide an optoelectronic integrated semiconductor package and a method for manufacturing the same.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an optoelectronic integrated semiconductor package and a method for manufacturing the same, which are used for solving the signal transmission problem between functional chips in the prior art.
To achieve the above and other related objects, the present invention provides a method for manufacturing an optoelectronic integrated semiconductor package, comprising the steps of:
providing a wafer-level electrical chip comprising a circuit region at the top and a base region at the bottom;
patterning the wafer level electrical chip to form a recess in the base region;
forming an optical waveguide wiring layer in the groove;
forming a first light-shielding protective layer covering the optical waveguide wiring layer on the surface of the substrate region;
forming a metal connecting piece on the surface of the circuit area, wherein the metal connecting piece is electrically connected with the circuit area;
cutting to form a composite functional chip, wherein in the composite functional chip, an adhesive layer is formed on the surface of the first shading protective layer;
providing a support substrate with a separation layer on the surface, forming a metal column on the separation layer, and bonding the composite function chip on the separation layer through the bonding layer;
forming an encapsulation layer which covers the metal column, the composite function chip and the separation layer and exposes the first end of the metal column and the metal connecting piece;
forming a rewiring layer on the packaging layer, wherein the rewiring layer is electrically connected with the first end of the metal column and the metal connecting piece;
removing the separation layer and the support substrate, and exposing the second ends of the metal posts and the adhesive layer;
patterning the adhesive layer and the first shading protection layer to form a waveguide light port exposing the optical waveguide wiring layer;
and providing an optical chip with a photosensitive area, bonding the optical chip on the packaging layer, electrically connecting the optical chip with the second end of the metal column, and arranging the photosensitive area corresponding to the waveguide optical port.
Optionally, between the step of forming the groove and the step of forming the optical waveguide wiring layer, a step of forming a second light shielding protection layer covering the bottom and the side walls of the groove is further included.
Alternatively, the method of forming the optical waveguide wiring layer includes a semiconductor exposure developing method, and the formed optical waveguide wiring layer includes an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer.
Optionally, the method for forming the first light-shielding protection layer includes a semiconductor exposure developing method, and the formed first light-shielding protection layer includes a metal first light-shielding protection layer or an organic-inorganic composite first light-shielding protection layer.
Optionally, the method for performing dicing to form the composite functional chip includes a mechanical dicing method or a laser dicing method.
Optionally, the method of patterning the adhesive layer and the first light shielding layer includes a laser etching method.
The invention also provides an optoelectronic integrated semiconductor packaging structure, which comprises:
rewiring layers;
the composite functional chip is positioned on the rewiring layer and comprises a circuit area positioned at the top and a substrate area positioned at the bottom, wherein a groove is formed in the substrate area, an optical waveguide wiring layer is arranged in the groove, a first shading protection layer and an adhesive layer which cover the optical waveguide wiring layer are arranged on the surface of the substrate area, waveguide light ports which expose the optical waveguide wiring layer are arranged in the first shading protection layer and the adhesive layer, a metal connecting piece which is electrically connected with the circuit area is arranged on the surface of the circuit area, and the metal connecting piece is electrically connected with the rewiring layer;
a metal pillar on the rewiring layer, the metal pillar having a first end electrically connected to the rewiring layer;
the packaging layer covers the metal column, the composite function chip and the rewiring layer, and exposes the second end of the metal column and the waveguide light port;
the optical chip is bonded on the packaging layer and is provided with a photosensitive area, the optical chip is electrically connected with the second end of the metal column, and the photosensitive area is correspondingly arranged with the waveguide light port.
Optionally, the device further comprises a second shading protection layer covering the bottom and the side wall of the groove.
Alternatively, the optical waveguide wiring layer includes an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer.
Optionally, the first light-shielding protective layer includes a metal first light-shielding protective layer or an organic-inorganic composite first light-shielding protective layer.
As described above, the photoelectric integrated semiconductor packaging structure and the preparation method thereof of the invention enable one side of the composite functional chip to be provided with the electric metal wiring layer for electric transmission by combining the metal column and the rewiring layer, and the other side to be provided with the optical waveguide wiring layer for optical transmission by combining the optical chip, thereby realizing the combined packaging of the optical chip and the electric chip, realizing photoelectric integration, reducing the packaging size, reducing the power consumption, improving the reliability, being suitable for high-density integrated packaging and realizing good photoelectric signal transmission.
Drawings
Fig. 1 is a schematic process flow diagram of an optoelectronic integrated semiconductor package according to an embodiment of the invention.
Fig. 2 is a schematic diagram of a wafer level chip according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram of the embodiment of the invention after forming the grooves.
Fig. 4a is a schematic diagram showing a structure after forming an optical waveguide wiring layer in an embodiment of the present invention.
Fig. 4b is a schematic view showing another structure after forming the optical waveguide wiring layer in the embodiment of the present invention.
Fig. 5 shows a schematic top view of fig. 4 a.
Fig. 6 is a schematic structural diagram of the first light-shielding protection layer according to an embodiment of the invention.
Fig. 7 is a schematic structural diagram of a composite functional chip formed by forming a first metal connection piece and cutting in an embodiment of the invention.
Fig. 8 is a schematic view showing the structure of a support substrate having a separation layer in the embodiment of the present invention.
Fig. 9 is a schematic structural diagram of a metal pillar and a bonded composite functional chip according to an embodiment of the invention.
Fig. 10 is a schematic structural diagram of an embodiment of the present invention after forming a package layer.
Fig. 11 is a schematic structural diagram of the re-wiring layer and the second metal connection member after forming in the embodiment of the invention.
Fig. 12 is a schematic view showing a structure after removing the separation layer and the supporting substrate in the embodiment of the invention.
Fig. 13 is a schematic diagram of a structure of a waveguide according to an embodiment of the invention after forming a light port.
Fig. 14 is a schematic diagram of a structure of a bonded optical chip according to an embodiment of the invention.
Description of element reference numerals
100-a composite functional chip; 101-wafer level electrical chips; 101 a-a circuit region; 101 b-a substrate region; 102-bonding pads; 103-grooves; 104-an optical waveguide wiring layer; 1051-a first light-shielding protective layer; 1052-a second light-shielding protective layer; 106-an adhesive layer; 107-a first metal connection; 108-a waveguide optical port; 200-supporting a substrate; 300-separating the layers; 400-metal columns; 500-packaging layers; 600-rewiring layer; 700-a second metal connector; 800-optical chip; 801-photosensitive area.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures, including embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact, and further, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.
As shown in fig. 1, the present embodiment provides a method for manufacturing an optoelectronic integrated semiconductor package structure, by manufacturing a composite functional chip, one side of the composite functional chip has an electrical metal wiring layer to combine with a metal pillar and a rewiring layer for electrical transmission, and the other side has an optical waveguide wiring layer to combine with an optical chip for optical transmission, so that the optical chip and the electrical chip can be packaged in a combined manner, optoelectronic integration is realized, the package size is reduced, the power consumption is reduced, the reliability is improved, and the method is suitable for high-density integrated package, and good optoelectronic signal transmission can be realized.
The following is a further description of the preparation of the optoelectronic integrated semiconductor package structure with reference to fig. 2 to 14, and specifically includes:
first, referring to fig. 1 and 2, step S1 is performed to provide a wafer level chip 101, where the wafer level chip 101 includes a circuit area 101a at the top and a base area 101b at the bottom.
Specifically, the size of the wafer level chip 101 may include, for example, 4 inches, 6 inches, 8 inches, 12 inches, etc., and the size of the wafer level chip 101 is not limited thereto and may be selected as needed.
The specific type of the wafer level electrical chip 101 may be selected according to the need, the circuit area 101a is disposed on the top of the wafer level electrical chip 101 for electrical signal transmission, and the substrate area 101b of the wafer level electrical chip 101 may provide space for the subsequent preparation of the optical waveguide wiring layer 104.
Only the pads 102 for electrical extraction in the circuit area 101a are illustrated in fig. 2, and the arrangement of the metal wiring layer in the circuit area 101a is not illustrated.
Next, referring to fig. 1 and 3, step S2 is performed to pattern the wafer level chip 101, and a recess 103 is formed in the base region 101b.
Specifically, the bottom non-circuit area of the wafer level chip 101 may be patterned by using a semiconductor photolithography technique to form a reserved channel for the preparation of the optical waveguide wiring layer 104, that is, the groove 103, and the shape of the groove 103 may be selected according to needs, which is not limited herein excessively.
Next, referring to fig. 1 and 4a, step S3 is performed to form an optical waveguide wiring layer 104 in the recess 103.
As an example, the method of forming the optical waveguide wiring layer 104 may include a semiconductor exposure developing method, the formed optical waveguide wiring layer 104 may include an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, a lithium borate optical waveguide wiring layer, or the like, and a material of the organic polymer optical waveguide wiring layer may be polymethyl methacrylate (PMMA), polystyrene (PS), polycarbonate (PC) epoxy, fluorine-containing polyimide, or the like, and the material, distribution, and preparation of the optical waveguide wiring layer 104 are not excessively limited herein.
In this case, fig. 5 illustrates a top view of fig. 4a, that is, fig. 4a may illustrate a schematic cross-sectional structure along a broken line in fig. 5, and the distribution of the optical waveguide wiring layer 104 is not excessively limited here.
Next, referring to fig. 1 and 6, step S4 is performed to form a first light shielding layer 1051 covering the optical waveguide layer 104 on the surface of the substrate region 101b.
As an example, a method of forming the first light-shielding protective layer 1051 may include a semiconductor exposure developing method, and the formed first light-shielding protective layer 1051 may include a metal first light-shielding protective layer, an organic-inorganic composite first light-shielding protective layer, or the like to cover the optical waveguide wiring layer 104 through the first light-shielding protective layer 1051 to reduce light loss.
In this embodiment, the first light-shielding layer 1051 is made of a metal material, such as copper, gold, aluminum, silver, platinum, titanium, etc., however, the first light-shielding layer 1051 may be made of an organic-inorganic composite material as required, and the specific choice of the first light-shielding layer 1051 is not limited herein.
Further, as shown in fig. 4b, after the recess 103 is formed and before the optical waveguide wiring layer 104 is formed, a second light shielding layer 1052 covering the bottom and the side walls of the recess 103 may be further formed, so that the optical waveguide wiring layer 104 is further protected by the second light shielding layer 1052, thereby avoiding the loss of light in the substrate region 101b and improving the transmission efficiency.
The method for forming the second light-shielding layer 1052 may include a semiconductor exposure developing method, and the material of the second light-shielding layer 1052 may include a metal material or an organic-inorganic composite material, and the material and preparation of the second light-shielding layer 1052 may be the same as those of the first light-shielding layer 1051, which is not limited herein.
Next, referring to fig. 1 and 7, step S5 is performed to form a metal connection on the surface of the circuit area 101a, and the metal connection is electrically connected to the circuit area 101 a.
Specifically, referring to fig. 7, in the present embodiment, the metal connection member adopts a metal pillar, i.e. the first metal connection member 107 in fig. 7, and the first metal connection member 107 is electrically connected to the bonding pad 102 so as to facilitate subsequent electrical extraction, and the type of the metal connection member is not limited thereto, but may be a metal bump, or a composite structure of a metal pillar and a metal bump, etc., which is not excessively limited herein, and may be selected according to requirements.
Next, referring to fig. 1 and 7, step S6 is performed to cut the composite functional chip 100, and in the composite functional chip 100, the adhesive layer 106 is formed on the surface of the first light shielding protection layer 1051.
As an example, the method of performing dicing to form the composite functional chip 100 may include a mechanical dicing method or a laser dicing method, and may be specifically selected as needed.
Specifically, when the dicing process is performed, a dual-film support structure (not shown) may be provided, in which the adhesive layer 106 is located on the surface of the dual-film support structure, and when the dicing process is performed, the adhesive layer 106 is also diced and separated, so that the surface of the diced and separated composite functional chip 100 has the adhesive layer 106, so that a subsequent bonding process is performed through the adhesive layer 106. The specific material of the double-membrane support structure is not limited herein, and may be selected as desired.
Next, referring to fig. 1, 8 and 9, step S7 is performed to provide the support substrate 200 having the separation layer 300 on the surface thereof, form the metal pillars 400 on the separation layer 300, and bond the complex function chip 100 to the separation layer 300 through the adhesive layer 106.
Specifically, the separation layer 300 may include, but is not limited to, an adhesive tape and a polymer layer, for example, the separation layer 300 may be a photothermal conversion layer, so that the separation layer 300 may be heated, for example, by laser, so as to remove the support substrate 200, thereby improving the operation convenience.
The sequence of forming the metal posts 400 and bonding the multifunctional chip 100 is not limited herein, and may be selected according to the need. The metal pillar 400 may be, for example, a copper metal pillar, but is not limited thereto, and a method for manufacturing the metal pillar 400 is not limited thereto.
Next, referring to fig. 1 and 10, step S8 is performed to form an encapsulation layer 500, where the encapsulation layer 500 covers the metal pillars 400, the composite functional chip 100 and the separation layer 300, and exposes the first ends of the metal pillars 400 and the metal connectors, i.e. the first metal connectors 107.
Specifically, the material of the encapsulation layer 500 may be epoxy resin, and the method for forming the encapsulation layer 500 may include molding, vacuum lamination, spin coating, etc., and the material and forming method of the encapsulation layer 500 are not limited herein.
After the encapsulation layer 500 is formed, the first end of the metal pillar 400 and the first metal connection 107 may be exposed by polishing, and the thickness of the encapsulation layer 500 may be thinned by a polishing process, so as to obtain a flat surface, where the polishing process may include, for example, chemical mechanical polishing (Chemical Mechanical Polishing, CMP), physical polishing, or a combination of physical polishing and CMP, which is not limited herein.
Next, referring to fig. 1 and 11, step S9 is performed to form a rewiring layer 600 on the encapsulation layer 500, where the rewiring layer 600 is electrically connected to the first end of the metal pillar 400 and the first metal connection 107.
Specifically, the re-wiring layer 600 includes an insulating dielectric layer and a metal wiring layer, through which electrical connection can be made, and the specific material, structure, preparation, etc. of the re-wiring layer 600 are not limited herein, and may be selected as needed.
Further, a second metal connector 700 electrically connected to the re-wiring layer 600 may be formed on the surface of the re-wiring layer 600, so as to facilitate subsequent electrical extraction, and the second metal connector 700 may include a metal bump, etc., and the specific type is not limited herein.
Next, referring to fig. 1 and 12, step S10 is performed to remove the separation layer 300 and the support substrate 200, and expose the second ends of the metal pillars 400 and the adhesive layer 106.
Specifically, when the light-heat conversion layer is used as the separation layer 300, a laser or the like may be used to heat the separation layer 300 to remove the support substrate 200, exposing the second end of the metal pillar 400 and the adhesive layer 106.
Next, referring to fig. 1 and 13, step S11 is performed to pattern the adhesive layer 106 and the first light shielding layer 1051, so as to form a waveguide light port 108 exposing the optical waveguide wiring layer 104.
As an example, the method of patterning the adhesive layer 106 and the first light shielding layer 1051 may include a laser etching method.
Specifically, the adhesive layer 106 and the first light shielding layer 1051 may be patterned by a laser etching method to form the waveguide optical port 108 exposing the optical waveguide wiring layer 104, so as to facilitate light transmission along the waveguide optical port 108. No undue limitations are made herein with respect to the morphology and size of the waveguide optical port 108.
Next, referring to fig. 1 and 14, step S12 is performed to provide an optical chip 800 with a photosensitive area 801, and the optical chip 800 is bonded on the encapsulation layer 500, the optical chip 800 is electrically connected to the second end of the metal pillar 400, and the photosensitive area 801 is disposed corresponding to the waveguide optical port 108 for optical transmission, as shown by the dashed line with an arrow in fig. 14.
Further, it is understood that steps S7 to S12 may be wafer-level preparation to increase productivity, and thus a dicing process step may be further included after step S12 to form the monomer structure shown in fig. 14, and steps S7 to S12 may be direct preparation of the monomer structure, as required, which is not limited herein.
Referring to fig. 2 to 14, the present embodiment further provides an optoelectronic integrated semiconductor package structure, which may be directly manufactured by the above manufacturing process, so that the materials, manufacturing processes, etc. of the semiconductor package structure may be referred to above, and of course, the optoelectronic integrated semiconductor package structure may also be manufactured by other manufacturing processes according to needs.
Specifically, in this embodiment, the optoelectronic integrated semiconductor package structure includes: rewiring layer 600, composite function chip 100, metal posts 400, encapsulation layer 500, and optical chip 800.
The multifunctional chip 100 is located on the rewiring layer 600, and includes a circuit area 101a located at the top and a base area 101b located at the bottom, wherein the base area 101b has a groove 103, the groove 103 has an optical waveguide wiring layer 104, the surface of the base area 101b has a first light shielding layer 1051 and an adhesive layer 106 covering the optical waveguide wiring layer 104, the first light shielding layer 1051 and the adhesive layer 106 have a waveguide light port 108 exposing the optical waveguide wiring layer 104, the surface of the circuit area 101a has a metal connector 107 electrically connected with the circuit area 101a, i.e. a first metal connector 107, such as a metal pillar, a metal bump, or a composite structure of a metal pillar and a metal bump, and the metal connector is electrically connected with the rewiring layer 600; the metal pillar 400 is located on the rewiring layer 600, and a first end of the metal pillar 400 is electrically connected with the rewiring layer 600; the packaging layer 500 covers the metal pillar 400, the multifunctional chip 100 and the rewiring layer 600, and exposes the second end of the metal pillar 400 and the waveguide optical port 108; the optical chip 800 is bonded on the encapsulation layer 500, the optical chip 800 has a photosensitive area 801, and the optical chip 800 is electrically connected to the second end of the metal pillar 400, and the photosensitive area 801 is disposed corresponding to the waveguide optical port 108 for optical transmission.
As an example, the optical waveguide wiring layer 104 may include an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer.
As an example, the first light shielding layer 1051 may include a metal first light shielding layer or an organic-inorganic composite first light shielding layer to cover the optical waveguide wiring layer 104 through the first light shielding layer 1051 to reduce light loss so that light is inputted and outputted only along the waveguide light port 108.
As an example, a second light shielding layer 1052 covering the bottom and the side walls of the recess 103 may be further included to further protect the optical waveguide wiring layer 104 by the second light shielding layer 1052, avoiding the loss of light in the substrate region 101b, and improving the transmission efficiency.
The first light shielding layer 1051 and the second light shielding layer 1052 may be made of the same material or different materials, which is not limited herein.
Further, there may be a metal connector, i.e., a second metal connector 700, electrically connected to the rewiring layer 600 on the surface of the rewiring layer 600, where the second metal connector 700 may be, for example, a metal bump, etc., which is not limited herein.
In summary, according to the optoelectronic integrated semiconductor package structure and the preparation method thereof, through preparing the composite functional chip, one side of the composite functional chip is provided with the electrical metal wiring layer to combine with the metal column and the rewiring layer for electrical transmission, and the other side is provided with the optical waveguide wiring layer to combine with the optical chip for optical transmission, so that the combined package of the optical chip and the electrical chip can be realized, the optoelectronic integration is realized, the package size is reduced, the power consumption is reduced, the reliability is improved, and the optoelectronic integrated semiconductor package structure is suitable for high-density integrated package, and good optoelectronic signal transmission can be realized.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. The preparation method of the photoelectric integrated semiconductor packaging structure is characterized by comprising the following steps of:
providing a wafer-level electrical chip comprising a circuit region at the top and a base region at the bottom;
patterning the wafer level electrical chip to form a recess in the base region;
forming an optical waveguide wiring layer in the groove;
forming a first light-shielding protective layer covering the optical waveguide wiring layer on the surface of the substrate region;
forming a metal connecting piece on the surface of the circuit area, wherein the metal connecting piece is electrically connected with the circuit area;
cutting to form a composite functional chip, wherein in the composite functional chip, an adhesive layer is formed on the surface of the first shading protective layer;
providing a support substrate with a separation layer on the surface, forming a metal column on the separation layer, and bonding the composite function chip on the separation layer through the bonding layer;
forming an encapsulation layer which covers the metal column, the composite function chip and the separation layer and exposes the first end of the metal column and the metal connecting piece;
forming a rewiring layer on the packaging layer, wherein the rewiring layer is electrically connected with the first end of the metal column and the metal connecting piece;
removing the separation layer and the support substrate, and exposing the second ends of the metal posts and the adhesive layer;
patterning the adhesive layer and the first shading protection layer to form a waveguide light port exposing the optical waveguide wiring layer;
and providing an optical chip with a photosensitive area, bonding the optical chip on the packaging layer, electrically connecting the optical chip with the second end of the metal column, and arranging the photosensitive area corresponding to the waveguide optical port.
2. The method for manufacturing an optoelectronic integrated semiconductor package according to claim 1, wherein: the method further includes a step of forming a second light shielding layer covering the bottom and the side walls of the groove between the step of forming the groove and the step of forming the optical waveguide wiring layer.
3. The method for manufacturing an optoelectronic integrated semiconductor package according to claim 1, wherein: the method for forming the optical waveguide wiring layer comprises a semiconductor exposure developing method, and the formed optical waveguide wiring layer comprises an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer or a lithium borate optical waveguide wiring layer.
4. The method for manufacturing an optoelectronic integrated semiconductor package according to claim 1, wherein: the method for forming the first light-shielding protection layer comprises a semiconductor exposure development method, and the formed first light-shielding protection layer comprises a metal first light-shielding protection layer or an organic-inorganic composite first light-shielding protection layer.
5. The method for manufacturing an optoelectronic integrated semiconductor package according to claim 1, wherein: the method for cutting to form the composite functional chip comprises a mechanical cutting method or a laser cutting method.
6. The method for manufacturing an optoelectronic integrated semiconductor package according to claim 1, wherein: the method for patterning the adhesive layer and the first shading protection layer comprises a laser etching method.
7. An optoelectronic integrated semiconductor package, the optoelectronic integrated semiconductor package comprising:
rewiring layers;
the composite functional chip is positioned on the rewiring layer and comprises a circuit area positioned at the top and a substrate area positioned at the bottom, wherein a groove is formed in the substrate area, an optical waveguide wiring layer is arranged in the groove, a first shading protection layer and an adhesive layer which cover the optical waveguide wiring layer are arranged on the surface of the substrate area, waveguide light ports which expose the optical waveguide wiring layer are arranged in the first shading protection layer and the adhesive layer, a metal connecting piece which is electrically connected with the circuit area is arranged on the surface of the circuit area, and the metal connecting piece is electrically connected with the rewiring layer;
a metal pillar on the rewiring layer, the metal pillar having a first end electrically connected to the rewiring layer;
the packaging layer covers the metal column, the composite function chip and the rewiring layer, and exposes the second end of the metal column and the waveguide light port;
the optical chip is bonded on the packaging layer and is provided with a photosensitive area, the optical chip is electrically connected with the second end of the metal column, and the photosensitive area is correspondingly arranged with the waveguide light port.
8. The optoelectronic integrated semiconductor package as set forth in claim 7, wherein: the second shading protection layer is used for covering the bottom and the side wall of the groove.
9. The optoelectronic integrated semiconductor package as set forth in claim 7, wherein: the optical waveguide wiring layer includes an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer.
10. The optoelectronic integrated semiconductor package as set forth in claim 7, wherein: the first light-shielding protective layer comprises a metal first light-shielding protective layer or an organic-inorganic composite first light-shielding protective layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311373189.4A CN117476472A (en) | 2023-10-20 | 2023-10-20 | Photoelectric integrated semiconductor packaging structure and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311373189.4A CN117476472A (en) | 2023-10-20 | 2023-10-20 | Photoelectric integrated semiconductor packaging structure and preparation method thereof |
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