CN117475858A - Pixel circuit and display panel - Google Patents

Pixel circuit and display panel Download PDF

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Publication number
CN117475858A
CN117475858A CN202310099158.8A CN202310099158A CN117475858A CN 117475858 A CN117475858 A CN 117475858A CN 202310099158 A CN202310099158 A CN 202310099158A CN 117475858 A CN117475858 A CN 117475858A
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CN
China
Prior art keywords
light
signal
switching tube
emitting device
light emitting
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Pending
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CN202310099158.8A
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Chinese (zh)
Inventor
宋会会
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to CN202310099158.8A priority Critical patent/CN117475858A/en
Publication of CN117475858A publication Critical patent/CN117475858A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The application discloses a pixel circuit and a display panel. The pixel circuit includes: the data writing module is used for writing data signals in a data writing stage; outputting the data signal in a light emitting stage; the first light-emitting module comprises a first light-emitting device and is used for controlling the first light-emitting device to emit light according to the data signal when the data signal reaches a preset threshold value; the second light-emitting module comprises a second light-emitting device and is used for controlling the second light-emitting device to emit light according to the data signal when the data signal does not reach the preset threshold value; the second light emitting device has a light emitting efficiency greater than that of the first light emitting device. The method and the device can improve the brightness uniformity during low gray scale display and reduce the power consumption during high gray scale display.

Description

Pixel circuit and display panel
Technical Field
The application relates to the technical field of display, in particular to a pixel circuit and a display panel.
Background
Currently, LTPO (Low Temperature Poly-Oxide ) display panels improve the lifetime of light emitting devices (e.g., OLED devices) in order to reduce power consumption, and increase the luminous efficiency of EL (light emitting layer) materials. However, the higher the luminous efficiency of the EL material, the smaller the operating current of the sub-pixel, which tends to cause problems such as uneven display luminance in low-gray-scale display.
Disclosure of Invention
The embodiment of the application provides a pixel circuit and a display panel, which can improve the brightness uniformity during low gray scale display and reduce the power consumption during high gray scale display.
The embodiment of the application provides a pixel circuit, which comprises:
the data writing module is used for writing data signals in a data writing stage; outputting the data signal in a light emitting stage;
the first light-emitting module comprises a first light-emitting device and is used for controlling the first light-emitting device to emit light according to the data signal when the data signal reaches a preset threshold value;
the second light-emitting module comprises a second light-emitting device and is used for controlling the second light-emitting device to emit light according to the data signal when the data signal does not reach the preset threshold value; the second light emitting device has a light emitting efficiency greater than that of the first light emitting device.
Optionally, the first light emitting module further includes a first switching tube, and the first light emitting module is further configured to input a first light emitting signal, and when the data signal reaches the preset threshold, turn on the first switching tube according to the first light emitting signal, so as to control the first light emitting device to emit light according to the data signal;
the second light-emitting module further comprises a second switch tube, and the second light-emitting module is further used for inputting a second light-emitting signal, and conducting the second switch tube according to the second light-emitting signal when the data signal does not reach the preset threshold value, so that the second light-emitting device is controlled to emit light according to the data signal.
Optionally, a control end of the first switching tube is connected to the first light-emitting signal, an input end of the first switching tube is connected to the data writing module, an output end of the first switching tube is connected to an anode of the first light-emitting device, and a cathode of the first light-emitting device is connected to a low-voltage signal;
the control end of the second switching tube is connected with the second light-emitting signal, the input end of the second switching tube is connected with the data writing module, the output end of the second switching tube is connected with the anode of the second light-emitting device, and the cathode of the second light-emitting device is connected with the low-voltage signal.
Optionally, the pixel circuit further includes:
the first reset module is used for resetting the anode of the first light-emitting device in a reset stage;
and the second reset module is used for resetting the anode of the second light-emitting device in a reset stage.
Optionally, the first reset module includes a third switching tube, and is further configured to input a reset signal and a first scanning signal, and in a reset stage, turn on the third switching tube according to the first scanning signal, and reset an anode of the first light emitting device according to the reset signal;
the second reset module comprises a fourth switch tube, and is further used for inputting the reset signal and the first scanning signal, conducting the fourth switch tube according to the first scanning signal in a reset stage, and resetting the anode of the second light-emitting device according to the reset signal.
Optionally, a control end of the third switching tube is connected to the first scanning signal, an input end of the third switching tube is connected to the reset signal, and an output end of the third switching tube is connected to an anode of the first light emitting device;
the control end of the fourth switching tube is connected with the first scanning signal, the input end of the fourth switching tube is connected with the reset signal, and the output end of the fourth switching tube is connected with the anode of the second light-emitting device.
Optionally, the data writing module includes a fifth switch tube, a sixth switch tube and a seventh switch tube, and is further configured to input a third light emitting signal and a second scanning signal, in a data writing stage, according to the third light emitting signal and the second scanning signal, turn on the fifth switch tube and the seventh switch tube, and turn off the sixth switch tube, so as to write the data signal, in a light emitting stage, according to the third light emitting signal and the second scanning signal, turn off the fifth switch tube, and turn on the sixth switch tube and the seventh switch tube, so as to output the data signal.
Optionally, when the data signal reaches the preset threshold, the first light-emitting signal and the third light-emitting signal are consistent in waveform; and when the data signal does not reach the preset threshold value, the second light-emitting signal is consistent with the waveform of the third light-emitting signal.
Optionally, the pixel circuit further includes:
and the initialization module is used for initializing the control end of the fifth switching tube in the initialization stage.
Correspondingly, the embodiment of the application also provides a display panel which comprises the pixel circuit.
The beneficial effects of this application are: through setting up first light emitting module and second light emitting module to when data signal reaches preset threshold value (gets into low gray scale display), the first light emitting device that luminous efficacy is less among the control first light emitting module shines, when data signal does not reach preset threshold value (gets into high gray scale display), the second light emitting device that luminous efficacy is great among the control second light emitting module shines, satisfies high low gray scale display's demand to luminous efficacy, improves the luminance homogeneity when low gray scale display, and reduces the consumption when high gray scale display.
Drawings
Technical solutions and other advantageous effects of the present application will be made apparent from the following detailed description of specific embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present application;
FIG. 2 is a signal timing diagram of a pixel circuit according to an embodiment of the present disclosure;
FIG. 3 is a signal timing diagram of a pixel circuit according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present application.
Detailed Description
Specific structural and functional details disclosed herein are merely representative and are for purposes of describing example embodiments of the present application. This application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientations or positional relationships illustrated in the drawings, merely to facilitate description of the present application and simplify the description, and do not indicate or imply that the devices or elements being referred to must have a particular orientation, be configured and operated in a particular orientation, and are therefore not to be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more. In addition, the term "include" and any variations thereof are intended to cover a non-exclusive inclusion.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The present application is further described below with reference to the drawings and examples.
Referring to fig. 1, a schematic structure of a pixel circuit according to an embodiment of the present application is shown. The pixel circuit can be applied to a display panel, and the display panel can be an LTPO display panel.
As shown in fig. 1, the pixel circuit provided in the embodiment of the invention includes a data writing module 1, a first light emitting module 2 and a second light emitting module 3, where the data writing module 1 is connected to the first light emitting module 2 and the second light emitting module 3 respectively.
The Data writing module 1 is used for writing a Data signal Data in a Data writing stage; in the light emitting stage, the Data signal Data is output. In the Data writing stage, the Data signal Data can be input to the Data writing module 1 through a source driving chip in the display panel, so that the Data signal Data is written into the Data writing module 1; in the light emitting stage, the Data writing module 1 outputs a Data signal Data to the first light emitting module 2 and the second light emitting module 3.
The first light emitting module 2 includes a first light emitting device D1, and the first light emitting module 2 is configured to control the first light emitting device D1 to emit light according to the Data signal Data when the Data signal Data reaches a preset threshold.
The second light emitting module 3 includes a second light emitting device D2, and the second light emitting module 3 is configured to control the second light emitting device D2 to emit light according to the Data signal Data when the Data signal Data does not reach a preset threshold.
Wherein, the luminous efficiency of the second light emitting device D2 is greater than the luminous efficiency of the first light emitting device D1. The first light emitting module 2 and the second light emitting module 3 do not operate simultaneously, i.e. the second light emitting module 3 does not operate when the first light emitting module 2 operates, and the first light emitting module 2 does not operate when the second light emitting module 3 operates.
The Data signal Data is a voltage signal, and the preset threshold is a preset voltage threshold. In the light emitting stage, if the Data signal Data reaches a preset threshold (i.e., the voltage of the Data signal Data reaches the preset voltage threshold), the display panel enters into low gray scale display, and the first light emitting device D1 is operated, the first light emitting device D1 emits light, the second light emitting module 3 is not operated, and the second light emitting device D2 does not emit light because the light emitting efficiency of the first light emitting device D1 is smaller. In this embodiment, the first light emitting device D1 with smaller light emitting efficiency is controlled to emit light during low gray scale display, so that the brightness uniformity during low gray scale display can be improved, the problems of display smear and the like can be improved, the taste of low gray scale display can be further improved, VGMP (maximum value of data signal during low gray scale display) can be reduced, and the power consumption can be reduced.
In the light emitting stage, if the Data signal Data does not reach the preset threshold (i.e., the voltage of the Data signal Data does not reach the preset voltage threshold), the display panel enters the high gray scale display, and the second light emitting device D2 is operated because the light emitting efficiency of the second light emitting device D2 is smaller, the second light emitting device D2 emits light, the first light emitting module 2 does not operate, and the first light emitting device D1 does not emit light. The embodiment controls the second light emitting device D2 having a larger luminous efficiency to emit light at the time of high gray scale display, and can reduce power consumption and improve the lifetime of the second light emitting device D2.
Specifically, the first light emitting module 2 further includes a first switching tube T6, and the first light emitting module 2 is further configured to input a first light emitting signal EM2, and when the Data signal Data reaches the preset threshold, turn on the first switching tube T6 according to the first light emitting signal EM2, so as to control the first light emitting device D1 to emit light according to the Data signal Data.
The first switching transistor T6 is connected between the data writing module 1 and the first light emitting device D1. When the first switching tube T6 is turned on, the Data signal Data may drive the first light emitting device D1 to emit light; when the first switching transistor T6 is turned off, the Data signal Data cannot drive the first light emitting device D1 to emit light. The first light-emitting signal EM2 is a signal with adjustable voltage, and in the light-emitting stage, if the Data signal Data reaches the preset threshold value, the voltage of the first light-emitting signal EM2 is adjusted to enable the first switch tube T6 to be conducted, and the first light-emitting device D1 emits light; if the Data signal Data does not reach the preset threshold, the voltage of the first light emitting signal EM2 is adjusted to turn off the first switching tube T6, and the first light emitting device D1 does not emit light.
The control end of the first switching tube T6 is connected to the first light-emitting signal EM2, the input end of the first switching tube T6 is connected to the data writing module 1, the output end of the first switching tube T6 is connected to the anode of the first light-emitting device D1, and the cathode of the first light-emitting device D1 is connected to the low-voltage signal VSS. The low voltage signal VSS may be a dc voltage.
The first switching transistor T6 may be a transistor (P-type transistor or N-type transistor), the control terminal of the first switching transistor T6 may be a gate of the transistor, the input terminal of the first switching transistor T6 may be a source (or drain) of the transistor, and the output terminal of the first switching transistor T6 may be a drain (or source) of the transistor. As shown in fig. 1, the first switch transistor T6 is a P-type transistor, the input end of the first switch transistor T6 may be a source of the transistor, and the output end of the first switch transistor T6 may be a drain of the transistor. In the light emitting stage, if the Data signal Data reaches the preset threshold, the first light emitting signal EM2 is at a low voltage; if the Data signal Data does not reach the preset threshold, the first light emitting signal EM2 is at a high voltage.
The second light emitting module 3 further includes a second switching tube T8, where the second light emitting module 3 is further configured to input a second light emitting signal EM3, and when the Data signal Data does not reach the preset threshold, turn on the second switching tube T8 according to the second light emitting signal EM3, so as to control the second light emitting device D2 to emit light according to the Data signal Data.
The second switching transistor T8 is connected between the data writing module 1 and the second light emitting device D2. When the second switching tube T8 is turned on, the Data signal Data may drive the second light emitting device D2 to emit light; when the second switching transistor T8 is turned off, the Data signal Data cannot drive the second light emitting device D2 to emit light. The second light-emitting signal EM3 is a signal with adjustable voltage, and in the light-emitting stage, if the Data signal Data does not reach the preset threshold value, the voltage of the second light-emitting signal EM3 is adjusted to enable the second switch tube T8 to be conducted, and the second light-emitting device D2 emits light; if the Data signal Data reaches the preset threshold, the voltage of the second light emitting signal EM3 is adjusted to turn off the second switching tube T8, and the second light emitting device D2 does not emit light.
The control end of the second switching tube T8 is connected to the second light-emitting signal EM3, the input end of the second switching tube T8 is connected to the data writing module 1, the output end of the second switching tube T8 is connected to the anode of the second light-emitting device D2, and the cathode of the second light-emitting device D2 is connected to the low-voltage signal VSS. The low voltage signal VSS may be a dc voltage.
The second switching transistor T8 may be a transistor (P-type transistor or N-type transistor), the control terminal of the second switching transistor T8 may be a gate of the transistor, the input terminal of the second switching transistor T8 may be a source (or drain) of the transistor, and the output terminal of the second switching transistor T8 may be a drain (or source) of the transistor. As shown in fig. 1, the second switching transistor T8 is a P-type transistor, the input end of the second switching transistor T8 may be a source of the transistor, and the output end of the second switching transistor T8 may be a drain of the transistor. In the light emitting stage, if the Data signal Data does not reach the preset threshold, the second light emitting signal EM3 is at a low voltage; if the Data signal Data reaches the preset threshold, the second light emitting signal EM3 is at a high voltage.
As shown in fig. 1, the pixel circuit may further comprise a first reset module 4 and a second reset module 5. The first reset module 4 is connected with the first light emitting module 2, and the second reset module 5 is connected with the second light emitting module 3.
The first reset module 4 is configured to reset the anode of the first light emitting device D1 during a reset phase. Specifically, the first reset module 4 includes a third switching tube T7, and the first reset module 4 is further configured to input a reset signal vi_ano and a first SCAN signal SCAN1, and in a reset stage, turn on the third switching tube T7 according to the first SCAN signal SCAN1, and reset the anode of the first light emitting device D1 according to the reset signal vi_ano.
The control end of the third switching tube T7 is connected to the first SCAN signal SCAN1, the input end of the third switching tube T7 is connected to the reset signal vi_ano, and the output end of the third switching tube T7 is connected to the anode of the first light emitting device D1.
The third switching transistor T7 may be a transistor (P-type transistor or N-type transistor), the control terminal of the third switching transistor T7 may be a gate of the transistor, the input terminal of the third switching transistor T7 may be a source (or drain) of the transistor, and the output terminal of the third switching transistor T7 may be a drain (or source) of the transistor. As shown in fig. 1, the third switching transistor T7 is a P-type transistor, the input end of the third switching transistor T7 may be a source electrode of the transistor, and the output end of the third switching transistor T7 may be a drain electrode of the transistor.
The second reset module 5 is configured to reset the anode of the second light emitting device D2 during a reset phase. Specifically, the second reset module 5 includes a fourth switching tube T9, and the second reset module 5 is further configured to input the reset signal vi_ano and the first SCAN signal SCAN1, in a reset stage, turn on the fourth switching tube T9 according to the first SCAN signal SCAN1, and reset the anode of the second light emitting device D2 according to the reset signal vi_ano.
The control end of the fourth switching tube T9 is connected to the first scanning signal SCAN1, the input end of the fourth switching tube T9 is connected to the reset signal Vi_Ano, and the output end of the fourth switching tube T9 is connected to the anode of the second light emitting device.
The fourth switching transistor T9 may be a transistor (P-type transistor or N-type transistor), the control terminal of the fourth switching transistor T9 may be a gate of the transistor, the input terminal of the fourth switching transistor T9 may be a source (or a drain) of the transistor, and the output terminal of the fourth switching transistor T9 may be a drain (or a source) of the transistor. As shown in fig. 1, the fourth switching transistor T9 is a P-type transistor, the input end of the fourth switching transistor T9 may be a source electrode of the transistor, and the output end of the fourth switching transistor T9 may be a drain electrode of the transistor.
As shown in fig. 1, the Data writing module 1 includes a fifth switching tube T2, a sixth switching tube T5 and a seventh switching tube T1, and the Data writing module 1 is further configured to input a third light emitting signal EM1 and a second SCAN signal SCAN2, in a Data writing stage, according to the third light emitting signal EM1 and the second SCAN signal SCAN2, turn on the fifth switching tube T2 and the seventh switching tube T1, and turn off the sixth switching tube T5 to write the Data signal Data, in a light emitting stage, according to the third light emitting signal EM1 and the second SCAN signal SCAN2, turn off the fifth switching tube T2, and turn on the sixth switching tube T5 and the seventh switching tube T1, so as to output the Data signal Data.
The data writing module 1 may further include an eighth switching tube T3, a first capacitor Cst, and a second capacitor Cboost. Specifically, the control end of the fifth switching tube T2 is connected to the second SCAN signal SCAN2, the input end of the fifth switching tube T2 is connected to the Data signal Data, the output end of the fifth switching tube T2 is connected to the output end of the sixth switching tube T5, the control end of the sixth switching tube T5 is connected to the third light emitting signal EM1, and the input end of the sixth switching tube T5 is connected to the high voltage signal VDD. The control end of the seventh switching tube T1 is connected with one end of the first capacitor Cst, the other end of the first capacitor Cst is connected with a high-voltage signal VDD, the input end of the seventh switching tube T1 is connected with the output end of the sixth switching tube T5, and the output end of the seventh switching tube T1 is respectively connected with the input end of the first switching tube T6 and the input end of the second switching tube T8. One end of the second capacitor Cboost is connected with the control end of the fifth switching tube T2, and the other end of the second capacitor Cboost is connected with the control end of the seventh switching tube T1. The control end of the eighth switching tube T3 is connected with the third scanning signal SCAN3, the input end of the eighth switching tube T3 is connected with the control end of the seventh switching tube T1, and the output end of the eighth switching tube T3 is connected with the output end of the seventh switching tube T1.
The first capacitor Cst is a storage capacitor, and is configured to provide a corresponding potential for the gate of the seventh switching tube T1 in the light-emitting stage, so as to control the conduction degree of the seventh switching tube T1. The second capacitor Cboost is a voltage stabilizing capacitor, and is used for stabilizing the gate potential of the seventh switching tube T1.
The sixth switching transistor T5 may be a transistor (P-type transistor or N-type transistor), the control terminal of the sixth switching transistor T5 may be a gate of the transistor, the input terminal of the sixth switching transistor T5 may be a source (or a drain) of the transistor, and the output terminal of the sixth switching transistor T5 may be a drain (or a source) of the transistor. As shown in fig. 1, the sixth switching transistor T5 is the same as the first switching transistor T6 and the second switching transistor T8, i.e., P-type transistors.
The on or off of the sixth switching tube T5 is controlled by the third light emitting signal EM 1. When the transistor types of the sixth switching tube T5 and the first switching tube T6 and the second switching tube T8 are the same, if the Data signal Data reaches the preset threshold, the waveforms of the first light-emitting signal EM2 and the third light-emitting signal EM1 are consistent; if the Data signal Data does not reach the preset threshold, the second light emitting signal EM3 is consistent with the waveform of the third light emitting signal EM 1.
The fifth, seventh and eighth switching transistors T2, T1 and T3 may each be a transistor (P-type transistor or N-type transistor). The control ends of the fifth switching tube T2, the seventh switching tube T1 and the eighth switching tube T3 may be gates of transistors, the input ends of the fifth switching tube T2, the seventh switching tube T1 and the eighth switching tube T3 may be sources (or drains) of transistors, and the output ends of the fifth switching tube T2, the seventh switching tube T1 and the eighth switching tube T3 may be drains (or sources) of transistors. As shown in fig. 1, the fifth switching tube T2 and the seventh switching tube T1 are P-type transistors, the input ends of the fifth switching tube T2 and the seventh switching tube T1 may be sources of the transistors, and the output ends of the fifth switching tube T2 and the seventh switching tube T1 may be drains of the transistors. The eighth switching transistor T3 is an N-type transistor, the input terminal of the eighth switching transistor T3 is a drain electrode of the transistor, and the output terminal of the eighth switching transistor T3 is a source electrode of the transistor.
As shown in fig. 1, the pixel circuit further includes an initialization module 6, and the initialization module 6 is connected to the data writing module 1. The initialization module 6 is configured to initialize the control terminal of the seventh switching tube T1 in an initialization stage.
Specifically, the initialization module 6 includes a ninth switching tube T4, a control end of the ninth switching tube T4 is connected to the fourth SCAN signal SCAN4, an input end of the ninth switching tube T4 is connected to the initialization signal vi_g, and an output end of the ninth switching tube T4 is connected to a control end of the seventh switching tube T1.
In the initialization stage, the ninth switching tube T4 is turned on according to the fourth SCAN signal SCAN4, and the control terminal of the seventh switching tube T1 is initialized according to the initialization signal vi_g.
The ninth switching transistor T4 may be a transistor (P-type transistor or N-type transistor), the control terminal of the ninth switching transistor T4 may be a gate of the transistor, the input terminal of the ninth switching transistor T4 may be a source (or drain) of the transistor, and the output terminal of the ninth switching transistor T4 may be a drain (or source) of the transistor. As shown in fig. 1, the ninth switching transistor T4 is an N-type transistor, the input terminal of the ninth switching transistor T4 may be a drain of the transistor, and the output terminal of the ninth switching transistor T4 may be a source of the transistor.
The following describes the operation principle of the pixel circuit according to the embodiment of the present application with reference to fig. 1 to 3.
When the display panel enters the low-gray-scale display, as shown in fig. 2, in the initialization stage, i.e., in the time period from T1 to T2, the third light-emitting signal EM1, the first light-emitting signal EM2, the second light-emitting signal EM3, the first scanning signal SCAN1, the second scanning signal SCAN2, and the fourth scanning signal SCAN4 are all at the high level H, and the third scanning signal SCAN3 is at the low level L, so that the first switching tube T6, the second switching tube T8, the third switching tube T7, the fourth switching tube T9, the fifth switching tube T2, the sixth switching tube T5, the seventh switching tube T1, and the eighth switching tube T3 are all turned off, and the ninth switching tube T4 is turned on to initialize the control end of the seventh switching tube T1.
In the reset phase and the data writing phase, the first period t2 to t3 and the second period t3 to t4 are included. As shown in fig. 2, in the first period, the third light emitting signal EM1, the first light emitting signal EM2, the second light emitting signal EM3 and the third scanning signal SCAN3 are all at a high level H, the fourth scanning signal SCAN4 is at a low level L, the first scanning signal SCAN1 is at a low level L and then at a high level H, the second scanning signal SCAN2 is at a high level H and then at a low level L, so that the first switching tube T6, the second switching tube T8, the sixth switching tube T5 and the ninth switching tube T4 are all turned off, the eighth switching tube T3 is turned on, the fifth switching tube T2 and the seventh switching tube T1 are turned off, the third switching tube T7 and the fourth switching tube T9 are turned on first to reset the anode of the first light emitting device D1 and the anode of the second light emitting device D2, and then the third switching tube T7 and the fourth switching tube T9 are turned off, the fifth switching tube T2 and the seventh switching tube T1 are turned on, and the data signal is written into the Q. In the second period, the third light emitting signal EM1, the first light emitting signal EM2 and the second light emitting signal EM3 are all at a high level H, the fourth scanning signal SCAN4 and the third scanning signal SCAN3 are all at a low level L, the first scanning signal SCAN1 is first at a low level L and then at a high level H, the second scanning signal SCAN2 is first at a high level H and then at a low level L, so that the first switching tube T6, the second switching tube T8, the sixth switching tube T5, the eighth switching tube T3 and the ninth switching tube T4 are all turned off, the fifth switching tube T2 and the seventh switching tube T1 are turned off, the third switching tube T7 and the fourth switching tube T9 are turned on first to reset the anode of the first light emitting device D1 and the anode of the second light emitting device D2, then the third switching tube T7 and the fourth switching tube T9 are turned off, and the fifth switching tube T2 and the seventh switching tube T1 are turned on, and the data signal is written into the point B.
In the light emitting stage, i.e. in the period from T4 to T5, the third light emitting signal EM1, the first light emitting signal EM2, the third SCAN signal SCAN3 and the fourth SCAN signal SCAN4 are at a low level L, and the second light emitting signal EM3, the first SCAN signal SCAN1 and the second SCAN signal SCAN2 are both at a high level H, so that the second switching tube T8, the third switching tube T7, the fourth switching tube T9, the ninth switching tube T4, the fifth switching tube T2 and the eighth switching tube T3 are all turned off, and the sixth switching tube T5, the seventh switching tube T1 and the first switching tube T6 are turned on to drive the first light emitting device D1 to emit light according to the data signal.
When the display panel enters the high gray scale display, as shown in fig. 3, in the initialization stage, i.e., in the time period from T1 to T2, the third light emitting signal EM1, the first light emitting signal EM2, the second light emitting signal EM3, the first scanning signal SCAN1, the second scanning signal SCAN2, and the fourth scanning signal SCAN4 are all at the high level H, and the third scanning signal SCAN3 is at the low level L, so that the first switching tube T6, the second switching tube T8, the third switching tube T7, the fourth switching tube T9, the fifth switching tube T2, the sixth switching tube T5, the seventh switching tube T1, and the eighth switching tube T3 are all turned off, and the ninth switching tube T4 is turned on to initialize the control end of the seventh switching tube T1.
In the reset phase and the data writing phase, the first period t2 to t3 and the second period t3 to t4 are included. As shown in fig. 2, in the first period, the third light emitting signal EM1, the first light emitting signal EM2, the second light emitting signal EM3 and the third scanning signal SCAN3 are all at a high level H, the fourth scanning signal SCAN4 is at a low level L, the first scanning signal SCAN1 is at a low level L and then at a high level H, the second scanning signal SCAN2 is at a high level H and then at a low level L, so that the first switching tube T6, the second switching tube T8, the sixth switching tube T5 and the ninth switching tube T4 are all turned off, the eighth switching tube T3 is turned on, the fifth switching tube T2 and the seventh switching tube T1 are turned off, the third switching tube T7 and the fourth switching tube T9 are turned on first to reset the anode of the first light emitting device D1 and the anode of the second light emitting device D2, and then the third switching tube T7 and the fourth switching tube T9 are turned off, the fifth switching tube T2 and the seventh switching tube T1 are turned on, and the data signal is written into the Q. In the second period, the third light emitting signal EM1, the first light emitting signal EM2 and the second light emitting signal EM3 are all at a high level H, the fourth scanning signal SCAN4 and the third scanning signal SCAN3 are all at a low level L, the first scanning signal SCAN1 is first at a low level L and then at a high level H, the second scanning signal SCAN2 is first at a high level H and then at a low level L, so that the first switching tube T6, the second switching tube T8, the sixth switching tube T5, the eighth switching tube T3 and the ninth switching tube T4 are all turned off, the fifth switching tube T2 and the seventh switching tube T1 are turned off, the third switching tube T7 and the fourth switching tube T9 are turned on first to reset the anode of the first light emitting device D1 and the anode of the second light emitting device D2, then the third switching tube T7 and the fourth switching tube T9 are turned off, and the fifth switching tube T2 and the seventh switching tube T1 are turned on, and the data signal is written into the point B.
In the light emitting stage, i.e. in the period from T4 to T5, the third light emitting signal EM1, the second light emitting signal EM3, the third SCAN signal SCAN3 and the fourth SCAN signal SCAN4 are at a low level L, and the first light emitting signal EM2, the first SCAN signal SCAN1 and the second SCAN signal SCAN2 are all at a high level H, so that the third switching tube T7, the fourth switching tube T9, the ninth switching tube T4, the fifth switching tube T2, the first switching tube T6 and the eighth switching tube T3 are all turned off, and the sixth switching tube T5, the seventh switching tube T1 and the second switching tube T8 are turned on to drive the second light emitting device D2 to emit light according to the data signal.
In summary, the embodiment of the application controls the first light emitting device with smaller luminous efficiency in the first light emitting module to emit light when the data signal reaches the preset threshold (enters the low gray level display) by setting the first light emitting module and the second light emitting module, controls the second light emitting device with larger luminous efficiency in the second light emitting module to emit light when the data signal does not reach the preset threshold (enters the high gray level display), meets the requirement of the high and low gray level display on the luminous efficiency, improves the brightness uniformity in the low gray level display, and reduces the power consumption in the high gray level display.
Correspondingly, the embodiment of the application also provides a display panel which comprises the pixel circuit in the embodiment. As shown in fig. 4, the display panel 100 includes a plurality of pixel circuits 200, and the plurality of pixel circuits 200 are distributed in a plurality of rows and a plurality of columns, and each pixel circuit 200 can be a pixel circuit in the above embodiment, which is not described in detail herein.
The display panel in the embodiment of the application can meet the requirement of high and low gray scale display on luminous efficiency, improves the brightness uniformity during low gray scale display, and reduces the power consumption.
In summary, although the present application has been described with reference to the preferred embodiments, the preferred embodiments are not intended to limit the application, and those skilled in the art can make various modifications and adaptations without departing from the spirit and scope of the application, and the scope of the application is therefore defined by the claims.

Claims (10)

1. A pixel circuit, comprising:
the data writing module is used for writing data signals in a data writing stage; outputting the data signal in a light emitting stage;
the first light-emitting module comprises a first light-emitting device and is used for controlling the first light-emitting device to emit light according to the data signal when the data signal reaches a preset threshold value;
the second light-emitting module comprises a second light-emitting device and is used for controlling the second light-emitting device to emit light according to the data signal when the data signal does not reach the preset threshold value; the second light emitting device has a light emitting efficiency greater than that of the first light emitting device.
2. The pixel circuit of claim 1, wherein the first light emitting module further comprises a first switching tube, the first light emitting module is further configured to input a first light emitting signal, and when the data signal reaches the preset threshold, turn on the first switching tube according to the first light emitting signal, so as to control the first light emitting device to emit light according to the data signal;
the second light-emitting module further comprises a second switch tube, and the second light-emitting module is further used for inputting a second light-emitting signal, and conducting the second switch tube according to the second light-emitting signal when the data signal does not reach the preset threshold value, so that the second light-emitting device is controlled to emit light according to the data signal.
3. The pixel circuit according to claim 2, wherein a control end of the first switching tube is connected to the first light-emitting signal, an input end of the first switching tube is connected to the data writing module, an output end of the first switching tube is connected to an anode of the first light-emitting device, and a cathode of the first light-emitting device is connected to a low-voltage signal;
the control end of the second switching tube is connected with the second light-emitting signal, the input end of the second switching tube is connected with the data writing module, the output end of the second switching tube is connected with the anode of the second light-emitting device, and the cathode of the second light-emitting device is connected with the low-voltage signal.
4. The pixel circuit of claim 1, wherein the pixel circuit further comprises:
the first reset module is used for resetting the anode of the first light-emitting device in a reset stage;
and the second reset module is used for resetting the anode of the second light-emitting device in a reset stage.
5. The pixel circuit of claim 4, wherein the first reset module includes a third switching tube, the first reset module is further configured to input a reset signal and a first scan signal, and in a reset phase, turn on the third switching tube according to the first scan signal and reset an anode of the first light emitting device according to the reset signal;
the second reset module comprises a fourth switch tube, and is further used for inputting the reset signal and the first scanning signal, conducting the fourth switch tube according to the first scanning signal in a reset stage, and resetting the anode of the second light-emitting device according to the reset signal.
6. The pixel circuit according to claim 5, wherein a control end of the third switching tube is connected to the first scanning signal, an input end of the third switching tube is connected to the reset signal, and an output end of the third switching tube is connected to an anode of the first light emitting device;
the control end of the fourth switching tube is connected with the first scanning signal, the input end of the fourth switching tube is connected with the reset signal, and the output end of the fourth switching tube is connected with the anode of the second light-emitting device.
7. The pixel circuit according to claim 2, wherein the data writing module includes a fifth switching tube, a sixth switching tube, and a seventh switching tube, the data writing module is further configured to input a third light emission signal and a second scan signal, turn on the fifth switching tube and the seventh switching tube according to the third light emission signal and the second scan signal, and turn off the sixth switching tube to write the data signal during a data writing period, turn off the fifth switching tube according to the third light emission signal and the second scan signal, and turn on the sixth switching tube and the seventh switching tube to output the data signal during a light emission period.
8. The pixel circuit of claim 7 wherein the first light-emitting signal corresponds to a waveform of the third light-emitting signal when the data signal reaches the preset threshold; and when the data signal does not reach the preset threshold value, the second light-emitting signal is consistent with the waveform of the third light-emitting signal.
9. The pixel circuit of claim 7, wherein the pixel circuit further comprises:
and the initialization module is used for initializing the control end of the fifth switching tube in the initialization stage.
10. A display panel comprising a pixel circuit according to any one of claims 1 to 9.
CN202310099158.8A 2023-01-31 2023-01-31 Pixel circuit and display panel Pending CN117475858A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310099158.8A CN117475858A (en) 2023-01-31 2023-01-31 Pixel circuit and display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310099158.8A CN117475858A (en) 2023-01-31 2023-01-31 Pixel circuit and display panel

Publications (1)

Publication Number Publication Date
CN117475858A true CN117475858A (en) 2024-01-30

Family

ID=89624427

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310099158.8A Pending CN117475858A (en) 2023-01-31 2023-01-31 Pixel circuit and display panel

Country Status (1)

Country Link
CN (1) CN117475858A (en)

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