CN117472807A

CN117472807A - Virtual address conversion method and device and electronic equipment

Info

Publication number: CN117472807A
Application number: CN202311828919.5A
Authority: CN
Inventors: 郇丹丹; 李祖松
Original assignee: Beijing Micro Core Technology Co ltd
Current assignee: Beijing Micro Core Technology Co ltd
Priority date: 2023-12-28
Filing date: 2023-12-28
Publication date: 2024-01-30
Anticipated expiration: 2043-12-28
Also published as: CN117472807B

Abstract

The embodiment of the application provides a virtual address conversion method, a virtual address conversion device and electronic equipment, and relates to the technical field of computers. The method comprises the following steps: compressing virtual page numbers and corresponding physical page numbers in page table entries based on preset virtual page step sizes in advance to obtain compression blocks corresponding to the page table entries; when the physical address conversion request is received, whether the compression block corresponding to each of the page table entries in the first-level translation lookaside buffer TLB comprises the target virtual address or not can be judged based on the high-order target virtual page number and the low-order target virtual page number of the target virtual address to be converted, and then the target physical address corresponding to the target virtual address is determined based on the judgment result. Compared with the prior art that the virtual page numbers and the corresponding physical page numbers are directly cached in the first-level TLB, more virtual page numbers and corresponding physical page numbers can be cached in a compression block mode, so that the hit rate of the virtual address in the first-level TLB can be improved to a certain extent.

Description

Virtual address conversion method and device and electronic equipment

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a virtual address conversion method, device, and electronic device.

Background

For any electronic device, the processing typically includes one or more central processing units (Central Processing Unit, CPU), memory management units (Memory Management Unit, MMU), and translation lookaside buffers (Translation Lookaside Buffer, TLB).

When the CPU receives a memory access request, the MMU converts a Virtual Address (Virtual Address) corresponding to the memory access request into a Physical Address (Physical Address), so as to access the memory through the Physical Address obtained by the conversion. In order to improve access efficiency, when the MMU translates a virtual address corresponding to a memory access request into a physical address, the MMU generally translates the virtual address into the physical address based on a partial Page Table Entry (PTE) of a Page Table cached in a first-level TLB.

However, since the first-level TLB has a limited memory capacity, page table entries of page tables that can be cached in the first-level TLB are limited, so that the hit rate of the virtual address in the first-level TLB is low when the virtual address is translated into a physical address based on the first-level TLB.

Disclosure of Invention

The application provides a virtual address translation method, a virtual address translation device and electronic equipment, which can effectively improve the hit rate of a virtual address in a first-level TLB to a certain extent when the virtual address is translated into a physical address based on the first-level TLB.

The embodiment of the application provides a virtual address conversion method, which may include:

receiving a physical address conversion request, wherein the physical address conversion request comprises a target virtual page number high-order bit and a target virtual page number low-order bit of a target virtual address to be converted;

judging whether the target virtual address is included in a compression block corresponding to each of a plurality of page table entries in a first-level translation lookaside buffer TLB based on the high-order target virtual page number and the low-order target virtual page number; the compression block is obtained by compressing virtual page numbers and corresponding physical page numbers in the page table entries based on preset virtual page step sizes;

and determining the target physical address corresponding to the target virtual address based on the judging result.

According to the method for translating a virtual address provided in the embodiment of the present application, the determining, based on the high-order virtual page number and the low-order virtual page number, whether the target virtual address is included in a compressed block corresponding to each of a plurality of page table entries in a first-level translation lookaside buffer TLB includes:

determining whether the plurality of page table entries comprise a target page table entry corresponding to the high bit of the target virtual page number;

And judging whether the target virtual address is included in a target compression block corresponding to the target page table entry based on the lower bits of the target virtual page number under the condition that the plurality of page table entries comprise the target page table entry.

According to the method for converting a virtual address provided in the embodiment of the present application, the determining, based on the low-order of the target virtual page number, whether the target virtual address is included in the target compression block corresponding to the target page table entry includes:

determining that the target virtual address is included in the target compression block under the condition that the target virtual page number low order is in the virtual page number range in the target compression block and the target virtual page number low order meets the multiple of the preset virtual page step length;

determining that the target virtual address is not included in the target compression block when the target virtual page number low order is not in the virtual page number range of the target compression block and/or the target virtual page number low order does not meet the multiple of the preset virtual page step length;

the virtual page number range is determined based on a virtual page number low-order minimum value in the target compression block and a virtual page number low-order maximum value in the target compression block.

According to the method for converting a virtual address provided in the embodiment of the present application, the determining, based on a determination result, a target physical address corresponding to the target virtual address includes:

under the condition that the target compression block comprises the target virtual address, determining a target physical page number corresponding to the target virtual address from the target compression block;

the target physical address is determined based on the target physical page number and an intra-page offset of the physical address.

According to the method for converting a virtual address provided in the embodiment of the present application, the physical page number in the target compression block meets the physical page step size, and the determining, from the target compression block, the target physical page number corresponding to the target virtual address includes:

the target physical page number is determined from the target compressed block based on the physical page step size and the target virtual address.

According to the method for converting a virtual address provided in the embodiment of the present application, the determining, based on the physical page step size and the target virtual address, the target physical page number from the target compressed block includes:

based on the base physical page number, according toDetermining the target physical page number;

Wherein PPN represents the target physical page number, PPN-Base represents the Base physical page number, stride_p represents the physical page step size, and m represents a multiple across a preset virtual page step size.

the target physical page number is determined according to PPN=PPN-base+strand_P < < i > by taking the Base physical page number as a reference;

wherein PPN represents the target physical page number, PPN-Base represents the Base physical page number, stride_p represents the physical page step size, i represents a left shift by i bits, i being determined based on a multiple m across a preset virtual page step size.

under the condition that the target virtual address is not included in the target compression block, searching a target physical page number corresponding to the target virtual address from a second-level TLB based on the high-order of the target virtual page number and the low-order of the target virtual page number;

According to the method for converting a virtual address provided in the embodiment of the present application, when the target compressed block does not include the target virtual address, the method further includes:

compressing virtual page numbers and corresponding physical page numbers in the target page table entries according to preset granularity to obtain the target compression block, wherein the target compression block comprises the target virtual address and the corresponding target physical page numbers;

the target compressed block is cached in a first level TLB.

According to the method for converting the virtual address provided by the embodiment of the application, the virtual page number and the corresponding physical page number in the target page table item are compressed according to the preset granularity, and the method comprises the following steps:

and compressing the virtual page number and the corresponding physical page number in the target page table item according to the preset granularity in a path filled by the first-level TLB based on the virtual page number and the corresponding physical page number in the target page table item.

According to an embodiment of the present application, the method for translating a virtual address, which caches the target compressed block in the first-level TLB, includes:

Caching the target compression block into the first-level TLB if the first-level TLB is not fully occupied;

or,

determining a page table item to be replaced from the first-level TLB according to a priority replacement sequence under the condition that the first-level TLB is fully occupied; replacing the compression block corresponding to the page table entry to be replaced with the target compression block;

wherein, the priority replacement sequence is as follows: uncompressed page table entries and compressed page table entries.

The embodiment of the application also provides a virtual address conversion device, which may include:

the device comprises a receiving unit, a processing unit and a processing unit, wherein the receiving unit is used for receiving a physical address conversion request, and the physical address conversion request comprises a target virtual page number high order and a target virtual page number low order of a target virtual address to be converted;

the first processing unit is used for judging whether the target virtual address is included in a compression block corresponding to each of a plurality of page table entries in the first-stage translation look-aside buffer TLB or not based on the high bit of the target virtual page number and the low bit of the target virtual page number; the compression block is obtained by compressing virtual page numbers and corresponding physical page numbers in the page table entries based on preset virtual page step sizes;

And the second processing unit is used for determining a target physical address corresponding to the target virtual address based on the judging result.

According to an embodiment of the present application, the first processing unit is configured to determine, based on the high-order target virtual page number and the low-order target virtual page number, whether compressed blocks corresponding to a plurality of page table entries in a TLB include the target virtual address, where the compressed blocks include the target virtual address, where the first processing unit includes:

According to the virtual address translation apparatus provided in the embodiment of the present application, the first processing unit is configured to determine, based on the low bits of the target virtual page number, whether a target compression block corresponding to the target page table entry includes the target virtual address, and includes:

According to the virtual address translation device provided in the embodiment of the present application, the second processing unit is configured to determine, based on a determination result, a target physical address corresponding to the target virtual address, and includes:

According to an embodiment of the present application, the physical page number in the target compression block satisfies a physical page step size, and the second processing unit is configured to determine, from the target compression block, a target physical page number corresponding to the target virtual address, where the target physical page number includes:

According to an embodiment of the present application, the second processing unit is configured to determine, based on the physical page step size and the target virtual address, the target physical page number from the target compression block, where the second processing unit includes:

According to the virtual address conversion device provided by the embodiment of the application, when the target compression block does not include the target virtual address, the device further includes a compression unit and a cache unit:

the compression unit is used for compressing the virtual page number and the corresponding physical page number in the target page table item according to a preset granularity to obtain the target compression block, wherein the target compression block comprises the target virtual address and the corresponding target physical page number;

the caching unit is used for caching the target compression block into the first-level TLB.

According to the virtual address translation device provided in the embodiment of the present application, the compression unit is configured to compress, according to a preset granularity, a virtual page number and a corresponding physical page number in the target page table entry, and includes:

According to an embodiment of the present application, the cache unit is configured to cache the target compressed block into the first-level TLB, and includes:

or,

The application also provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the virtual address translation method according to any one of the above when executing the program.

The present application also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method of virtual address translation as described in any of the above.

The present application also provides a computer program product comprising a computer program which, when executed by a processor, implements a method of translating a virtual address as described in any of the above.

According to the virtual address conversion method, the virtual address conversion device and the electronic equipment, the virtual page and the physical page of the page table item are considered to have continuous characteristics and span (Stride) growth characteristics, so that virtual page numbers and corresponding physical page numbers in the page table item are compressed in advance based on a preset virtual page step length to obtain a compressed block corresponding to the page table item; when the physical address conversion request is received, whether the compression block corresponding to each of the page table entries in the first-level TLB comprises the target virtual address or not can be judged based on the high-order virtual page number of the target virtual address to be converted and the low-order virtual page number of the target virtual address, and then the target physical address corresponding to the target virtual address is determined based on the judgment result. Compared with the prior art that the virtual page numbers and the corresponding physical page numbers are directly cached in the first-level TLB, more virtual page numbers and corresponding physical page numbers can be cached in a compression block mode, so that the hit rate of the virtual address in the first-level TLB can be improved to a certain extent.

Drawings

For a clearer description of the present application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flow chart of a virtual address conversion method provided in an embodiment of the present application;

FIG. 2 is a flowchart illustrating a method for determining whether a compressed block corresponding to each of a plurality of page table entries in a first-level TLB includes a target virtual address according to an embodiment of the present application;

FIG. 3 is a schematic diagram of translating virtual addresses into physical addresses according to an embodiment of the present application;

FIG. 4 is a flowchart illustrating a method for buffering a target compressed block in a first-level TLB according to an embodiment of the present application;

FIG. 5 is a flowchart illustrating another virtual address translation method according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a virtual address translation device according to an embodiment of the present application;

fig. 7 is a schematic entity structure diagram of an electronic device according to an embodiment of the present application.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is apparent that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

In embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: there are three cases, a alone, a and B together, and B alone, wherein a, B may be singular or plural. In the text description of the present application, the character "/" generally indicates that the front-rear association object is an or relationship.

The technical scheme provided by the embodiment of the application can be applied to the scene of virtual address conversion. When the CPU receives the memory access request, the virtual address corresponding to the memory access request is converted into a physical address through the MMU, so that the memory is accessed through the physical address obtained through conversion. When the MMU translates a virtual address corresponding to a memory access request into a physical address, in order to improve access efficiency, the MMU generally translates the virtual address into the physical address based on a portion of page table entries of page tables cached in the first-level TLB.

One page table item corresponds to one page, and the page table item contains relevant information of the corresponding page, such as a physical page number, a protection mark, a modification mark and the like, and can be specifically set according to actual needs. Wherein the physical page number is the key for the operating system to map virtual addresses to physical addresses.

When the MMU converts the virtual address into the physical address based on part of page table items cached in the first-level TLB, the MMU accesses the TLB first, if the TLB contains page table items from the virtual address corresponding to the memory access request to the physical address, the virtual address is considered to hit in the first-level TLB, namely TLB hit, and the virtual address can be directly converted into the physical address based on the page table items; otherwise, the virtual address is considered to be missed in the first-level TLB, namely TLB miss; in this case, the MMU needs to further access the next-level storage system, or the memory searches a page table entry from a virtual address corresponding to the memory access request to a physical address, and converts the virtual address to the physical address based on the searched page table entry, thereby realizing conversion of the virtual address to the physical address.

In order to improve the hit rate of the virtual address in the first-level TLB to a certain extent, the embodiment of the present application provides a virtual address translation method, which considers that virtual pages and physical pages of page table entries have continuous characteristics and span length (Stride) increasing characteristics, so in the embodiment of the present application, virtual page numbers and corresponding physical page numbers in page table entries can be compressed in advance based on preset virtual page step length to obtain compression blocks corresponding to page table entries; when the physical address conversion request is received, whether the compression block corresponding to each of the page table entries in the first-level TLB comprises the target virtual address or not can be judged based on the high-order virtual page number of the target virtual address to be converted and the low-order virtual page number of the target virtual address, and then the target physical address corresponding to the target virtual address is determined based on the judgment result. Compared with the prior art that the virtual page numbers and the corresponding physical page numbers are directly cached in the first-level TLB, more virtual page numbers and corresponding physical page numbers can be cached in a compression block mode, so that the hit rate of the virtual address in the first-level TLB can be improved to a certain extent.

It may be understood that, in the embodiment of the present application, the value of the preset virtual page step may be set according to actual needs, where the embodiment of the present application is not further limited to the specific value of the preset virtual page step.

The method for converting virtual addresses provided in the present application will be described in detail in the following several specific embodiments. It is to be understood that the following embodiments may be combined with each other and that some embodiments may not be repeated for the same or similar concepts or processes.

Fig. 1 is a flow chart of a virtual address conversion method provided in an embodiment of the present application, where the virtual address conversion method may be executed by a software and/or hardware device. For example, referring to fig. 1, the method for converting a virtual address may include:

s101, receiving a physical address conversion request, wherein the physical address conversion request comprises a target virtual page number high order and a target virtual page number low order of a target virtual address to be converted.

Wherein, the high order of the target virtual page number generally refers to the index part in the page table, which is used for finding the corresponding entry in the page table; the low order of the target virtual page number generally refers to the offset in the page table entry used to locate a specific physical address in the found entry.

It can be appreciated that, in the embodiment of the present application, considering that the number of page table entries is too large, it may be very time-consuming to find the whole page table entries, so, in order to improve the efficiency of memory access, the virtual page number may be divided into two parts, i.e. a high virtual page number and a low virtual page number, so that the operating system may quickly locate the corresponding page table entries in a smaller index space, thereby locating a specific physical address.

S102, judging whether a compression block corresponding to each of a plurality of page table entries in a primary translation look-aside buffer comprises a target virtual address or not based on a target virtual page number high order and a target virtual page number low order; the compression block is obtained by compressing virtual page numbers and corresponding physical page numbers in page table entries based on preset virtual page step sizes.

The page table entry may include a virtual page number high VPN-H and a virtual page number low, the virtual page number low minimum value of the page table entry coverage area may be denoted as VPN-L0, the virtual page number low maximum value may be denoted as VPN-L1, the virtual page step size may be denoted as stride_v in the preset virtual page step size, the physical page step size may be denoted as stride_p, the virtual page step size stride_v refers to the number of pages of two compressed virtual page intervals, and the physical page step size stride_p refers to the number of pages of two compressed physical page intervals.

It will be appreciated that in embodiments of the present application, virtual page size stride_v may not be equal to physical page size stride_p, as the operating system may use different page sizes or memory management policies.

Illustratively, when the virtual page step size stride_v is 1, it can be understood that consecutive virtual page numbers are compressed; when the physical page step size stride_p is 1, it can be understood that consecutive physical page numbers are compressed.

Considering that virtual pages and physical pages of page table entries have continuous characteristics and span length increasing characteristics, in order to enable a first-level TLB (virtual to first) namely an L1 TLB to cache more virtual page numbers and corresponding physical page numbers, so that the hit rate of virtual addresses in the first-level TLB is improved to a certain extent.

Compared with the prior art that the virtual page number and the corresponding physical page number are directly cached in the first-level TLB, more virtual page numbers and corresponding physical page numbers can be cached in a compressed block mode, so that the capacity utilization rate of the TLB is improved, when a physical address conversion request is received, whether the target virtual address is included in the compressed block corresponding to each of a plurality of page table items in the first-level TLB or not can be judged based on the high-order virtual page number and the low-order virtual page number of the target virtual address to be converted, and then the target physical address corresponding to the target virtual address is determined based on the judgment result, namely the following S103 is executed:

S103, determining a target physical address corresponding to the target virtual address based on the judging result.

It can be seen that, in the embodiment of the present application, considering that the virtual page and the physical page of the page table entry have not only continuous characteristics, but also span (Stride) growth characteristics, the virtual page number and the corresponding physical page number in the page table entry are compressed in advance based on the preset virtual page step length, so as to obtain a compressed block corresponding to the page table entry; when the physical address conversion request is received, whether the compression block corresponding to each of the page table entries in the first-level TLB comprises the target virtual address or not can be judged based on the high-order virtual page number of the target virtual address to be converted and the low-order virtual page number of the target virtual address, and then the target physical address corresponding to the target virtual address is determined based on the judgment result. Compared with the prior art that the virtual page numbers and the corresponding physical page numbers are directly cached in the first-level TLB, more virtual page numbers and corresponding physical page numbers can be cached in a compression block mode, so that the hit rate of the virtual address in the first-level TLB can be improved to a certain extent.

Based on the embodiment shown in fig. 1, in order to facilitate understanding how to determine whether the compressed block corresponding to each of the plurality of page table entries in the first-level TLB includes the target virtual address based on the target virtual page number high-order and the target virtual page number low-order in S102, the embodiment shown in fig. 2 will be described in detail below.

Fig. 2 is a flowchart of a method for determining whether a compressed block corresponding to each of a plurality of page table entries in a first-level TLB includes a target virtual address according to an embodiment of the present application, where the method may be performed by a software and/or hardware device. For example, referring to fig. 2, the method may include:

s201, determining whether a plurality of page table entries comprise target page table entries corresponding to high bits of target virtual page numbers.

When judging whether the compression block corresponding to each of the plurality of page table entries in the first-level TLB comprises a target virtual address, determining whether the plurality of page table entries comprise a target page table entry corresponding to the high-order of the target virtual page number, namely searching for a corresponding entry; if the plurality of page table entries do not include the target page table entry corresponding to the high-order virtual page number, the compressed block corresponding to the plurality of page table entries does not include the target virtual address, in this case, the target physical page number corresponding to the target virtual address may be searched from the second-level TLB based on the high-order virtual page number and the low-order virtual page number; and determining the target physical address based on the target physical page number and the intra-page offset of the physical address, thereby realizing conversion from the virtual address to the physical address.

Conversely, if the plurality of page table entries includes the target page table entry corresponding to the upper bit of the target virtual page number, the following S202 is executed:

s202, judging whether a target virtual address is included in a target compression block corresponding to the target page table item based on the low order of the target virtual page number when the plurality of page table items include the target page table item.

For example, when determining whether the target compression block corresponding to the target page table entry includes the target virtual address based on the target virtual page number low order, it may be determined whether the target virtual page number low order is within the virtual page number range in the target compression block, and whether the target virtual page number low order satisfies the multiple of the preset virtual page step size, so as to determine whether the target compression block includes the target virtual address; and determining the target physical address corresponding to the target virtual address based on the judging result. The virtual page number range is determined based on a virtual page number low-order minimum value in the target compressed block and a virtual page number low-order maximum value in the target compressed block.

For example, referring to fig. 3, fig. 3 is a schematic diagram of converting a virtual address to a physical address, where when determining whether a low-order virtual page number is within a virtual page number range in a compressed block and whether the low-order virtual page number meets a multiple of a preset virtual page step size, it may be determined that: ({ virtual address virtual page number high-order VPN-H, virtual page number low-order virtual address VPN-L } ] = { virtual page number high-order TLB VPN-H, virtual page number low-order minimum value TLB VPN-L0 }) & & ({ virtual page number high-order VPN-H, virtual page number low-order VPN-L } < = { virtual page number high-order TLB VPN-H, virtual page number low-order maximum value TLB VPN-L1 }) & } ({ virtual page number high-order VPN-H, virtual page number low-order VPN-L } satisfies multiples of virtual page step size stride_V span). Where "&" represents a logical AND, "{ }" represents a collage.

It will be appreciated that in the embodiment of the present application, the virtual page step size stride_v only affects hit determination whether the virtual page number falls within the page table entry range, and does not affect generation of the physical page number (Physical Page Number, PPN).

For example, in the case that the low order of the target virtual page number is within the virtual page number range in the target compression block and the low order of the target virtual page number satisfies the multiple of the preset virtual page step, the specific implementation of determining the target physical address corresponding to the target virtual address according to the determination result may be seen in S203-S204 below. In the case that the low order of the target virtual page number is not within the virtual page number range of the target compressed block and/or the low order of the target virtual page number is not a multiple of the preset virtual page step, the specific implementation of the target physical address corresponding to the target virtual address is determined according to the determination result, see S205-S206 below.

S203, determining that the target compression block comprises a target virtual address under the condition that the low order of the target virtual page number is in the virtual page number range in the target compression block and the low order of the target virtual page number meets the multiple of the preset virtual page step length.

And under the condition that the low order of the target virtual page number is in the virtual page number range in the target compression block and the low order of the target virtual page number meets the multiple of the preset virtual page step length, determining that the target virtual address hits in the first-level TLB, namely the target virtual address is included in the target compression block.

S204, under the condition that the target compression block comprises the target virtual address, determining a target physical page number corresponding to the target virtual address from the target compression block; and determining the target physical address based on the target physical page number and the intra-page offset of the physical address.

In the case of determining that the target virtual address hits in the first-level TLB, the target physical page number corresponding to the target virtual address may be determined directly from the target compression block.

Illustratively, in the embodiment of the present application, when determining the target physical page number from the target compressed block based on the physical page step size and the target virtual address, at least two possible implementations may be included:

in one possible implementation, the base physical page number may be used as a reference, according toA target physical page number is determined.

Wherein PPN represents a target physical page number, PPN-Base represents a Base physical page number, stride_P represents a physical page step size, and m represents a multiple across a preset virtual page step size. For example, when the virtual address is the target virtual address, the { target virtual page number high order VPN-H of the virtual address, virtual page number low order VPN-L } spans m virtual page step steps stride_V as compared to the { virtual page number high order TLB VPN-H, virtual page number low order TLB VPN-L } hit.

With physical page step size stride_P and m both being implemented as powers of 2, e.g. 1 (2 ⁰ ）、2（2 ¹ ）、4（2 ² ）、8（2 ³ ) And the like, namely, the stride_p is configured as an nth power of 2 (n is an integer of 0 or more), and m is an i power of 2 (i is an integer of 0 or more). When n is 0, it means that the physical page step size stride_p is 1, compressing the 4KB base pages whose physical addresses are consecutive.

It can be understood that, in the embodiment of the present application, the physical page step sizes stride_p and m are all implemented by powers of 2, which can simplify the process of generating the target physical page number in the present application, that is, the next possible implementation manner:

in another possible implementation, when determining the target physical page number, the target physical page number may be determined according to ppn=ppn-base+stride_p < < i, based on the Base physical page number.

Wherein PPN represents a target physical page number, PPN-Base represents a Base physical page number, stride_p represents a physical page step size, i represents a left shift by i bits, and i is determined based on a multiple m across a preset virtual page step size.

After the target physical page number is determined, the target physical address can be determined based on PPN-base+Stride_P < < i > and Offset, and the physical address { PPN-base+Stride_P < < i, offset } is obtained, so that only shift is needed, no operation is needed, and the conversion efficiency of the physical address can be effectively improved.

After the target physical page number is determined based on the two possible implementations, the method can be based onAnd Offset, determining the target physical address, or based on PPN-base+Stride_P<<i and Offset, determining the target physical address, so that after conversion to the target physical addressThe converted target physical address +.>Alternatively, { PPN-base+StrideP<<i, offset return to instruction to find TLB to +.>Or { PPN-base+StrideP }<<i, offset }, performing memory access.

Where Offset represents the intra-page Offset of the physical address, it is understood that in the embodiment of the present application, the intra-page Offset of the physical address is the same as the intra-page Offset of the virtual address.

Wherein the number of bits of the intra-page Offset of the physical address is determined according to the base page size, and the base page size of the general processor is 4KB (2 ¹² Byte), then the Offset is the lowest 12 bits, i.e., from 0 to 11 bits. The lower bit number of the virtual page number of the TLB is determined according to the virtual page range and the base page size of the TLB supporting compression, the bit number x of the lower bit is determined based on the virtual page compression range/the base page size, and x meets 2 ^x The virtual page compression range/base page size is the maximum compression of one TLB entry by several virtual pages. If compression within the 8KB virtual page range is supported, the lower bit of the virtual page number is 1 bit, namely 2 ¹ =8kb/4 KB, supporting compression in the range of 2 pages. If merging in the range of 2MB is supported, the lower bits of the virtual page number are 9 bits, i.e. 2 ⁹ =2 MB/4KB, supporting compression in the 512-page range. The lower bits of the virtual page number are the 12 to 11+ x bits from the virtual address. The upper bits of the virtual page number are from 12+x bits to the most significant bits of the virtual address. For example, a fifth generation reduced instruction set (Reduced Instruction Set Computer-Five, RISC-V) processor supporting the Sv39 paging mechanism has a virtual address length of 39 bits and a physical address length of 56 bits. The upper bits of the virtual page number are from 12+ x bits to 38 bits. The x of the compression range supported by the processor may be configured by software or set to a fixed value by hardware. If the configuration is carried out by software, a TLB compression control register is also arranged, and the x value is written into the control register by a software operating system according to analysis of program behaviors.

S205, determining that the target virtual address is not included in the target compression block when the low order of the target virtual page number is not in the virtual page number range of the target compression block and/or the low order of the target virtual page number is not in the multiple of the preset virtual page step.

The virtual page number range is determined based on a virtual page number low-order minimum value in the target page table entry and a virtual page number low-order maximum value in the target page table entry.

And if the low order of the target virtual page number is not in the virtual page number range of the target compression block and/or the low order of the target virtual page number is not in the multiple of the preset virtual page step length, the target virtual address is not hit in the first-level TLB, and the target virtual address is not included in the target compression block.

S206, searching a target physical page number corresponding to the target virtual address from the secondary TLB based on the high-order virtual page number and the low-order virtual page number of the target under the condition that the target virtual address is not included in the target compression block; and determining the target physical address based on the target physical page number and the intra-page offset of the physical address.

If the target virtual address is determined to miss in the first-level TLB, the L2 TLB can be marked as being further filled by the second-level TLB, namely, the target physical page number corresponding to the target virtual address is searched from the second-level TLB; and determining the target physical address based on the target physical page number and the intra-page offset of the physical address, so that even if the target virtual address misses in the first-level TLB, access to the TLB is not affected, and the time sequence critical path affecting the processor is effectively avoided.

It can be understood that, the method for determining the target physical address based on the target physical page number and the intra-page offset of the physical address is similar to the method for determining the target physical address based on the target physical page number and the intra-page offset of the physical address in S204 described above, and the description about determining the target physical address based on the target physical page number and the intra-page offset of the physical address in S204 described above will not be repeated herein.

It can be seen that, in this embodiment of the present application, when determining whether the compression block corresponding to each of the plurality of page table entries in the first-level TLB includes the target virtual address based on the high-order virtual page number and the low-order virtual page number, it may be determined whether the target compression block corresponding to the target page table entry includes the target virtual address based on the low-order virtual page number if the plurality of page table entries include the target page table entry, and determine the target physical page number corresponding to the target virtual address from the target compression block if the low-order virtual page number is within the virtual page number range in the target compression block and the low-order virtual page number satisfies the multiple of the preset virtual page step; the target physical address is determined based on the target physical page number and the intra-page offset of the physical address, so that the hit rate of the virtual address in the first-level TLB can be improved to a certain extent; searching a target physical page number corresponding to the target virtual address from the secondary TLB under the condition that the low order of the target virtual page number is not in the virtual page number range of the target compression block and/or the low order of the target virtual page number is not a multiple of a preset virtual page step length; and determining the target physical address based on the target physical page number and the intra-page offset of the physical address. Therefore, even if the target virtual address misses in the first-level TLB, the target physical page number corresponding to the target virtual address can be searched from the second-level TLB, and access to the TLB is not affected, so that the influence on a timing critical path of a processor is effectively avoided.

Based on the embodiment shown in fig. 2, when the target virtual address misses in the first-level TLB, after the target physical page number corresponding to the target virtual address is found in the second-level TLB, it may be further determined whether the target virtual address can be compressed according to the virtual page step size stride_v and the physical page step size stride_p within the compression granularity range of the second-level TLB, if the target virtual address can be compressed according to the virtual page step size stride_v and the physical page step size stride_p, virtual pages of multiple continuous or virtual page-crossing step sizes stride_v and page table entries of multiple physical pages of continuous or physical page-crossing step sizes stride_p may be compressed as one PTE table entry, and the compressed page table entries are returned to the first-level TLB; conversely, if the virtual page step size stride_v and the physical page step size stride_p cannot be compressed, the page table entries of the virtual page and the physical page are directly returned to the first-level TLB, so as to expand the page table entries cached in the first-level TLB, thereby providing a basis for the conversion of the subsequent physical address.

For example, referring to fig. 4, fig. 4 is a flowchart of a method for caching a target compressed block in a first-level TLB according to an embodiment of the present application, where the caching method may include:

s401, compressing virtual page numbers and corresponding physical page numbers in target page table entries according to preset granularity to obtain target compression blocks, wherein the target compression blocks comprise target virtual addresses and corresponding target physical page numbers.

The preset granularity may be determined based on a burst return width of the L2 TLB for accessing the L2 Cache. For example, burst returns have a width of 64 bytes (Byte), i.e., 512 bits. Typically, the burst return width also corresponds to the bit width of the Cache Line (L2 Cache Line) of the level two Cache.

For example, in the embodiment of the present application, when the virtual page number and the corresponding physical page number in the target page table entry are compressed according to the preset granularity, the virtual page number and the corresponding physical page number in the target page table entry may be compressed according to the preset granularity in the path for filling the first-level TLB, that is, the TLB compressed page table entry generation logic may be implemented on the path for filling the first-level TLB by the L2 TLB. The L2 TLB can return the compressed block of the page table entry to the L1 TLB, and the key path of the processor pipeline for accessing the L1 TLB is not affected.

In combination with the above related description, when the virtual page number and the corresponding physical page number in the target page table entry are compressed, it may be first determined whether the virtual page number and the corresponding physical page number can be compressed according to the virtual page step size stride_v and the physical page step size stride_p, if the virtual page number and the physical page step size stride_p can be compressed according to the virtual page step size stride_v and the physical page step size stride_p, a plurality of virtual pages of continuous or cross virtual page step size stride_v and page table entries of a plurality of physical pages of continuous or cross physical page step size stride_p can be compressed, so as to obtain a corresponding target compressed block, and the preset granularity is the virtual page step size stride_v and the physical page step size stride_p, and the target compressed block is used as a PTE table entry, and the compressed page table entry is returned to the first level of TLB.

When the virtual page number and the corresponding physical page number in the target page table item are compressed, the page table item PTE returned by the L2 TLB to the L1 TLB, namely a plurality of PTEs cached by the L2 TLB, is compressed in a plurality of PTE granularity ranges, a plurality of 4KB crossing the stride_V and base pages crossing the stride_P are compressed, and when the virtual page step size stride_V is 1, the continuous virtual page number can be understood to be compressed; when the physical page step size stride_p is 1, it can be understood that consecutive physical page numbers are compressed.

S402, buffering the target compression block into a first-level translation look-aside buffer.

Illustratively, caching the target compressed block in the first-level TLB may include at least two possible scenarios:

in one possible scenario, the first-level TLB is not fully occupied, which means that there is a storage space in the first-level TLB that can cache the target compressed block, and then the target compressed block can be directly cached in the first-level TLB, so as to expand the page table entry cached in the first-level TLB, thereby providing a basis for the translation of the subsequent physical address.

In another possible scenario, the first-level TLB is fully occupied, which indicates that no storage space in the first-level TLB may cache the target compressed block, and then the page table entry to be replaced may be determined from the first-level TLB according to the priority replacement order; and replacing the compression block corresponding to the page table entry to be replaced with the target compression block.

The priority replacement sequence is as follows: the uncompressed page table item and the compressed page table item, namely, the uncompressed TLB page table item is preferentially used as the page table item to be replaced, and the compressed TLB page table item is used as the page table item to be replaced under the condition that the uncompressed TLB page table item does not exist, and the compressed TLB page table item can be specifically set according to actual needs.

For example, in the embodiment of the present application, when the compressed TLB page table entry is used as the page table entry to be replaced, the selection policy may include: random replacement (Random), least recently used (Least Recently Used, LRU), least frequently used (Least Frequently Used, LFU), first-in first-out (First In First Out, FIFO), etc., may be specifically set according to actual needs, and the embodiments of the present application are only described by taking these several selection policies as examples, but are not limited thereto.

It can be seen that, in the embodiment of the present application, when the target virtual address misses in the first-level TLB, the virtual page number and the corresponding physical page number in the target page table entry found in the second-level TLB may be compressed according to a preset granularity, so as to obtain a target compression block, and the target compression block is cached in the first-level TLB, so that the page table entry cached in the first-level TLB may be expanded, and a basis is provided for the translation of the subsequent physical address.

In order to facilitate understanding of the virtual address translation method provided in the embodiments of the present application, a detailed description will be given below of the virtual address translation method provided in the embodiments of the present application by way of a specific embodiment.

For example, referring to fig. 5, fig. 5 is a flowchart of another virtual address translation method according to an embodiment of the present application, where the translation method may include:

upon receiving the physical address conversion request, the physical address conversion request includes a virtual page number high VPN-H and a virtual page number low of the virtual address to be converted, then judging ({ virtual page number high VPN-H, virtual page number low virtual address VPN-L } ] = { virtual page number high TLB VPN-H, virtual page number low minimum TLB VPN-L0 }) & } - ({ virtual page number high VPN-H, virtual page number low VPN-L } < = { virtual page number high TLB VPN-H, virtual page number low maximum TLB VPN-L1 }) & } - ({ virtual page number high VPN-H, the virtual page number low-order VPN-L satisfies the multiple of the virtual page step size stride_V span), "&" represents logical AND "{ }" represents spelling, namely if the virtual address virtual page number is greater than or equal to the minimum virtual page number of the TLB table entry and the virtual address virtual page number is less than or equal to the item of the maximum virtual page number of the TLB table entry in the first-stage translation look-aside buffer TLB, and satisfies the multiple of the virtual page number according to the virtual page step size stride_V span, determining that the judgment result is the first-stage translation look-aside buffer TLB hit, otherwise determining that the judgment result is the first-stage translation look-aside buffer TLB failure.

And when the judgment result is that the first-level TLB hits, generating a physical address corresponding to the virtual address. Obtaining a physical page number PPN as from a first level TLB hitM represents the virtual page number { virtual address VPN-H, virtual address VPN-L } accessing the TLB virtual address spanning m stride_V pages compared to the minimum virtual page number { TLB VPN-H, TLB VPN-L0} hitting the page table entry range. The intra-page Offset of the physical address is the same as the intra-page Offset of the virtual address; the converted physical address +.>An instruction is returned to find the first-level TLB.

When the judgment result is that the first-level TLB is invalid, the second-level TLB (L2 TLB) is accessed. When the L2 TLB returns a page table item PTE to the first-level TLB, in the compression granularity range, whether the page table item PTE can be compressed according to a virtual page step size stride_V and a physical page step size stride_P is judged. If so, compressing multiple virtual pages of continuous or stride_V and page table entries of multiple physical pages of continuous or stride_P as one PTE table entry, and returning the compressed page table entries to the first-level TLB. If not, the requested page table entry is returned directly to the first-level TLB.

When the page table entry is returned to the first-level TLB, if the first-level TLB page table entry is not fully occupied, i.e. the first-level TLB is not full, the physical address is returned to the first-level TLB, an empty entry of the page table entry is occupied, and the physical address is returned to the physical address translation request for searching the first-level TLB. If the first level TLB page table entry is fully occupied, i.e., the TLB is full, then the replacement entry is selected, and the policy is selected based on the following criteria: the method comprises the steps of selecting to replace an uncompressed TLB (TLB) table item according to a selection strategy, selecting to replace a compressed TLB table item according to the selection strategy, returning a physical address to a first-level TLB, occupying a replacement item of a page table item, and returning the physical address to a physical address translation request for searching the first-level TLB.

Illustratively, in an embodiment of the present application, the selection policy may include: random replacement, least recently used, least frequently used, first in first out, etc., may be specifically set according to actual needs, and the embodiments of the present application are only described by taking these selection strategies as examples, but the embodiments of the present application are not limited thereto.

The virtual address conversion device provided in the present application will be described below, and the virtual address conversion device described below and the virtual address conversion method described above may be referred to correspondingly to each other.

Fig. 6 is a schematic structural diagram of a virtual address translation device according to an embodiment of the present application, for example, referring to fig. 6, the virtual address translation device may include:

a receiving unit 601, configured to receive a physical address conversion request, where the physical address conversion request includes a target virtual page number high order and a target virtual page number low order of a target virtual address to be converted.

A first processing unit 602, configured to determine, based on the high-order virtual page number and the low-order virtual page number, whether the target virtual address is included in a compressed block corresponding to each of a plurality of page table entries in the TLB; the compression block is obtained by compressing virtual page numbers and corresponding physical page numbers in the page table entries based on preset virtual page step sizes.

The second processing unit 603 is configured to determine a target physical address corresponding to the target virtual address based on the determination result.

For example, in the embodiment of the present application, the first processing unit 602 is configured to determine, based on the high-order target virtual page number and the low-order target virtual page number, whether the compressed blocks corresponding to the page table entries in the first-level TLB include the target virtual address, where the determining includes:

For example, in the embodiment of the present application, the first processing unit 602 is configured to determine, based on the low bits of the target virtual page number, whether the target virtual address is included in the target compression block corresponding to the target page table entry, including:

For example, in the embodiment of the present application, the second processing unit 603 is configured to determine, based on a determination result, a target physical address corresponding to the target virtual address, including:

For example, in the embodiment of the present application, the physical page number in the target compression block meets a physical page step size, and the second processing unit 603 is configured to determine, from the target compression block, a target physical page number corresponding to the target virtual address, including:

For example, in the embodiment of the present application, the second processing unit 603 is configured to determine, based on the physical page step size and the target virtual address, the target physical page number from the target compressed block, where the determining includes:

In an example, in this embodiment of the present application, in a case where the target virtual address is not included in the target compression block, the virtual address conversion apparatus further includes a compression unit and a cache unit.

In an embodiment of the present application, the compressing unit is configured to compress, according to a preset granularity, a virtual page number and a corresponding physical page number in the target page table entry, where the compressing unit includes:

For example, in an embodiment of the present application, the caching unit is configured to cache the target compressed block into the first-level TLB, and includes:

or,

The embodiment of the present application provides a virtual address conversion device, which can execute the technical scheme of the virtual address conversion method in any of the embodiments, and the implementation principle and beneficial effects of the virtual address conversion method are similar to those of the virtual address conversion method, and can be referred to herein without redundant description.

Fig. 7 is a schematic physical structure diagram of an electronic device according to an embodiment of the present application, as shown in fig. 7, the electronic device may include: processor 710, communication interface (Communications Interface) 720, memory 730, and communication bus 740, wherein processor 710, communication interface 720, memory 730 communicate with each other via communication bus 740. Processor 710 may call logic instructions in memory 730 to perform a method of virtual address translation, the method comprising: receiving a physical address conversion request, wherein the physical address conversion request comprises a target virtual page number high-order bit and a target virtual page number low-order bit of a target virtual address to be converted; judging whether the target virtual address is included in a compression block corresponding to each of a plurality of page table entries in a first-level translation lookaside buffer TLB based on the high-order target virtual page number and the low-order target virtual page number; the compression block is obtained by compressing virtual page numbers and corresponding physical page numbers in the page table entries based on preset virtual page step sizes; and determining the target physical address corresponding to the target virtual address based on the judging result.

Further, the logic instructions in the memory 730 described above may be implemented in the form of software functional units and may be stored in a computer readable storage medium when sold or used as a stand alone product. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

In another aspect, the present application also provides a computer program product, the computer program product including a computer program, the computer program being storable on a non-transitory computer readable storage medium, the computer program, when executed by a processor, being capable of executing a method of translating a virtual address provided by the methods described above, the method comprising: receiving a physical address conversion request, wherein the physical address conversion request comprises a target virtual page number high-order bit and a target virtual page number low-order bit of a target virtual address to be converted; judging whether the target virtual address is included in a compression block corresponding to each of a plurality of page table entries in a first-level translation lookaside buffer TLB based on the high-order target virtual page number and the low-order target virtual page number; the compression block is obtained by compressing virtual page numbers and corresponding physical page numbers in the page table entries based on preset virtual page step sizes; and determining the target physical address corresponding to the target virtual address based on the judging result.

In yet another aspect, the present application also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform a method of translating virtual addresses provided by the above methods, the method comprising: receiving a physical address conversion request, wherein the physical address conversion request comprises a target virtual page number high-order bit and a target virtual page number low-order bit of a target virtual address to be converted; judging whether the target virtual address is included in a compression block corresponding to each of a plurality of page table entries in a first-level translation lookaside buffer TLB based on the high-order target virtual page number and the low-order target virtual page number; the compression block is obtained by compressing virtual page numbers and corresponding physical page numbers in the page table entries based on preset virtual page step sizes; and determining the target physical address corresponding to the target virtual address based on the judging result.

The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.

From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.

Claims

1. A method for translating a virtual address, comprising:

2. The method of claim 1, wherein determining whether the target virtual address is included in a compressed block corresponding to each of a plurality of page table entries in a first-level translation lookaside buffer TLB based on the target virtual page number high order and the target virtual page number low order comprises:

3. The method of claim 2, wherein the determining whether the target virtual address is included in the target compression block corresponding to the target page table entry based on the target virtual page number low order bits comprises:

4. A method according to claim 2 or 3, wherein determining, based on the determination result, the target physical address corresponding to the target virtual address includes:

5. The method of claim 4, wherein the physical page number in the target compressed block satisfies a physical page step size, and wherein determining the target physical page number corresponding to the target virtual address from the target compressed block comprises:

6. The method of claim 5, wherein the determining the target physical page number from the target compressed block based on the physical page step size and the target virtual address comprises:

7. The method of claim 5, wherein the determining the target physical page number from the target compressed block based on the physical page step size and the target virtual address comprises:

8. A method according to claim 2 or 3, wherein determining, based on the determination result, the target physical address corresponding to the target virtual address includes:

9. The method of claim 8, wherein in the event that the target virtual address is not included in the target compressed block, the method further comprises:

The target compressed block is cached in a first level TLB.

10. The method of claim 9, wherein compressing the virtual page number and the corresponding physical page number in the target page table entry at a predetermined granularity comprises:

and compressing the virtual page number and the corresponding physical page number in the target page table item according to a preset granularity in a path filled by the first-level TLB based on the virtual page number and the corresponding physical page number in the target page table item.

11. The method of claim 9, wherein the caching the target compressed block into the first-level TLB comprises:

or,

12. A virtual address translation apparatus, comprising:

13. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the virtual address translation method according to any one of claims 1 to 11 when executing the program.

14. A non-transitory computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when executed by a processor, implements the virtual address translation method according to any one of claims 1 to 11.