CN117472805B - Virtual IO device memory management system based on virtio - Google Patents
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
- G06F2009/45579—I/O management, e.g. providing access to device drivers or storage
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
- G06F2009/45583—Memory management, e.g. access or allocation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a virtual IO device memory management system based on virtio, which comprises a virtio interface, a control unit and a processing unit, wherein the virtio interface is based on a virtio protocol framework, and a virtio standardized interface is realized; the control unit is used for interacting with the virtio interface to acquire the table item information required by address conversion, and the processing unit is used for analyzing and processing the table item information transmitted by the control unit and executing an address conversion flow. The processing unit comprises a calling logic unit and a hardware acceleration engine unit, wherein the calling logic unit is used for synchronizing a page table in Guest OS to the hardware acceleration engine unit, and the hardware acceleration engine unit is a hardware execution body of an address translation process of a stage2 stage of a physical IOMMU, and when the processing unit executes the address translation process, the hardware acceleration engine unit is called to carry out address translation acceleration.
Description
Technical Field
The application relates to the technical field of virtualization, in particular to a virtual IO device memory management system based on virtio.
Background
With the development of cloud computing, virtualization and other technologies, interaction between a virtualized system and physical IO devices is required to meet the requirements of extremely high speed and low latency, and the overhead of system resources of a Host (Host, i.e., host) is required to be reduced as much as possible.
In the Virtualization system, the way of leading PCIe hardware equipment to an operating system (Guest OS) on a virtual machine is a problem solving thought, the technical foundation is based on an IOMMU and an SR-IOV, the main function of the IOMMU is that equipment DMA can access a physical memory area of the machine at any time, meanwhile, the security is ensured, the DMA refers to direct memory access, the SR-IOV is Single Root I/O Virtualization, and the technology of packaging, managing and even sharing disk I/O equipment network cards of a server like equipment can be allowed by the Windows operating system and a Hypervisor (Hypervisor) of Microsoft or ESxi of VMware company. The microsoft Hyper-V is a virtualization product, the VMware is a computer virtualization software development and sales enterprise, and the ESXi is a virtualization hypervisor architecture.
Meanwhile, in some virtualization scenarios, devices which are directly connected to a virtual machine are transmitted to a user state of Guest OS, user state driving is operated in the user state of Guest OS, for example, DPDK technology is a high-performance network driving component developed by INTEL company, DPDK is used for providing a simple, convenient, complete and quick data packet processing solution for a data plane application program, and the main technology is user state, polling instead interrupt, zero copy, network card RSS, access DirectIO and the like, so that vIOMMU is needed at the moment, wherein vIOMMU refers to virtual IOMMU, and the IOMMU is a computer term and represents input/output memory management unit-input/output memory management unit.
The virtio is an open-source IO interface protocol specification, and the virtio equipment defined by the virtio protocol specification is virtual IO equipment realized by software, so that the hardware acceleration exploration of the virtio equipment based on the virtio protocol specification can solve the problem of the requirement of a computer system on the high-speed and low-delay IO equipment, and can effectively reduce the cost of system resources of a Host. virtio-iommu is a virtual device capable of managing Direct Memory Access (DMA) of one or more device nodes, which can manage both user states of a physical PCIe device through to an operating system (gueastos) on a virtual machine and DMA accesses of a full-virtualized device and a paravirtualized device.
In patent publication No. CN 112612574A, entitled "memory access management unit, system and address translation method for input/output device", a memory access management unit, system and address translation method for input/output device are provided for implementing virtual IOMMU, as shown in fig. 1, where the system includes: a memory access management unit of an input/output device running in an operating system of the virtual machine; the memory access management unit of the input/output device includes: the virtual function execution unit is configured to execute conversion from a virtual address corresponding to a memory access request of an input/output device to a physical address, wherein the input/output device is a device required for realizing the function of an application program running on the virtual machine, and the access request carries the virtual address; and the virtual function control unit is configured to control the virtual function execution unit to complete address conversion. The method mainly adopts a memory management method of simulating physical IOMMU by software to achieve the user mode of transmitting virtual equipment or direct physical equipment to Guest OS. The prior art embodiment improves the security of the application programs running on the virtual operating systems of the virtual machines.
However, this prior art still has many disadvantages, as detailed below:
(1) Dependencies on CPU architecture: the design does not consider the cross-platform performance of the vIOMMU, and the address translation method is different under different CPU architectures, for example, the address translation method is different under an x86 architecture and an ARM aarch64 architecture, and cannot be suitable for the types of virtual machines under different CPU architectures.
(2) The address conversion stage adopts pure software simulation to consume the calculation resources of the Host, and is characterized in that the address conversion stage adopts pure software simulation to calculate the CPU of the Host and consume more memory resources, and particularly the page table searching process consumes serious calculation resources of the CPU.
Disclosure of Invention
The invention provides a virtual IO device memory management system based on virtio, which is used for solving two problems of address conversion of a virtual machine to IO devices: 1) The cross-platform unavailability of the vIOMMU; 2) And the IO equipment performs address conversion stage by adopting pure software simulation, so that the Host computing resource is consumed. The technical scheme is as follows:
the virtual IO device memory management system based on the virtio comprises a virtio interface, a control unit and a processing unit, wherein the virtio interface is a virtio standardized interface realized based on a virtio protocol framework, the control unit is used for interacting with the virtio interface to acquire table item information required by address conversion, and the processing unit is used for analyzing and processing the table item information transmitted by the control unit and executing an address conversion flow.
The processing unit comprises a calling logic unit and a hardware acceleration engine unit, wherein the calling logic unit is used for synchronizing a page table in Guest OS to the hardware acceleration engine unit, and the hardware acceleration engine unit adopts a hardware execution body of a stage2 address translation flow of a Host IOMMU to realize that the processing unit calls the hardware acceleration engine unit to carry out address translation acceleration when executing the address translation flow.
The page table is a table in which MMU or IOMMU records address translation information.
The workflow of the virtual IO device memory management system based on virtio comprises the following steps:
s11: creating a virtual machine, and initializing a virtualized IO device memory management system in Guest OS;
s12: the control unit acquires initialized page table related table item information and sends the page table related table item information to the processing unit;
s13: the calling logic unit in the processing unit sends the page table related table item information to the hardware acceleration engine through a VFIO interface and a hardware acceleration engine driver, wherein the VFIO interface is a virtual machine IO interface;
s14: the hardware acceleration engine acquires the information of the page table related table items needing address translation and prepares the translation task.
The processing unit realizes hardware accelerated address conversion through the hardware acceleration engine unit and comprises the following steps:
s21: the control unit of the virtualized IO device memory management system shares the entry information of the page table required by Guest OS to the call logic unit of the processing unit;
s22: and when the processing unit performs address translation, the hardware acceleration engine unit is called to analyze the page table.
Compared with the prior art, the hardware acceleration engine unit can accelerate the conversion speed of the equipment and reduce the consumption of CPU computing resources of a physical computer system by providing a standardized virtio interface and enabling the system to be better suitable for the virtualization technology ecology based on the virtio protocol specification.
Drawings
FIG. 1 is a virtualized platform system based on an x86 hardware platform;
FIG. 2 is a schematic diagram of the architecture of the virtual IO device memory management system;
FIG. 3 is a schematic diagram of address translation of a processing unit implementing hardware acceleration by a hardware acceleration engine unit;
FIG. 4 is a schematic diagram of the hardware accelerated address translation flow.
Detailed Description
The memory of a computer system is organized into an array of M consecutive bytes, each byte having a unique physical address, and the simplest way for a CPU to access the memory is to use the physical address. In the existing virtual addressing method, a Virtual Address (VA) is generated by a CPU, then the virtual address is translated into an actual physical address by an MMU (Memory Management Unit memory management unit), and then the physical addressing is performed, and the process is HVA-MMU-HPA, where HVA refers to a host virtual address, and HPA refers to a host physical address. For a device, the address it accesses is called an IOVA (IO virtual address), and the device's access to a physical address needs to go through an IOMMU, a process called IOVA-IOMMU-HPA.
And installing a Virtual Machine (VM) on the Host machine, wherein the VM is a client machine, and the VM is provided with a virtual physical address (GPA) corresponding to the VM, and an operating system (Guest OS) on the corresponding installed VM adopts a virtual addressing method when running. For a virtual machine device on a virtual machine, its access address is called gIOVA (IO virtual address of the virtual machine), and the virtual machine device access to the virtual physical address needs to pass through a vIOMMU, which is a gIOVA-vIOMMU-HPA.
When the virtualized address translation research is carried out, the virtual machine provided by the prior art does not consider cross-CPU platforms, is not suitable for all CPU architectures, and does not plan the software ecology of the IO interface, namely, different IOMMU solutions exist under different CPU architectures. Further, when the device research of the virtio specification is performed, the device based on the virtio specification has no dependency on the CPU architecture. Therefore, through researching the virtio and adopting a unified scheme to plan the device and the software for thinking design, the virtio and the address conversion method are combined to form the virtio-iommu device, so that the dependence of the address conversion device on a CPU architecture is eliminated, the standardized io interface specification of the virtio is inherited, and the virtio-iommu device is suitable for the rich software ecology of the virtio.
When the invention is used for researching the virtual equipment for address conversion, the virtual equipment in the prior art is simulated by pure software, and the CPU calculation and the memory resource consumption of the Host are relatively high. Further, in performing physical device research of address translation, it was found that the physical device of address translation supports two stages of address translation of stage1 and stage2, where stage1 is used for translation of IOVA- > HPA (IO virtual address to host physical address), stage2 is used for translation of GPA- > HPA (client physical address to host physical address), and stage2 can be used for a through device in a virtualized system.
Through research on a virtualization system, it is found that the physical device for address translation and the virtual device for address translation can be combined, that is, the address translation flow of stage1 of the physical device for address translation is implemented as the back end of the virtual device for address translation (virtual IOMMU device, for example, virtual IO-IOMMU) to achieve the effect of hardware acceleration on the virtual IO memory management system for address translation, where the virtual IO-IOMMU is a virtual IOMMU device for software simulation conforming to the virtual IO protocol specification.
Based on the above, as shown in fig. 2, the present invention provides a virtual IO device memory management system based on virtio, including: the device comprises a virtio interface, a control unit and a processing unit, wherein the virtio interface is based on a virtio protocol framework and realizes a virtio standardized interface; the control unit is used for interacting with the virtio interface to acquire the table item information required by address conversion, and the processing unit is used for analyzing and processing the table item information transmitted by the control unit and executing an address conversion flow.
The control unit obtains entry information required for address translation, wherein the address translation is related to an application scenario, for example, if a vIOMMU is used for user mode driving of a virtual machine, the address translation is translation of gIOVA- > GPA; if used in nested virtualization, that address translation is a translation of gGPA (nested client physical address) - > GPA, as a vIOMMU, does not declare what scenario itself is used in, as the invention can be applied to all scenarios where vIOMMU is applicable.
The processing unit comprises a calling logic unit and a hardware acceleration engine unit, wherein the calling logic unit is used for synchronizing a page table in Guest OS to the hardware acceleration engine unit, and the hardware acceleration engine unit can adopt a hardware execution main body of a stage2 address translation flow of a Host IOMMU to realize that the processing unit calls the hardware acceleration engine unit to carry out address translation acceleration when executing the address translation flow. The page table is a table in which MMU or IOMMU records address translation information.
Through the virtual IO device memory management system based on the virtio, the address conversion between an operating system (Guest OS) on a virtual machine and a hardware IO device is realized. The virtual IO device memory management system workflow based on virtio comprises the following steps:
s11: creating a virtual machine, and initializing a virtualized IO device memory management system in Guest OS;
s12: the control unit acquires initialized page table related table item information and sends the page table related table item information to the processing unit;
s13: the calling logic unit in the processing unit sends the page table related table item information to the hardware acceleration engine through a VFIO interface and a hardware acceleration engine driver, wherein the VFIO interface is a virtual machine IO interface;
s14: the hardware acceleration engine acquires the information of the page table related table items needing address translation and prepares the translation task.
As shown in connection with FIG. 3, a plurality of virtual machines, including VM0-VMn, are installed on the Host through emulation processor software (QEMU) and run on the Host through QEMU processes. An application software APP is installed on the virtual machine. When an operating system (Guest OS) on a virtual machine needs to access the IO device of a physical hardware system, the virtualized IO device memory management system provided by the invention can be realized. The processing unit realizes the address conversion of hardware acceleration through the hardware acceleration engine unit, and comprises the following steps:
s21: the control unit of the virtualized IO device memory management system shares the entry information of the page table required by Guest OS to the call logic unit of the processing unit;
s22: and when the processing unit performs address translation, the hardware acceleration engine unit is called to analyze the page table. Wherein the hardware acceleration engine unit may be invoked by multiple virtual machine systems.
In the embodiment, taking a scenario that the physical IO device is directly connected to the virtual machine and the physical IO device is directly transferred to a user state of the gueastos, and the gueastos runs a user state driver (for example, DPDK) as an example, as shown in a hardware accelerated address translation flow shown in fig. 4:
s21: creating and starting a virtual machine;
s22: a user state driver in Guest OS applies for a memory space through a VFIO interface to obtain a virtual IO address gIOVA of a virtual machine, and configures a virtual IO device memory management system to establish gIOVA-GPA mapping;
s23: configuring the gIOVA to a DMA related register of a virtual IO device instantiated by a Hypervisor (QEMU is a Hypervisor) through a VFIO interface;
because the scene is that the physical IO device is directly connected to the virtual machine, the register of the virtual IO device instantiated in the Hypervisor is the same as the physical IO device, and therefore the virtual IO device instantiated in the Hypervisor has the same DMA related register in combination with the physical IO device.
S24: the virtual IO device memory management system presents a virtual interface to the outside, the inside of the virtual IO device memory management system is connected with a control unit of the virtual IO device memory management system, and gIOVA- > GPA mapping information is shared to a hardware acceleration engine unit through a hardware acceleration engine driver;
s25: the virtualized IO device memory management system initiates the address conversion from gIOVA to GPA, and a processing unit of the virtualized IO device memory management system calls a hardware acceleration engine unit to convert gIOVA-GPA in stage 1;
s26: the virtual IO device configures the converted GPA to a DMA of the physical IO device, and configures an IO device memory management unit (IOMMU) to establish GPA-HPA mapping;
s27: DMA of the physical IO device initiates address access of the GPA;
s28: and the memory management unit of the physical IO equipment performs conversion of GPA- > HPA in stage2 to obtain the HPA. Because any virtual address is ultimately translated to the memory address of the physical host, the actual data is accessed.
The mapping relation of the left virtual frame gIOVA-GPA-HPA plays a role in prompting a right system.
In the present invention, abbreviations and key terms are defined as follows:
virtio: virtio is an I/O paravirtualized solution, is a set of general purpose I/O device virtualized programs, and is an abstraction of a set of general purpose I/O devices in paravirtualized hypervisors.
IO device: input/Output (I/O) devices in a computer system.
Host: host computers, commonly defined in a centralized computer model as large time-sharing computer systems, are also referred to in virtualization technology as hosts.
Guest: in contrast to the physical Host, i.e., the guest, the application in virtualization technology is a virtual machine.
GuestOS: in virtualization technology, an operating system runs on a virtual machine.
VM: virtual Machine.
SR-IOV: the SR-IOV (Single Root I/O Virtualization) technology is a Virtualization solution based on hardware, and can improve performance and scalability. The SR-IOV standard allows PCIe (PeripheralComponent Interconnect Express ) devices to be shared efficiently between virtual machines, and it is implemented in hardware, achieving I/O performance comparable to native performance.
VT-d: intel Virtualization Technology for Directed I/O (VT-d), virtualization technology of I/O.
IOMMU: input/Output Memory Management Unit, IO device memory management unit.
virtio-iommu: a virtual IOMMU device that conforms to software emulation of the virtio protocol specification.
DMA: direct Memory Access, direct memory access, direct access to hardware device resources via DMA controllers, without the involvement of a CPU.
DPDK: data Plane Development Kit, the data plane development suite is mainly operated based on a Linux system, and is used for a function library and a driving set for rapid data packet processing, so that the data processing performance and throughput can be greatly improved, and the working efficiency of a data plane application program can be improved.
x86: a processor architecture.
ARM: the uk ARM company is a globally leading semiconductor Intellectual Property (IP) provider.
aarch64: the ARM company pushes out a reduced instruction set processor shelf.
GVA: guest Virtual Address, guest virtual addresses.
GPA: guest Physical Address, client physical address.
HPA: host Physical Address, host physical address.
Linux: linux, which is called GNU/Linux in full, is a free-to-use and freely-spread UNIX-like operating system.
A client: guests, for hosts, are virtual machines created on physical hosts, referred to as clients.
Host machine: host, for a client, is the physical Host where the virtual machine is located.
IOVA: IO Virtual Address, which refers to IO virtual addresses.
Through research on a virtualization system, the invention can combine physical equipment for address translation with virtual equipment for address translation, namely, the address translation flow of stage1 of the physical equipment for address translation is realized as the back end of virtual equipment (virtual IOMMU equipment, such as virtual IO-IOMMU) for address translation, so as to achieve the effect of hardware acceleration of the virtual IO memory management system for address translation, wherein the virtual IO-IOMMU is virtual IOMMU equipment which accords with software simulation of the virtual IO protocol specification.
Claims (4)
1. A virtual IO device memory management system based on virtio is characterized in that: the device comprises a virtio interface, a control unit and a processing unit, wherein the virtio interface is a virtio standardized interface realized based on a virtio protocol framework, the control unit is used for interacting with the virtio interface to acquire item information required by address conversion, and the processing unit is used for analyzing and processing the item information transmitted by the control unit and executing an address conversion flow; the address conversion process of the stage1 of the physical equipment for address conversion is realized as the rear end of the virtual equipment for address conversion by combining the physical equipment for address conversion with the virtual equipment for address conversion, so that hardware acceleration is carried out on a virtual IO memory management system for address conversion, and the dependence of the address conversion equipment on a CPU architecture is eliminated; the processing unit comprises a calling logic unit and a hardware acceleration engine unit, wherein the calling logic unit is used for synchronizing a page table in Guest OS to the hardware acceleration engine unit, and the hardware acceleration engine unit adopts a hardware execution main body of a stage2 address translation flow of a Host IOMMU to realize that the processing unit calls the hardware acceleration engine unit to carry out address translation acceleration when executing the address translation flow; the virtual IO device memory management system workflow based on virtio comprises the following steps:
s21: creating and starting a virtual machine;
s22: a user state driver in Guest OS applies for a memory space through a VFIO interface to obtain a virtual IO address gIOVA of a virtual machine, and configures a virtual IO device memory management system to establish gIOVA-GPA mapping;
s23: configuring the gIOVA to a DMA related register of the virtual IO device instantiated by the Hypervisor through a VFIO interface;
s24: the virtual IO device memory management system presents a virtual interface to the outside, the inside of the virtual IO device memory management system is connected with a control unit of the virtual IO device memory management system, and gIOVA- > GPA mapping information is shared to a hardware acceleration engine unit through a hardware acceleration engine driver;
s25: the virtualized IO device memory management system initiates the address conversion from gIOVA to GPA, and a processing unit of the virtualized IO device memory management system calls a hardware acceleration engine unit to convert gIOVA-GPA in stage 1;
s26: the virtual IO device configures the converted GPA to a DMA of the physical IO device, and configures an IO device memory management unit to establish GPA-HPA mapping;
s27: DMA of the physical IO device initiates address access of the GPA;
s28: and the memory management unit of the physical IO equipment performs conversion of GPA- > HPA in stage2 to obtain the HPA.
2. The virtual IO device memory management system of claim 1 wherein: the page table is a table in which MMU or IOMMU records address translation information.
3. The virtual IO device memory management system of claim 1 wherein: the workflow of the virtual IO device memory management system based on virtio comprises the following steps:
s11: creating a virtual machine, and initializing a virtualized IO device memory management system in Guest OS;
s12: the control unit acquires initialized page table related table item information and sends the page table related table item information to the processing unit;
s13: the calling logic unit in the processing unit sends the page table related table item information to the hardware acceleration engine through a VFIO interface and a hardware acceleration engine driver, wherein the VFIO interface is a virtual machine IO interface;
s14: the hardware acceleration engine acquires the information of the page table related table items needing address translation and prepares the translation task.
4. The virtual IO device memory management system of claim 1 wherein: the processing unit realizes hardware accelerated address conversion through the hardware acceleration engine unit and comprises the following steps:
the control unit of the virtualized IO device memory management system shares the entry information of the page table required by Guest OS to the call logic unit of the processing unit;
and when the processing unit performs address translation, the hardware acceleration engine unit is called to analyze the page table.
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