CN117472035B - Verification method for software and hardware of main control system - Google Patents
Verification method for software and hardware of main control system Download PDFInfo
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
- G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
- G05B23/0218—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults
- G05B23/0221—Preprocessing measurements, e.g. data collection rate adjustment; Standardization of measurements; Time series or signal analysis, e.g. frequency analysis or wavelets; Trustworthiness of measurements; Indexes therefor; Measurements using easily measured parameters to estimate parameters difficult to measure; Virtual sensor creation; De-noising; Sensor fusion; Unconventional preprocessing inherently present in specific fault detection methods like PCA-based methods
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Abstract
The invention discloses a verification method of software and hardware of a main control system, and belongs to the technical field of wind turbines, wherein the method reads an identification code of the hardware through the software of the main control system; the acquired identification codes are converted into unified identification codes of the whole hardware system, an identification file for software verification is generated by acquiring server database information, the unified identification codes are acquired and combined for verification through a main control system, and the matching effectiveness between software and hardware is verified through verification; according to the verification method of the software and hardware of the main control system, on the concrete principle design, the main control system is adopted to generate the identification code which can be identified by the server, the identification code is processed by the server to generate the identification file, and the encryption function is realized by further processing the identification file and verifying the identification code with the original identification code in the main control system.
Description
Technical Field
The invention relates to a verification method for software and hardware of a main control system, and belongs to the technical field of wind turbines.
Background
The fan main control system is a core control system of the wind generating set, and the reliability of the fan main control system directly influences indexes such as safety, running stability and reliability of the set. The main control system consists of a set of control system hardware and control software, and because of certain difference between different hardware, the reliability of the main control system is directly affected by the matching of the software and the hardware, and therefore, the matching relationship between the software and the hardware is required to be identified and checked during the design of the control system so as to ensure the reliable operation of the whole system.
Disclosure of Invention
The invention aims at: aiming at the problems, a method for checking the hardware of the main control system is provided, and when the method passes the checking, the main control system software can normally enter an initialization flow to start operation; when the verification fails, the main control system software cannot enter the initialization flow, and the safety of the unit is effectively ensured.
The technical scheme adopted by the invention is as follows:
a method for verifying software and hardware of a main control system comprises the following steps of;
s1, reading an identification code of hardware through software of a main control system;
s2, converting the acquired identification code into a unified identification code of the whole hardware system;
s3, after the server database information obtains the unified identification code, an identification file for software verification is generated;
s4, the master control system acquires the identification file and performs verification by combining the unified identification code, and the matching effectiveness between the software and the hardware is verified through verification.
Further, in step S2, the method further includes the following steps:
s21, reading a serial number a1 of the controller module through software;
s22, reading serial numbers of other hardware modules one by one through software, wherein the serial numbers are a2, a3, … and an; wherein a1, a2, a3, …, an is n1 character strings of specific length;
s23, combining all serial numbers into a character string A representing hardware configuration by a specific character string splicing method f1, specifically, A=f1 (a 1, a2, a3, …, an);
s24, converting the acquired character string A into m integer value arrays, wherein each array comprises n2 byte integer values which are respectively B1, B2, … and Bm;
s25, converting the obtained m integer value arrays into m integer values, respectively obtaining C1, C2, … and Cm, and combining the integer values C1, C2, … and Cm into a unified identification code D.
Further, in step S25, the specific algorithm for converting the acquired m number of arrays into m integer values further includes the following steps:
s251, reading integer value array element B1 with the length of n2 bytes;
s252, calculating an intermediate integer value X, Y, Z through the obtained integer array B1 of n2 bytes;
the specific calculation mode is as follows:
X=(∑B[i])%a；
Y=(∏((B[i]*B[i])>>b))%c；
Z=Ω(B[i]<<d)；
s253, obtaining integer value C1 through the obtained intermediate integer value X, Y, Z;
the specific calculation mode is as follows:
C1=X&&e+Y&&f+Z&&g；
wherein a, b, c, d, e, f, g are specific integer values set; the & & is binary bitwise AND; % is the remainder; > is binary right shift; < is binary shift left; Σ is a summation item by item (1 < =i < =n2); pi is a product term by term (1 < =i < =n2); omega is the itemized exclusive or (1 < =i < =n2); bi is the value of the i-th element in the fetch group B;
s254, reading B2 and calculating C2 according to the steps from S251 to S253, and calculating Cm one by one until Cm is obtained.
Further, the step S3 further includes the following steps:
s31, reading a unified identification code D of an integer numerical array with the length m generated by a main control system;
s32, converting the unified identification code into an identification file code E of an integer numerical array with the length of t, wherein t is more than m;
s33, writing the identification file code E into the identification file.
Further, in step S4, the method further includes the following steps:
s41, the main control system reads the identification file to obtain an identification file code E;
s42, converting the identification file code E into a check code F of an integer numerical array with the length of m;
s43, reading the unified identification code D, comparing whether the check code F is consistent with the unified identification code D, if so, checking to pass, and if not, checking to fail.
Further, in step S32, the conversion process is implemented by an algorithm Q, where the algorithm Q is specifically: e=q (D, M, N);
in step S42, the conversion process is implemented by an algorithm Q, where the algorithm Q is specifically: f=q (E, P, N);
wherein N, M and P are integer arrays of values of length t;
the algorithm Q comprises the steps of:
d1, reading integer value array G, and supplementing integer value elements with 0 when the length of G is m, so that the length of G is t, wherein t is more than m;
d2, reading integer value arrays H, J, wherein the lengths of the integer value arrays H, J are t;
d3, reading integer value arrays K, wherein K is equal to E or F, and enabling the integer value arrays K to be equal to a set specific integer value array h;
and D4, sequentially obtaining the integer value arrays H after calculation, comparing the set specific integer value arrays p through the H, obtaining the integer value arrays K if the comparison results are the same, and repeating calculation if the comparison results are different.
Further, in step D4, the calculation method is specifically as follows:
L=(H&&x)%y；
K=Q1（Q2（K,G）,H）；
G=Q1（Q2（G,G）,J）；
H=Q3（Q4（H,L）,z）；
wherein h, x, y, z, p are a specific integer value array;
g, H, J, K, L are integer arrays of values of length t;
q1, Q2, Q3, Q4 are sub-algorithms;
the & & is binary bitwise AND;
% is the remainder.
Further, the sub-algorithm Q1 includes the following steps:
d11, reading integer value arrays X1, Y1, the lengths of which are t, wherein x1=q2 (K, G) or Q2 (G, G), corresponding y1=h or J;
d12, let i1=t, and perform the following calculation in order:
b1=(X1[i1]/Y1[i1])-c1；
X1=X1-Y1*b1;
Z1=Z1+b1;
X1=Q4(X1,Q2(Y1,Y1));
Z1=Z1+(X1⊕(Y1,c1))*c1;
wherein b1, c1 are specific integer values;
x1, Y1 and Z1 are integer numerical arrays with the length of t;
one is binary bitwise exclusive OR;
and D13, judging whether i1 is greater than 1 and smaller than or equal to 1, acquiring the integer value array X1 calculated in the step D12, and if so, repeating the calculation in the step D12 with i1-1 in sequence.
Further, the sub-algorithm Q2 includes the following steps:
d21, reading integer value arrays X2, Y2, the lengths of which are t, wherein x2=k or G, and corresponding y2=g;
d22, let i2=1, j2=1, d1=0, and sequentially perform the following calculations:
Z2[i2+j2-b2]=(Z2[i2+j2-b2]+X2[i2]*Y2[j2]+d1)%e1;
d1=(Z2[i2+j2]+(X2[i2]*Y2[j2])/e1)%e1;
Z2[i2+j2]=Z2[i2+j2]+(X2[i2]*Y2[j2])/e1-d1;
b2 D1, e1 is a specific integer number;
x2, Y2 and Z2 are integer numerical arrays with the length of t;
% is the remainder;
d23, judging whether j2 is greater than or equal to t, if so, repeating the calculation of the step D22 with j2+ 1; if the value is greater than or equal to t, executing the judgment of i 2;
d24, determining whether i2 is greater than or equal to t, if less than t, repeating steps D22 and D23 with i2+1 and j2=1; if t is greater than or equal to t, the integer value array Z2 calculated in the step D22 is obtained.
Further, the sub-algorithm Q3 includes the following steps:
d31, reading integer value arrays X3, Y3, the lengths of which are t, wherein x3=q4 (H, L), corresponding y3=z;
d32, let i3=t, and perform the following calculation in order:
b3=(X3[i3]/Y3[i3])-d2;
X3=X3-Y3*b3;
Z3=Z3+b3;
X3=Q4（X3,Q2（Y3,d2））;
Z3=Z3+(X3⊕(Y3,d2))*d2;
b3 and d2 are specific integer values;
x3, Y3 and Z3 are integer numerical arrays with the length of t;
d33, judging whether i3 is larger than 1, if i3 is larger than 1, repeating the step D32 with i-1; if i3 is less than or equal to 1, the integer value array Z3 calculated in step D32 is obtained.
Further, the sub-algorithm Q4 includes the following steps:
d41, reading integer value arrays X4, Y4, the lengths of which are t, wherein x4=h, and corresponding y4=l;
d42, let i4=1, d3=0, and perform the following calculation in order:
d3=((X4[i4]+b4-Y4[i4])-d3)>>e2;
Z4[i4]=(X4[i4]+b4-Y4[i4]-d3)%g1;
b4, d3, e2, g1 are specific integer values;
x4, Y4 and Z4 are integer numerical arrays with the length of t;
% is the remainder;
> is binary right shift;
d43, judging whether i4 is greater than or equal to t, if i4 is greater than or equal to t, obtaining integer value array Z4 calculated in step D42; if i4 is less than t, repeat step D42 with i4+1.
In summary, due to the adoption of the technical scheme, the beneficial effects of the invention are as follows:
according to the verification method of the software and hardware of the main control system, the main control system is adopted to generate the identification code which can be identified by the server, the server is used for processing the identification code to generate the identification file, the identification file is further processed in the main control system and verified with the original identification code, and the encryption function is realized.
Drawings
The invention will now be described by way of example and with reference to the accompanying drawings in which:
FIG. 1 is a schematic flow chart of the present invention;
FIG. 2 is a flow chart of a master control system generating a unified identification code;
FIG. 3 is a schematic algorithm flow chart of step S25;
FIG. 4 is a schematic flow chart of a server generating an identification file;
FIG. 5 is a schematic diagram of a flow of master control system verification;
FIG. 6 is a flow chart of algorithm Q;
FIG. 7 is a flow chart of algorithm Q1;
FIG. 8 is a flow chart of algorithm Q2;
FIG. 9 is a flow chart of algorithm Q3;
fig. 10 is a flow chart of algorithm Q4.
Detailed Description
All of the features disclosed in this specification, or all of the steps in a method or process disclosed, may be combined in any combination, except for mutually exclusive features and/or steps.
Any feature disclosed in this specification may be replaced by alternative features serving the same or equivalent purpose, unless expressly stated otherwise. That is, each feature is one example only of a generic series of equivalent or similar features, unless expressly stated otherwise.
Examples
The verification method of the software and hardware of the main control system, as shown in figures 1 to 10, comprises the following steps of;
s1, reading an identification code of hardware through software of a main control system;
s2, converting the acquired identification code into a unified identification code of the whole hardware system;
s3, after the server database information obtains the unified identification code, an identification file for software verification is generated;
s4, the master control system acquires the identification file and performs verification by combining the unified identification code, and the matching effectiveness between the software and the hardware is verified through verification.
In this embodiment, unlike the conventional encryption method, the method has the advantages that the master control system is adopted to generate the unified identification code, the server is used for acquiring the unified identification code, the data is processed and then the unified identification code is regenerated to obtain the identification file, the identification file is acquired by the master control system again to be identified, the comparison and verification are performed on the identification file and the original unified identification code, and the encryption of the master control system is realized after the comparison and verification.
As a more specific design, in the above specific step design, in step S2, the following steps are further included:
s21, reading a serial number a1 of the controller module through software;
s22, reading serial numbers of other hardware modules one by one through software, wherein the serial numbers are a2, a3, … and an; wherein a1, a2, a3, …, an is n1 character strings of specific length;
s23, combining all serial numbers into a character string A representing hardware configuration by a specific character string splicing method f1, specifically, A=f1 (a 1, a2, a3, …, an);
s24, converting the acquired character string A into m integer value arrays, wherein each array comprises n2 byte integer values which are respectively B1, B2, … and Bm;
s25, converting the obtained m integer value arrays into m integer values, respectively obtaining C1, C2, … and Cm, and combining the integer values C1, C2, … and Cm into a unified identification code D.
In the above specific operation manner, the main purpose is to convert the array into a new number and combine the new numbers into a new combination to form a unified identification code, where D is also m integer number arrays.
On the basis of the above specific design, as a more specific design, the specific algorithm for converting the acquired m number sets into m integer values in step S25 further includes the steps of:
s251, reading integer value array element B1 with the length of n2 bytes;
s252, calculating an intermediate integer value X, Y, Z through the obtained integer array B1 of n2 bytes;
the specific calculation mode is as follows:
X=(∑B[i])%a；
Y=(∏((B[i]*B[i])>>b))%c；
Z=Ω(B[i]<<d)；
s253, obtaining integer value C1 through the obtained intermediate integer value X, Y, Z;
the specific calculation mode is as follows:
C1=X&&e+Y&&f+Z&&g；
wherein a, b, c, d, e, f, g are specific integer values set; the & & is binary bitwise AND; % is the remainder; > is binary right shift; < is binary shift left; Σ is a summation item by item (1 < =i < =n2); pi is a product term by term (1 < =i < =n2); omega is the itemized exclusive or (1 < =i < =n2); bi is the value of the i-th element in the fetch group B;
s254, reading B2 and calculating C2 according to the steps from S251 to S253, and calculating Cm one by one until Cm is obtained.
Based on the specific design, the calculation of the unified identification code D is completed, and further the operation and the operation of the unified identification code D in the server are further designed, and the step S3 further comprises the following steps:
s31, reading a unified identification code D of an integer numerical array with the length m generated by a main control system;
s32, converting the unified identification code into an identification file code E of an integer numerical array with the length of t, wherein t is more than m;
s33, writing the identification file code E into the identification file.
Further, after the identification file is obtained, the identification file is obtained through the main control system, and is compared with the unified identification code through calculation, so that a verification result is obtained, and in particular, in the step S4, the method further comprises the following steps:
s41, the main control system reads the identification file to obtain an identification file code E;
s42, converting the identification file code E into a check code F of an integer numerical array with the length of m;
s43, reading the unified identification code D, comparing whether the check code F is consistent with the unified identification code D, if so, checking to pass, and if not, checking to fail.
In the above specific design, the process of converting the unified identification code D into the identification file and then into the check code F is further optimized, specifically, in step S32, the conversion process is implemented by an algorithm Q, where the algorithm Q specifically is: e=q (D, M, N);
in step S42, the conversion process is implemented by an algorithm Q, where the algorithm Q is specifically: f=q (E, P, N);
wherein N, M and P are integer arrays of values of length t, where t > m;
in particular, the algorithm Q comprises the following steps:
d1, reading integer value array G, and supplementing integer value elements with 0 when the length of G is m, so that the length of G is t, wherein t is more than m;
d2, reading integer value arrays H, J, wherein the lengths of the integer value arrays H, J are t;
d3, reading integer value arrays K, wherein K is equal to E or F, and enabling the integer value arrays K to be equal to a set specific integer value array h;
and D4, sequentially obtaining the integer value arrays H after calculation, comparing the set specific integer value arrays p through the H, obtaining the integer value arrays K if the comparison results are the same, and repeating calculation if the comparison results are different.
In step D4, the calculation method is specifically as follows:
L=(H&&x)%y；
K=Q1（Q2（K,G）,H）；
G=Q1（Q2（G,G）,J）；
H=Q3（Q4（H,L）,z）；
wherein h, x, y, z, p are a specific integer value array;
g, H, J, K, L are integer arrays of values of length t;
q1, Q2, Q3, Q4 are sub-algorithms;
the & & is binary bitwise AND;
% is the remainder.
For the above algorithm, further designs are respectively aimed at the algorithms Q1, Q2, Q3 and Q4, wherein the sub-algorithm Q1 comprises the following steps:
d11, reading integer value arrays X1, Y1, the lengths of which are t, wherein x1=q2 (K, G) or Q2 (G, G), corresponding y1=h or J;
d12, let i1=t, and perform the following calculation in order:
b1=(X1[i1]/Y1[i1])-c1；
X1=X1-Y1*b1;
Z1=Z1+b1;
X1=Q4(X1,Q2(Y1,Y1));
Z1=Z1+(X1⊕(Y1,c1))*c1;
wherein b1, c1 are specific integer values;
x1, Y1 and Z1 are integer numerical arrays with the length of t;
one is binary bitwise exclusive OR;
and D13, judging whether i1 is greater than 1 and smaller than or equal to 1, acquiring the integer value array X1 calculated in the step D12, and if so, repeating the calculation in the step D12 with i1-1 in sequence.
The sub-algorithm Q2 includes the steps of:
d21, reading integer value arrays X2, Y2, the lengths of which are t, wherein x2=k or G, and corresponding y2=g;
d22, let i2=1, j2=1, d1=0, and sequentially perform the following calculations:
Z2[i2+j2-b2]=(Z2[i2+j2-b2]+X2[i2]*Y2[j2]+d1)%e1;
d1=(Z2[i2+j2]+(X2[i2]*Y2[j2])/e1)%e1;
Z2[i2+j2]=Z2[i2+j2]+(X2[i2]*Y2[j2])/e1-d1;
b2 D1, e1 is a specific integer number;
x2, Y2 and Z2 are integer numerical arrays with the length of t;
% is the remainder;
d23, judging whether j2 is greater than or equal to t, if so, repeating the calculation of the step D22 with j2+ 1; if the value is greater than or equal to t, executing the judgment of i 2;
d24, determining whether i2 is greater than or equal to t, if less than t, repeating steps D22 and D23 with i2+1 and j2=1; if t is greater than or equal to t, the integer value array Z2 calculated in the step D22 is obtained.
The sub-algorithm Q3 includes the following steps:
d31, reading integer value arrays X3, Y3, the lengths of which are t, wherein x3=q4 (H, L), corresponding y3=z;
d32, let i3=t, and perform the following calculation in order:
b3=(X3[i3]/Y3[i3])-d2;
X3=X3-Y3*b3;
Z3=Z3+b3;
X3=Q4（X3,Q2（Y3,d2））;
Z3=Z3+(X3⊕(Y3,d2))*d2;
b3 and d2 are specific integer values;
x3, Y3 and Z3 are integer numerical arrays with the length of t;
d33, judging whether i3 is larger than 1, if i3 is larger than 1, repeating the step D32 with i-1; if i3 is less than or equal to 1, the integer value array Z3 calculated in step D32 is obtained.
The sub-algorithm Q4 includes the steps of:
d41, reading integer value arrays X4, Y4, the lengths of which are t, wherein x4=h, and corresponding y4=l;
d42, let i4=1, d3=0, and perform the following calculation in order:
d3=((X4[i4]+b4-Y4[i4])-d3)>>e2;
Z4[i4]=(X4[i4]+b4-Y4[i4]-d3)%g1;
b4, d3, e2, g1 are specific integer values;
x4, Y4 and Z4 are integer numerical arrays with the length of t;
% is the remainder;
> is binary right shift;
d43, judging whether i4 is greater than or equal to t, if i4 is greater than or equal to t, obtaining integer value array Z4 calculated in step D42; if i4 is less than t, repeat step D42 with i4+1.
According to the verification method of the software and hardware of the main control system, the main control system is adopted to generate the identification code which can be identified by the server, the server is used for processing the identification code to generate the identification file, the identification file is further processed in the main control system and verified with the original identification code, and the encryption function is realized.
The invention is not limited to the specific embodiments described above. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification, as well as to any novel one, or any novel combination, of the steps of the method or process disclosed.
Claims (3)
1. A method for checking software and hardware of a main control system is characterized by comprising the following steps: comprises the following steps of;
s1, reading an identification code of hardware through software of a main control system;
s2, converting the acquired identification code into a unified identification code of the whole hardware system;
in step S2, the method further comprises the steps of:
s21, reading a serial number a1 of the controller module through software;
s22, reading serial numbers of other hardware modules one by one through software, wherein the serial numbers are a2, a3, … and an; wherein a1, a2, a3, …, an is n1 character strings of specific length;
s23, combining all serial numbers into a character string A representing hardware configuration by a specific character string splicing method f1, specifically, A=f1 (a 1, a2, a3, …, an);
s24, converting the acquired character string A into m integer value arrays, wherein each array comprises n2 byte integer values which are respectively B1, B2, … and Bm;
s25, converting the obtained m integer value arrays into m integer values, respectively obtaining C1, C2, … and Cm, and combining the integer values C1, C2, … and Cm into a unified identification code D;
s3, after the server database information obtains the unified identification code, an identification file for software verification is generated;
step S3 further comprises the steps of:
s31, reading a unified identification code D of an integer numerical array with the length m generated by a main control system;
s32, converting the unified identification code into an identification file code E of an integer numerical array with the length of t, wherein t is more than m;
s33, writing the identification file code E into the identification file;
s4, the main control system acquires the identification file, verifies the identification code uniformly, and verifies the matching effectiveness between the software and the hardware through verification;
in step S32, the conversion process is implemented by an algorithm Q, where the algorithm Q is specifically: e=q (D, M, N);
in step S4, the identification file code E is converted into the check code F by the algorithm Q, which specifically is: f=q (E, P, N);
wherein N, M and P are integer arrays of values of length t;
the algorithm Q comprises the steps of:
d1, reading integer value array G, and supplementing integer value elements with 0 when the length of G is m, so that the length of G is t, wherein t is more than m;
d2, reading integer value arrays H, J, wherein the lengths of the integer value arrays H, J are t;
d3, reading integer value arrays K, wherein K is equal to E or F, and enabling the integer value arrays K to be equal to a set specific integer value array h;
d4, sequentially obtaining the integer value arrays H after calculation, comparing the set specific integer value arrays p through the H, obtaining integer value arrays K if the comparison results are the same, and repeating calculation if the comparison results are different;
in step D4, the calculation method is specifically as follows:
L=(H&&x)%y；
K=Q1（Q2（K,G）,H）；
G=Q1（Q2（G,G）,J）；
H=Q3（Q4（H,L）,z）；
wherein h, x, y, z, p are a specific integer value array;
g, H, J, K, L are integer arrays of values of length t;
q1, Q2, Q3, Q4 are sub-algorithms;
the & & is binary bitwise AND;
% is the remainder;
the sub-algorithm Q1 includes the following steps:
d11, reading integer value arrays X1, Y1, the lengths of which are t, wherein x1=q2 (K, G) or Q2 (G, G), corresponding y1=h or J;
d12, let i1=t, and perform the following calculation in order:
b1=(X1[i1]/Y1[i1])-c1；
X1=X1-Y1*b1;
Z1=Z1+b1;
X1=Q4(X1,Q2(Y1,Y1));
Z1=Z1+(X1⊕(Y1,c1))*c1;
wherein b1, c1 are specific integer values;
x1, Y1 and Z1 are integer numerical arrays with the length of t;
one is binary bitwise exclusive OR;
d13, judging whether i1 is greater than 1 and smaller than or equal to 1, acquiring the integer numerical array X1 calculated in the step D12, and if so, repeating the calculation in the step D12 with i1-1 in sequence;
the sub-algorithm Q2 includes the steps of:
d21, reading integer value arrays X2, Y2, the lengths of which are t, wherein x2=k or G, and corresponding y2=g;
d22, let i2=1, j2=1, d1=0, and sequentially perform the following calculations:
Z2[i2+j2-b2]=(Z2[i2+j2-b2]+X2[i2]*Y2[j2]+d1)%e1;
d1=(Z2[i2+j2]+(X2[i2]*Y2[j2])/e1)%e1;
Z2[i2+j2]=Z2[i2+j2]+(X2[i2]*Y2[j2])/e1-d1;
b2 D1, e1 is a specific integer number;
x2, Y2 and Z2 are integer numerical arrays with the length of t;
% is the remainder;
d23, judging whether j2 is greater than or equal to t, if so, repeating the calculation of the step D22 with j2+ 1; if the value is greater than or equal to t, executing the judgment of i 2;
d24, determining whether i2 is greater than or equal to t, if less than t, repeating steps D22 and D23 with i2+1 and j2=1; if the integer value is greater than or equal to t, acquiring an integer value array Z2 calculated in the step D22;
the sub-algorithm Q3 includes the following steps:
d31, reading integer value arrays X3, Y3, the lengths of which are t, wherein x3=q4 (H, L), corresponding y3=z;
d32, let i3=t, and perform the following calculation in order:
b3=(X3[i3]/Y3[i3])-d2;
X3=X3-Y3*b3;
Z3=Z3+b3;
X3=Q4（X3,Q2（Y3,d2））;
Z3=Z3+(X3⊕(Y3,d2))*d2;
b3 and d2 are specific integer values;
x3, Y3 and Z3 are integer numerical arrays with the length of t;
d33, judging whether i3 is larger than 1, if i3 is larger than 1, repeating the step D32 with i-1; if i3 is less than or equal to 1, acquiring an integer value array Z3 calculated in the step D32;
the sub-algorithm Q4 includes the steps of:
d41, reading integer value arrays X4, Y4, the lengths of which are t, wherein x4=h, and corresponding y4=l;
d42, let i4=1, d3=0, and perform the following calculation in order:
d3=((X4[i4]+b4-Y4[i4])-d3)>>e2;
Z4[i4]=(X4[i4]+b4-Y4[i4]-d3)%g1;
b4, d3, e2, g1 are specific integer values;
x4, Y4 and Z4 are integer numerical arrays with the length of t;
% is the remainder;
> is binary right shift;
d43, judging whether i4 is greater than or equal to t, if i4 is greater than or equal to t, obtaining integer value array Z4 calculated in step D42; if i4 is less than t, repeat step D42 with i4+1.
2. The method for verifying software and hardware of a master control system according to claim 1, wherein: in step S25, the specific algorithm for converting the acquired m number of arrays into m integer values further includes the steps of:
s251, reading integer value array element B1 with the length of n2 bytes;
s252, calculating an intermediate integer value X, Y, Z through the obtained integer array B1 of n2 bytes;
the specific calculation mode is as follows:
X=(∑B[i])%a；
Y=(∏((B[i]*B[i])>>b))%c；
Z=Ω(B[i]<<d)；
s253, obtaining integer value C1 through the obtained intermediate integer value X, Y, Z;
the specific calculation mode is as follows:
C1=X&&e+Y&&f+Z&&g；
wherein a, b, c, d, e, f, g are specific integer values set; the & & is binary bitwise AND; % is the remainder; > is binary right shift; < is binary shift left; Σ is a summation item by item (1 < =i < =n2); pi is a product term by term (1 < =i < =n2); omega is the itemized exclusive or (1 < =i < =n2); bi is the value of the i-th element in the fetch group B;
s254, reading B2 and calculating C2 according to the steps from S251 to S253, and calculating Cm one by one until Cm is obtained.
3. The method for verifying software and hardware of a master control system according to claim 1, wherein: in step S4, the method further comprises the steps of:
s41, the main control system reads the identification file to obtain an identification file code E;
s42, converting the identification file code E into a check code F of an integer numerical array with the length of m;
s43, reading the unified identification code D, comparing whether the check code F is consistent with the unified identification code D, if so, checking to pass, and if not, checking to fail.
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