CN117471936A - Semi-physical logic verification method, system, upper computer, control panel and medium - Google Patents

Abstract

The application provides a semi-physical logic verification method, a system, an upper computer, a control board and a medium, wherein the semi-physical logic verification method comprises the steps that after a configured logic verification use case is obtained by the upper computer, the logic verification use case is translated into data meeting the requirement of the control board, the control board converts the logic verification use case configured by the upper computer into a corresponding logic control signal and sends the corresponding logic control signal to an embedded device to be verified for logic verification, and the upper computer can realize logic verification without injecting logic execution codes into the embedded device to be verified, namely without adding additional programs in the embedded device to be verified. Therefore, the semi-physical logic verification method, the semi-physical logic verification system, the upper computer, the control panel and the medium have good compatibility.

Description

Semi-physical logic verification method, system, upper computer, control panel and medium

Technical Field

The application relates to the field of embedded technology, in particular to a semi-physical logic verification method, a semi-physical logic verification system, an upper computer, a control board and a medium.

Background

The embedded device is a core unit of a product generally, whether the embedded device reliably determines the quality of the whole product, and if the embedded device can be fully and comprehensively logically verified in the early stage of the product, the reliability of the product can be greatly improved, and various troublesome problems possibly occurring in the actual operation process after the product is released can be reduced.

The existing embedded device generally performs logic verification in the following manner: the upper computer sequentially sends the configured verification cases to the embedded equipment to be tested, the embedded equipment activates an automatic verification process after receiving the test cases, replaces key node codes, validates related logic, and sends the completed verification results to the verification case management tool after execution is completed. The existing logic verification mode is not suitable for the embedded equipment without reserved code injection logic because the code injection is needed for the embedded equipment to be verified, and the corresponding logic verification test cannot be performed unless the embedded equipment to be verified is upgraded or improved, but the embedded equipment to be verified is upgraded or improved, so that the risk of the equipment is increased to a certain extent. Therefore, the existing logic verification method has poor compatibility.

Disclosure of Invention

In order to solve the existing technical problems, a high-compatibility semi-physical logic verification method, a logic verification system, an upper computer, a control board and a computer readable storage medium are provided.

According to a first aspect of an embodiment of the present application, there is provided a method for verifying semi-physical logic, including:

Translating the logic verification use case into a logic execution instruction set matched with a control board, and sending a corresponding logic execution instruction in the logic execution instruction set to the control board according to a preset sending strategy so as to control the control board to send a corresponding logic control signal to the embedded equipment to be verified;

and monitoring feedback data forwarded by the control board, and analyzing the feedback data to obtain a logic verification result of the embedded device to be verified, wherein the feedback data is running state data output by the embedded device to be verified based on the corresponding logic control signal.

According to a second aspect of an embodiment of the present application, there is provided a method for verifying a semi-physical logic, including:

downloading a logic verification case from an upper computer, and executing a logic execution instruction corresponding to a logic instruction set according to a preset execution strategy according to a logic instruction set corresponding to the logic case so as to send a corresponding logic control signal to the embedded equipment to be verified;

and analyzing the feedback data to obtain a logic verification result of the embedded equipment to be verified and sending the logic verification result to the upper computer.

According to a third aspect of the embodiments of the present application, there is provided a host computer, including a first memory and a first processor, where the first memory stores a computer readable program, and the first processor implements the semi-physical logic verification method as provided according to the first aspect of the embodiments of the present application when executing the computer readable program.

According to a fourth aspect of the embodiments of the present application, there is provided a control board, including a second memory and a second processor, where the second memory stores a computer readable program, and the second processor implements the semi-physical logic verification method as provided according to the second aspect of the embodiments of the present application when executing the computer readable program.

According to a fifth aspect of the embodiments of the present application, there is provided a semi-physical logic verification system, including the host computer and a control board communicatively connected to the host computer provided according to the third aspect of the embodiments of the present application, where the control board is communicatively connected to an embedded device to be verified; or alternatively, the first and second heat exchangers may be,

the control board is in communication connection with the embedded device to be verified.

According to a sixth aspect of the embodiments of the present application, there is provided a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program when executed by a processor implements the above-mentioned semi-physical logic verification method according to the first aspect or the second aspect of the embodiments of the present application.

From the above, in the semi-physical logic verification method, system, upper computer, control board and medium provided in some embodiments of the present application, after obtaining the configured logic verification use case, the upper computer translates the logic verification use case into data meeting the requirement of the control board, the control board converts the logic verification use case configured by the upper computer into a corresponding logic control signal and sends the corresponding logic control signal to the embedded device to be verified for logic verification, and receives the feedback data of the control board, and analyzes the logic verification result from the feedback data, so that the upper computer can realize logic verification without injecting logic execution codes into the embedded device to be verified, i.e. without adding additional programs in the embedded device to be verified. Therefore, the semi-physical logic verification method, the semi-physical logic verification system, the upper computer, the control panel and the medium provided by some embodiments of the application have good compatibility.

Drawings

FIG. 1 is a schematic diagram of a semi-physical logic verification system according to some embodiments of the present application;

FIG. 2 is a flow chart of a first semi-physical logic verification method according to some embodiments of the present application;

FIG. 3 is a flowchart illustrating a logic verification result obtained by an upper computer according to feedback data in a first semi-physical logic verification method according to some embodiments of the present application;

FIG. 4 is a schematic diagram of a workflow of a first semi-physical logic verification system provided in accordance with some embodiments of the present application;

FIG. 5 is a flowchart of a second semi-physical logic verification method according to some embodiments of the present disclosure;

FIG. 6 is a schematic diagram illustrating a workflow of a second semi-physical logic verification system according to some embodiments of the present application.

Detailed Description

The technical scheme of the application is further elaborated below by referring to the drawings in the specification and the specific embodiments.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the implementations of the present application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

In the description of the present application, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.

Fig. 1 is a schematic diagram of a semi-physical logic verification system according to some embodiments of the present application. The semi-physical logic verification refers to the construction of a virtual verification environment, and a logic verification mode of adding physical embedded equipment to be verified into a logic verification system. The semi-physical logic verification system comprises an upper computer 1 and a control board 2, wherein the upper computer 1 is connected with embedded equipment 3 to be verified through the control board 2. Specifically, the upper computer 1 may be connected to the control board 2 through an ethernet or a USB data line, so as to perform data transmission and reception with the control board 2. That is, the control board 2 includes an ethernet interface and/or a USB interface, and the host computer 1 is connected to the control board 2 via an ethernet network or remotely, or directly connected to the control board 2 via a USB. The upper computer 1 can send data to the control panel 2, and the control panel 2 can also transmit corresponding data back to the control panel. The control board 2 is provided with a plurality of interfaces for connecting with the embedded device 3 to be verified, and logic control signals are sent to the corresponding interfaces in the embedded device 3 to be verified through the interfaces of the control board 2 so as to control the embedded device 3 to be verified to execute corresponding logic and generate corresponding feedback data output, so that corresponding logic verification results are obtained based on analysis of the feedback data. The analysis of the feedback data may be local analysis or remote analysis. The local analysis mode is as follows: the control board 2 forwards feedback data output by the embedded equipment 3 to be verified to the upper computer 1, and the upper computer 1 obtains a logic verification result of the embedded equipment to be verified according to analysis of the feedback data; the remote analysis mode is as follows: the control board 2 analyzes the received feedback data to obtain a logic verification result of the embedded device to be verified, and uploads the logic verification result to the upper computer 1. The interface between the control board 2 and the embedded device 3 to be verified comprises a serial communication interface, a relay interface, an input/output interface, and/or other interfaces (such as an expansion interface), and the like, and further comprises a power supply control interface. The serial communication interfaces include 232 interface, 485 interface, etc. and the input/output interfaces include AI/AO/D I/DO (analog input/analog output/digital input/digital output) interface. In some embodiments, the control board 2 sends a logic control signal to the embedded device 3 to be verified to supply power to control the embedded device 3 to be verified to be in various power supply states, so that the embedded device 3 to be verified can be controlled to perform corresponding logic verification in various power supply states. Among these, various power supply states of the embedded device 3 to be verified include a power-on state, a power-off or power-off state, and the like. In some embodiments, one control board 2 may be connected with a plurality of different embedded devices 3 to be authenticated through corresponding interfaces.

The upper computer 1 is used for obtaining a logic verification case, translating the logic verification case into a protocol required by the control board 2, converting a corresponding logic execution instruction in the logic verification case into a corresponding logic control signal by the control board 2, and then transmitting the corresponding logic control signal to the embedded device 3 to be verified so as to control the embedded device 3 to be verified to execute corresponding logic. Because a control board 2 is adopted for switching, the expandability is strong, and the upper computer 1 can realize logic verification without injecting codes into the embedded device 3 to be verified, namely without adding additional programs in the embedded device 3 to be verified. Therefore, the semi-physical logic verification system provided by some embodiments of the application has better compatibility.

In some embodiments, the feedback signal output by the embedded device 3 to be verified is locally parsed, and the upper computer 1 includes a first memory and a first processor, where a computer readable program is stored in the first memory, and the first processor implements the steps in the first semi-physical logic verification method provided in any one of the embodiments according to the present application when executing the computer readable program. The flow chart of the first semi-physical logic verification method according to some embodiments of the present application is shown in fig. 2, and the first semi-physical logic verification method includes S12 and S14.

S12: and translating the logic verification use case into a logic execution instruction set matched with the control board, and sending a corresponding logic execution instruction in the logic execution instruction set to the control board according to a preset sending strategy so as to control the control board to send a corresponding logic control signal to the embedded device to be verified.

The upper computer 1 may select a corresponding logical verification use case from the logical verification use case library based on user selection, or may import a corresponding logical verification use case based on user operation. After obtaining the logic verification use case, the upper computer 1 may configure the logic verification use case by using an imaged block diagram, so as to execute corresponding logic verification according to the configured logic verification use case. Specifically, the upper computer 1 may perform configuration of the logic verification case by using a code/script configuration, a form import configuration, or the like, in addition to the graphical block diagram configuration.

When the upper computer 1 obtains the configured logic verification use cases, the logic verification use cases are translated into custom protocol data meeting the requirements of the control panel 2, and the custom protocol data is sent to the control panel through Ethernet or USB. Specifically, the logic verification case includes each logic execution instruction corresponding to each logic to be executed, and each logic execution instruction forms a logic execution instruction set. After translating the logic verification use case into a logic execution instruction set matched with the control board 2, the upper computer 1 sends a corresponding logic execution instruction according to a preset sending strategy.

The upper computer 1 sends a logic execution instruction to the control board 2 each time, so that the control board 2 outputs a corresponding logic control signal to the embedded device 3 to be verified, and accordingly the embedded device 3 to be verified is controlled to execute corresponding logic according to the received logic control signal, and corresponding feedback data is output.

S14: and monitoring feedback data forwarded by the control board, and analyzing the feedback data to obtain a logic verification result of the embedded equipment to be verified, wherein the feedback data is running state data output by the embedded equipment to be verified based on a corresponding logic control signal.

The control board 2 forwards the received feedback data to the upper computer 1 in real time so as to realize real-time monitoring of the feedback data by the upper computer 1, and compared with the existing logic verification methods, the logic verification reliability is effectively improved. Some existing logic verification methods cannot ensure the real-time transmission of messages between the embedded device 3 to be verified and the configured logic verification case tool (the upper computer 1), and are not beneficial to the execution of logic under low delay. In addition, the existing logic verification method needs to return feedback data to the upper computer 1 once after all logic execution instructions in the logic verification case are executed, and by adopting the logic verification method, if the embedded device 3 to be verified suddenly has a (active or passive) power failure condition before all logic execution instructions are not executed, the power supply loss can lead to that the previously executed processing condition is not returned to the upper computer 1, and the reliability is poor. In the first semi-physical logic verification method provided by the embodiment of the application, the control board 2 forwards the feedback signal output by the embedded device 3 to be verified to the upper computer 1 in real time for monitoring, so that the reliability of logic verification is effectively ensured.

In addition, in the first semi-physical logic verification method provided in some embodiments of the present application, since a control board 2 is used to convert a logic execution instruction sent by the upper computer 1 into a corresponding logic control signal and forward the logic control signal to the embedded device 3 to be verified, the expandability is very strong, and the upper computer 1 can implement logic verification without injecting codes into the embedded device 3 to be verified, that is, without adding additional programs in the embedded device 3 to be verified. Therefore, the first semi-physical logic verification method provided by some embodiments of the present application has better reliability and better compatibility.

In some embodiments, the feedback data forwarded by the listening control board 2 specifically includes: and obtaining and displaying the change trend data of the feedback data according to the feedback data monitored in real time. In some embodiments, the embedded device 3 to be verified is a temperature controlled device, such as an air conditioner, a refrigeration unit, or the like. And feedback data such as temperature, humidity and/or carbon dioxide concentration and the like output by a corresponding sensor in the embedded equipment 3 to be verified so as to detect the change trend of the temperature, humidity and/or carbon dioxide concentration in the environment where the monitoring temperature control equipment is located according to the feedback data, thereby better simulating the display environment to carry out randomized logic verification. The upper computer 1 can obtain the logic execution result corresponding to each logic execution instruction in real time by monitoring the feedback data in real time, so as to determine whether to change logic execution instructions of some logic to be executed later according to the logic execution result obtained currently. The logic execution instructions for changing some logic to be executed include adding, modifying or deleting a logic execution instruction to be executed in the logic verification case, which is equivalent to updating the logic verification case. Therefore, the first semi-physical logic verification method provided according to some embodiments of the present application has more flexibility in selecting logic execution instructions, is not limited to using block diagram flow to describe logic verification cases, and is suitable for simulating complex real-world environments to perform related logic verification. The existing logic verification method is to directly send logic execution instructions corresponding to each logic to be executed to the embedded device 3 to be verified in sequence, and return an execution result to the host computer 1 after the embedded device 3 to be verified completes execution of all the logic, so that logic verification suspension or temporary addition of new logic execution instructions cannot be realized, and flexibility is relatively poor.

After obtaining the configured logic use cases to be verified, the upper computer 1 translates each logic execution instruction in the logic verification use cases into a custom protocol meeting the requirement of the control panel 2 and sequentially sends the custom protocol to the control panel 2 according to a preset sending strategy. In some existing logic verification methods, the upper computer 1 sequentially sends each logic execution instruction in the logic use case to the control board 2 according to a fixed execution sequence, so that the logic execution instruction cannot be changed halfway, and the logic verification flexibility is low. In some embodiments of the present application, the preset sending policy is specifically: and determining the logic execution instruction which needs to be sent to the control board 2 according to the logic execution result corresponding to the logic execution instruction which is sent to the control board 2. And determining a logic execution result corresponding to the logic execution instruction according to the corresponding feedback data. In the first semi-physical logic verification method provided in some embodiments of the present application, feedback data corresponding to each logic execution instruction is sent to the upper computer 1 in real time by the control board 2, and the upper computer 1 performs corresponding analysis according to the feedback data monitored in real time, so as to obtain a real-time logic execution result of logic verification, and determines a next logic execution instruction to be executed according to the current logic execution result. For example, based on the current logic execution result, it is determined whether to continue executing the original logic execution instruction of the next logic to be executed or to execute the variant logic execution instruction of the next logic to be executed. When it is determined that the current logic verification item fails to execute the logic according to the current logic execution result, for example, the remaining logic execution instructions of the current logic verification item are not executed continuously, but the next logic verification item of the current logic verification item is skipped to execute the corresponding logic execution instructions.

In some embodiments, the determining, according to the logic execution result corresponding to the logic execution instruction sent to the control board 2 before, the logic execution instruction to be sent to the control board 2 after the last further includes: and determining whether to trigger the variant logic execution instruction corresponding to the next logic to be executed according to the logic execution result corresponding to the previous logic to be executed. If yes, determining the variant logic execution instruction as a logic execution instruction which needs to be sent to the control board 2; if not, taking the original logic execution instruction corresponding to the logic to be executed as the logic execution instruction which needs to be sent to the control panel 2. The variant logic execution instruction of the later logic to be executed triggered according to the previous logic execution result is equivalent to modifying the logic verification case in the middle of logic verification. Specifically, in some embodiments, when the logic execution result of the previous logic to be executed is abnormal, a variant logic execution instruction of the next logic to be executed needs to be triggered.

In some embodiments, it is necessary to verify multiple logic verification items of the embedded device 3 to be verified, where each logic verification item corresponds to one or more logic to be executed, and each logic to be executed needs to execute according to a corresponding logic execution instruction. Each logical verification item may be referred to as a node and the result of the logical execution corresponding to each logical verification item may be referred to as node data of the corresponding node. Each logic to be executed in each logic verification item is called a child node of the corresponding node, and the logic execution result corresponding to each logic execution instruction is child node data of the corresponding child node. In some embodiments, the current node corresponding to the currently executed item to be verified includes a plurality of child nodes, such as child node a and child node B. If the currently executed child node is the child node a, according to the child node data of the child node a, whether the logic execution instruction corresponding to the child node B is the original logic execution instruction B1 or the variant logic execution instruction B2 is called as the conditional triggering variant execution logic, and the triggering condition is that whether the logic execution result of the currently executed logic meets the triggering condition. In some embodiments, if the logic execution result of the child node a fails, the child node B in the current node is not executed any more, and it is determined that the logic execution of the current node is completed, and the node data of the current node is output. The node data of the current node comprises the child node data of all child nodes under the current node or the data representing the logic verification result of the current node determined according to the corresponding child node data. When each sub node is executed, the corresponding sub node data and the current monitored feedback data are required to be recorded, and after all the sub nodes needing to be executed in the current node are executed, the sub node data in the current node are processed to obtain the node data of the current node and display and output.

In some embodiments, the logic verification case is a logic verification case corresponding to a plurality of logic verification items, that is, the logic execution instruction set includes a plurality of logic execution instruction sets corresponding to the plurality of logic verification items, respectively. Each logic execution instruction group comprises logic execution instructions of each logic to be executed in the corresponding logic verification item. In some embodiments, the embedded device 3 to be verified is an air conditioning device, and each logic verification item includes a start-up verification logic item and a mode switching verification logic item, where the logic to be executed corresponding to the mode switching verification logic item includes switching to a cooling mode, switching to a heating mode, and switching to a dehumidifying mode. Taking the mode switching verification logic item as an example, if the execution result of any one logic of switching to the cooling mode, switching to the heating mode and switching to the dehumidifying mode fails, the logic verification failure of the mode switching logic verification item is described.

In some embodiments, referring to fig. 3, the logic verification result of the embedded device to be verified is obtained according to the feedback data in S14, which specifically includes S142 and S144.

S142: after each logic execution instruction which is required to be sent to the control board in each logic execution instruction group is sent, logic verification results of corresponding logic verification items are obtained and displayed, and the logic verification results of the logic verification items are determined according to each logic execution result of each corresponding logic execution instruction.

Each logic execution instruction to be sent to the control board 2 in each logic execution instruction group is sent to be completed, namely each logic to be executed in each logic verification item is all executed, namely verification of each node is all completed. And determining a logic verification result corresponding to each logic verification item according to a logic execution result of the corresponding logic to be executed.

After each logic execution instruction to be sent to the control board 2 in each logic execution instruction group is sent to be completed, corresponding data processing is performed on the logic execution result (corresponding to the child node data of the child node) of each logic execution instruction executed in the logic instruction group with the current execution completed, so as to obtain the logic verification result of the corresponding logic verification item, namely the node data of the node.

S144: and after the logic verification results of the plurality of logic verification items are respectively obtained, obtaining and displaying the logic verification result of the embedded device to be verified according to the logic verification results of the plurality of logic verification items.

The logic verification result of the embedded device 3 to be verified is a result determined according to the logic verification results of the plurality of logic verification, if the currently executed logic verification item is the last logic verification item in all the logic verification items to be executed, the logic verification results of all the logic verification items can be obtained after the execution of the current logic verification item is completed, so that the logic verification result of the embedded device 3 to be verified is obtained, otherwise, the next logic verification item needs to be executed continuously until all the logic verification items are executed completely and the logic verification results of all the logic verification items are obtained. If the logic verification results corresponding to all the logic verification items are verification success, determining that the logic verification of the embedded device 3 to be verified is successful, otherwise, determining that the logic verification is failure or abnormal.

Further, in some embodiments, the logic verification result of the embedded device 3 to be verified is obtained and displayed according to the logic verification results of the plurality of logic verification items in S144, and specifically includes: based on the logical verification results of the plurality of logical verification items, a logical verification report for verifying the embedded device 3 is generated and displayed. After judging that all logic verification items to be verified are subjected to logic verification, generating a logic verification report according to the logic verification results of all logic verification items and displaying and outputting, otherwise, continuing to wait for the upper computer to send a corresponding logic execution instruction of the next logic verification item, and continuing to execute the next logic verification item. And outputting the logic verification result of each logic verification item in the form of a logic verification report, so that the logic verification result can be conveniently managed.

In some embodiments, prior to S142 above, the first semi-physical logic verification method further comprises: judging whether a logic execution result corresponding to a logic execution instruction currently sent to the control panel fails or whether the logic execution instruction currently sent to the control panel is the last logic execution instruction in the corresponding logic execution instruction group; if yes, judging that each logic execution instruction in the corresponding logic execution instruction group, which is required to be sent to the control board, is sent to completion, namely judging that the logic verification of the currently executed logic verification item is completed, and if the logic verification item which is not executed in the bit is still available in the follow-up, continuing to wait for the upper computer 1 to send the corresponding logic execution instruction of the next logic verification item. If not, continuing to wait for the upper computer 1 to send a logic execution instruction which is needed to be executed next and corresponds to the logic verification item which is executed currently.

In some embodiments, the present application provides a first semi-physical logic verification system, and the structural block diagram of the first semi-physical logic verification system may also be shown in fig. 1, where the first semi-physical logic verification system includes an upper computer 1 to which the first semi-physical logic verification method according to any embodiment of the present application is applied, and a control board 2 connected to the upper computer 1. The upper computer 1 sequentially sends corresponding logic execution instructions to the control board 2 according to a preset sending strategy and a custom protocol required by the control board 2, and the control board 2 is used for sequentially forwarding the logic execution instructions issued by the upper computer 1 to the embedded device 3 to be verified so as to control the embedded device 3 to be verified to output corresponding feedback data according to the output feedback data. The control board 2 then forwards the feedback data output by the embedded device 3 to be verified to the upper computer 1, and the upper computer 1 monitors and analyzes the feedback data to obtain the logic execution result corresponding to each logic execution instruction in real time, so as to obtain the logic verification result of the embedded device 3 to be verified, and output a corresponding logic verification report. The logical verification report may be a tabular report or a text report.

The upper computer 1 determines the next logic execution instruction to be executed according to the currently acquired logic execution result, that is, the upper computer 1 determines what data needs to be sent to each interface of the control board 2 at the next moment according to the logic execution result of the previous logic execution instruction. Each interface of the control board 2 connected with the embedded device 3 to be verified is respectively corresponding to one data area, namely an identification address, of the control board 2, and when the embedded device to be verified is logically verified, the upper computer 1 does not need to know the existence of the embedded device 3 to be verified and/or the interface information of the embedded device 3 to be verified, but only needs to control the corresponding data area in the control board 2, so that the control board 2 outputs a corresponding logic control signal through the interface. The logic of the device 3 to be embedded is virtualized as some nodes of the control board 2 so that most of the logic can be multiplexed, only by modifying the cross-relationship. The upper computer 1 can determine the next logic verification trend based on the logic execution result of the logic execution instruction which is executed previously, so that the first semi-physical logic verification system has more flexibility. In the first semi-physical logic verification system, the upper computer 1 monitors feedback data forwarded by the control board in real time, and the upper computer 1 is connected with the control board 2 through the Ethernet or USB, so that the logic verification connection mode with higher speed can achieve millisecond logic delay.

Fig. 4 is a schematic workflow diagram of a first semi-physical logic verification system according to some embodiments of the present application. When the logic verification process starts, the upper computer 1 needs to acquire the logic verification use cases, and acquires the logic verification use cases imported by the user or selected from the logic verification use case library. After the upper computer 1 acquires the logic verification use cases, the logic verification use cases are translated into logic execution instructions matched with the control board 2, and each logic execution instruction is sequentially sent to the control board 2 according to a custom protocol required by the control board 2. In addition, the upper computer 1 may perform the graphic configuration of the logic verification case and then translate the logic verification case. In order to facilitate the subsequent reuse of the currently configured logical verification use cases, the graphically configured logical verification use cases may be derived from the host computer 1 to be stored in a logical verification use case library as subsequently usable logical verification use cases. The control board 2 generates corresponding logic control signals according to the received logic execution instructions and outputs the corresponding logic control signals to the embedded equipment 3 to be verified so as to forward the corresponding logic execution instructions to the embedded equipment 3 to be verified. After receiving the logic control signal, the embedded device 3 to be verified executes corresponding logic to be executed according to the logic control signal and outputs corresponding feedback data. The control board 2 receives feedback data output by the embedded device 3 to be verified in real time and forwards the feedback data to the upper computer 1. The upper computer 1 analyzes the feedback data received in real time to obtain a logic execution result corresponding to the logic execution instruction which is currently issued, and judges whether the data which triggers logic to send currently exists or not according to the logic execution result which is currently analyzed, namely whether the variant logic execution instruction which triggers the next logic to be verified exists or not. If the judgment result is that the trigger exists, a variant logic execution instruction of the next logic to be executed is sent to the control board 2, otherwise, the original logic execution instruction of the next logic to be executed is sent in sequence, and the logic execution result corresponding to the logic execution instruction which is executed currently and the current feedback data are recorded, namely the child node data and the monitoring data of the child node which is executed currently are recorded. Then, judging whether the current node (current logic verification item) is verified, if yes, processing the child node data of the current node to obtain the node data of the current node, and outputting and displaying the node data of the current node; if the result of the judgment is no, the upper computer 1 continues to sequentially send the data (logic execution instruction) which are needed to be sent and remain waiting for the feedback data of the embedded device 3 to be verified in the current logic verification item. After the node data of the current node is output, judging whether all the node data are output currently, namely whether all the nodes are verified, if so, outputting a logic verification report according to all the node data, otherwise, the upper computer 1 continues to sequentially send data (logic execution instructions) to be sent in the next logic verification item, and continues to wait for feedback data of the embedded device 3 to be verified. In some embodiments, after the verification of the current node is completed, if it is determined that there are remaining nodes that are not verified, the upper computer 1 continues to control the verification of the next node, and outputs a prompt message that the verification is not completed.

From the above, in the first semi-physical logic verification system provided in some embodiments of the present application, the control board 2 is used as a transfer board for issuing logic execution instructions by the upper computer 1, the upper computer 1 indirectly performs automatic logic verification on the embedded device 3 to be verified by the translated logic execution instructions, and all data processing in all verification processes is performed in the upper computer 1 and converted into a graphic interface which can be understood by a user, so that real-time interaction of data and reliability of logic verification under long time are facilitated. Because the first semi-physical logic verification system provided by some embodiments of the present application can control the embedded device 3 to be verified to continue to perform logic verification after power failure or power restoration through the control board 2, the reliability of long-time logic verification is ensured, and the running condition of the embedded device 3 to be verified when power supply is unstable and the running condition of the embedded device 3 to be verified when internal logic is abnormal can be verified. In addition, the upper computer 1 translates the configured logic verification use cases into logic execution instructions meeting the requirements of the control board 2 and sequentially issues the logic execution instructions so as to control the automatic logic verification of the embedded device 3 to be verified, and decides the subsequent logic verification trend according to the logic execution results of real-time monitoring, thereby being convenient for the management and multiplexing of the logic verification use cases and being capable of controlling the suspension, change, deletion and addition of logic execution at any time. The manual participation of logic verification is reduced to a greater extent, so that not only are the labor cost and the time cost saved, but also the flexibility and the reliability of logic verification are improved. In addition, the upper computer 1 can adopt various forms to input logic verification cases, such as forms of programs, scripts, block diagrams, tables and the like, which is beneficial to reducing the difficulty of the hands of equipment verification personnel, and can reduce the learning cost of embedded equipment verification due to more logic verification case configuration schemes. In addition, the first semi-physical logic verification system provided by some embodiments of the present application adopts a layered decoupling mode, the upper computer 1 only needs to know the corresponding data area in the control board 2, does not need to know the internal logic of the embedded device 3 to be verified, only needs to know the logic corresponding to the embedded device 3 to be verified in the control board 2, and meanwhile, the upper computer 1 performs logic verification on the embedded device 3 to be verified by means of the control board 2, does not need to inject codes into the embedded device 3 to be verified, has higher compatibility, and enables the old embedded device 3 to be verified to perform logic verification without modifying things, so that automatic logic verification can be realized by directly connecting to the control board 2. Therefore, the upper computer 1 and the embedded equipment 3 with verification are connected through the control board 2, so that logic verification of a plurality of different embedded equipment 3 to be verified can be realized at the same time, and the expandability, the instantaneity and the stability of the logic verification are improved.

In some embodiments, the feedback signal output by the embedded device 3 to be verified in fig. 1 is remote analysis, that is, the control board 2 in fig. 1 analyzes the feedback signal to obtain a logic execution result corresponding to the logic verification item, and uploads the logic execution result to the upper computer 1 for processing to obtain the logic verification result of the embedded device 3 to be verified. The control board 2 includes a second memory in which a computer readable program is stored, and a second processor that, when executing the computer readable program, implements the steps of the second semi-physical logic verification method provided in accordance with any one of the embodiments of the present application. The flow chart of the second semi-physical logic verification method according to some embodiments of the present application is shown in fig. 5, and the second semi-physical logic verification method includes S22 and S24.

S22, downloading a logic verification case from the upper computer, and executing a logic execution instruction corresponding to the logic instruction set according to a preset execution strategy according to a logic instruction set corresponding to the logic case so as to send a corresponding logic control signal to the embedded device to be verified.

The upper computer 1 converts the configured logic verification cases into the logic of the control board 2 at one time, and burns the logic to the control board 2, namely, the control board 2 downloads the logic verification cases from the upper computer 1, and then sequentially executes corresponding logic execution instructions in the logic verification cases according to a preset execution strategy so as to sequentially convert the corresponding logic execution instructions into logic control signals for controlling the embedded device 3 to be verified to execute corresponding logic.

In some embodiments, the preset execution policy is: and determining the logic execution instruction which needs to be executed to the next time according to the logic execution result corresponding to the previous logic execution instruction. Wherein the logic execution result corresponding to the logic execution instruction is determined according to the corresponding feedback data received from the embedded device 3 to be verified.

Further, in some embodiments, according to the logic execution result corresponding to the previous logic execution instruction, determining that the logic execution instruction to be executed later is specifically: determining whether to trigger a variant logic execution instruction corresponding to the next logic to be executed according to a logic execution result corresponding to the previous logic to be executed; if yes, triggering and executing a variant logic execution finger of the later logic to be executed; if not, executing the original logic execution instruction corresponding to the logic to be executed.

And S24, analyzing the feedback data to obtain a logic verification result of the embedded equipment to be verified and transmitting the logic verification result to the upper computer.

And analyzing the feedback data in real time in the control board 2 to obtain logic execution results of each logic execution instruction, and uploading the node data (the logic verification result of the current logic verification item, namely the logic verification result of the embedded device 3 to be verified, which is currently obtained) of the current node (the current logic verification item) to the upper computer 1 until the verification of the current node is completed. The logic verification method for remote analysis is suitable for logic verification when remote connection or high real-time performance is required. Because the control board 2 adopts a real-time operating system, when logic verification is executed, delay of microsecond level can be achieved, each logic execution instruction is executed in the control board 2 in a queue form, when the logic execution instruction of each node is executed, the execution result data is returned and displayed on the upper computer 1, if the upper computer 1 cannot receive the execution result data, the control board 2 firstly caches the node data of the current node and the subsequent node data and sends the node data in a merging mode, and after the logic execution instructions of all the nodes are executed, the upper computer 1 can uniformly generate a logic verification report of the embedded device 3 to be verified according to the node data of each node. In other embodiments, the control board 2 may also send the logic execution result corresponding to each logic execution instruction to the upper computer 1 in real time. The second semi-physical logic verification method provided by some embodiments of the present application achieves the same effect as the first semi-physical logic verification method provided by some embodiments of the present application, which is not described here again, except that the first semi-physical logic verification method uses local resolution, and the second semi-physical logic verification method uses remote resolution. Compared with the first semi-physical logic verification method of local analysis, the second semi-physical logic verification method has the advantages that all data are processed in the control board 2, and the method is suitable for simultaneous batch verification of a plurality of logic devices 3 to be verified, so that the flexibility of logic verification is further improved.

In the second semi-physical logic verification method, the upper computer 1 converts a logic verification case into logic required by the control board 2, the logic verification case is burnt into the control board 2, the control board 2 automatically performs logic verification on the embedded equipment 3 to be verified under the condition that the control board is separated from the upper computer 1, remote verification is realized, a logic verification result of each node is returned to the upper computer 1 when the logic verification result is completed in operation, the real-time performance of the scheme can reach a microsecond-level high time sequence, and the embedded equipment 3 to be verified in a plurality of different places and the operation conditions of the embedded equipment to be verified in different environments can be verified simultaneously. Therefore, the second semi-physical logic verification method provided by some embodiments of the present application can realize distributed logic verification of devices to be embedded in different places, and can perform remote verification, and only after a verification personnel deploys a logic verification case in the upper computer 1, the verification personnel can verify a plurality of devices to be verified on one or more control boards 2 at the same time.

In some embodiments, the control board 2 sends the logic verification result of each logic verification item to the upper computer 1 after the execution of each logic execution instruction corresponding to each logic verification item is completed. Specifically, the control board 2 determines whether the logic execution result corresponding to the currently executed logic execution instruction fails or whether the currently executed logic execution instruction is the last logic execution instruction to be executed in the corresponding logic verification item; if yes, judging that all logic execution instructions to be executed in the corresponding logic verification item are executed, otherwise, continuing to execute the next logic execution instruction in the corresponding logic verification item.

In the second semi-physical logic verification method, the control board 2 is also used for controlling the power supply of the embedded device 3 to be verified, namely, the control board 2 outputs logic control signals including power supply control signals sent to the power supply control end, and the power supply control signals are used for controlling the embedded device to be verified to perform corresponding logic verification in different power supply states.

In some embodiments, the present application provides a second semi-physical logic verification system, and the structural block diagram of the second semi-physical logic verification system may also be shown in fig. 1, where the second semi-physical logic verification system includes an upper computer 1 to which the second semi-physical logic verification method according to any embodiment of the present application is applied, and a control board 2 connected to the upper computer 1. After the upper computer 1 is configured with the logic verification case, the logic verification case is translated and packaged into a custom protocol required by the control board 2, and the custom protocol is burnt into the control board 2. The control board 2 is used for executing each logic execution instruction in the logic verification use case according to a preset execution strategy so as to send a corresponding logic control signal to the embedded device 3 to be verified, so as to control the embedded device 3 to be verified to output corresponding feedback data according to the output. The control board 2 analyzes the feedback number output by the embedded device 3 to be verified to obtain a logic execution result corresponding to each logic execution instruction, and returns the logic execution result to the upper computer 1 according to the nodes so as to output a corresponding logic verification report by the upper computer 1. The control board 2 determines a logic execution instruction to be executed next according to a logic execution result corresponding to the logic execution instruction currently executed.

Fig. 6 is a schematic workflow diagram of a second semi-physical logic verification system according to some embodiments of the present application. When the logic verification process starts, the logic verification use cases are acquired, then the logic verification use cases are imported into the upper computer 1, and the upper computer 1 translates and packages the logic verification use cases for downloading by the control board 2. The host computer 1 may also perform the translation after performing the graphic configuration on the logic verification use case. In order to facilitate the subsequent reuse of the currently configured logical verification use cases, the graphically configured logical verification use cases may be derived from the host computer 1 to be stored in a logical verification use case library as subsequently usable logical verification use cases. The control board 2 downloads the logic verification cases from the upper computer 1, and sequentially executes each logic execution instruction in the logic verification cases according to a preset execution strategy, so as to sequentially send corresponding logic control signals to the embedded device 3 to be verified. The embedded device 3 to be verified generates corresponding feedback data according to the received logic control signal, and outputs the feedback data to the control board 2. The control board 2 receives feedback data and analyzes the feedback data to obtain a logic execution result corresponding to a logic execution instruction, determines whether to trigger logic to send data or not according to the logic execution result obtained currently, namely whether to trigger a variant logic execution instruction of the next logic to be executed, if yes, the control board 2 executes the variant logic execution instruction of the next logic to be executed, if not, the control board 2 judges whether all logic execution instructions required to be executed by the current node are completed or not, namely whether the current node is verified to be completed or not. And when judging that the verification of the current node is not finished, continuing to sequentially execute the original logic execution instruction of the next logic to be executed in the current node, otherwise, sending the node data of the current node to the upper computer 1 for display. The control board 2 judges whether the current node data is successfully transmitted, if not, the current node data is cached and transmitted in combination with the subsequent node data, or transmitted after establishing correct connection with the upper computer. After the upper computer 2 receives the data of each node, outputting and displaying the data of each node, judging whether all nodes are verified, if yes, outputting a logic verification report, if not, waiting for the control board 2 to continuously execute the logic execution instructions which are required to be executed in sequence, and continuously waiting for feedback data of the embedded device 3 to be verified. When the upper computer 1 judges that the verification of all the nodes is not finished currently, prompt information that the verification is not finished is further displayed.

The embodiment of the application further provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements each step in the first semi-physical logic verification method or the second semi-physical logic verification method according to any embodiment of the application, and can achieve the same technical effect, so that repetition is avoided, and no further description is provided herein. Among them, a computer readable storage medium such as Read-only memory (ROM), random Access Memory (RAM), magnetic disk or optical disk, and the like.

The foregoing is merely a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes or substitutions should be covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A method of verifying semi-physical logic, comprising:

translating the logic verification use case into a logic execution instruction set matched with a control board, and sending a corresponding logic execution instruction in the logic execution instruction set to the control board according to a preset sending strategy so as to control the control board to send a corresponding logic control signal to the embedded equipment to be verified;

And monitoring feedback data forwarded by the control board, and analyzing the feedback data to obtain a logic verification result of the embedded device to be verified, wherein the feedback data is running state data output by the embedded device to be verified based on the corresponding logic control signal.

2. The method for verifying semi-physical logic according to claim 1, wherein the predetermined transmission policy is:

determining the logic execution instruction which needs to be sent to the control board according to the logic execution result corresponding to the logic execution instruction which is sent to the control board;

and determining a logic execution result corresponding to the logic execution instruction according to the corresponding feedback data.

3. The method for verifying the semi-physical logic according to claim 2, wherein determining the logic execution instruction to be transmitted to the control board according to the logic execution result corresponding to the logic execution instruction previously transmitted to the control board comprises:

determining whether to trigger a variant logic execution instruction corresponding to the next logic to be executed according to the logic execution result corresponding to the previous logic to be executed;

If yes, determining the variant logic execution instruction as the logic execution instruction which needs to be sent to the control panel;

if not, taking the original logic execution instruction corresponding to the next logic to be executed as the next logic execution instruction which needs to be sent to the control board.

4. The method for verifying semi-physical logic according to claim 1, wherein the set of logic execution instructions includes a plurality of logic execution instruction groups corresponding to a plurality of logic verification items, respectively, and the obtaining the logic verification result of the embedded device to be verified according to the feedback data includes:

after the logic execution instructions which are required to be sent to the control panel in each logic execution instruction group are sent, logic verification results of the corresponding logic verification items are obtained and displayed, and the logic verification results of the logic verification items are determined according to the logic execution results of the corresponding logic execution instructions;

and after the logic verification results of the logic verification items are respectively obtained, obtaining and displaying the logic verification results of the embedded equipment to be verified according to the logic verification results of the logic verification items.

5. The method for verifying semi-physical logic according to claim 1, wherein the logic control signal comprises a power supply control signal sent to a power supply control terminal, and the power supply control signal is used for controlling the embedded device to be verified to perform corresponding logic verification in different power supply states.

6. A method of verifying semi-physical logic, comprising:

downloading a logic verification case from an upper computer, and executing a logic execution instruction corresponding to a logic instruction set according to a preset execution strategy according to a logic instruction set corresponding to the logic verification case so as to send a corresponding logic control signal to the embedded device to be verified;

and analyzing the feedback data to obtain a logic verification result of the embedded equipment to be verified and sending the logic verification result to the upper computer.

7. A host computer comprising a first memory and a first processor, wherein a computer readable program is stored in the first memory, and the first processor implements the semi-physical logic verification method according to any one of claims 1 to 5 when the computer readable program is executed.

8. A control board comprising a second memory and a second processor, wherein the second memory stores a computer readable program, and the second processor implements the semi-physical logic verification method of claim 6 when executing the computer readable program.

9. A semi-physical logic verification system, which is characterized by comprising the upper computer and a control board in communication connection with the upper computer, wherein the control board is in communication connection with embedded equipment to be verified; or alternatively, the first and second heat exchangers may be,

a control board and an upper computer in communication connection with the control board, wherein the control board is in communication connection with an embedded device to be verified.

10. A computer readable storage medium, characterized in that it has stored thereon a computer program which, when executed by a processor, implements the semi-physical logic verification method according to any one of claims 1 to 6.