CN117460259A

CN117460259A - Chip assembly structure and forming method thereof

Info

Publication number: CN117460259A
Application number: CN202311259030.XA
Authority: CN
Inventors: 野口紘希; 王奕
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-10-03
Filing date: 2023-09-26
Publication date: 2024-01-26

Abstract

A chip assembly structure and method of forming the same is provided, the structure including a first chip-containing structure and a second chip-containing structure. The first chip-containing structure includes a back-end-of-line (BEOL) memory die that includes an array of memory cells and a metal interconnect structure electrically connected to corresponding nodes of the array of memory cells. The BEOL memory die does not have any semiconductor material portions or the lateral extent of each semiconductor material portion within the BEOL memory die is less than the lateral extent of each memory cell within the array of memory cells. The first chip-containing structure includes first bond structures, and a subset of the first bond structures are electrically connected to metal interconnect structures in the BEOL memory die. The second chip-containing structure includes a control circuit including a field effect transistor configured to control operation of the memory cell array and further including a second bonding structure. The second bonding structure is bonded to the first bonding structure by metal-to-metal bonding or through substrate via mediated bonding.

Description

Chip assembly structure and forming method thereof

Technical Field

Embodiments of the present application relate to chip assembly structures and methods of forming the same.

Background

The memory array requires control circuitry to control the operation of the memory cells within the memory array. The control circuit requires the formation of a field effect transistor on the semiconductor substrate. Accordingly, control circuitry is formed on a semiconductor substrate and a memory array is formed within a back end of line (BEOL) structure overlying the control circuitry. This approach produces a device in which the memory array and control circuitry are integrated within the same semiconductor die.

Disclosure of Invention

According to an aspect of an embodiment of the present application, there is provided a chip assembly structure including: a first chip-containing structure comprising a back-end-of-line (BEOL) memory die, the BEOL memory die comprising an array of memory cells and metal interconnect structures electrically connected to corresponding nodes of the array of memory cells, wherein the BEOL memory die is devoid of any semiconductor material portion or the lateral extent of each semiconductor material portion within the BEOL memory die is less than the lateral extent of each memory cell within the array of memory cells, the first chip-containing structure comprising a first bond structure, and a subset of the first bond structures are electrically connected to the metal interconnect structures in the BEOL memory die; and a second chip-containing structure including a control circuit including a field effect transistor configured to control operation of the memory cell array and further including a second bonding structure; wherein the second bonding structure is bonded to the first bonding structure by metal-to-metal bonding or through substrate via mediated bonding.

According to an aspect of an embodiment of the present application, there is provided a chip assembly structure including: a first chip-containing structure comprising a back-end-of-line (BEOL) memory die, the BEOL memory die comprising an array of memory cells and metal interconnect structures electrically connected to corresponding nodes of the array of memory cells, wherein the BEOL memory die does not contain any field effect transistors, the first chip-containing structure comprises a first bond structure, and a subset of the first bond structures are electrically connected to the metal interconnect structures in the BEOL memory die; and a second chip-containing structure including a control circuit including a field effect transistor configured to control operation of the memory cell array and further including a second bonding structure, wherein the second bonding structure is bonded to the first bonding structure by metal-to-metal bonding or through substrate via-mediated bonding.

According to one aspect of embodiments of the present application, there is provided a method of forming a chip assembly structure, the method comprising: forming a first chip-containing structure comprising a back-end-of-line (BEOL) memory die, wherein the BEOL memory die comprises an array of memory cells and metal interconnect structures electrically connected to corresponding nodes of the array of memory cells, wherein the BEOL memory die is devoid of any semiconductor material portion or each semiconductor material portion within the BEOL memory die has a lateral extent that is less than a lateral extent of each memory cell within the array of memory cells, and a subset of the first bond structures are electrically connected to the metal interconnect structures in the BEOL memory die; providing a second chip-containing structure comprising a control circuit comprising a field effect transistor configured to control operation of the memory cell array and further comprising a second bonding structure; and bonding the second chip-containing structure to the first chip-containing structure by inducing a metal-to-metal bond or a through substrate via mediated bond between the second bonding structure and the first bonding structure.

Drawings

The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a vertical cross-sectional view of a chip assembly structure including a first chip-containing structure and a second chip-containing structure according to an embodiment of the present disclosure.

Fig. 2A illustrates a first configuration of a chip assembly structure according to an embodiment of the present disclosure.

Fig. 2B illustrates a second configuration of a chip assembly structure according to an embodiment of the present disclosure.

Fig. 3A is a perspective view of an assembly of a first chip-containing structure and a second chip-containing structure including a single die-to-die connection region, in accordance with an embodiment of the present disclosure.

Fig. 3B is a perspective view of an assembly of a first chip-containing structure and a second chip-containing structure that includes two die-to-die connection regions, in accordance with an embodiment of the present disclosure.

Fig. 3C is a schematic top view of the region of the first chip-containing structure of fig. 3B.

FIG. 3D is a perspective view of components electrically connected to a memory cell in an assembly of a first chip-containing structure and a second chip-containing structure, where the memory cell is a three terminal device connected to a word line and two bit lines.

Fig. 3E is a schematic vertical cross-sectional view of the engagement assembly of fig. 3D.

Fig. 4 is an exemplary layout of a through substrate via structure that may be used in a chip assembly structure according to an embodiment of the present disclosure.

Fig. 5 is an exemplary layout of a bond pad array that may be used for hybrid bonding of a chip assembly structure according to an embodiment of the present disclosure.

Fig. 6A-6F illustrate various configurations of a first chip-containing structure in embodiments in which the first chip-containing structure includes a redistribution structure, according to embodiments of the present disclosure.

Fig. 7A-7G illustrate various configurations of a first chip-containing structure in an embodiment in which the first chip-containing structure includes an interposer, according to an embodiment of the present disclosure.

Fig. 8A and 8B illustrate various configurations of a first chip-containing structure in an embodiment of a chip assembly in which the first chip-containing structure does not include a redistribution structure and an interposer, according to an embodiment of the present disclosure.

Fig. 9 is a schematic vertical cross-sectional view of a memory-containing die and a peripheral die that may be used in a chip assembly structure according to an embodiment of the disclosure.

Fig. 10A is a schematic vertical cross-sectional view of a chip assembly structure including two memory die and a peripheral die, in accordance with an embodiment of the disclosure.

Fig. 10B is a schematic vertical cross-sectional view of a chip assembly structure including a memory die and a peripheral die, in accordance with an embodiment of the disclosure.

Fig. 10C is a schematic vertical cross-sectional view of another chip assembly structure including a memory die and a peripheral die, in accordance with an embodiment of the disclosure.

Fig. 11 illustrates the formation of a backside substrate through-hole structure on the backside of a peripheral die that may be used in the chip assembly structure of the present disclosure.

Fig. 12 is a flowchart illustrating general processing steps for manufacturing a chip assembly structure according to an embodiment of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, for ease of description, spaced relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations shown in the drawings, the term spaced apart relationship is intended to include different orientations of the device in use or operation. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spaced apart relationship descriptors used herein interpreted accordingly. Unless otherwise indicated, elements having the same reference numerals refer to the same elements and are assumed to have the same material composition and the same thickness range.

In general, the various embodiment structures and methods disclosed herein can be used to form a chip assembly structure in which a memory array and peripheral circuitry controlling operation of the memory array can be implemented in different semiconductor dies. The memory array may be implemented in a back-end-of-line (BEOL) memory die without any front-end-of-line device components, such as a semiconductor substrate. Peripheral circuitry may be implemented in front end of line (FEOL) device die including a semiconductor substrate. A first chip-containing structure including a BEOL memory die is prepared and a second chip-containing structure including a FEOL device die is provided. The first chip-containing structure and the second chip-containing structure may be integrated into the chip assembly structure using die-to-die (D2D) connections. In some embodiments, the first chip-containing structure may include at least one additional BEOL memory die, at least one logic die, a redistribution structure, and/or an interposer structure.

Since the memory array and peripheral circuitry may be disposed in different semiconductor die, one set of processing steps for fabricating the BEOL memory die and the set of processing steps for fabricating the FEOL device die may be independently selected, i.e., without regard to the impact of another set of processing steps for forming another semiconductor die on device performance. Thus, a set of processing steps for fabricating a BEOL memory die may be optimized without regard to the set of processing steps for fabricating a FEOL device die, and vice versa. This provides independent optimization of BEOL memory die and FEOL device die. For example, BEOL memory dies may be optimized with emphasis on the density of memory cells, and FEOL device dies may be optimized during operation with emphasis on device speed, reduction in process variability, and reliability of semiconductor devices (including but not limited to reliability of the device with respect to supply voltage variations). Furthermore, separate fabrication and optimization of BEOL memory die and FEOL device die may provide a low cost high performance chip assembly structure. Various embodiments of the present disclosure are now described with reference to the drawings.

Referring to fig. 1, a chip assembly structure including a first chip-containing structure 100 and a second chip-containing structure 200 is shown, according to an embodiment of the present disclosure. The first chip-containing structure 100 includes a back-end-of-line (BEOL) memory die (not explicitly shown) that includes an array of memory cells and metal interconnect structures electrically connected to corresponding nodes of the memory cells. The first chip-containing structure 100 may be comprised of BEOL memory dies or may include at least one additional component, such as at least one additional BEOL memory die, at least one logic die, at least one redistribution structure, and/or at least one interposer, such as at least an organic interposer.

As used herein, "back-end-of-line component" or "BEOL component" refers to any component formed at the contact level or metal interconnect level. A "metal interconnect level" refers to a level through which a metal interconnect structure, such as a metal line or metal via structure, extends vertically. As used herein, "front end of line component" or "FEOL component" refers to any component that is formed prior to forming any contact level structure if the contact level structure is subsequently formed, or without forming any contact level structure or any metal interconnect structure (i.e., without subsequently forming any contact level structure or any metal interconnect structure).

In general, FEOL components refer to semiconductor device components that may be formed during a CMOS fabrication process prior to forming any contact via structures on a node of a field effect transistor, BEOL components refer to semiconductor device components that are formed during or after an earliest contact via formation process that forms a contact via structure on a node of a field effect transistor. In embodiments that integrate any non-conventional fabrication steps into a CMOS fabrication process, the component formed after any contact via structures are formed on the nodes of the field effect transistor is a FEOL component; and the component formed during or after the earliest contact via formation process that forms the contact via structure on the node of the field effect transistor is the BEOL assembly.

Generally, FEOL components can be formed within a semiconductor substrate, directly on a semiconductor substrate, or indirectly on a semiconductor base without any intervening metal interconnect structure between the semiconductor substrate and the component. Examples of FEOL components include planar field effect transistors, fin field effect transistors, full-gate field effect transistors, which use a portion of a semiconductor substrate as part of a channel, and any device component that includes a portion of the semiconductor substrate having a lateral extent that is greater than the lateral extent of the corresponding device component. Typically, for each FEOL component, no metal interconnect structure extends vertically from a first level comprising a top surface of the FEOL component to a second level comprising a bottom surface of the FEOL component, or the FEOL component contacts or is laterally surrounded by a layer of semiconductor material having a larger lateral extent than the FEOL component.

Any components formed during or after the earliest contact via structure formation are BEOL components. Examples of BEOL components include any dielectric material layer embedded in a metal via structure or embedded in a metal line structure, any metal interconnect structure, memory cells formed without any portion of a semiconductor substrate, selector cells formed without any portion of a semiconductor substrate, thin film transistors formed without any portion of a semiconductor substrate (but may include patterned semiconductor material portions having lateral extents that do not exceed the lateral extents of individual thin film transistors or of a merged thin film transistor cluster), and bond pads. Typically, for each BEOL assembly, at least one metal interconnect structure extends vertically from a first level including a top surface of the BEOL assembly to a second level including a bottom surface of the BEOL assembly, and the BEOL assembly does not contact and is not laterally surrounded by a layer of semiconductor material having a greater lateral extent than the BEOL assembly.

As used herein, "back-end-of-line memory die" or "BEOL memory die" refers to a die that includes a memory array and that includes back-end-of-line components but not front-end-of-line components. In other words, the BEOL memory die does not contain any FEOL components and includes a memory array and BEOL components. As a corollary, the BEOL memory die does not contain any semiconductor material portions, or in embodiments where there are any semiconductor material portions within the BEOL memory die, the lateral extent of each semiconductor material portion within the BEOL memory die is less than the lateral extent of each memory cell within the array of memory cells. In other words, in embodiments where there are any semiconductor material portions within the BEOL memory die, each such semiconductor material portion has a lateral extent that is smaller than the lateral extent of any individual memory cell within the BEOL memory die. The lateral extent of each memory cell within a BEOL memory die may be calculated by the pitch (periodicity) of the BEOL memory die and is the greater of two-dimensional pitches of the memory cells along two different horizontal directions, or in the embodiment of a one-dimensional array, is a one-dimensional pitch.

The first chip-containing structure 100 includes a first bonding structure 180. At least a subset of the first bond structures 180 are electrically connected to metal interconnect structures in the BEOL memory die. In one embodiment, the first bond structure 180 may be laterally surrounded by a first bond level dielectric layer 160, which first bond level dielectric layer 160 may include a dielectric material (such as silicon oxide) that may provide a dielectric-to-dielectric bond, or may include a passivating dielectric material (such as silicon nitride or silicon carbide nitride).

According to an aspect of the present disclosure, a second chip-containing structure 200 is provided. The second chip-containing structure 200 may include a control circuit-containing die including control circuitry including field effect transistors configured to control operation of the memory cell array in the BEOL memory die. Further, the second chip-containing structure 200 includes a second bonding structure 280, the second bonding structure 280 being configured to provide die-to-die bonding with the first bonding structure 180 in the first chip-containing structure 100.

According to an aspect of the present disclosure, die-to-die bonding used between the first chip-containing structure 100 and the second chip-containing structure may use metal-to-metal bonding or through substrate via-mediated bonding.

As used herein, "metal-to-metal bonding" refers to a bonding method and bonding structure wherein the bonding structure is formed by direct contact between a first metal surface and a second metal surface and interdiffusion of metal atoms across a bonding interface between the first metal surface and the second metal surface. An exemplary metal-to-metal bond is a copper-to-copper bond. In embodiments where die-to-die bonding uses metal-to-metal bonding, the first bonding structure 180 (such as a first copper bonding pad) is directly bonded to the second bonding structure 280 (such as a second copper bonding pad).

In one embodiment, the dielectric bond between pairs of dielectric material layers may be used in combination with a metal-to-metal bond. This type of joint is referred to herein as a hybrid joint. Typically, hybrid bonding uses metal-to-metal bonding and dielectric-to-dielectric bonding. In embodiments using hybrid bonding, the first bonding structure 180 may be embedded in the first bond level dielectric layer 160 and the second bonding structure 280 may be embedded in the second bond level dielectric layer 260. The first bond level dielectric layer 160 may be bonded to the second bond level dielectric layer 260 by a dielectric-to-dielectric bond such as a silicon oxide-to-silicon oxide bond.

As used herein, "through substrate via mediated bonding" refers to a bonding method or bonding structure in which an array of through substrate via structures extending vertically through an embedded matrix material is used to provide bonding between a first die and a second die such that an array of solder material portions provides bonding between bonding pads in the first die and the through substrate via structures. In one embodiment, the array of through substrate via structures may be embedded in a substrate (which may be a semiconductor substrate or a dielectric substrate) and may be attached to the second die by an additional array of solder material portions that are bonded to a corresponding pair of through substrate via structures and pads in the second die. Alternatively, an array of through substrate via structures may be located within the second semiconductor die.

In an illustrative example, a substrate 300 including an array of Through Substrate Via (TSV) structures 380 may be provided, a first array of solder material portions 190 may be used to attach the first bonding structure 180 to the array of TSV structures 380, and a second array of solder material portions 290 may be used to attach the second bonding structure 280 to the array of TSV structures 380. In another illustrative example, the array of TSV structures 380 may include a first bonding structure 180. In other words, the first bonding structure 180 may be formed as an array of TSV structures 380. In this embodiment, an array of solder material portions 190 may be used to provide a bond between the first bond structure 180 (which is TSV structure 380) and the second bond structure 280. In yet another illustrative example, the array of TSV structures 380 may include a second bonding structure 280. In other words, the second bonding structure 280 may be formed as an array of TSV structures 380. In this embodiment, an array of solder material portions 190 may be used to provide a bond between the first bond structure 180 and the second bond structure 280 (which is TSV structure 380).

Typically, the electrical nodes of the BEOL memory die may be connected to the electrical nodes containing the control circuit die by an array of TSV structures 380 or by metal-to-metal bonding between pairs of bonding structures (180, 280). Electrical connections may be provided for all bit lines and all word lines in a memory array within a BEOL memory die. The control-containing circuit die may include the entire control circuitry of the BEOL memory die. For example, the control-containing circuit die may include all peripheral circuits including, but not limited to, bit line drivers, word line drivers, sense amplifiers, design for testability (DFT) circuits, scan chain circuits, built-in self-test (BIST) circuits, error Correction Circuits (ECC), phase-locked loop (PLL) circuits, electrically programmable fuse (e-fuse) circuits, input/output (IO) circuits, voltage generator (power supply) circuits, and the like.

Generally, a front side (i.e., top surface) or a back side (i.e., bottom surface) of the first chip-containing structure 100 may be used to form the first bonding structure 180. Similarly, the front side (i.e., top surface) or back side (i.e., bottom surface) of the second chip-containing structure 200 may be used to form the second bonding structure 280. As such, the second chip-containing structure 200 may be bonded to the first chip-containing structure 100 using a front-to-front bond, a front-to-back bond, a back-to-front bond, or a back-to-back bond. Furthermore, as will be set forth in detail below, at least one additional structure other than a BEOL memory die may also be integrated, and the first chip-containing structure 100 may include at least one additional BEOL memory die, at least one logic die, a redistribution structure, and/or an interposer structure.

Referring to fig. 2A, a first configuration of a chip assembly structure according to an embodiment of the present disclosure is shown. In a first configuration, the first chip-containing structure 100 is comprised of a single BEOL memory die. A single BEOL memory die includes a memory array, such as a two-dimensional memory array or a three-dimensional memory array, formed within a layer of dielectric material. Die-to-die connection interconnect structures (including first bond structures 180 embedded within first bond level dielectric material layer 160) may be formed within BEOL memory dies. The die-to-die interconnect structure is also referred to as a "D2D connection". The first engagement structure 180 may be provided in any of the configurations discussed with reference to fig. 1. The first bonding structure 180 may be used to bond the BEOL memory die to the peripheral die through the second bonding structure 280 in a manner consistent with the description of fig. 1.

Referring to fig. 2B, a second configuration of a chip assembly structure according to an embodiment of the present disclosure is shown. In a second configuration, the first chip-containing structure 100 includes a plurality of BEOL memory dies vertically stacked and interconnected with each other. Each of the plurality of BEOL memory dies includes a respective memory array, such as a two-dimensional memory array or a three-dimensional memory array formed within a respective set of layers of dielectric material. The bottommost BEOL memory die includes die-to-die connection interconnect structures (including first bond structures 180 embedded within first bond level dielectric material layer 160). The first engagement structure 180 may be provided in any of the configurations discussed with reference to fig. 1. Each vertically adjacent pair of BEOL memory dies may be interconnected to each other by additional die-to-die connection structures.

For example, a first BEOL memory die within each vertically adjacent pair of BEOL memory dies may include a third bond structure 480 embedded in a third bond level dielectric layer 460, and a second BEOL memory die within each vertically adjacent pair of BEOL memory dies may include a fourth bond structure 580 embedded in a fourth bond level dielectric layer 560. The third bond structure 480 may be bonded to the fourth bond structure 580 by metal-to-metal bonding or through substrate via mediated bonding. In one embodiment, the third bond structure 480 may be bonded to the fourth bond structure 580 by a metal-to-metal bond, and the third bond level dielectric layer 460 may be bonded to the first bond level dielectric layer 560 by a dielectric bond. In one embodiment, one, more, or each vertically adjacent pair of BEOL memory dies may be bonded by hybrid bonding.

Alternatively or additionally, one, more or each vertically adjacent pair of BEOL memory dies may be bonded via a through substrate via mediated bond. For example, a substrate 600 may be provided that includes an array of Through Substrate Via (TSV) structures 680, a third array of solder material portions 490 may be used to attach a third bonding structure 480 to the array of TSV structures 680, and a fourth array of solder material portions 590 may be used to attach a fourth bonding structure 580 to the array of TSV structures 680. In another illustrative example, the array of TSV structures 680 may include a third bonding structure 480. In other words, the third bonding structure 480 may be formed as an array of TSV structures 680. In this embodiment, an array of solder material portions 490 may be used to provide a bond between a third bond structure 480 (which is TSV structure 680) and a fourth bond structure 580. In yet another illustrative example, the array of TSV structures 680 may include a fourth bonding structure 580. In other words, the fourth bonding structure 580 may be formed as an array of TSV structures 680. In this embodiment, an array of solder material portions 490 may be used to provide a bond between the third bond structure 480 and a fourth bond structure 580 (which is a TSV structure 680).

Referring to fig. 3A, the area around the bonding interface between the first chip-containing structure and the second chip-containing structure is shown in a perspective view. A die-to-die connection structure, such as a through substrate via structure or a hybrid bond structure, may be used to provide a conductive path between the first chip-containing structure and the second chip-containing structure. The first chip-containing structure includes a BEOL memory die and may optionally include at least one additional BEOL memory die, at least one logic die, a redistribution structure, and/or an interposer structure. The second chip-containing structure includes a control-containing circuit die including control circuitry for each memory array within the at least one BEOL memory die. The die-to-die connection structure may provide electrical connections for each component of the control circuit (such as a word line driver, sense amplifier, etc.). The control-containing circuit die may include various peripheral circuits that are not directly related to the operation of the memory array in the at least one BEOL memory die. For example, the various peripheral circuits may include high voltage circuits and/or analog circuits. In some embodiments, control circuitry in the control-containing circuit die may be configured to control each of the memory arrays located within the stack of the plurality of BEOL memory dies. In this embodiment, the total die area containing the control circuit die may be reduced by sharing the control circuit with multiple memory arrays.

The first chip-containing structure may include a two-dimensional array of memory elements. In embodiments in which the memory elements are two-terminal memory devices, word Lines (WL) and Bit Lines (BL) may be used to access each two-terminal memory device. The die-to-die connection structure for the bit lines is explicitly shown in fig. 3A, and the die-to-die connection structure for the word lines is not explicitly shown, but such die-to-die connection structure for the word lines exists in the bonding assembly and provides electrical connection between the two chip-containing bonding structures. In general, the layout of the first and second engagement structures 180, 280 may be optimized as desired.

Referring to fig. 3B and 3C, in an embodiment in which the first chip-containing structure may include a two-dimensional array of memory elements and the memory elements are three-terminal memory devices, portions of the bonding assembly are shown. In this embodiment, a Word Line (WL), a first bit line (BL 1), and a second bit line (BL 2) may be used to access each three-terminal memory device. In the illustrated configuration, the first bit line and the second bit line may be formed on the same level. The die-to-die connection structure for the first bit line and the die-to-die connection structure for the second bit line are explicitly shown in fig. 3B and 3C, although such die-to-die connection structure for the word line exists in the bonding assembly and provides electrical connection between the two chip-containing bonding structures.

Referring to fig. 3D and 3E, in an embodiment in which the first chip-containing structure may include a two-dimensional array of memory elements and the memory elements are three-terminal memory devices, portions of the bonding assembly are shown. In this embodiment, a Word Line (WL), a first bit line (BL 1), and a second bit line (BL 2) may be used to access each three-terminal memory device. In the illustrated configuration, the first bit line and the second bit line may be formed at different levels and thus spaced apart from the second chip-containing structure by different vertical distances. The die-to-die connection structure for the first bit line and the die-to-die connection structure for the second bit line are explicitly shown in fig. 3D and 3E, although such die-to-die connection structure for the word line exists in the bonding assembly and provides electrical connection between the two chip-containing bonding structures.

Referring to fig. 4, in an embodiment in which an array of TSV structures 380 may be used as a die-to-die connection structure, an exemplary layout for a Through Substrate Via (TSV) structure 380 is shown. In embodiments where the array of TSV structures 380 may be used as a die-to-die connection structure, dedicated regions for forming the die-to-die connection structure may be formed outside of the region of the memory array (i.e., the array region). In one embodiment, each TSV structure 380 may have a height that is greater than the lateral dimension (i.e., the maximum lateral dimension). In one embodiment, TSV structures 380 may have a corresponding cylindrical shape or a corresponding pillar shape. While such area overhead is required, stacks of multiple BEOL memory dies can be formed without any further area penalty (i.e., without any additional device area overhead). In this embodiment, a single control circuit in the control-containing circuit die may control multiple memory arrays located within a stack of multiple BEOL memory dies. In a non-limiting illustrative example, the control circuit may include a Word Line Driver (WLDRV), a Sense Amplifier (SA), a Multiplexer (MUX), an input output circuit (IO), an Error Correction Circuit (ECC), and various peripheral circuits.

Referring to fig. 5, an exemplary layout for a bond pad array is shown that may be used for hybrid bonding of chip assembly structures according to embodiments of the present disclosure. In this embodiment, the first and second bonding structures 180 and 280 may include bonding pads. In one embodiment, each bond pad may have a respective lateral dimension that is greater than the height. Forming the first and second bonding structures 180, 280 as bond pads does not add any overhead to the BEOL memory die. As described above, dielectric-to-dielectric bonding may be used between the first chip-containing structure 100 and the second chip-containing structure 200 along with metal-to-metal bonding used between the mating of the bonding structures (180, 280). In this embodiment, the first chip-containing structure 100 and the second chip-containing structure 200 may be bonded to each other by hybrid bonding. Hybrid bonding may provide high-speed, high-bandwidth connections between pairs of chips. In one embodiment, a single BEOL memory die may be attached to a control-containing circuit die. In one embodiment, the bond between the first chip-containing structure 100 and the second chip-containing structure 200 may be a front-side-to-front (F2F) bond.

Referring collectively to fig. 1-5, in accordance with various embodiments of the present disclosure, there is provided a chip assembly structure comprising: a first chip-containing structure 100 comprising a back-end-of-line (BEOL) memory die comprising an array of memory cells and metal interconnect structures electrically connected to corresponding nodes of the memory cells, wherein the BEOL memory die is devoid of any semiconductor material portion or each semiconductor material portion within the BEOL memory die has a lateral extent that is less than a lateral extent of each memory cell within the array of memory cells, the first chip-containing structure 100 comprises a first bonding structure 180, and a subset of the first bonding structures 180 are electrically connected to the metal interconnect structures in the BEOL memory die; and a second chip-containing structure 200 comprising control circuitry including field effect transistors configured to control operation of the memory cell array, and further comprising a second bonding structure 280, wherein the second bonding structure 280 is bonded to the first bonding structure 180 by metal-to-metal bonding or through substrate via-mediated bonding.

In one embodiment, at least one set of bonding structures selected from the first bonding structure 180 and the second bonding structure 280 includes an array of Through Substrate Via (TSV) structures, with a corresponding height of the TSV being greater than a corresponding lateral dimension.

In one embodiment, at least one set of bonding structures selected from the first bonding structure 180 and the second bonding structure 280 comprises an array of metal bonding pads having a corresponding lateral dimension greater than a corresponding thickness.

In one embodiment, the first bond structure 180 is laterally surrounded by the first bond level dielectric layer 160; the second bond structure 280 is laterally surrounded by the second bond level dielectric layer 260; and the second bond level dielectric layer 260 is bonded to the first bond level dielectric layer 160 by dielectric-to-dielectric bonding, for example, in embodiments of hybrid bonding between the first chip-containing structure 100 and the second chip-containing structure 200.

In one embodiment, the first bond structure 180 is laterally surrounded by the first bond level dielectric layer 160; the second bond structure 280 is laterally surrounded by the second bond level dielectric layer 260; and the second bond level dielectric layer 200 is vertically spaced apart from the first bond level dielectric layer 160 by a gap, such as, for example, in embodiments where through-substrate vias mediate bonding between the first chip-containing structure 100 and the second chip-containing structure 200.

In one embodiment, the BEOL memory die is devoid of any field effect transistor. In one embodiment, the BEOL memory die does not contain any semiconductor material.

Typically, BEOL memory dies do not contain any FEOL components. Thus, the BEOL memory die does not contain any semiconductor substrate. In one embodiment, the array of memory cells and the metal interconnect structure in the BEOL memory die are laterally surrounded by a set of dielectric material layers of the BEOL memory die; and the set of dielectric material layers extends continuously from the bottom surface of the BEOL memory die to the top surface of the BEOL memory die without a space between any adjacent pair of dielectric material layers within the set of dielectric material layers. In other words, any point on the dielectric bottom surface of the BEOL memory die may be connected to any point on the dielectric top surface of the BEOL memory die by a respective continuous path that extends only through the set of dielectric material layers.

In one embodiment, the control circuitry includes Complementary Metal Oxide Semiconductor (CMOS) circuitry on a single crystal semiconductor substrate, and the additional metal interconnect structure is located between the CMOS circuitry and the second bonding structure 280.

In one embodiment, the first bond structure 180 is located within a BEOL memory die.

According to another aspect of the present disclosure, there is provided a chip assembly structure including: a first chip-containing structure 100 comprising a back-end-of-line (BEOL) memory die comprising an array of memory cells and metal interconnect structures electrically connected to corresponding nodes of the memory cells, wherein the BEOL memory die is devoid of any field effect transistors, the first chip-containing structure 100 comprises first bond structures 180, and a subset of the first bond structures 180 are electrically connected to the metal interconnect structures in the BEOL memory die; and a second chip-containing structure 200 comprising control circuitry including field effect transistors configured to control operation of the memory cell array, and further comprising a second bonding structure 280, wherein the second bonding structure 280 is bonded to the first bonding structure 180 by metal-to-metal bonding or through substrate via-mediated bonding.

In one embodiment, the memory cell array and the metal interconnect structure are laterally surrounded by a set of layers of dielectric material; and the set of dielectric material layers extends continuously from the bottom surface of the BEOL memory die to the top surface of the BEOL memory die without a space between any adjacent pair of dielectric material layers within the set of dielectric material layers.

In general, the first chip-containing structure may include at least one additional BEOL memory die, at least one redistribution structure, at least one interposer structure, and/or at least one logic die.

Fig. 6A-6E illustrate various configurations of a first chip-containing structure in an embodiment, the first chip-containing structure including a redistribution structure according to an embodiment of the present disclosure.

A redistribution structure refers to a collection of redistribution interconnect structures embedded within at least one redistribution dielectric layer (at least one RDL layer). Each of the redistribution dielectric layers may comprise a polymeric material or silicate glass (e.g., undoped silicate glass or doped silicate glass). The redistribution interconnect structure may be formed by depositing and patterning a metallic material. In one embodiment, at least one semiconductor die of the plurality of semiconductor dies may be molded in a molding compound die frame (not explicitly shown), and a redistribution structure may be formed over a combination of the molding compound die frame and the at least one semiconductor die. In this embodiment, a subset of the redistribution interconnect structures may be formed directly on the metal bonding structures on the at least one semiconductor die. In another embodiment, a redistribution structure may be formed on a carrier substrate, and at least one semiconductor die, which may be a plurality of semiconductor dies, may be attached to the redistribution structure using at least one underfill material portion and an optional molding compound die frame.

Referring to fig. 6A, a configuration of a first chip-containing structure is shown, which corresponds to an embodiment in which the BEOL memory die and Application Processor (AP) logic die are attached to M instances of a combination of redistribution structures. The integer M is positive, i.e., 1, 2, 3, 4, etc. Die-to-die connection structures, such as first bonding structures 180, may be formed on the distal side of the redistribution structure away from the BEOL memory die. The redistribution dielectric layer may be the first junction level dielectric layer 160.

Referring to fig. 6B, a configuration of a first chip-containing structure is shown, which corresponds to an embodiment in which a plurality of BEOL memory dies and Application Processor (AP) logic dies are attached to M instances of a combination of redistribution structures. The integer M is positive, i.e., 1, 2, 3, 4, etc. Die-to-die connection structures, such as first bonding structures 180, may be formed on the distal side of the redistribution structure away from the BEOL memory die. The redistribution dielectric layer may be the first junction level dielectric layer 160.

In some embodiments, an insulator through-hole (TIV) structure may be used in conjunction with the molding compound die frame to provide additional vertical signal paths.

Referring to fig. 6C, a configuration of a first chip-containing structure is shown, which corresponds to an embodiment in which the BEOL memory die and Application Processor (AP) logic die are attached to M instances of a combination of redistribution structures. The integer M is positive, i.e., 1, 2, 3, 4, etc. Furthermore, the TIV structure is embedded within a mold compound die frame that laterally surrounds the BEOL memory die and the AP logic die. For example, at least one semiconductor die may be attached to M instances of a combination of BEOL memory die and AP logic die using an array of at least one solder material portion or using any other chip attachment method. In the example shown, the dynamic random access die is attached to M instances of a combination of BEOL memory die and AP logic die. Die-to-die connection structures such as first bonding structure 180 may be formed on the distal side of the redistribution structure away from the BEOL memory die. The redistribution dielectric layer may be the first junction level dielectric layer 160.

Referring to fig. 6D, a configuration of a first chip-containing structure is shown, which corresponds to an embodiment in which the BEOL memory die and Application Processor (AP) logic die are attached to M instances of a combination of redistribution structures. The integer M is positive, i.e., 1, 2, 3, 4, etc. Furthermore, the TIV structure is embedded within a mold compound die frame that laterally surrounds the BEOL memory die and the AP logic die. By forming additional redistribution structures directly on the M instances of the combination of BEOL memory die and AP logic die, for example, additional redistribution structures may be attached to the M instances of the combination of BEOL memory die and AP logic die. Die-to-die connection structures such as first bonding structure 180 may be formed on the distal side of the redistribution structure away from the BEOL memory die. The redistribution dielectric layer may be the first junction level dielectric layer 160.

Referring to fig. 6E, a configuration of a first chip-containing structure is shown that can be derived from the configuration shown in fig. 6D by attaching additional semiconductor dies to the additional redistribution structure. In the example shown, the additional semiconductor die may include an AP logic die. Multiple AP logic dies and additional memory dies (e.g., BEOL memory dies; not shown) may be attached to the additional redistribution structure.

Referring to fig. 6F, a configuration of a first chip-containing structure is shown that may be derived from the configuration shown in fig. 6E by exchanging the positions of the BEOL memory die and the AP logic die.

Referring collectively to fig. 6A-6F, the first chip-containing structure 100 may or may not include a redistribution structure having a redistribution dielectric layer and a redistribution routing interconnect; the first engagement structure 180 is located within the redistribution structure; and the BEOL memory die is located on a redistribution structure on an opposite side of the second chip-containing structure 200. In some embodiments, a subset of metal interconnect structures within the BEOL memory die may contact a subset of redistribution routing interconnects.

An interposer refers to a structure comprising a set of redistribution interconnect structures (at least one RDL layer) embedded within at least one redistribution dielectric layer and provided with at least one set of bonding structures for solder bump bonding or metal-to-metal bonding on at least one side. The interposer may comprise an organic interposer or a ceramic interposer. Each of the redistribution dielectric layers may comprise a polymeric material or silicate glass (e.g., undoped silicate glass or doped silicate glass). The redistribution interconnect structure may be formed by depositing and patterning a metallic material. In one embodiment, at least one semiconductor die of the plurality of semiconductor dies may be attached to the interposer by an array of respective solder material portions (i.e., using solder bumps such as micro bumps). Alternatively or additionally, at least one semiconductor die of the plurality of semiconductor dies may be attached to the interposer by metal-to-metal bonding or through substrate via mediated bonding.

Referring to fig. 7A, a configuration of a first chip-containing structure is shown that corresponds to an embodiment in which M instances of a combination of BEOL memory die and Application Processor (AP) logic die are attached to an interposer. The integer M is positive, i.e., 1, 2, 3, 4, etc. A die-to-die connection structure, such as first bonding structure 180, may be formed on a distal side of the interposer away from the BEOL memory die. The redistribution dielectric layer within the interposer may be the first bond level dielectric layer 160.

Referring to fig. 7B, a configuration of a first chip-containing structure is shown that corresponds to an embodiment in which M instances of a combination of a plurality of BEOL memory dies and Application Processor (AP) logic dies are attached to an interposer. The integer M is positive, i.e., 1, 2, 3, 4, etc. A die-to-die connection structure, such as first bonding structure 180, may be formed on a distal side of the interposer away from the BEOL memory die. The redistribution dielectric layer within the interposer may be the first bond level dielectric layer 160.

Referring to fig. 7C, a configuration of a first chip-containing structure is shown that may be derived from the configuration shown in fig. 7A or 7B by forming a redistribution structure on one side of M instances of a combination of BEOL memory die and AP logic die, which are located on opposite sides of an interposer. Furthermore, additional semiconductor die may be attached to the redistribution structure. In the example shown, the additional semiconductor die may include M instances of at least one logic die (which may include an AP logic die). In one embodiment, a plurality of AP logic dies and additional memory dies (e.g., BEOL memory dies; not shown) may be attached to the redistribution structure. A die-to-die connection structure, such as first bonding structure 180, may be formed on a distal side of the interposer away from the BEOL memory die. The redistribution dielectric layer within the interposer may be the first bond level dielectric layer 160.

Referring to fig. 7D, a configuration of a first chip-containing structure is shown that can be derived from the structure shown in fig. 6A by attaching an interposer to the structure shown in fig. 6A. In this embodiment, the redistribution structure may be attached to the interposer via a metal-to-metal bond (e.g., a hybrid bond) or via a through-substrate via-mediated bond. A die-to-die connection structure, such as first bonding structure 180, may be formed on a distal side of the interposer away from the BEOL memory die. The redistribution dielectric layer within the interposer may be the first bond level dielectric layer 160.

Referring to fig. 7E, a configuration of a first chip-containing structure is shown that may be derived from the configuration shown in fig. 7A by replacing M instances of the combination of BEOL memory die and Application Processor (AP) logic die with a multi-layer stack comprising at least one BEOL memory die and logic die (e.g., AP logic die). The at least one BEOL memory die and the logic die may be interconnected to each other by an array of bump structures (e.g., micro-bump structures; not shown), by metal-to-metal bonding, or by through-substrate via-mediated bonding. Subsets of the interposer-facing semiconductor die within the multi-layer stack may be attached to the interposer via respective arrays of solder material portions (i.e., solder bumps). In one embodiment, one or more of the at least one BEOL memory die may be bonded to the interposer by a respective array of solder material portions, or alternatively, bonded by metal-to-metal bonding or via-substrate mediated bonding. In general, M instances of a multilayer stack of semiconductor die can be attached to an interposer, where M is a positive integer (e.g., 1, 2, 3, 4, etc.).

Referring to fig. 7F, a configuration of a first chip-containing structure is shown that can be derived from the configuration shown in fig. 7E by rearranging the positions of the semiconductor die within the multi-layer stack such that at least one BEOL memory die is indirectly attached to an interposer through at least one logic die (such as at least one AP logic die). In one embodiment, one or more of the at least one BEOL memory die may be directly bonded to a respective logic die by a respective array of solder material portions, or alternatively, bonded by metal-to-metal bonding or via-substrate mediated bonding. In general, M instances of a multilayer stack of semiconductor die can be attached to an interposer, where M is a positive integer (e.g., 1, 2, 3, 4, etc.).

Referring to fig. 7G, a configuration of a first chip-containing structure is shown that may be derived from the configuration shown in fig. 7E or from the configuration shown in fig. 7F by attaching at least one additional memory die (e.g., at least one dynamic random access memory die). In some embodiments, a vertical stack of N memory dies may be attached, where N is a positive integer. In one embodiment, one or more of the at least one BEOL memory die may be bonded directly or indirectly to the interposer through a respective array of solder material portions, or alternatively, bonded through metal-to-metal or through substrate through-hole mediated bonding. In general, M instances of a multilayer stack of semiconductor die can be attached to an interposer, where M is a positive integer (e.g., 1, 2, 3, 4, etc.). As described above, a die-to-die bonding structure, such as first bonding structure 180, may be formed on the distal side of the interposer away from the BEOL memory die. The redistribution dielectric layer within the interposer may be the first bond level dielectric layer 160.

Referring collectively to fig. 7A-7F, the first chip-containing structure 100 may include an interposer that includes a redistribution dielectric layer and a redistribution routing interconnect; the first bonding structure 180 is located within the interposer; the BEOL memory die is attached to the redistribution structure on the opposite side of the second chip-containing structure 200 via an array of solder material portions or via metal-to-metal bonding or via through-substrate via-mediated bonding.

Fig. 8A and 8B illustrate various configurations of a first chip-containing structure in an embodiment of a chip assembly in which the first chip-containing structure does not include a redistribution structure and an interposer, according to one embodiment of the present disclosure.

Referring to fig. 8A, a configuration of a first chip-containing structure is shown that corresponds to an embodiment of a vertical stack of the first chip-containing structure including at least one first level semiconductor die and at least one second level semiconductor die. Alternatively, multiple instances (e.g., M instances) of at least one semiconductor die may be implemented as a one-dimensional array or a two-dimensional array that repeats along a horizontal direction. A die-to-die connection structure, such as first bond structure 180, may be formed within at least one first level semiconductor die, and each of the at least one first level semiconductor die may include a respective layer of dielectric material that serves as first bond level dielectric layer 160. In one embodiment, the at least one second tier semiconductor die may comprise at least one BEOL memory die. In one embodiment, one or more of the at least one BEOL memory die may be directly bonded to a respective logic die by a respective array of solder material portions, or alternatively, bonded by metal-to-metal bonding or via-substrate mediated bonding.

Referring to fig. 8B, a configuration of a first chip-containing structure is shown that may be derived from the configuration shown in fig. 8A by placing at least one BEOL memory die at a first level. In other words, one or more of the at least one first level semiconductor die comprises one or more BEOL memory die. A die-to-die connection structure, such as first bonding structure 180, may be formed within at least one first level semiconductor die, and thus within one or more BEOL memory dies. Each of the at least one first level semiconductor die may include a respective layer of dielectric material that serves as a first bond level dielectric layer 160. In one embodiment, the at least one second tier semiconductor die may include at least one logic die, such as at least one AP logic die. In one embodiment, one or more of the at least one BEOL memory die may then be directly bonded to the second chip-containing structure 200 via metal-to-metal bonding or via through-substrate via-mediated bonding.

In general, each BEOL memory die may comprise any type of memory device known in the art as long as such memory device is not integrated with field effect transistors that require portions of a semiconductor substrate. For example, a dynamic random access memory device including a combination of a deep trench capacitor formed within a semiconductor substrate and an access field effect transistor using a portion of the semiconductor substrate as a channel is not used as a BEOL memory device of the present disclosure.

Fig. 9 is a schematic vertical cross-sectional view of a memory-containing die and a peripheral die that may be used in a chip assembly structure according to an embodiment of the disclosure. As described above, any memory cell that does not require a portion of a semiconductor substrate may be used as a memory cell within the BEOL memory die of the present disclosure. As a non-limiting illustrative example, each of the memory cells in the memory array of the BEOL memory die of the present disclosure may include a respective memory cell selected from the group consisting of: a resistive random access memory cell; a conductive bridge random access memory cell; a phase change memory cell; a magnetoresistive random access memory cell; a dynamic random access memory cell; ferroelectric random access memory cells.

Further, one, more, and/or each BEOL memory die within the first chip-containing structure 100 of the present disclosure may include an array of selector cells. In one embodiment, each selector cell is electrically connected to a respective memory cell within the array of memory cells; and each selector unit comprises a respective selector unit selected from the group consisting of: oxygen vacancy-based selector cells (which may or may not include a blocking oxide layer, such as an alumina layer); a diode selector unit (e.g., an NPN diode unit); a metal-insulator-metal (MIM) selector unit; and an Ovonic Threshold Switch (OTS) selector unit.

In general, any type of selector cell that can be formed as a BEOL assembly can be integrated into the BEOL memory die of the present disclosure. In one embodiment, switching devices, which may be fabricated as BEOL components, may be integrated into the BEOL memory die of the present disclosure. Such switching devices may include thin film transistors or tunneling field effect transistors using semiconductor metal oxide material portions having lateral extents that are no greater than the lateral extent of each memory cell, switching devices using two-dimensional materials such as nanowires or graphene, or any other BEOL switching device, i.e., switching devices that may be formed at the metal interconnect level.

As described above, the BEOL memory die does not contain any FEOL components. Therefore, the BEOL memory die is devoid of any semiconductor substrate. In one embodiment, the array of memory cells and the metal interconnect structure in the BEOL memory die are laterally surrounded by a set of dielectric material layers of the BEOL memory die; and the set of dielectric material layers extends continuously from the bottom surface of the BEOL memory die to the top surface of the BEOL memory die without a space between any adjacent pair of dielectric material layers within the set of dielectric material layers. In other words, any point on the dielectric bottom surface of the BEOL memory die may be connected to any point on the dielectric top surface of the BEOL memory die by a respective continuous path that extends only through the set of layers of dielectric material.

Fig. 10A is a schematic vertical cross-sectional view of a chip assembly structure including two memory die and a peripheral die, in accordance with an embodiment of the disclosure. In this example, multiple BEOL memory dies may share the same control circuitry located within a control-containing circuit die that is located within a second chip-containing structure. The control-containing circuit die and the first BEOL memory die may be connected to each other by metal-to-metal bonding or through-substrate via-mediated bonding. The second BEOL memory die may be connected to the first BEOL memory die by metal-to-metal bonding or through substrate via mediated bonding. In general, word line drivers may or may not be shared with multiple BEOL memory dies. The bit line drivers (and sense amplifiers) may or may not be shared with the plurality of BEOL memory die. Each BEOL memory die may include a respective array of memory cells and may optionally include a respective array of selector elements.

Fig. 10B and 10C are schematic vertical cross-sectional views of a chip assembly structure including a memory die and a peripheral die, according to an embodiment of the disclosure. In some embodiments, each memory device within a memory-containing die (such as a BEOL memory die) may include a series connection of a memory element and a selector element. The memory element and the selector element may be interconnected to each other by a respective metal interconnect structure, such as a metal via structure or a metal pad structure. The memory element may be above or below the selector element. In one embodiment, the memory element may be closer to the control-containing circuit die than the selector element to the control-containing circuit die. In one embodiment, the selector element may be closer to the control-containing circuit die than the selector element to the control-containing circuit die.

In general, a BEOL memory die may be composed of an array of memory devices (such as a two-dimensional array of memory devices), metal interconnect structures and metal pads electrically connected to the array of memory devices, and a layer of dielectric material embedded in the array of memory devices. The BEOL memory die may be devoid of any semiconductor substrate or any layer of semiconductor material. The BEOL memory die may be free of any semiconductor material unless the memory device includes a semiconductor material. Thus, in embodiments where the memory device does not contain any semiconductor material, the BEOL memory die may not contain any semiconductor material. In embodiments in which the memory device includes semiconductor material, any such semiconductor material may be embodied as a component of the memory device, and each portion of any semiconductor material in the BEOL memory die may have a spatial extent that is less than the spatial extent of a unit memory cell.

Referring to fig. 11, a backside substrate through-via structure may be selectively formed on the backside of the second chip-containing structure of the present disclosure. In this embodiment, the chip assembly structure of the present disclosure may be mounted on a package substrate using a backside substrate through-hole structure, or mounted on an interposer.

Referring to step 1210 and fig. 1-10C, a first chip-containing structure 100 may be formed that includes a back-end-of-line (BEOL) memory die that includes an array of memory cells and metal interconnect structures electrically connected to respective nodes of the memory cells. The BEOL memory die does not contain any semiconductor material portions or the lateral extent of each semiconductor material portion within the BEOL memory die is less than the lateral extent of each memory cell within the array of memory cells, the first chip-containing structure 100 includes a first bonding structure 180. A subset of the first bond structures 180 are electrically connected to metal interconnect structures in the BEOL memory die.

In one embodiment, the BEOL memory die does not contain any field effect transistors. In one embodiment, the first chip-containing structure 100 comprises a redistribution structure, interposer, or at least another semiconductor chip that is covered, underlying, or laterally surrounded by the same molding compound frame as the BEOL memory die.

Referring to step 1220 and fig. 1-5 and 9-11, a second chip-containing structure 200 is provided that includes a control circuit including a field effect transistor configured to control operation of the memory cell array and further including a second bonding structure 280.

Referring to step 1230 and fig. 1-11, the second chip-containing structure 200 may be bonded to the first chip-containing structure 100 by inducing a metal-to-metal bond between the second bonding structure 280 and the first bonding structure 180 or by through-substrate via-mediated bonding.

Referring to all of the drawings, according to one aspect of the present disclosure, a chip assembly structure of the present disclosure may include: a first chip-containing structure 100 comprising a back-end-of-line (BEOL) memory die comprising an array of memory cells and metal interconnect structures electrically connected to corresponding nodes of the array of memory cells, wherein the BEOL memory die does not have any semiconductor material portions or the lateral extent of each semiconductor material portion within the BEOL memory die is less than the lateral extent of each memory cell within the array of memory cells, the first chip-containing structure 100 comprises a first bonding structure 180, and a subset of the first bonding structures 180 are electrically connected to the metal interconnect structures in the BEOL memory die; and a second chip-containing structure 200 comprising control circuitry including field effect transistors configured to control operation of the memory cell array, and further comprising a second bonding structure 280, wherein the second bonding structure 280 is bonded to the first bonding structure 180 by metal-to-metal bonding or through substrate via-mediated bonding.

In some embodiments, at least one set of bond structures selected from the first bond structure and the second bond structure includes an array of through substrate via TSV structures, the TSV structures having respective heights that are greater than respective lateral dimensions.

In some embodiments, at least one set of bonding structures selected from the first bonding structure and the second bonding structure comprises an array of metal bonding pads having a corresponding lateral dimension greater than a corresponding thickness.

In some embodiments, the first bond structure is laterally surrounded by a first bond level dielectric layer; the second bonding structure is laterally surrounded by a second bonding level dielectric layer; and the second bond level dielectric layer is bonded to the first bond level dielectric layer by a dielectric-to-dielectric bond.

In some embodiments, the first bond structure is laterally surrounded by a first bond level dielectric layer; the second bonding structure is laterally surrounded by a second bonding level dielectric layer; and the second bond level dielectric layer is vertically spaced apart from the first bond level dielectric layer by a gap.

In some embodiments, the BEOL memory die does not contain any field effect transistors.

In some embodiments, the BEOL memory die does not contain any semiconductor material.

In some embodiments, the memory cell array and the metal interconnect structure are laterally surrounded by a set of layers of dielectric material; and the set of dielectric material layers extends continuously from the bottom surface of the BEOL memory die to the top surface of the BEOL memory die without a space between any adjacent pair of dielectric material layers within the set of dielectric material layers.

In some embodiments, the control circuit includes a Complementary Metal Oxide Semiconductor (CMOS) circuit on a single crystal semiconductor substrate; and an additional metal interconnect structure is located between the CMOS circuit and the second bonding structure.

In some embodiments, the first chip-containing structure includes a redistribution structure including a redistribution dielectric layer and a redistribution routing interconnect; the first engagement structure is located within the redistribution structure; and the BEOL memory die is located on a redistribution structure on an opposite side of the second chip-containing structure.

In some embodiments, the first chip-containing structure includes an interposer that includes a redistribution dielectric layer and a redistribution routing interconnect; the first bonding structure is positioned in the interposer; and the BEOL memory die is attached to the interposer on an opposite side of the second chip-containing structure via an array of solder material portions or via metal-to-metal bonding or through-substrate via-mediated bonding.

In some embodiments, the first bond structure is located within the BEOL memory die.

With reference to all the figures, according to another aspect of the present disclosure, there is provided a chip assembly structure comprising: a first chip-containing structure 100 comprising a back-end-of-line (BEOL) memory die comprising an array of memory cells and metal interconnect structures electrically connected to corresponding nodes of the array of memory cells, wherein the BEOL memory die does not contain any field effect transistors, the first chip-containing structure 100 comprises first bond structures 180, and a subset of the first bond structures 180 are electrically connected to metal interconnect structures in the BEOL memory die; and a second chip-containing structure 200 comprising control circuitry including field effect transistors configured to control operation of the memory cell array, and further comprising a second bonding structure 280, wherein the second bonding structure 280 is bonded to the first bonding structure 180 by metal-to-metal bonding or through substrate via-mediated bonding.

In some embodiments, each memory cell in the array of memory cells includes a corresponding memory cell selected from the group consisting of: a resistive random access memory cell; a conductive bridge random access memory cell; a phase change memory cell; a magnetoresistive random access memory cell; a dynamic random access memory cell; and ferroelectric random access memory cells.

In some embodiments, the BEOL memory die further comprises an array of selector cells, wherein: each selector cell in the array of selector cells is electrically connected to a corresponding memory cell within the array of memory cells; and each selector cell in the array of selector cells comprises a corresponding selector cell selected from the group consisting of: an oxygen vacancy based selector unit; a diode selector unit; a metal-insulator-metal selector unit; and an bidirectional threshold switch selector unit.

According to another aspect of the present disclosure, there is provided a method of forming a chip assembly structure, the method comprising: forming a first chip-containing structure comprising a back-end-of-line (BEOL) memory die, wherein the BEOL memory die comprises an array of memory cells and metal interconnect structures electrically connected to corresponding nodes of the array of memory cells, wherein the BEOL memory die is devoid of any semiconductor material portion or each semiconductor material portion within the BEOL memory die has a lateral extent that is less than a lateral extent of each memory cell within the array of memory cells, and a subset of the first bond structures are electrically connected to the metal interconnect structures in the BEOL memory die; providing a second chip-containing structure comprising a control circuit comprising a field effect transistor configured to control operation of the memory cell array and further comprising a second bonding structure; and bonding the second chip-containing structure to the first chip-containing structure by inducing a metal-to-metal bond or a through substrate via mediated bond between the second bonding structure and the first bonding structure.

In some embodiments, the first chip-containing structure includes a redistribution structure, an interposer, or at least another semiconductor chip, located above, formed below, or laterally surrounded by a molding compound frame that is the same as the BEOL memory die.

Various embodiments of the present disclosure may be used to fabricate semiconductor devices that include BEOL memory dies, i.e., memory dies that are composed of only BEOL components and that are free of FEOL components. The fabrication process of the BEOL memory die of the present disclosure may be optimized without regard to any performance degradation of FEOL devices used to control the operation of memory arrays in BEOL memory chips. By separating all FEOL devices from the BEOL memory die, the BEOL memory die may be fabricated to obtain optimal performance of the memory device. The BEOL memory die may be bonded into a first chip-containing structure and the control circuitry provided within a control-containing circuit die, which may be or may be bonded within a second chip-containing structure. The first chip-containing structure and the second chip-containing structure may be bonded to each other by metal-to-metal bonding or through-substrate via-mediated bonding.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A chip assembly structure, comprising:

a first chip-containing structure comprising a back-end-of-line memory die comprising an array of memory cells and metal interconnect structures electrically connected to corresponding nodes of the array of memory cells, wherein the back-end-of-line memory die is devoid of any semiconductor material portion or each semiconductor material portion within the back-end-of-line memory die has a lateral extent that is less than a lateral extent of each memory cell within the array of memory cells, the first chip-containing structure comprises a first bonding structure, and a subset of the first bonding structures are electrically connected to the metal interconnect structures in the back-end-of-line memory die; and

A second chip-containing structure comprising a control circuit including a field effect transistor configured to control operation of the memory cell array and further comprising a second bonding structure;

wherein the second bonding structure is bonded to the first bonding structure by metal-to-metal bonding or through substrate via mediated bonding.

2. The chip assembly structure of claim 1, wherein at least one set of bond structures selected from the first bond structure and the second bond structure comprises an array of through-substrate via structures having respective heights that are greater than respective lateral dimensions.

3. The chip assembly structure of claim 1, wherein at least one set of bond structures selected from the first bond structure and the second bond structure comprises an array of metal bond pads having a corresponding lateral dimension greater than a corresponding thickness.

4. The chip assembly structure of claim 1, wherein:

the first bond structure is laterally surrounded by a first bond level dielectric layer;

the second bond structure is laterally surrounded by a second bond level dielectric layer; and

The second bond level dielectric layer is bonded to the first bond level dielectric layer by a dielectric-to-dielectric bond.

5. The chip assembly structure of claim 1, wherein:

the second bond level dielectric layer is vertically spaced apart from the first bond level dielectric layer by a gap.

6. The chip assembly structure of claim 1 wherein the back-end-of-line memory die is free of any field effect transistors.

7. The chip assembly structure of claim 1 wherein the back-end-of-line memory die is free of any semiconductor material.

8. The chip assembly structure of claim 1, wherein:

the memory cell array and the metal interconnect structure are laterally surrounded by a set of layers of dielectric material; and

the set of dielectric material layers extends continuously from the bottom surface of the back-end-of-line memory die to the top surface of the back-end-of-line memory die without spaces between any adjacent pair of dielectric material layers within the set of dielectric material layers.

9. A chip assembly structure, comprising:

a first chip-containing structure comprising a back-end-of-line memory die comprising an array of memory cells and metal interconnect structures electrically connected to corresponding nodes of the array of memory cells, wherein the back-end-of-line memory die does not contain any field effect transistors, the first chip-containing structure comprises a first bonding structure, and a subset of the first bonding structures are electrically connected to the metal interconnect structures in the back-end-of-line memory die; and

a second chip-containing structure comprising a control circuit including a field effect transistor configured to control operation of the memory cell array and further comprising a second bonding structure,

10. A method of forming a chip assembly structure, the method comprising:

forming a first chip-containing structure comprising a back-end-of-line memory die, wherein the back-end-of-line memory die comprises an array of memory cells and metal interconnect structures electrically connected to corresponding nodes of the array of memory cells, wherein the back-end-of-line memory die has no semiconductor material portion or each semiconductor material portion within the back-end-of-line memory die has a lateral extent that is less than a lateral extent of each memory cell within the array of memory cells, and a subset of the first bonding structures is electrically connected to the metal interconnect structures in the back-end-of-line memory die;

Providing a second chip-containing structure comprising a control circuit comprising a field effect transistor configured to control operation of the memory cell array and further comprising a second bonding structure; and

the second chip-containing structure is bonded to the first chip-containing structure by inducing a metal-to-metal bond or a through substrate via mediated bond between the second bonding structure and the first bonding structure.