CN117457737A - Method for forming buried bit line, memory and manufacturing method thereof - Google Patents

Method for forming buried bit line, memory and manufacturing method thereof Download PDF

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Publication number
CN117457737A
CN117457737A CN202211268239.8A CN202211268239A CN117457737A CN 117457737 A CN117457737 A CN 117457737A CN 202211268239 A CN202211268239 A CN 202211268239A CN 117457737 A CN117457737 A CN 117457737A
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China
Prior art keywords
dielectric layer
layer
semiconductor
trench
substrate
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CN202211268239.8A
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Chinese (zh)
Inventor
刘朝
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Changxin Technology Group Co ltd
Beijing Superstring Academy of Memory Technology
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Changxin Technology Group Co ltd
Beijing Superstring Academy of Memory Technology
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Priority to CN202211268239.8A priority Critical patent/CN117457737A/en
Priority to PCT/CN2022/140176 priority patent/WO2024082422A1/en
Publication of CN117457737A publication Critical patent/CN117457737A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method of forming buried bit lines, a memory, and a method of manufacturing the same, the memory including a plurality of transistors, and: the first dielectric layer, the second dielectric layer and the third dielectric layer are sequentially arranged on the substrate, the first dielectric layer and the third dielectric layer are oxide layers, and the second dielectric layer is a nitride layer; a plurality of first grooves extending along the column direction and arranged at intervals in the row direction and a plurality of second grooves extending along the row direction and arranged at intervals in the column direction are arranged on the substrate, and the first grooves extend to a set depth in the second dielectric layer; a plurality of semiconductor columns in one-to-one correspondence with the transistors, arranged at intervals in a row direction and a column direction, each column of semiconductor columns being disposed in one first trench; and a plurality of bit lines disposed in the first trenches and extending in the column direction, the semiconductor pillars being located on and connected to the bit lines. The bit line of the memory is not easy to break, and is lower in resistance and better in stability.

Description

Method for forming buried bit line, memory and manufacturing method thereof
Technical Field
The present application relates to the field of memory, and more particularly, to a method of forming buried bit lines, a memory, and a method of manufacturing the same.
Background
As transistor sizes become smaller, short channel effects of metal oxide semiconductor field effect transistors (Metal Oxide Semiconductor Field Effect Transistor, MOSFETs) become more severe, impeding further device feature size scaling. In order to suppress the short channel effect, and continuing the moore's law, researchers have proposed various solutions, among which a Gate-All-Around Field Effect Transistor (GAAFET) has excellent Gate control capability and compatibility with the current transistor manufacturing process technology, and is highly competitive among many transistors. GAAFET can be classified into a planar structure and a Vertical structure (i.e., vertical Gate-All-Around Field Effect Transistor, vgafet)) according to the orientation of the channel. VGAAFET occupies a smaller area and has a greater advantage in 3D integration and routing.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the application.
The embodiment of the application provides a memory, which comprises a plurality of transistors and further comprises:
a substrate on which a first dielectric layer, a second dielectric layer and a third dielectric layer are sequentially arranged; the first dielectric layer and the third dielectric layer are oxide layers, and the second dielectric layer is a nitride layer; the substrate is also provided with a plurality of first grooves extending along the column direction and arranged at intervals in the row direction and a plurality of second grooves extending along the row direction and arranged at intervals in the column direction; each of the first trenches extends into the second dielectric layer in a direction perpendicular to the substrate by a set depth h1;
A plurality of semiconductor columns, each corresponding to a channel of one of the transistors, the semiconductor columns being arranged at intervals in a row direction and a column direction, each column of semiconductor columns being disposed in one of the first trenches, adjacent two rows of semiconductor columns being spaced apart by the second trench; each semiconductor column extends to be columnar along a direction perpendicular to the substrate;
and a plurality of bit lines extending along the column direction and distributed at intervals in the row direction, wherein the bit lines are arranged in the region corresponding to the second dielectric layer in the first trench, the semiconductor column is positioned on the bit lines in the first trench, and the bit lines are connected with the end part of the semiconductor column, which is close to the substrate.
In an embodiment of the present application, the material of the semiconductor pillar may be a metal oxide semiconductor material.
In an embodiment of the present application, the memory may further include a gate surrounding a sidewall of the semiconductor pillar and insulated from the semiconductor pillar by a gate insulating layer, the gate being connected to the word line.
In embodiments of the present application, the gate insulating layers on the opposite sidewalls of two adjacent semiconductor pillars may be connected together.
In an embodiment of the present application, the memory may further include a fourth dielectric layer disposed in the second trench and between the bit line and the gate insulating layer.
In an embodiment of the present application, the memory may further include a fifth dielectric layer disposed in the second trench and located between a surface of the gate near one end of the substrate and the gate insulating layer.
In an embodiment of the present application, the memory may further include a sixth dielectric layer disposed between two gates of the same second trench, spacing the two gates apart.
In an embodiment of the present application, the fourth dielectric layer may include a first sub-dielectric layer and a second sub-dielectric layer, the first sub-dielectric layer is disposed between an inner wall of the second trench and the second sub-dielectric layer, and materials of the first sub-dielectric layer and the second sub-dielectric layer are the same or different.
In an embodiment of the present application, the material of the bit line may be metal;
the materials of the first dielectric layer and the third dielectric layer may be each independently selected from any one or more of silicon oxide and silicon oxycarbonitride;
The material of the second dielectric layer may be selected from any one or more of silicon nitride and silicon carbonitride.
In an embodiment of the present application, the materials of the fourth dielectric layer, the fifth dielectric layer, and the sixth dielectric layer may each be independently selected from any one or more of silicon oxide, silicon nitride, silicon carbonitride oxide, and silicon carbonitride.
In an embodiment of the present application, the memory may further include a first barrier layer disposed between the semiconductor pillar and a portion of the sidewall of the first trench above the bit line.
In an embodiment of the present application, the memory may further include an adhesion layer disposed on an inner wall of a region where the bit line is located in the first trench, and a second barrier layer disposed between the adhesion layer and the bit line.
The embodiment of the application also provides a method for forming the buried bit line, which comprises the following steps:
providing a substrate;
sequentially depositing a first dielectric layer, a second dielectric layer and a third dielectric layer on the substrate, wherein the first dielectric layer and the third dielectric layer are oxide layers, and the second dielectric layer is a nitride layer and is provided with an upper surface far away from the substrate;
Etching a plurality of first grooves extending along the column direction and arranged at intervals in the row direction on the third dielectric layer, and enabling the first grooves to expose the upper surface of the second dielectric layer, wherein the first grooves divide the third dielectric layer into a plurality of blocking walls at intervals;
depositing a sacrificial barrier layer on the inner wall of the first trench;
etching the sacrificial blocking layer positioned on the upper surface of the second dielectric layer in the first groove to expose the upper surface of the second dielectric layer, and etching the exposed second dielectric layer to enable the first groove to extend to a set depth h1 in the second dielectric layer in the direction perpendicular to the substrate;
filling bit line materials in the first grooves;
removing the sacrificial barrier layer in the first trench and the bit line material of the region corresponding to the third dielectric layer in the first trench, the bit line material of the region corresponding to the second dielectric layer in the first trench forming a bit line extending in a column direction;
a first barrier layer is deposited on sidewalls of the corresponding region of the third dielectric layer in the first trench, and a semiconductor layer is deposited in the first trench, the bit line being buried between the semiconductor layer and the second dielectric layer.
The embodiment of the application also provides a manufacturing method of the memory, which comprises the following steps:
providing a substrate;
sequentially depositing a first dielectric layer, a second dielectric layer and a third dielectric layer on the substrate, wherein the first dielectric layer and the third dielectric layer are oxide layers, and the second dielectric layer is a nitride layer and is provided with an upper surface far away from the substrate;
etching a plurality of first grooves extending along the column direction and arranged at intervals in the row direction on the third dielectric layer, and enabling the first grooves to expose the upper surface of the second dielectric layer, wherein the first grooves divide the third dielectric layer into a plurality of blocking walls at intervals;
depositing a sacrificial barrier layer on the inner wall of the first trench;
etching the sacrificial blocking layer positioned on the upper surface of the second dielectric layer in the first groove to expose the upper surface of the second dielectric layer, and etching the exposed second dielectric layer to enable the first groove to extend to a set depth h1 in the second dielectric layer in the direction perpendicular to the substrate;
filling bit line materials in the first grooves;
removing the sacrificial barrier layer in the first trench and the bit line material of the region corresponding to the third dielectric layer in the first trench, the bit line material of the region corresponding to the second dielectric layer in the first trench forming a bit line extending in a column direction;
Depositing a first barrier layer on sidewalls of the corresponding region of the third dielectric layer in the first trench, and depositing a semiconductor layer in the first trench, the bit line being buried between the semiconductor layer and the second dielectric layer;
etching a plurality of second grooves which extend in the row direction and are arranged at intervals in the column direction in the barrier wall and the semiconductor layer, and enabling the second grooves to expose the upper surface of the bit line, wherein the second grooves divide the semiconductor layer into a plurality of semiconductor columns at intervals, the semiconductor columns extend into columns along the direction perpendicular to the substrate, and the end parts, close to the substrate, of the semiconductor columns are connected with the bit line;
depositing a fourth dielectric layer in the second trench;
removing the first barrier layer, the third dielectric layer and the fourth dielectric layer which are positioned at the upper part between two adjacent semiconductor columns, and exposing the side wall of the whole upper part of each semiconductor column;
sequentially depositing a gate insulating layer and a fifth dielectric layer on the surface of the substrate, wherein the gate insulating layer and the fifth dielectric layer cover the exposed surfaces of the semiconductor column, the third dielectric layer and the fourth dielectric layer, and depositing a sixth dielectric layer on the surface of the substrate, wherein the sixth dielectric layer covers the fifth dielectric layer and fills the residual space of the second trench;
Removing the sixth dielectric layer and the gate insulating layer which are positioned on the upper part between the surface of the semiconductor column and the adjacent two semiconductor columns, removing the fifth dielectric layer on the side walls of the semiconductor columns, and depositing gate materials in the space which is formed after the fifth dielectric layer on the side walls of the semiconductor columns is removed, so as to form a gate surrounding each side wall of the semiconductor column;
and depositing a seventh dielectric layer on the surface of the substrate, wherein the seventh dielectric layer covers the surface of the semiconductor column, the surface of the gate insulating layer and the surface of the gate electrode, so as to obtain the memory.
According to the memory provided by the embodiment of the application, the bit line is buried in the nitride layer below the semiconductor column, so that on one hand, the aggregation phenomenon easily occurring when the bit line is formed in the silicon substrate can be avoided, and on the other hand, the space of the memory can be saved, and the storage density of the memory can be improved; moreover, a bit line can be formed in one first groove, and compared with the bit line formed by connecting tungsten tips in a plurality of grooves in a tip-to-tip mode, the bit line of the memory is not easy to break, and is lower in resistance and better in stability.
According to the method for forming the buried bit line, before the first groove extends into the second dielectric layer, the sacrificial blocking layer is deposited on the inner wall of the first groove, when the first groove extends into the second dielectric layer through etching later and the bit line such as tungsten is formed through back etching, the sacrificial blocking layer can serve as a protective layer of the blocking wall, the blocking wall is prevented from being etched, a high etching selection ratio is not needed, and the process can be simplified.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The accompanying drawings are included to provide an understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.
Fig. 1 is a schematic longitudinal sectional structure of a memory according to an exemplary embodiment of the present application in a front view direction;
FIG. 2 is a schematic longitudinal cross-sectional view of the memory of FIG. 1 in a side view;
FIG. 3 is a schematic three-dimensional structure of the memory of FIG. 1;
fig. 4A is a schematic view of a longitudinal cross-sectional structure in a side view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory according to an exemplary embodiment of the present application;
fig. 4B is a schematic view of a longitudinal cross-sectional structure in a side view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory according to an exemplary embodiment of the present application;
fig. 4C is a schematic view of a longitudinal cross-sectional structure in a side view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory according to an exemplary embodiment of the present application;
fig. 4D is a schematic view of a longitudinal cross-sectional structure in a side view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory according to an exemplary embodiment of the present application;
fig. 4E is a schematic view of a longitudinal cross-sectional structure in a side view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory according to an exemplary embodiment of the present application;
fig. 4F is a schematic view of a longitudinal cross-sectional structure in a side view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory according to an exemplary embodiment of the present application;
fig. 4G is a schematic view of a longitudinal cross-sectional structure in a side view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory according to an exemplary embodiment of the present application;
Fig. 4H is a schematic view of a longitudinal cross-sectional structure in a side view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory according to an exemplary embodiment of the present application;
fig. 4I is a schematic view showing a longitudinal cross-sectional structure in a front view direction of an intermediate product obtained in an intermediate step of a method for manufacturing a memory according to an exemplary embodiment of the present application;
fig. 4J is a schematic view of a longitudinal section in a front view direction of an intermediate product obtained in an intermediate step of a method for manufacturing a memory according to an exemplary embodiment of the present application;
fig. 4K is a schematic view showing a longitudinal cross-sectional structure in a front view direction of an intermediate product obtained in an intermediate step of a method for manufacturing a memory according to an exemplary embodiment of the present application;
fig. 4L is a schematic view of a longitudinal cross-sectional structure in a side view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory according to an exemplary embodiment of the present application;
fig. 4M is a schematic view of a longitudinal cross-sectional structure in a front view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory according to an exemplary embodiment of the present application;
fig. 4N is a schematic view of a longitudinal cross-sectional structure of an intermediate product obtained in an intermediate step of a method for manufacturing a memory according to an exemplary embodiment of the present application in a front view direction.
The meaning of the individual reference symbols in the drawings is:
10-a substrate; 20-semiconductor pillars; a 20' -semiconductor layer; 21-source regions; 22-channel region; 23-drain region; 30-bit lines; a 30' -bit wire material; 41-a first dielectric layer; 42-a second dielectric layer; 43-a third dielectric layer; 44-a fourth dielectric layer; 441-a first sub-dielectric layer; 442-a second sub-dielectric layer; 45-a fifth dielectric layer; 46-a sixth dielectric layer; 47-seventh dielectric layer; 51-a first trench; 52-a second trench; 60-grid electrode; 70-a gate insulation layer; 81-a first barrier layer; 82-a sacrificial barrier layer;
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail hereinafter with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be arbitrarily combined with each other.
The embodiments herein may be embodied in a number of different forms. One of ordinary skill in the art will readily recognize the fact that the implementations and content may be transformed into a wide variety of forms without departing from the spirit and scope of the present application. Therefore, the present application should not be construed as being limited to the following description of the embodiments. Embodiments and features of embodiments in this application may be combined with each other arbitrarily without conflict.
The scale of the drawings in this application may be referred to in the actual process, but is not limited thereto. For example: the width-to-length ratio of the semiconductor layer, the thickness and the spacing of each film layer can be adjusted according to actual needs. The drawings described in the present application are only schematic in structure, and one mode of the present application is not limited to the shapes or the numerical values shown in the drawings, etc.
In the present specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, which indicate an azimuth or a positional relationship, are used to describe positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application. The positional relationship of the constituent elements is appropriately changed according to the direction in which the respective constituent elements are described. Therefore, the present invention is not limited to the words described in the specification, and may be appropriately replaced according to circumstances.
In this specification, the terms "disposed," "connected," and "connected" are to be construed broadly, unless explicitly stated or limited otherwise. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In the description of the present application, ordinal numbers such as "first", "second", etc., are provided to avoid intermixing of constituent elements, and are not intended to be limiting in terms of number.
In this specification, "film" and "layer" may be exchanged with each other. For example, the "dielectric layer" may be replaced with "dielectric film" in some cases.
Buried Bit Lines (BBLs) may be formed using the following method: forming grooves capable of spacing the silicon substrate into a plurality of silicon columns (pilar) on the silicon substrate, etching the bottoms of the grooves to form oval grooves, depositing titanium (Ti) on the inner walls of the grooves, reacting the titanium (Ti) with silicon in the silicon substrate to form titanium silicon (TiSi), filling tungsten (W) into the grooves to electrically connect tungsten in two adjacent grooves, and etching excessive tungsten above the grooves by etching back. The bit line is buried in the silicon substrate by the process flow, and the agglomeration of titanium is easy to occur in the silicon substrate, and the deposition thickness of the titanium needs to be controlled to prevent the agglomeration phenomenon, so that the process has high requirements on conditions. In addition, the bit line is formed by electrically connecting tungsten arranged in a plurality of grooves, the contact surface between the adjacent grooves is small, and if the tungsten in one groove and the tungsten in the adjacent groove are not effectively connected, the whole bit line is broken. Moreover, a high selectivity is required in the tungsten etch back process to prevent the semiconductor pillars from being etched away.
The embodiment of the application provides a memory, which comprises a plurality of transistors and further comprises:
a substrate on which a first dielectric layer, a second dielectric layer and a third dielectric layer are sequentially arranged; the first dielectric layer and the third dielectric layer are oxide layers, and the second dielectric layer is a nitride layer; the substrate is also provided with a plurality of first grooves extending along the column direction and arranged at intervals in the row direction and a plurality of second grooves extending along the row direction and arranged at intervals in the column direction; each of the first trenches extends into the second dielectric layer in a direction perpendicular to the substrate by a set depth h1;
a plurality of semiconductor columns, each corresponding to a channel of one of the transistors, the semiconductor columns being arranged at intervals in a row direction and a column direction, each column of semiconductor columns being disposed in one of the first trenches, adjacent two rows of semiconductor columns being spaced apart by the second trench; each semiconductor column extends to be columnar along a direction perpendicular to the substrate;
and a plurality of bit lines extending along the column direction and distributed at intervals in the row direction, wherein the bit lines are arranged in the region corresponding to the second dielectric layer in the first trench, the semiconductor column is positioned on the bit lines in the first trench, and the bit lines are connected with the end part of the semiconductor column, which is close to the substrate.
According to the memory provided by the embodiment of the application, the bit line is buried in the nitride layer below the semiconductor column, so that on one hand, the aggregation phenomenon easily occurring when the bit line is formed in the silicon substrate can be avoided, and on the other hand, the space of the memory can be saved, and the storage density of the memory can be improved; moreover, a bit line can be formed in one first groove, and compared with the bit line formed by connecting tungsten tips in a plurality of grooves in a tip-to-tip mode, the bit line of the memory is not easy to break, and is lower in resistance and better in stability.
Fig. 1 is a schematic longitudinal sectional structure of a memory according to an exemplary embodiment of the present application in a front view direction; FIG. 2 is a schematic longitudinal cross-sectional view of the memory of FIG. 1 in a side view; fig. 3 is a schematic three-dimensional structure of the memory of fig. 1. As shown in fig. 1 to 3, in an exemplary embodiment of the present application, the memory includes a plurality of transistors, and may further include: a substrate 10, a plurality of semiconductor pillars 20, and a plurality of bit lines 30;
a first dielectric layer 41, a second dielectric layer 42 and a third dielectric layer 43 are sequentially disposed on the substrate 10, the first dielectric layer 41 and the third dielectric layer 43 are oxide layers, and the second dielectric layer 42 is a nitride layer; the substrate 10 is provided thereon with a plurality of first trenches 51 extending in the column direction and arranged at intervals in the row direction and a plurality of second trenches 52 extending in the row direction and arranged at intervals in the column direction, as shown in fig. 1 and 2, the first trenches 51 may be provided in the third dielectric layer 43, and each of the first trenches 51 may extend into the second dielectric layer 42 by a set depth h1 in a direction perpendicular to the substrate 10, and the second trenches 52 may be provided in the third dielectric layer 43;
A plurality of semiconductor pillars 20 are arranged at intervals in the row direction and the column direction, each semiconductor pillar 20 corresponds to a channel of one of the transistors, each column of semiconductor pillars 20 is disposed in one first trench 51, and two adjacent rows of semiconductor pillars 20 are spaced apart by a second trench 52; each semiconductor pillar 20 extends in a pillar shape along a direction perpendicular to the substrate 10, and each semiconductor pillar 20 may sequentially include a source region 21, a channel region 22, and a drain region 23 along a direction perpendicular to the substrate 10;
a plurality of bit lines 30 extend in the column direction and are spaced apart in the row direction, the bit lines 30 are disposed in the first trenches 51 in regions corresponding to the second dielectric layers 42, the semiconductor pillars 20 are located on the bit lines 30 in the first trenches 51, the bit lines 30 are connected to ends of the semiconductor pillars 20 near the substrate 10, the bit lines 30 are connected to the source regions 21 in the memory shown in fig. 1 and 2, and the bit lines 30 may be connected to the drain regions 23 in the memory of other embodiments.
In embodiments of the present application, the depth h1 of the first trench extending into the second dielectric layer may be smaller than the thickness of the second dielectric layer.
In an embodiment of the present application, the second trench may expose a surface of the bit line on a side away from the substrate, that is, the second trench stops on a surface of the bit line on a side away from the substrate.
In an embodiment of the present application, the material of the semiconductor pillar may be a metal oxide semiconductor material.
For example, the material of the semiconductor pillar may be selected from indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), zinc stannate (ZTO), indium zinc oxide (Indium Zinc Oxide, IZO), zinc oxide (ZnO) x ) Indium tungsten oxide (InWO), indium zinc tin oxide (Indium Zinc Tin Oxide, IZTO), indium oxide (InO) x For example, in 2 O 3 ) Tin oxide (SnO) x For example, snO 2 ) Titanium oxide (TiO) x ) Zinc oxynitride (Zn) x O y N z ) Magnesium zinc oxide (Mg) x Zn y O z ) Zirconium indium zinc oxide (Zr) x In y Zn z O a ) Hafnium indium zinc oxide (Hf) x In y Zn z O a ) Aluminum tin indium zinc oxide (Al x Sn y In z Zn a O d ) Indium zinc silicon oxide (Si x In y Zn z O a ) Aluminum zinc tin oxide (Al x Zn y Sn z O a ) Gallium zinc tin oxide%Ga x Zn y Sn z O a ) Zirconium zinc tin oxide (Zr) x Zn y Sn z O a ) And indium gallium silicon oxide (InGaSiO) x ) For another example, the material of the semiconductor pillar may be IGZO, and compared with the existing memory using monocrystalline silicon as the channel material, the memory using IGZO as the channel material can obtain lower resistance, higher current switching ratio and higher stability.
In an embodiment of the present application, as shown in fig. 1 and 2, the memory may further include a gate 60, where the gate 60 is disposed on a sidewall of the semiconductor pillar 20, for example, the gate 60 may be disposed on a sidewall of the channel 22 region and surrounds the channel region 22, the gate 60 is insulated from the semiconductor pillar 20 by a gate insulating layer 70, and the gate 60 is connected to a word line (not shown in the figures).
In the embodiment of the present application, the longitudinal sectional shape of the region corresponding to the second dielectric layer in the first trench may be the same at each position in the direction perpendicular to the extending direction of the first trench. In an embodiment of the present application, as shown in fig. 1 and 2, gate insulating layers 70 on opposite sidewalls of adjacent two semiconductor pillars 20 may be connected together.
In an embodiment of the present application, as shown in fig. 1, the memory may further include a fourth dielectric layer 44, where the fourth dielectric layer 44 is disposed in the second trench 52 and between the bit line 30 and the gate insulating layer 70.
In the embodiment of the present application, as shown in fig. 1, the fourth dielectric layer 44 may include a first sub-dielectric layer 441 and a second sub-dielectric layer 442, the first sub-dielectric layer 441 is disposed between the inner wall of the second trench 52 and the second sub-dielectric layer 442, and the materials of the first sub-dielectric layer 441 and the second sub-dielectric layer 442 are the same or different.
In an embodiment of the present application, as shown in fig. 1, the memory may further include a fifth dielectric layer 45, where the fifth dielectric layer 45 is disposed in the second trench 52 and is located between a surface of the gate 60 near one end of the substrate 10 and the gate insulating layer 70.
In an embodiment of the present application, as shown in fig. 1, the memory may further include a sixth dielectric layer 46, and a sixth dielectric layer 60 is disposed between two gates 60 of the same second trench 52, and separates the two gates 60.
In an embodiment of the present application, the material of the bit line may be a metal, for example, the material of the bit line may be selected from any one or more of tungsten, copper, and aluminum.
In an embodiment of the present application, the materials of the first dielectric layer and the third dielectric layer may be each independently selected from any one or more of silicon oxide and silicon oxycarbonitride;
the material of the second dielectric layer may be selected from any one or more of silicon nitride and silicon carbonitride.
The nitride layer may form a dense second dielectric layer that may prevent metal bit line material deposited in the first trench in a region corresponding to the second dielectric layer from penetrating into the second dielectric layer. The oxide layer forms the first dielectric layer to prevent the second dielectric layer formed by the nitride layer from contacting the silicon-containing substrate such as monocrystalline silicon. The third dielectric layer is formed by adopting a material different from the second dielectric layer, so that obvious limit can be formed between the second dielectric layer and the third dielectric layer, and the first trench can be controlled to stop on the surface of the second dielectric layer in the process of etching to form the first trench.
In an embodiment of the present application, the materials of the fourth dielectric layer, the fifth dielectric layer, and the sixth dielectric layer may each be independently selected from any one or more of silicon oxide, silicon nitride, silicon carbonitride oxide, and silicon carbonitride.
When the fourth dielectric layer includes the first sub-dielectric layer and the second sub-dielectric layer, the first sub-dielectric layer and the second sub-dielectric layer may be formed using different materials, respectively, or the first sub-dielectric layer and the second sub-dielectric layer may be formed using the same material.
In an embodiment of the present application, as shown in fig. 2, the memory may further include a first barrier layer 81, where the first barrier layer 81 is disposed between the semiconductor pillar 20 and a portion of the sidewall of the first trench 51 above the bit line.
In an embodiment of the present application, the material of the first blocking layer may be selected from any one or more of silicon nitride and silicon carbonitride. Nitride such as silicon nitride may form a dense first barrier layer to avoid penetration of subsequently deposited metal bit line material into the third dielectric layer.
In an embodiment of the present application, the memory device may further include an adhesion layer (not shown) disposed on an inner wall of a region where the bit line is located in the first trench, and a second barrier layer (not shown) disposed between the adhesion layer and the bit line.
In embodiments of the present application, the material of the second barrier layer may be selected from any one or more of titanium nitride (e.g., tiN) and tantalum nitride (e.g., taN); the thickness of the barrier layer may be 2nm to 2.5nm.
In the embodiment of the present application, the material of the adhesion layer may be selected from any one or more of titanium (Ti) and tantalum (Ta); the thickness of the adhesion layer may be 2nm to 2.5nm.
For example, when the material of the bit line is tungsten, the material of the second barrier layer may be titanium nitride, and the material of the adhesion layer may be titanium; when the material of the bit line is copper, the material of the second barrier layer may be tantalum nitride, and the material of the adhesion layer may be tantalum.
The second barrier layer can prevent the metal bit line material deposited later from penetrating into the third dielectric layer, but the second barrier layer formed by materials such as titanium nitride, tantalum nitride and the like has poor direct adhesion with the third dielectric layer, and the second barrier layer is easy to fall off, so that an adhesion layer is arranged between the third dielectric layer and the second barrier layer to improve the adhesion.
In an embodiment of the present application, the first trench may be perpendicular to the substrate, and the second trench may be perpendicular to the substrate.
In embodiments of the present application, the substrate may beAs monocrystalline Silicon substrates, and also as semiconductor-On-insulator (Semiconductor On Insulator, SOI) substrates, e.g. Silicon-On-sapphire (Silicon On Sapphire, SOS) substrates, silicon-On-Glass (SOG) substrates, epitaxial layers of Silicon or other semiconductor or optoelectronic materials based On base semiconductors, e.g. Silicon-germanium (Si) 1-x Ge x Where x may be, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP). The substrate may or may not be doped.
In the embodiment of the present application, the height of the semiconductor pillar in the direction perpendicular to the substrate may be set according to actual electrical requirements, for example, may be 10nm to 50nm.
In an embodiment of the present application, the material of the gate electrode may be selected from any one or more of titanium nitride (TiN), aluminum, and aluminum-containing alloy; or,
the material of the gate may be selected from any one or more of conductor materials formed by group IVA elements, for example, the material of the gate may be selected from any one or more of polysilicon, polysilicon germanium, and the like; alternatively, the material of the gate may be a metal oxide conductor material. The metal oxide conductor material and the metal oxide semiconductor material forming the semiconductor column are both metal oxide materials, and can be better compatible. For example, the material of the gate electrode may be Indium Tin Oxide (ITO) or the like, and the ITO material has a small resistance.
In embodiments of the present application, the material of the gate insulating layer may be selected from silicon oxide (e.g., siO 2 ) Hafnium oxide (e.g., hfO) 2 ) Zirconium oxide (e.g., zrO) and aluminum oxide (e.g., al) 2 O 3 ) Any one or more of the following. The gate insulating layer may have a single-layer structure or a multi-layer structure, and for example, may include a two-layer structure formed of silicon oxide and hafnium oxide, wherein the silicon oxide layer is in contact with the channel region and the hafnium oxide layer is in contact with the gate electrode. The thickness of the gate insulating layer may be set according to practical electrical requirements, for example, may be 2nm to 5nm.
In an embodiment of the present application, the transistor may be a Vertical gate-all-around (VGAA); the memory may be a transistor-containing device, such as dynamic random access memory (Dynamic Random Access Memory, DRAM), magnetic random access memory (Magnetic Random Access Memory, MRAM), or the like.
The embodiment of the application also provides a method for forming the buried bit line, which comprises the following steps:
providing a substrate;
sequentially depositing a first dielectric layer, a second dielectric layer and a third dielectric layer on the substrate, wherein the first dielectric layer and the third dielectric layer are oxide layers, and the second dielectric layer is a nitride layer and is provided with an upper surface far away from the substrate;
Etching a plurality of first grooves extending along the column direction and arranged at intervals in the row direction on the third dielectric layer, and enabling the first grooves to expose the upper surface of the second dielectric layer, wherein the first grooves divide the third dielectric layer into a plurality of blocking walls at intervals;
depositing a sacrificial barrier layer on the inner wall of the first trench;
etching the sacrificial blocking layer positioned on the upper surface of the second dielectric layer in the first groove to expose the upper surface of the second dielectric layer, and etching the exposed second dielectric layer to enable the first groove to extend to a set depth h1 in the second dielectric layer in the direction perpendicular to the substrate;
filling bit line materials in the first grooves;
removing the sacrificial barrier layer in the first trench and the bit line material of the region corresponding to the third dielectric layer in the first trench, the bit line material of the region corresponding to the second dielectric layer in the first trench forming a bit line extending in a column direction;
a first barrier layer is deposited on sidewalls of the corresponding region of the third dielectric layer in the first trench, and a semiconductor layer is deposited in the first trench, the bit line being buried between the semiconductor layer and the second dielectric layer.
According to the method for forming the buried bit line, before the first groove extends into the second dielectric layer, the sacrificial blocking layer is deposited on the inner wall of the first groove, when the first groove extends into the second dielectric layer through etching later and the bit line such as tungsten is formed through back etching, the sacrificial blocking layer can serve as a protective layer of the blocking wall, the blocking wall is prevented from being etched, a high etching selection ratio is not needed, and the process can be simplified.
The embodiment of the application also provides a manufacturing method of the memory, which comprises the following steps:
providing a substrate;
sequentially depositing a first dielectric layer, a second dielectric layer and a third dielectric layer on the substrate, wherein the first dielectric layer and the third dielectric layer are oxide layers, and the second dielectric layer is a nitride layer and is provided with an upper surface far away from the substrate;
etching a plurality of first grooves extending along the column direction and arranged at intervals in the row direction on the third dielectric layer, and enabling the first grooves to expose the upper surface of the second dielectric layer, wherein the first grooves divide the third dielectric layer into a plurality of blocking walls at intervals;
depositing a sacrificial barrier layer on the inner wall of the first trench;
Etching the sacrificial blocking layer positioned on the upper surface of the second dielectric layer in the first groove to expose the upper surface of the second dielectric layer, and etching the exposed second dielectric layer to enable the first groove to extend to a set depth h1 in the second dielectric layer in the direction perpendicular to the substrate;
filling bit line materials in the first grooves;
removing the sacrificial barrier layer in the first trench and the bit line material of the region corresponding to the third dielectric layer in the first trench, the bit line material of the region corresponding to the second dielectric layer in the first trench forming a bit line extending in a column direction;
depositing a first barrier layer on sidewalls of the corresponding region of the third dielectric layer in the first trench, and depositing a semiconductor layer in the first trench, the bit line being buried between the semiconductor layer and the second dielectric layer;
etching a plurality of second grooves which extend in the row direction and are arranged at intervals in the column direction in the barrier wall and the semiconductor layer, and enabling the second grooves to expose the upper surface of the bit line, wherein the second grooves divide the semiconductor layer into a plurality of semiconductor columns at intervals, the semiconductor columns extend into columns along the direction perpendicular to the substrate, and the end parts, close to the substrate, of the semiconductor columns are connected with the bit line;
Depositing a fourth dielectric layer in the second trench;
removing the first barrier layer, the third dielectric layer and the fourth dielectric layer which are positioned at the upper part between two adjacent semiconductor columns, and exposing the side wall of the whole upper part of each semiconductor column;
sequentially depositing a gate insulating layer and a fifth dielectric layer on the surface of the substrate, wherein the gate insulating layer and the fifth dielectric layer cover the exposed surfaces of the semiconductor column, the third dielectric layer and the fourth dielectric layer, and depositing a sixth dielectric layer on the surface of the substrate, wherein the sixth dielectric layer covers the fifth dielectric layer and fills the residual space of the second trench;
removing the sixth dielectric layer and the gate insulating layer which are positioned on the upper part between the surface of the semiconductor column and the adjacent two semiconductor columns, removing the fifth dielectric layer on the side walls of the semiconductor columns, and depositing gate materials in the space which is formed after the fifth dielectric layer on the side walls of the semiconductor columns is removed, so as to form a gate surrounding each side wall of the semiconductor column;
and depositing a seventh dielectric layer on the surface of the substrate, wherein the seventh dielectric layer covers the surface of the semiconductor column, the surface of the gate insulating layer and the surface of the gate electrode, so as to obtain the memory.
In an embodiment of the present application, the filling the bit line material in the first trench may include: and depositing an adhesion layer and a second barrier layer on the inner wall of the first groove in sequence, and filling bit line materials in the residual space of the first groove.
In an embodiment of the present application, the material of the first blocking layer may be selected from any one or more of silicon nitride, and silicon carbonitride.
In an embodiment of the present application, the depositing a fourth dielectric layer in the second trench includes: and depositing a first sub-dielectric layer on the inner wall (comprising the side wall and the bottom surface) of the second groove, filling the second sub-dielectric layer in the residual space of the second groove, and forming a fourth dielectric layer by the first sub-dielectric layer and the second sub-dielectric layer.
Fig. 4A to 4N are schematic longitudinal sectional structures of intermediate products obtained in an intermediate step of a method for manufacturing a memory according to an exemplary embodiment of the present application. As shown in fig. 4A to 4N and fig. 1 to 2, in an exemplary embodiment of the present application, the method of manufacturing a memory may include:
s10: providing a substrate 10, as shown in fig. 4A;
s20: sequentially depositing a first dielectric layer 41, a second dielectric layer 42 and a third dielectric layer 43 on the substrate 10 to obtain an intermediate product as shown in fig. 4B; wherein the first dielectric layer 41 and the third dielectric layer 43 are oxide layers, and the second dielectric layer 42 is a nitride layer;
S30: etching a plurality of first trenches 51 extending along the column direction and arranged at intervals in the row direction on the third dielectric layer 43, exposing the upper surface of the second dielectric layer 42 to the first trenches 51, and separating the third dielectric layer 43 into a plurality of barrier walls by the first trenches 51 to obtain an intermediate product as shown in fig. 4C;
s40: depositing a sacrificial barrier layer 82 on the surface of the substrate 10 to cover the surface of the third dielectric layer 43 and the inner walls (including the side walls and the bottom surface) of the first trench 51, thereby obtaining an intermediate product as shown in fig. 4D; wherein, the material of the sacrificial barrier layer 82 may be silicon nitride, and the thickness may be 5nm;
s50: etching the surface of the third dielectric layer 43 and the sacrificial barrier layer 82 located on the upper surface of the second dielectric layer 42 (i.e. the bottom surface of the first trench 51) in the first trench 51 to expose the upper surface of the second dielectric layer 42, and etching the exposed second dielectric layer 42 to enable the first trench 51 to extend to a set depth h1 in the second dielectric layer 42 in the direction perpendicular to the substrate 10, wherein the extended first trench 51 does not penetrate through the second dielectric layer 42, i.e. h1 is smaller than the thickness of the second dielectric layer 42, so as to obtain an intermediate product as shown in fig. 4E;
s60: an adhesion layer (not shown) and a second barrier layer (not shown) are sequentially deposited on the inner wall of the first trench 51, and the bit line material 30' is filled in the remaining space in the first trench 51, resulting in an intermediate product as shown in fig. 4F;
S70: removing the sacrificial barrier layer 82, the adhesion layer, the second barrier layer, and the bit line material 30' in the first trench 51 corresponding to the region of the third dielectric layer 43, leaving the bit line material 30' in the first trench 51 corresponding to the region of the second dielectric layer 42, and forming the bit line 30 extending in the column direction from the remaining bit line material 30', to obtain an intermediate product as shown in fig. 4G;
s80: depositing a first barrier layer 81 on the sidewalls of the region of the first trench 51 corresponding to the third dielectric layer 43, and depositing a semiconductor layer 20 'in the first trench 51, wherein the bit line 30 is buried between the semiconductor layer 20' and the second dielectric layer 42, to obtain an intermediate product as shown in fig. 4H; the materials of the first barrier layer 81 and the sacrificial barrier layer 82 may be the same, for example, silicon nitride, or different;
s90: etching a plurality of second trenches 52 extending in the row direction and arranged at intervals in the column direction in the barrier wall and the semiconductor layer 20', and exposing the second trenches 52 to the upper surface of the bit line 30, wherein the second trenches 52 space the semiconductor layer 20' into a plurality of semiconductor pillars 20, the semiconductor pillars 20 extend in a direction perpendicular to the substrate 10 to form pillars, the semiconductor pillars 20 sequentially comprise a source region 21, a channel region 22 and a drain region 23, and an end portion (the source region 21 in this embodiment) of the semiconductor pillars 20, which is close to the substrate 10, is connected to the bit line 30, to obtain an intermediate product as shown in fig. 4I; in other embodiments, drain region 23 may also be in contact with and connected to bit line 30;
S100: depositing a first sub-dielectric layer 441 on the inner wall (including the side wall and the bottom) of the second trench 52, and filling a second sub-dielectric layer 442 in the remaining space of the second trench 52, wherein the first sub-dielectric layer 441 and the second sub-dielectric layer 442 form a fourth dielectric layer 44, so as to obtain an intermediate product as shown in fig. 4J; wherein the materials of the first sub-dielectric layer 441 and the second sub-dielectric layer 442 are the same or different;
s110: removing the first barrier layer 81, the third dielectric layer 43 and the fourth dielectric layer 44 located at the upper part (corresponding to the drain region and the channel region) between two adjacent semiconductor pillars, exposing the side wall of the entire upper part of each semiconductor pillar 20, and obtaining an intermediate product as shown in fig. 4K and 4L;
s120: depositing a gate insulating layer 70 and a fifth dielectric layer 45 on the exposed surfaces of the semiconductor pillars 20, the third dielectric layer 43 and the fourth dielectric layer 44 in sequence on the surface of the substrate 10, and depositing a sixth dielectric layer 46 on the surface of the substrate 10 to cover the fifth dielectric layer 45 and fill the second trenches 52, thereby obtaining an intermediate product as shown in fig. 4M; wherein the material of the sixth dielectric layer 46 and the material of the second sub-dielectric layer 442 may be the same;
S130: removing the sixth dielectric layer 46 and the gate insulating layer on the upper portion between the surface of the semiconductor pillar 20 and the adjacent two semiconductor pillars 20, and removing the fifth dielectric layer 45 on the sidewalls of the semiconductor pillars 20, and depositing gate material in the space vacated after removing the fifth dielectric layer 45 on the sidewalls of the semiconductor pillars 20, to form a gate surrounding each of the sidewalls of the semiconductor pillars, to obtain an intermediate product as shown in fig. 4N;
s140: a seventh dielectric layer 47 is deposited on the surface portion of the substrate 10 to cover the surface of the semiconductor pillar 20, the surface of the gate insulating layer 70 and the surface of the gate electrode 60, resulting in the memory shown in fig. 1.
In embodiments of the present application, the first trench and/or the second trench may be formed using a Self-aligned dual imaging (Self-aligned Double Patterning, SADP) process.
In embodiments of the present application, the methods of depositing the first dielectric layer, the second dielectric layer, the third dielectric layer, the fourth dielectric layer, the fifth dielectric layer, the sixth dielectric layer, and the seventh dielectric layer may each be independently selected from any one of atomic layer deposition (Atomic Layer Deposition, ALD) and chemical vapor deposition (Chemical Vapor Deposition, CVD).
The embodiment of the application also provides electronic equipment, which comprises the memory provided by the embodiment of the application.
In an embodiment of the present application, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.
Although the embodiments disclosed in the present application are described above, the embodiments are only used for facilitating understanding of the present application, and are not intended to limit the present application. Any person skilled in the art to which this application pertains will be able to make any modifications and variations in form and detail of implementation without departing from the spirit and scope of the disclosure, but the scope of the application is still subject to the scope of the claims that follow.

Claims (10)

1. A memory comprising a plurality of transistors, the memory further comprising:
a substrate on which a first dielectric layer, a second dielectric layer and a third dielectric layer are sequentially arranged; the first dielectric layer and the third dielectric layer are oxide layers, and the second dielectric layer is a nitride layer;
the substrate is provided with a plurality of first grooves extending along the column direction and arranged at intervals in the row direction and a plurality of second grooves extending along the row direction and arranged at intervals in the column direction; each of the first trenches extends into the second dielectric layer in a direction perpendicular to the substrate by a set depth h1;
A plurality of semiconductor columns, each corresponding to a channel of one of the transistors, the semiconductor columns being arranged at intervals in a row direction and a column direction, each column of semiconductor columns being disposed in one of the first trenches, adjacent two rows of semiconductor columns being spaced apart by the second trench; each semiconductor column extends to be columnar along a direction perpendicular to the substrate;
and a plurality of bit lines extending along the column direction and distributed at intervals in the row direction, wherein the bit lines are arranged in the region corresponding to the second dielectric layer in the first trench, the semiconductor column is positioned on the bit lines in the first trench, and the bit lines are connected with the end part of the semiconductor column, which is close to the substrate.
2. The memory of claim 1, wherein the semiconductor pillar is a metal oxide semiconductor material.
3. The memory of claim 1 or 2, further comprising a gate surrounding a sidewall of the semiconductor pillar and insulated from the semiconductor pillar by a gate insulating layer, the gate being connected to a word line.
4. A memory according to claim 3, wherein gate insulating layers on opposite sidewalls of adjacent two of the semiconductor pillars are connected together;
The memory further includes a fourth dielectric layer disposed in the second trench and between the bit line and the gate insulating layer; and/or
The memory further comprises a fifth dielectric layer which is arranged in the second groove and is positioned between the surface of one end, close to the substrate, of the gate and the gate insulating layer; and/or
The memory further includes a sixth dielectric layer disposed between and spacing the two gates of the same second trench.
5. The memory of claim 4, wherein the fourth dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer, the first sub-dielectric layer is disposed between an inner wall of the second trench and the second sub-dielectric layer, and materials of the first sub-dielectric layer and the second sub-dielectric layer are the same or different.
6. The memory of claim 4, wherein the material of the bit line is metal;
the materials of the first dielectric layer and the third dielectric layer are respectively and independently selected from any one or more of silicon oxide and silicon carbonitride oxide;
The material of the second dielectric layer is selected from any one or more of silicon nitride and silicon carbonitride;
the materials of the fourth dielectric layer, the fifth dielectric layer and the sixth dielectric layer are each independently selected from any one or more of silicon oxide, silicon nitride, silicon carbonitride oxide and silicon carbonitride.
7. The memory defined by any of claims 1-6, further comprising a first barrier layer disposed between the semiconductor pillar and a portion of the sidewall of the first trench that is above the bit line.
8. The memory according to any one of claims 1 to 6, further comprising an adhesion layer provided on an inner wall of a region where the bit line is located in the first trench, and a second barrier layer provided between the adhesion layer and the bit line.
9. A method of forming buried bit lines, comprising:
providing a substrate;
sequentially depositing a first dielectric layer, a second dielectric layer and a third dielectric layer on the substrate, wherein the first dielectric layer and the third dielectric layer are oxide layers, and the second dielectric layer is a nitride layer and is provided with an upper surface far away from the substrate;
Etching a plurality of first grooves extending along the column direction and arranged at intervals in the row direction on the third dielectric layer, and enabling the first grooves to expose the upper surface of the second dielectric layer, wherein the first grooves divide the third dielectric layer into a plurality of blocking walls at intervals;
depositing a sacrificial barrier layer on the inner wall of the first trench;
etching the sacrificial blocking layer positioned on the upper surface of the second dielectric layer in the first groove to expose the upper surface of the second dielectric layer, and etching the exposed second dielectric layer to enable the first groove to extend to a set depth h1 in the second dielectric layer in the direction perpendicular to the substrate;
filling bit line materials in the first grooves;
removing the sacrificial barrier layer in the first trench and the bit line material of the region corresponding to the third dielectric layer in the first trench, the bit line material of the region corresponding to the second dielectric layer in the first trench forming a bit line extending in a column direction;
a first barrier layer is deposited on sidewalls of the corresponding region of the third dielectric layer in the first trench, and a semiconductor layer is deposited in the first trench, the bit line being buried between the semiconductor layer and the second dielectric layer.
10. A method of manufacturing a memory, comprising:
providing a substrate;
sequentially depositing a first dielectric layer, a second dielectric layer and a third dielectric layer on the substrate, wherein the first dielectric layer and the third dielectric layer are oxide layers, and the second dielectric layer is a nitride layer and is provided with an upper surface far away from the substrate;
etching a plurality of first grooves extending along the column direction and arranged at intervals in the row direction on the third dielectric layer, and enabling the first grooves to expose the upper surface of the second dielectric layer, wherein the first grooves divide the third dielectric layer into a plurality of blocking walls at intervals;
depositing a sacrificial barrier layer on the inner wall of the first trench;
etching the sacrificial blocking layer positioned on the upper surface of the second dielectric layer in the first groove to expose the upper surface of the second dielectric layer, and etching the exposed second dielectric layer to enable the first groove to extend to a set depth h1 in the second dielectric layer in the direction perpendicular to the substrate;
filling bit line materials in the first grooves;
removing the sacrificial barrier layer in the first trench and the bit line material of the region corresponding to the third dielectric layer in the first trench, the bit line material of the region corresponding to the second dielectric layer in the first trench forming a bit line extending in a column direction;
Depositing a first barrier layer on sidewalls of the corresponding region of the third dielectric layer in the first trench, and depositing a semiconductor layer in the first trench, the bit line being buried between the semiconductor layer and the second dielectric layer;
etching a plurality of second grooves which extend in the row direction and are arranged at intervals in the column direction in the barrier wall and the semiconductor layer, and enabling the second grooves to expose the upper surface of the bit line, wherein the second grooves divide the semiconductor layer into a plurality of semiconductor columns at intervals, the semiconductor columns extend into columns along the direction perpendicular to the substrate, and the end parts, close to the substrate, of the semiconductor columns are connected with the bit line;
depositing a fourth dielectric layer in the second trench;
removing the first barrier layer, the third dielectric layer and the fourth dielectric layer which are positioned at the upper part between two adjacent semiconductor columns, and exposing the side wall of the whole upper part of each semiconductor column;
sequentially depositing a gate insulating layer and a fifth dielectric layer on the surface of the substrate, wherein the gate insulating layer and the fifth dielectric layer cover the exposed surfaces of the semiconductor column, the third dielectric layer and the fourth dielectric layer, and depositing a sixth dielectric layer on the surface of the substrate, wherein the sixth dielectric layer covers the fifth dielectric layer and fills the residual space of the second trench;
Removing the sixth dielectric layer and the gate insulating layer which are positioned on the upper part between the surface of the semiconductor column and the adjacent two semiconductor columns, removing the fifth dielectric layer on the side walls of the semiconductor columns, and depositing gate materials in the space which is formed after the fifth dielectric layer on the side walls of the semiconductor columns is removed, so as to form a gate surrounding each side wall of the semiconductor column;
and depositing a seventh dielectric layer on the surface of the substrate, wherein the seventh dielectric layer covers the surface of the semiconductor column, the surface of the gate insulating layer and the surface of the gate electrode, so as to obtain the memory.
CN202211268239.8A 2022-10-17 2022-10-17 Method for forming buried bit line, memory and manufacturing method thereof Pending CN117457737A (en)

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