CN117456951A - Pixel driving circuit and display panel - Google Patents

Pixel driving circuit and display panel Download PDF

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Publication number
CN117456951A
CN117456951A CN202311376076.XA CN202311376076A CN117456951A CN 117456951 A CN117456951 A CN 117456951A CN 202311376076 A CN202311376076 A CN 202311376076A CN 117456951 A CN117456951 A CN 117456951A
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CN
China
Prior art keywords
transistor
voltage signal
modulation unit
light
pulse width
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Pending
Application number
CN202311376076.XA
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Chinese (zh)
Inventor
张蒙蒙
张剑
翟思敏
郭耀明
成富平
项国庆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to CN202311376076.XA priority Critical patent/CN117456951A/en
Publication of CN117456951A publication Critical patent/CN117456951A/en
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/32—Pulse-control circuits
    • H05B45/325—Pulse-width modulation [PWM]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/32—Pulse-control circuits
    • H05B45/33—Pulse-amplitude modulation [PAM]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The application discloses a pixel driving circuit and a display panel. The circuit includes a light emitting device; the integration operation module is used for receiving a first voltage signal with a constant voltage value and outputting a second voltage signal with a time-varying voltage value; the driving control module is respectively connected with the light emitting device and the integral operation module and is used for receiving the second voltage signal and controlling the light emitting time of the light emitting device according to the second voltage signal when the picture is displayed. The present application more rapidly and more precisely controls the light emission time of the light emitting device in the display panel.

Description

Pixel driving circuit and display panel
Technical Field
The application relates to the technical field of driving of display panels, in particular to a pixel driving circuit and a display panel.
Background
Liquid crystal displays, such as thin film transistor liquid crystal displays (TFT-LCDs), are popular because of their small size, light weight, low power consumption, and high display quality. The current common driving mode of the LED display technology is PWM and PAM.
The driving modes of the display technology include PAM (Pulse Amplitude Modulation ), PWM (Pulse Width Modulation, pulse width modulation) and PHM (a mixture of PAM and PWM), wherein the PWM driving has a high requirement on a driving chip, the PAM driving has poor image quality at the time of low gray scale display, and the PWM and PAM mixed driving, i.e., PHM driving can integrate the advantages of both, and the disadvantages of the other side are improved, so that the research is widely conducted.
However, in the conventional PHM driving scheme, the light emitting time is controlled by using a triangular wave signal or a rectangular wave signal, so that the light emitting time is difficult to control.
Disclosure of Invention
The embodiment of the application provides a pixel driving circuit and a display panel, which solve the technical problem that low-power shutdown display cannot be realized.
In a first aspect, the present application provides a pixel driving circuit, comprising:
a light emitting device;
the integration operation module is used for receiving a first voltage signal with a constant voltage value and outputting a second voltage signal with a time-varying voltage value;
the driving control module is respectively connected with the light emitting device and the integral operation module and is used for receiving the second voltage signal and controlling the light emitting time of the light emitting device according to the second voltage signal when the picture is displayed.
In some embodiments, the integration operation module includes: the circuit comprises an operational amplifier, a first resistor, a second resistor and a first capacitor;
the first end of the first resistor is connected with the first voltage signal;
the inverting input end of the operational amplifier is respectively connected with the second end of the first resistor and the first end of the first capacitor;
the non-inverting input end of the operational amplifier is connected with the second resistor and then grounded;
and the output end of the operational amplifier is respectively connected with the second end of the first capacitor and the driving control module so as to output the second voltage signal to the driving control module.
In some embodiments, the relationship of the second voltage signal and the first voltage signal satisfies the following formula:
the relationship of the second voltage signal and the first voltage signal satisfies the following formula:
wherein u is o For the second voltage signal, u I For the first voltage signal, R is the resistance value of the first resistor, C is the capacitance value of the first capacitor, RC is the integration time constant, t 2 Receiving the opening time of the first voltage signal for the integral operation module, t 1 For the integration operation module to receive the turn-off time of the first voltage signal, u0 (t 1) is the initial voltage value of the second voltage signal.
In some embodiments, the drive control module includes: a driving transistor, a pulse width modulation unit and a pulse amplitude modulation unit;
one of a source and a drain of the driving transistor is connected to an anode of the light emitting device;
the first end of the pulse amplitude modulation unit is connected with a pulse amplitude control signal, the second end of the pulse amplitude modulation unit is connected with a second data signal, and the third end of the pulse amplitude modulation unit is connected with the grid electrode of the driving transistor;
the first end of the pulse width modulation unit is connected with a pulse width control signal, the second end of the pulse width modulation unit is connected with a first data signal, the third end of the pulse width modulation unit is connected with the grid electrode of the driving transistor, and the pulse width modulation unit is used for controlling the light emitting time of the light emitting device according to the second voltage signal.
In some embodiments, the pulse width modulation unit includes:
a potential writing subunit, wherein a first end of the potential writing subunit is used as a first end of the pulse width modulation unit to be connected with the pulse width control signal, and a second end of the potential writing subunit is used as a second end of the pulse amplitude modulation unit to be connected with the first data signal;
the first end of the light-emitting time control subunit is respectively connected with the third end of the potential writing subunit and the output end of the operational amplifier, the second end of the light-emitting time control subunit is used as the third end of the pulse width modulation unit to be connected with the grid electrode of the driving transistor, the third end of the light-emitting time control subunit is connected with a first control signal, and the light-emitting time control subunit is used for controlling the light-emitting time of the light-emitting device according to the second voltage signal output by the output end of the operational amplifier.
In some embodiments, the light emission time control subunit includes a fourth transistor having a gate configured as a first terminal of the light emission time control subunit, one of a source and a drain configured as a second terminal of the light emission time control subunit, and the other of the source and the drain configured as a third terminal of the light emission time control subunit.
In some embodiments, the potential writing subunit includes a fifth transistor having a gate configured as a first terminal of the potential writing subunit, one of a source and a drain configured as a second terminal of the potential writing subunit, and the other of the source and the drain configured as a third terminal of the potential writing subunit.
In some embodiments, the pulse amplitude modulation unit comprises: a first transistor, a gate of the first transistor being configured as a first terminal of the pulse width modulation unit, one of a source and a drain of the first transistor being configured as a second terminal of the pulse width modulation unit, and the other of the source and the drain of the first transistor being configured as a third terminal of the pulse width modulation unit.
In some embodiments, the pixel driving circuit further comprises:
one end of the storage capacitor is connected with the grid electrode of the driving transistor, and the other end of the storage capacitor is respectively connected with one of the source electrode and the drain electrode of the driving transistor and the anode of the light-emitting device;
a third transistor, one of a source and a drain of the third transistor being connected to one of the source and the drain of the driving transistor, the other of the source and the drain of the third transistor being connected to a reference voltage signal, a gate of the third transistor being connected to a sense control signal;
the other of the source electrode and the drain electrode of the driving transistor is connected with a positive power supply signal, and the cathode of the light emitting device is connected with a negative power supply signal.
In a second aspect, the present application further provides a display panel, including the pixel driving circuit of the first aspect.
The beneficial effects are that: the embodiment of the application provides a pixel driving circuit and a display panel, after receiving a first voltage signal with a constant voltage value through an integral operation module to generate a second voltage signal with a time-varying voltage value, the application can control the light-emitting time of a light-emitting device through the second voltage signal, so that the display time or the light-emitting time of the light-emitting device in the display panel can be controlled more rapidly and more accurately.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic circuit diagram of a first circuit of a pixel driving circuit according to the prior art.
Fig. 2 is a timing diagram of the pixel driving circuit shown in fig. 1.
Fig. 3 is a schematic circuit diagram of a second type of pixel driving circuit according to the prior art.
Fig. 4 is a timing diagram of the pixel driving circuit shown in fig. 3.
Fig. 5 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present application.
Fig. 6 is a schematic circuit diagram of a pixel driving circuit according to an embodiment of the present application.
Fig. 7 is a timing diagram of a first voltage signal input by the integration operation module according to an embodiment of the present application.
Fig. 8 is a timing diagram of a second voltage signal output by the integration operation module according to the embodiment of the present application.
Fig. 9 is a timing diagram according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "one end," "the other end," and the like are based on the orientation or positional relationship shown in the drawings, and are merely for convenience of description of the present application and to simplify the description, rather than to indicate or imply that the apparatus or element being referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "" "is two or more, unless explicitly defined otherwise.
It should be noted that in the embodiments of the present application, "connected" is understood to mean electrically connected, and two electrical components may be connected directly or indirectly between two electrical components. For example, a may be directly connected to B, or indirectly connected to B via one or more other electrical components.
In the circuit structure provided in the embodiments of the present application, the first node, the second node, and the like are not nodes representing actually existing components, but represent junction points of related coupling in the circuit diagram, that is, the nodes are equivalent nodes formed by the junction points of the related coupling in the circuit diagram.
The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not in themselves indicate the relationship between the various embodiments and/or arrangements discussed. In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The application provides a pixel driving circuit and a display panel. The display panel in the embodiment of the application can be used for mobile phones, tablet computers, desktop computers, laptop computers, electronic readers, handheld computers, electronic display screens, notebook computers, ultra-mobile Personal Computer (UMPC), netbooks, cellular phones, personal digital assistants (Personal Digital Assistant, PDA), augmented Reality (Augmented Reality, AR) \virtual Reality (VR) devices, media players, wearable devices, digital cameras, car navigation devices, and the like.
The display panel may be a liquid crystal display panel. The present application is not limited to the type of liquid crystal display panel. The liquid crystal display panel provided by the application can be a horizontal electric field type liquid crystal display panel, such as a Fringe FieldSwitching, FFS (Fringe) or In-Plane Switching (IPS) type liquid crystal display panel, or a vertical electric field type liquid crystal display panel, such as a Twisted Nematic (TN) type liquid crystal display panel, or a Multi-domain vertical alignment (Multi-domain Vertical Alignment, MVA) type liquid crystal display panel.
The driving modes of the display technology include PAM, PWM and a mixture of the two. Among them, the PWM driving method has advantages of constant current, high luminous efficiency, and good low gray scale display image quality, so that PWM or PWM-based hybrid driving method has been widely studied.
The pixel driving circuit shown in fig. 1 adopts a PWM driving method, and the display time of the pixel driving circuit can be controlled by a signal SPWM, but the signal SPWM needs a high frequency, and when it is generated by a gate driving IC (Integrated Circuit ), the gate driving IC is required to have a high performance, and the number of lines of the pixel driving circuit that the gate driving IC can drive is not large.
As shown in fig. 2, the operation of the pixel driving circuit in fig. 1 includes a preparation phase in which the G-point potential V-G and the potential V-SPWM of the signal SPWM are both low, and thus the light emitting current I-LED does not flow in the light emitting device LED. In the light-emitting stage, when the G point potential V-G is high, the light-emitting current I-LED flows in the LED of the light-emitting device; however, when the potential V-SPWM of the signal SPWM is high, the light emitting current I-LED will stop flowing through the light emitting device LED.
The pixel driving circuit shown in fig. 3 adopts another PWM driving method, and the potential of the point a can be raised at a constant speed by initializing the potential of the point a to a corresponding initial voltage and utilizing the coupling effect of the capacitor C5. The time required for the potential at point a to rise from different initial voltages to the threshold voltage of T4 is different, so that the time for T4 to turn on or turn off is also different, and further the display time or light emission time of the pixel driving circuit is also different. As shown in fig. 4, the operation of the pixel driving circuit in fig. 3 includes a preparation phase in which the G-point potential V-G and the potential V-Sweep of the signal Sweep are both low, and thus the light emitting current I-LED does not flow through the light emitting device LED. In the light-emitting stage, when the G point potential V-G is high, the light-emitting current I-LED flows in the LED of the light-emitting device; however, as the potential V-Sweep of the signal Sweep is gradually raised, there is a slow falling process of the G-point potential V-G, resulting in that the light emitting current I-LED is not stopped immediately, and thus the light emitting time of the pixel driving circuit is difficult to control accurately. Therefore, due to the uniform change of the potential at the point a, the slow turn-off or turn-off of the T4 and T2 as shown in fig. 4 occurs, and thus the light emitting time is difficult to control accurately.
The pixel driving circuit and the display panel of the present application are described below with reference to the drawings of the specification to solve the above-described problems.
Referring to fig. 5, a schematic structural diagram of a pixel driving circuit 10 according to an embodiment of the present application is shown in fig. 5, where the pixel driving circuit includes:
a light emitting device LED;
an integral operation module 100 for receiving a first voltage signal u with constant voltage value I And outputs a second voltage signal u whose voltage value varies with time o ；
A driving control module 200 connected to the light emitting device LED and the integral operation module 100, respectively, wherein the driving control module 200 is configured to receive the second voltage signal u o And controlling the light emitting time of the light emitting device LED according to the second voltage signal uo when the picture is displayed.
Specifically, as shown In fig. 5, the anode of the light emitting device LED is connected to the voltage output terminal of the driving control module 200, and the electrical signal output terminal Out of the integration operation module 100 is connected to the voltage input terminal In2 of the driving control module 200. The integral operation module 100 includes an electrical signal inputThe terminal In1 and the electrical signal output terminal Out are connected to the electrical signal input terminal In1 of the integral operation module 100 at the initial time, i.e. when the pixel driving circuit is not powered on I Therefore, the voltage value of the electrical signal output terminal Out of the integration operation module 100 is 0. After the pixel driving circuit is powered on, the electrical signal input terminal In1 of the integration operation module 100 receives a first voltage signal u, which is a dc voltage with a constant voltage value as shown In fig. 7 I Receiving a first voltage signal u at an electrical signal input terminal In1 I After that, the integration operation module 100 calculates the first voltage signal u I Processing to obtain a second voltage signal u with a voltage value linearly changing along with time o Then, the second voltage signal u is outputted through the electrical signal output terminal Out of the integration operation module 100 o The voltage input terminal In2 is input to the driving control module 200, and is used for receiving the second voltage signal u when the display panel needs to display a picture o To control the light emission time of the light emitting device LEDs in the pixel driving circuit of each pixel unit.
In some embodiments, the light emitting device LED may be any one of a mini light emitting diode, a micro light emitting diode, a quantum dot light emitting diode, and an organic light emitting diode.
It can be understood that the pixel driving circuit provided in this embodiment receives the first voltage signal u with constant voltage value through the integration operation module 100 I Generating a second voltage signal u whose voltage value varies with time o After that, through the second voltage signal u o The display time or the light emitting time of the light emitting device LEDs in the display panel can be controlled more rapidly and more accurately by controlling the light emitting time of the light emitting device LEDs.
In some embodiments of the present application, the integral operation module 100 includes: the circuit comprises an operational amplifier PI, a first resistor R1, a second resistor R2 and a first capacitor C1;
the first end of the first resistor R1 is connected to the first voltage signal u I ；
The inverting input end of the operational amplifier PI is respectively connected with the second end of the first resistor R1 and the first end of the first capacitor C1;
the non-inverting input end of the operational amplifier PI is connected with the second resistor R2 and then grounded;
the output end of the operational amplifier PI is respectively connected with the second end of the first capacitor C1 and the driving control module 200 to output the second voltage signal u to the driving control module 200 o 。
Specifically, as shown in FIG. 5, a first end of the first resistor R1 is connected to the electrical signal input end to be connected to the first voltage signal u I The output end of the operational amplifier PI is connected to the electrical signal output end Out to provide the second voltage signal u to the driving control module 200 o . An integral relationship exists between the voltage across the first capacitor C1 and the current flowing through the capacitor, so that the second voltage signal u output by the output end of the operational amplifier PI o Is proportional to the voltage across the first capacitor C1, and the first voltage signal u is connected to the electrical signal input terminal of the integral operation module 100 I In direct proportion to the current flowing through the capacitor, a first voltage signal u I The integrated operation relation with the second voltage signal uo can be formed.
In some embodiments of the present application, a second capacitor C2 is connected in series between the output terminal of the operational amplifier PI and the output terminal Out of the electrical signal, and the second voltage signal u output from the output terminal of the operational amplifier PI can be outputted through the second capacitor C2 o The filtering process is performed to obtain a dc voltage, so as to prevent the driving control module 200 from being disturbed.
In some embodiments of the present application, to prevent the gain of the low-frequency signal from being excessively large, a third resistor is connected in parallel to the first capacitor C1, and the resistance value of the third resistor is ten times greater than that of the first resistor R1.
In some embodiments of the present application, the second voltage signal u o And the first voltage signal u I The relationship of (2) satisfies the following formula:
wherein u is o For the second voltage signal, u I For the first voltage signal, R is the resistance value of the first resistor, C is the capacitance value of the first capacitor, RC is the integration time constant, t 2 Receiving the opening time of the first voltage signal for the integral operation module, t 1 For the integration operation module to receive the turn-off time of the first voltage signal, u0 (t 1) is the initial voltage value of the second voltage signal.
Specifically, the current flowing through the first capacitor C1 is equal to the current flowing through the first resistor R1,
first voltage signal u I The first resistor R1 is added to the inverting input end of the operational amplifier PI, and a deep negative feedback is led back between the output end and the inverting input end of the operational amplifier PI through the first capacitor C1 to form a basic integrating circuit.
In order to balance the resistances of the two inputs of the operational amplifier PI to ground, the resistance of the second resistor R2 connected to the non-inverting input is generally equal to the resistance of the first resistor R1 connected to the inverting input, i.e., r=r'. Wherein R' is the resistance value of the second resistor R2.
Since the inverting output end of the operational amplifier PI is "virtually short", the relationship between the second voltage signal uo and the voltage values across the first capacitor C1 satisfies uo= -uc, and it can be seen that the second voltage signal uo is proportional to the voltage across the first capacitor C1. Where uc is the voltage value across the first capacitor C1. Because the inverting output end of the operational amplifier PI is "virtually off", the current flowing through the inverting input end of the operational amplifier PI is zero, and the current value flowing through the first resistor R1 and the current value flowing through the first capacitor C1 satisfy i1=ic, where i1 is the current value flowing through the first resistor R1 and ic is the current value flowing through the first capacitor C1. Thus, u1=i1r= icR, i.e. the first voltage signal u, can be derived I Proportional to the value of the current flowing through the first capacitor C1. From the above expressions, the first voltage signal u I And a second voltage signal u o The relationship of (2) satisfies the following formula:
where the product of the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1 is referred to as an integration time constant. Wherein the second voltage signal u o And a first voltage signal u I The sign indicates that the circuit implements an inverting function, so the integrating operation module 100 in the embodiment of the present application is an inverting integrating operation circuit. In order to satisfy the integral operation relationship, the integral time constant RC must be greater than the first voltage signal u I Is a function of the input period of the input device.
In some embodiments of the present application, the driving control module 200 includes: a driving transistor T2, a pulse width modulation unit 210, and a pulse amplitude modulation unit 220;
one of a source and a drain of the driving transistor T2 is connected to an anode of the light emitting device LED;
a first end of the pulse amplitude modulation unit 220 is connected to a pulse amplitude control signal SPAM, a second end of the pulse amplitude modulation unit 220 is connected to a second data signal spam_data, and a third end of the pulse amplitude modulation unit 220 is connected to a gate of the driving transistor T2;
a first end of the pulse width modulation unit 210 is connected to a pulse width control signal SPWM, a second end of the pulse width modulation unit 210 is connected to a first data signal spwm_data, a third end of the pulse width modulation unit 210 is connected to the gate of the driving transistor T2, and is configured to generate a second voltage signal u according to the second voltage signal u o And controlling the light emitting time of the LED.
Specifically, as shown in fig. 6, the driving control module 200 includes a driving transistor T2 connected to an anode of the light emitting device LED, where a gate of the driving transistor T2 is connected to the pulse amplitude modulation unit 220 and the pulse width modulation unit 210, respectively, the pulse amplitude modulation unit 220 is connected to the pulse amplitude control signal SPAM, and the pulse width modulation unit 210 is connected to the pulse width control signal SPWM, so that the light emitting time of the light emitting device LED is accurately controlled by the pulse width modulation unit 210 according to a duration of the pulse amplitude control signal SPAM when the light emitting device LED is displayed in low gray scale. The light emitting brightness of the light emitting device LED is controlled by the pulse amplitude modulation unit 220 through the driving transistor T2 according to the voltage value of the second data signal spam_data. In summary, PWM driving is pulse width modulation, controlling brightness by time, i.e. voltage is unchanged; PAM driving is pulse amplitude modulation, and brightness is controlled by voltage, i.e. time is unchanged.
In some embodiments of the present application, the pulse width modulation unit 210 includes:
the potential writing subunit 211, wherein a first end of the potential writing subunit 211 is used as a first end of the pulse width modulation unit 210 to be connected to the pulse width control signal SPWM, and a second end of the potential writing subunit 211 is used as a second end of the pulse width modulation unit 210 to be connected to the first data signal spwm_data;
the light-emitting time control subunit 212, a first end of the light-emitting time control subunit 212 is connected to the third end of the potential writing subunit 211 and the output end of the operational amplifier PI, a second end of the light-emitting time control subunit 212 is connected to the gate of the driving transistor T2 as the third end of the pulse width modulation unit 210, a third end of the light-emitting time control subunit 212 is connected to a first control signal Vneg, and the light-emitting time control subunit 212 is configured to output the second voltage signal u according to the output end of the operational amplifier PI 0 And controlling the light emitting time of the LED.
Specifically, the light-emitting time control subunit 212 is configured to turn off the driving transistor T2 in time, so when the driving transistor T2 is an N-channel thin film transistor, the potential of the first control signal Vneg may be a low potential, for example, a zero potential. When the driving transistor T2 is a P-channel thin film transistor, the potential of the first control signal Vneg may be a high potential. After the potential writing subunit 211 receives the first data signal spwm_data and the pulse width control signal SPWM, an initial potential may be written into the light emission time control subunit 212.
In some embodiments of the present application, the light-emitting time control subunit 212 includes a fourth transistor T4, the gate of the fourth transistor T4 is configured as the first terminal of the light-emitting time control subunit 212, one of the source and the drain of the fourth transistor T4 is configured as the second terminal of the light-emitting time control subunit 212, and the other of the source and the drain of the fourth transistor T4 is configured as the third terminal of the light-emitting time control subunit 212.
Specifically, the gate of the fourth transistor T4 is configured such that the first terminal of the light-emitting time control subunit 212 is connected to the first node B, one of the source and the drain of the fourth transistor T4 is configured such that the second terminal of the light-emitting time control subunit 212 is connected to the gate of the driving transistor T2 and the pulse amplitude modulation unit 220, respectively, and the other of the source and the drain of the fourth transistor T4 is configured such that the third terminal of the light-emitting time control subunit 212 is connected to the first control signal Vneg. The first node B is connected to the output terminal of the operational amplifier PI in the integration operation module 100, that is, the gate of the fourth transistor T4 is connected to the second voltage signal uo output by the operational amplifier PI, as shown in fig. 8, the voltage value of the second voltage signal uo decreases with time, that is, the second voltage signal uo is at a high potential at the beginning of a frame, and then the second voltage signal uo is at a zero potential or a negative potential at the later stage with time.
The fourth transistor T4 may be a P-channel thin film transistor, and the potential of the first control signal Vneg is a high potential. At this time, as shown in fig. 8, the potential writing subunit 211 writes a high-potential second voltage signal uo at the beginning of a frame, and as time goes by, the second voltage signal uo provided to the first node B by the integration operation module 100 becomes zero potential or negative potential, which is sufficient to make the fourth transistor T4 conductive, and the driving transistor T2 is turned off when the fourth transistor T4 is conductive. The driving transistor T2 is turned on when the second voltage signal uo provided to the first node B by the integration operation module 100 decreases to such an extent that the fourth transistor T4 is turned off. Accordingly, the switching of the fourth transistor T4 may be controlled by the second voltage signal uo provided to the first node B by the integration operation module 100 to control the switching state of the driving transistor T2, thereby controlling the light emitting time of the light emitting device LED connected to the driving transistor T2.
The fourth transistor T4 may be an N-channel thin film transistor, and the potential of the first control signal Vneg is low. The pwm unit 20 further includes an inverter 24, an input terminal of the inverter 24 is connected to one of a source and a drain of a fifth transistor T5 in the embodiment below, and an output terminal of the inverter 24 is connected to a gate of a fourth transistor T4. At this time, as shown in fig. 8, the potential writing subunit 211 writes a high-potential second voltage signal uo at the beginning of a frame, and as time goes by, the second voltage signal uo provided to the first node B by the integration operation module 100 becomes zero potential or negative potential, the low level input to the gate of the fourth transistor T4 can be changed to high level by the inverter, which is sufficient to turn on the fourth transistor T4, and the driving transistor T2 is turned off when the fourth transistor T4 is turned on. The driving transistor T2 is turned on when the second voltage signal uo provided to the first node B by the integration operation module 100 decreases to such an extent that the fourth transistor T4 is turned off. Accordingly, the switching of the fourth transistor T4 may be controlled by the second voltage signal uo provided to the first node B by the integration operation module 100 to control the switching state of the driving transistor T2, thereby controlling the light emitting time of the light emitting device LED connected to the driving transistor T2.
Because the inverter 24 has a signal shaping function, the rising edge and/or the falling edge of the signal can be more approaching to the ideal vertical gradient, the fourth transistor T4 can be turned on or off more rapidly or timely, the driving transistor T2 is turned off, and the light emitting time of the light emitting device LED can be controlled more precisely.
In some embodiments of the present application, the potential writing subunit 211 includes a fifth transistor T5, a gate of the fifth transistor T5 is configured as a first terminal of the potential writing subunit 211, one of a source and a drain of the fifth transistor T5 is configured as a second terminal of the potential writing subunit 211, and the other of the source and the drain of the fifth transistor T5 is configured as a third terminal of the potential writing subunit 211.
Specifically, the third terminal of the potential writing subunit is connected to the first node B by one of the source and the drain of the fifth transistor T5, the other of the source and the drain of the fifth transistor T5 is configured to access the first data signal spwm_data by the second terminal of the potential writing subunit 211, and the gate of the fifth transistor T5 is configured to access the pulse width control signal SPWM by the first terminal of the potential writing subunit 211. The pulse width control signal SPWM controls the fifth transistor T5 to write the first data signal spwm_data to the gate of the driving transistor T2.
In some embodiments of the present application, the pulse amplitude modulation unit 220 includes: a first transistor T1, a gate of the first transistor T1 is configured as a first terminal of the pulse width modulation unit 220, one of a source and a drain of the first transistor T1 is configured as a second terminal of the pulse amplitude modulation unit 220, and the other of the source and the drain of the first transistor T1 is configured as a third terminal of the pulse amplitude modulation unit 220.
Specifically, the other of the source and the drain of the first transistor T1 is configured such that the third terminal of the pulse width modulation unit 220 is connected to the gate of the driving transistor T2, the gate of the first transistor T1 is configured such that the first terminal of the pulse width modulation unit 220 is connected to the pulse width control signal SPAM, and one of the source and the drain of the first transistor T1 is configured such that the second terminal of the pulse width modulation unit is connected to the second data signal spam_data. The pulse width control signal SPAM controls the first transistor T1 to write the second data signal spam_data to the gate of the driving transistor T2. The first data signal spwm_data and the second data signal spam_data may be the same or different.
In some embodiments of the present application, the pixel driving circuit further includes:
a storage capacitor C3, wherein one end of the storage capacitor C3 is connected with the gate of the driving transistor T2, and the other end of the storage capacitor C3 is connected with one of the source and the drain of the driving transistor T2 and the anode of the light emitting device LED, respectively;
a third transistor T3, one of a source and a drain of the third transistor T3 being connected to one of a source and a drain of the driving transistor T2, the other of the source and the drain of the third transistor T3 being connected to a reference voltage signal, a gate of the third transistor T3 being connected to a Sense control signal Sense;
the other of the source electrode and the drain electrode of the driving transistor T2 is connected with a positive power supply signal, and the cathode of the light emitting device LED is connected with a negative power supply signal.
Specifically, in the operation of the pixel driving circuit shown in fig. 6, in the preparation phase, under the control of the pulse width control signal SPAM, the second data signal spam_data is written to the second node G, i.e. the gate of the writing value driving transistor T2, the fifth transistor T5 is turned on under the control of the pulse width control signal SPWM, and the first data signal spwm_data is written to an initial potential at the gate of the fourth transistor T4, i.e. the first node B. The third transistor T3 writes the reference voltage signal to the third node S at the access to initialize the third node S. Meanwhile, under the control of the sensing control signal Sense, the reference voltage signal Vref initializes the potential of the third node S, and the potential writing subunit 211 writes an initial potential at the first node B.
Referring to fig. 9, fig. 9 is a timing diagram provided in the embodiment of the present application, during an initial period of a writing phase, the first data signal spwm_data is provided to the first node B with different initial voltages, and the potential of the first node B is pulled down through the second capacitor C2, and because the potentials provided by the first node B are different in the initial period, the first node B is pulled down so that the time when the fourth transistor T4 is turned on is different, and the time when the voltage of the first control signal Vneg is written to the second node G is also different, that is, the time when the driving transistor T2 is turned off is also different, that is, the light emitting time of the light emitting device LED lamp is also different.
In the light-emitting phase, the potential V of the second node G G That is, the gate potential of the driving transistor T2 jumps to a high potential, so that the driving transistor T2 is turned on, and the light emitting current can flow through the light emitting device LED so that the light emitting device LED starts to emit light. Subsequently, since the second voltage signal uo provided to the first node B by the integration operation module 100 becomes zero potential or negative potential over time, the first node B potential V A Continuously descend, when nowWhen the voltage is reduced to the preset voltage, the fourth transistor T4 can be charged through the storage capacitor C3 due to the coupling effect of the storage capacitor C3 until the fourth transistor T4 is turned on, the driving transistor T2 is turned off, and the light emitting device LED stops displaying, so that the light emitting time of the light emitting device LED can be controlled.
The embodiment of the application also provides a display panel, which comprises the pixel driving circuit corresponding to the embodiment shown in fig. 5 to 6.
In the pixel driving circuit provided in this embodiment, after the integration operation module 100 receives the first voltage signal uI with a constant voltage value to generate the second voltage signal uo with a time-varying voltage value, the second voltage signal uo controls the light emitting time of the light emitting device LED, so that the display time or the light emitting time of the light emitting device LED in the display panel can be controlled more rapidly and more accurately.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The foregoing has described in detail a pixel driving circuit and a display panel provided by embodiments of the present application, and specific examples have been applied herein to illustrate the principles and implementations of the present application, and the description of the foregoing embodiments is only for aiding in understanding the method and core idea of the present application; meanwhile, those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, and the present description should not be construed as limiting the present application in view of the above. Moreover, it will be apparent to those skilled in the art that various modifications and variations can be made without departing from the principles of the present application, and such modifications and variations are considered to be within the scope of the present application.

Claims (10)

1. A pixel driving circuit, comprising:
a light emitting device;
the integration operation module is used for receiving a first voltage signal with a constant voltage value and outputting a second voltage signal with a time-varying voltage value;
the driving control module is respectively connected with the light emitting device and the integral operation module and is used for receiving the second voltage signal and controlling the light emitting time of the light emitting device according to the second voltage signal when the picture is displayed.
2. The pixel driving circuit according to claim 1, wherein the integration operation module comprises: the circuit comprises an operational amplifier, a first resistor, a second resistor and a first capacitor;
the first end of the first resistor is connected with the first voltage signal;
the inverting input end of the operational amplifier is respectively connected with the second end of the first resistor and the first end of the first capacitor;
the non-inverting input end of the operational amplifier is connected with the second resistor and then grounded;
and the output end of the operational amplifier is respectively connected with the second end of the first capacitor and the driving control module so as to output the second voltage signal to the driving control module.
3. The pixel driving circuit according to claim 2, wherein the relationship of the second voltage signal and the first voltage signal satisfies the following formula:
wherein u is o For the second voltage signal, u I For the first voltage signal, R is the resistance value of the first resistor, C is the capacitance value of the first capacitor, RC is the integration time constant, t 2 Receiving the opening time of the first voltage signal for the integral operation module, t 1 For the integration operation module to receive the turn-off time of the first voltage signal, u0 (t 1) is the initial voltage value of the second voltage signal.
4. The pixel driving circuit according to claim 2, wherein the driving control module includes: a driving transistor, a pulse width modulation unit and a pulse amplitude modulation unit;
one of a source and a drain of the driving transistor is connected to an anode of the light emitting device;
the first end of the pulse amplitude modulation unit is connected with a pulse amplitude control signal, the second end of the pulse amplitude modulation unit is connected with a second data signal, and the third end of the pulse amplitude modulation unit is connected with the grid electrode of the driving transistor;
the first end of the pulse width modulation unit is connected with a pulse width control signal, the second end of the pulse width modulation unit is connected with a first data signal, the third end of the pulse width modulation unit is connected with the grid electrode of the driving transistor, and the pulse width modulation unit is used for controlling the light emitting time of the light emitting device according to the second voltage signal.
5. The pixel driving circuit according to claim 4, wherein the pulse width modulation unit includes:
a potential writing subunit, wherein a first end of the potential writing subunit is used as a first end of the pulse width modulation unit to be connected with the pulse width control signal, and a second end of the potential writing subunit is used as a second end of the pulse amplitude modulation unit to be connected with the first data signal;
the first end of the light-emitting time control subunit is respectively connected with the third end of the potential writing subunit and the output end of the operational amplifier, the second end of the light-emitting time control subunit is used as the third end of the pulse width modulation unit to be connected with the grid electrode of the driving transistor, the third end of the light-emitting time control subunit is connected with a first control signal, and the light-emitting time control subunit is used for controlling the light-emitting time of the light-emitting device according to the second voltage signal output by the output end of the operational amplifier.
6. The pixel driving circuit according to claim 5, wherein the light-emitting time control subunit comprises a fourth transistor, a gate of the fourth transistor being configured as a first terminal of the light-emitting time control subunit, one of a source and a drain of the fourth transistor being configured as a second terminal of the light-emitting time control subunit, and the other of the source and the drain of the fourth transistor being configured as a third terminal of the light-emitting time control subunit.
7. The pixel driving circuit according to claim 6, wherein the potential writing subunit includes a fifth transistor, a gate of the fifth transistor being configured as a first terminal of the potential writing subunit, one of a source and a drain of the fifth transistor being configured as a second terminal of the potential writing subunit, and the other of the source and the drain of the fifth transistor being configured as a third terminal of the potential writing subunit.
8. The pixel driving circuit according to claim 7, wherein the pulse amplitude modulation unit comprises: a first transistor, a gate of the first transistor being configured as a first terminal of the pulse width modulation unit, one of a source and a drain of the first transistor being configured as a second terminal of the pulse width modulation unit, and the other of the source and the drain of the first transistor being configured as a third terminal of the pulse width modulation unit.
9. A pixel driving circuit according to any one of claims 4 to 8, wherein the pixel driving circuit further comprises:
one end of the storage capacitor is connected with the grid electrode of the driving transistor, and the other end of the storage capacitor is respectively connected with one of the source electrode and the drain electrode of the driving transistor and the anode of the light-emitting device;
a third transistor, one of a source and a drain of the third transistor being connected to one of the source and the drain of the driving transistor, the other of the source and the drain of the third transistor being connected to a reference voltage signal, a gate of the third transistor being connected to a sense control signal;
the other of the source electrode and the drain electrode of the driving transistor is connected with a positive power supply signal, and the cathode of the light emitting device is connected with a negative power supply signal.
10. A display panel comprising a pixel driving circuit according to any one of claims 1 to 9.
CN202311376076.XA 2023-10-23 2023-10-23 Pixel driving circuit and display panel Pending CN117456951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311376076.XA CN117456951A (en) 2023-10-23 2023-10-23 Pixel driving circuit and display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311376076.XA CN117456951A (en) 2023-10-23 2023-10-23 Pixel driving circuit and display panel

Publications (1)

Publication Number Publication Date
CN117456951A true CN117456951A (en) 2024-01-26

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311376076.XA Pending CN117456951A (en) 2023-10-23 2023-10-23 Pixel driving circuit and display panel

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Country Link
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