CN117453495B - Chip supporting online error correction and debugging, design method and related equipment - Google Patents
Chip supporting online error correction and debugging, design method and related equipment Download PDFInfo
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Abstract
The invention relates to the technical field of chips, and discloses a chip supporting online error correction and debugging, a design method and related equipment, wherein the chip comprises: the register monitoring module acquires the value of the appointed register in real time, acquires a first preset abnormal triggering condition according to the first preset configuration information, and throws out an abnormality if the value of the register meets the first preset abnormal triggering condition; the memory monitoring module acquires the value of the appointed memory address in real time, acquires a second preset abnormal triggering condition according to the second preset configuration information, and throws out an abnormality if the value of the memory address meets the second preset abnormal triggering condition; and the locking module is used for carrying out corresponding configuration modification in the unlocking state after the chip is reset, and locking after the configuration modification is completed. The chip supporting online error correction and debugging can find out the abnormality and timely process the abnormality in the running process of the program, thereby improving the reliability and the safety of the program.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a chip supporting online error correction and debugging, a design method, a computer device, and a computer readable storage medium.
Background
In modern computer systems, debugging of programs is one of the important links in computer software development, and the purpose of the debugging is to find various problems in program codes and improve the correctness, safety and reliability of program operation. The traditional program debugging method adopts breakpoint setting and code tracking technology, and is a program which is directly executed, and the method is more effective because the execution flow of the program is single. However, due to programmer's errors, malware, and other factors, various exceptions may occur to the program during chip operation, such as stack overflows, memory leaks, illegal access to memory, and the like. These abnormal conditions may cause problems such as program crashes, data loss, information leakage, security holes, etc.
Many monitoring and debugging techniques have been proposed, such as breakpoints, traces, debuggers, etc. However, these techniques require a programmer to manually set breakpoints or print debug information, and debugging and repair can only be performed after a program crashes or an abnormal situation occurs. The debugging mode is low in efficiency, difficult to cope with abnormal conditions of complex programs and poor in reliability and safety.
Disclosure of Invention
The embodiment of the invention aims to provide a chip supporting online error correction and debugging so as to solve the problems of troublesome operation monitoring, poor reliability and poor safety of the existing program in the chip.
In order to solve the technical problems, in a first aspect, an embodiment of the present invention provides a chip supporting online error correction and debugging, where the chip includes a register monitoring module, a memory monitoring module, and a locking module;
the register monitoring module is used for preselecting a designated register, acquiring the value of the designated register in real time, acquiring a first preset abnormal triggering condition according to first preset configuration information, and throwing out an abnormality if the value of the register meets the first preset abnormal triggering condition;
the memory monitoring module is used for presetting a designated memory address, acquiring the value of the designated memory address in real time, acquiring a second preset abnormal triggering condition according to second preset configuration information, and throwing out an abnormality if the value of the memory address meets the second preset abnormal triggering condition;
the locking module is used for being in an unlocking state after the chip is reset, and can carry out corresponding configuration modification on the first preset configuration information and/or the second preset configuration information in the unlocking state, and the locking module is used for locking after the configuration modification is finished, and cannot carry out any configuration modification after the locking.
Preferably, when the first preset abnormal triggering condition is a magnitude relation, the register monitoring module includes:
the first acquisition unit is used for acquiring a plurality of monitoring table entries, and each monitoring table entry monitors the value of one register;
the first control register is used for configuring the current monitoring table item;
a first threshold register for setting a first threshold;
the first judging unit is used for judging whether the value of the register and the first threshold value trigger an exception when the size relation is met or trigger an exception when the size relation is not met;
if the size relation is configured to be met, an abnormality occurs, and if the size relation is met, the abnormality is triggered;
if the size relationship is configured not to be satisfied, an exception occurs, and if not, an exception is triggered.
Preferably, when the first preset abnormal triggering condition is a range relationship, the chip further includes:
a second threshold register for setting a second threshold;
the second judging unit is used for judging whether the value of the register, the first threshold value and the second threshold value trigger the abnormality when the range relation is met or trigger the abnormality when the range relation is not met;
if the range relation is configured to be met, an abnormality occurs, and if the range relation is met, the abnormality is triggered;
if an exception occurs when the range relationship is configured not to be satisfied, then if not, an exception is triggered.
Preferably, the second judging unit is further configured to set a register selection bit to select the SP register;
setting the condition judgment bit satisfies the following relationship: the first threshold value is less than or equal to the SP register is less than or equal to the second threshold value;
setting the exception triggering bit to trigger an exception when the following relationship is not satisfied: the first threshold value is less than or equal to the SP register is less than or equal to the second threshold value;
setting a first threshold value register as a stack bottom address, and setting a second threshold value register as a stack top address;
setting an enabling bit to be in a locking state, and completing configuration of the monitoring table item of the current bar;
and triggering an exception when the value of the SP register exceeds the range from the value of the stack bottom address to the value of the stack top address.
Preferably, the first preset exception triggering condition further includes a relationship and a read-write state for monitoring a value designated bit of the register.
Preferably, when the second preset abnormal triggering condition is a size relationship, the memory monitoring module includes:
the second acquisition unit is used for acquiring a plurality of monitoring table entries, and each monitoring table entry monitors the value of one memory address;
the second control register is used for configuring the current monitoring table item;
a third threshold register for setting a third threshold;
the third judging unit is used for judging the value of the memory address and a preset third threshold value; triggering an exception when the size relationship is satisfied or triggering an exception when the size relationship is not satisfied;
if the size relation is configured to be met, an abnormality occurs, and if the size relation is met, the abnormality is triggered;
if the size relationship is configured not to be satisfied, an exception occurs, and if not, an exception is triggered.
Preferably, when the second preset abnormal triggering condition is a range relationship, the memory monitoring module further includes:
a fourth threshold register for setting a fourth threshold;
a fourth judging module, configured to judge whether the value of the memory address, the third threshold value and a preset fourth threshold value are an exception triggering when the range relation is satisfied or an exception triggering when the range relation is not satisfied;
if the range relation is configured to be met, an abnormality occurs, and if the range relation is met, the abnormality is triggered;
if an exception occurs when the range relationship is configured not to be satisfied, then if not, an exception is triggered.
In a second aspect, an embodiment of the present invention provides a chip design method supporting online error correction and debugging, the chip design method including the steps of:
preselect the appointed register, obtain the value of the appointed register in real time, and obtain the first and presetted exception triggering condition according to the first and presetted configuration information, if the value of the said register meets the said first and presetted exception triggering condition, throw out the exception;
presetting a designated memory address, acquiring the value of the designated memory address in real time, acquiring a second preset abnormal triggering condition according to second preset configuration information, and throwing out an abnormality if the value of the memory address meets the second preset abnormal triggering condition;
after the chip is reset, the first preset configuration information and the second preset configuration information are in an unlocking state, corresponding configuration modification can be carried out on the first preset configuration information and/or the second preset configuration information in the unlocking state, locking is carried out after the configuration modification is finished, and any configuration modification cannot be carried out after the locking.
In a third aspect, an embodiment of the present invention provides a computer device, where the computer device includes a memory, a processor, and a chip design program that is stored on the memory and is capable of running on the processor and supports online error correction and debugging, and the processor implements the steps in the chip design method that supports online error correction and debugging as described above when executing the chip design program that supports online error correction and debugging.
In a fourth aspect, an embodiment of the present invention provides a computer readable storage medium having stored thereon a chip design program supporting online debugging and debugging, which when executed by a processor, implements the steps in the chip design method supporting online debugging and debugging as described above.
Compared with the prior art, the chip supporting online error correction and debugging in the invention acquires the value of the designated register in real time, acquires a first preset abnormal trigger condition according to the first preset configuration information, and throws out an abnormality if the value of the register meets the first preset abnormal trigger condition; acquiring a value of a specified memory address in real time, acquiring a second preset abnormal triggering condition according to second preset configuration information, and throwing out an abnormality if the value of the memory address meets the second preset abnormal triggering condition; after the chip is reset, the locking module is in an unlocking state, corresponding configuration modification can be carried out on the first preset configuration information and/or the second preset configuration information in the unlocking state, locking is carried out after the configuration modification is finished, and any configuration modification cannot be carried out after the locking; therefore, the abnormality can be found and processed in time in the running process of the program, and the reliability and the safety of the program are improved. Meanwhile, when program execution in the chip is problematic, the program execution can directly enter into an exception processing process, detailed information of the problem is recorded, and debugging efficiency is improved. The method can monitor the values of any register and memory address, can adapt to different programs and application scenes, and has high flexibility. The method can be realized by adding the register monitoring module and the memory monitoring module, does not need to carry out large-scale modification on the existing CPU architecture, and is simple to realize.
Drawings
For a clearer description of the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the description below are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art, wherein:
FIG. 1 is a block diagram of a chip supporting online error correction and debugging provided by an embodiment of the present invention;
FIG. 2 is a block diagram of a register monitor module according to an embodiment of the present invention;
FIG. 3 is a block diagram of a memory monitor module according to an embodiment of the present invention;
FIG. 4 is a flow chart of a chip design method supporting online error correction and debugging provided by an embodiment of the present invention;
fig. 5 is a block diagram of a computer device according to an embodiment of the present invention.
Detailed Description
The following description of the technical solutions in the embodiments of the present invention will be clear and complete, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
Referring to fig. 1-3, an embodiment of the present invention provides a chip 200 supporting online error correction and debugging, the chip includes a register monitor module 201, a memory monitor module 202, and a lock module 203;
the register monitoring module 201 is configured to pre-select a specified register, obtain a value of the specified register in real time, obtain a first preset exception triggering condition according to first preset configuration information, and throw an exception if the value of the register meets the first preset exception triggering condition.
The method comprises the steps of monitoring the value of a selected register in real time in the execution process of a software program by a central processing unit (Central Processing Unit, CPU for short), judging the value of the selected register according to a first preset abnormal triggering condition, triggering an abnormality when the value of the selected register meets the set first preset abnormal triggering condition, and obtaining corresponding register configuration information.
In this embodiment, a plurality of registers are preselected, values of each specified register are obtained in real time, and register configuration information of each specified register is obtained according to a plurality of first preset exception triggering conditions.
Alternatively, the acquisition is not just data of one register, but values of a plurality of registers may be monitored simultaneously. For example, the register monitoring option is used for monitoring the value of the SP register, so that the stack overflow condition can be well detected. When the value of the SP register exceeds the range of the stack, an exception is triggered, and program breakdown or security problem caused by stack overflow is prevented.
The memory monitoring module 202 is configured to preset a specified memory address, obtain a value of the specified memory address in real time, obtain a second preset abnormal triggering condition according to second preset configuration information, and throw out an abnormality if the value of the memory address meets the second preset abnormal triggering condition.
And when the value of the memory address meets the set second preset abnormal triggering condition, triggering an abnormality and obtaining corresponding memory address configuration information.
Alternatively, the acquisition is not just a value of a memory address, but may monitor values of multiple segments of memory space at the same time. For example, the value of a key variable is monitored using a memory address monitoring option, and the condition that the variable is illegally modified can be detected. When the value of the variable in the memory is illegally modified, an exception is triggered, and the security problem caused by the fact that the data is tampered is prevented.
And the locking module 203 is configured to, after the chip is reset, be in an unlocked state, and in the unlocked state, perform corresponding configuration modification on the first preset configuration information and/or the second preset configuration information, lock after the configuration modification is completed, and cannot perform any configuration modification after the locking.
When the chip is reset, the locking module 203 is in an unlocked state, and software can configure the corresponding register monitoring module 201 and the memory monitoring module 202. After the configuration is completed, the software sets the lock module to the lock state according to the corresponding register monitor module 201 and memory monitor module 202, after which the software will no longer be able to modify any configuration of the register monitor module 201, memory monitor module 202, and lock module 203.
Specifically, the register monitoring module 201 obtains the value of the specified register in real time, and obtains a first preset abnormal triggering condition according to first preset configuration information, and if the value of the register meets the first preset abnormal triggering condition, the abnormality is thrown out; the memory monitoring module 202 obtains the value of the specified memory address in real time, and obtains a second preset abnormal triggering condition according to second preset configuration information, and if the value of the memory address meets the second preset abnormal triggering condition, the memory address throws out an abnormality; after the chip is reset, the locking module 203 is in an unlocked state, and in the unlocked state, the first preset configuration information and/or the second preset configuration information can be subjected to corresponding configuration modification, and after the configuration modification is finished, the locking module 203 locks, and after the configuration modification, any configuration modification cannot be performed. Therefore, the abnormality can be found and processed in time in the running process of the program, and the reliability and the safety of the program are improved. Meanwhile, when the program execution is problematic, the program execution can directly enter an exception handling process, detailed information of the problem is recorded, and debugging efficiency is improved. The method can monitor the values of any register and memory address, can adapt to different programs and application scenes, and has high flexibility. The implementation can be realized by adding the register monitoring module 201 and the memory monitoring module 202, and the large-scale modification of the existing CPU architecture is not needed, so that the implementation is simple.
In this embodiment, when the first preset abnormal triggering condition is a size relationship, the register monitoring module 201 includes:
the first obtaining unit 2011 is configured to obtain a plurality of monitoring entries, where each monitoring entry monitors a value of one of the registers.
Wherein 0 represents disable and 1 represents enable by enabling the monitor table entry for enabling or disabling the monitor table entry.
A first threshold register 2012 for setting a first threshold;
a first control register 2013, configured to configure the current monitoring entry;
a first determining unit 2014, configured to determine whether the value of the register and the first threshold value trigger an exception when the size relationship is satisfied or trigger an exception when the size relationship is not satisfied;
if the size relation is configured to be met, an abnormality occurs, and if the size relation is met, the abnormality is triggered;
if the size relationship is configured not to be satisfied, an exception occurs, and if not, an exception is triggered.
In this embodiment, when the first preset abnormal triggering condition is a range relationship, the register monitoring module 201 further includes:
a second threshold register 2015 for setting a second threshold;
a second determining unit 2016 configured to determine whether the value of the register, the first threshold value, and the second threshold value satisfy the range relationship, or not satisfy the range relationship;
if the range relation is configured to be met, an abnormality occurs, and if the range relation is met, the abnormality is triggered;
if an exception occurs when the range relationship is configured not to be satisfied, then if not, an exception is triggered.
The first threshold value and the second threshold value are set through corresponding threshold value registers, and each threshold value register is provided with one threshold value. Of course, the threshold value is not only the first threshold value and the second threshold value, but also may be plural, and specifically, the threshold value is selectively set according to the requirement.
Specifically, the locking mode is used for locking the monitoring table item; wherein 0: an unlocked state. The reset is set to 0 by the hardware, at which time the software can modify the 3 registers of the entry. 1: a locked state. After the software sets the bit to 1, the entry is locked, and the corresponding 3 registers cannot be modified unless the chip is reset.
For selecting the registers to be monitored, a total of 1024 registers can be selected for 10 bits. The specific bit number can be adjusted according to actual conditions, and the number of registers to be monitored can be covered.
Wherein, different values of the first preset abnormal trigger condition represent different judging conditions, and the final conditions are obtained by combining the different judging conditions with the two threshold registers. The value of the register is denoted by V-! =means not equal. T1 and T2 represent the first threshold value of the first threshold value register 2012 and the second threshold value of the second threshold value register, respectively, and the different values of the condition judgment bits have the following meanings. The definition of bit number and judging condition can be adjusted according to actual condition in concrete implementation.
The magnitude relation of the first preset abnormal triggering condition is as follows:
V=T1，V<T1，V≤T1，V>T1，V≥T1，V!=T1。
wherein, the range relation is as follows:
T1<V<T2，T1≤V<T2，T1<V≤T2，T1≤V≤T2。
in this embodiment, the first preset exception triggering condition further includes a relationship and a read-write state for monitoring a value designated bit of the register.
The relationship of monitoring the value-designated bits of the register is as follows:
V&T1=T2，V&T1<T2，V&T1≤T2，V&T1>T2，V&T1≥T2，V&T1!=T2，V|T1=T2，V|T1<T2，V|T1≤T2，V|T1>T2，V|T1≥T2，V|T1!=T2。
this allows the monitoring to be accurate in place, and for a certain value, more accurate.
The read-write state includes a register being read, a register being written, and a register value being changed. At this time, the first threshold value and the second threshold value do not generate specific threshold values, and only the read-write state can be realized.
In this way, by specifying bit monitoring and read-write states for the register values according to different size relationships and range relationships, whether the above-described judgment conditions are satisfied or not is judged, and 0: the condition is satisfied to trigger exception, 1: the condition triggering abnormality is not satisfied, and the abnormal condition triggering condition can be selected according to the setting of a user. The method can directly enter the exception handling process when the program execution has problems, record the detailed information of the problems and improve the debugging efficiency.
In this embodiment, the second determining unit 2016 is further configured to set a register selection bit to select an SP register; setting the condition judgment bit satisfies the following relationship: the first threshold value is less than or equal to the SP register is less than or equal to the second threshold value; setting the exception triggering bit to trigger an exception when the following relationship is not satisfied: the first threshold value is less than or equal to the SP register is less than or equal to the second threshold value; setting the first threshold register 2012 to the bottom of the stack address and the second threshold register 2015 to the top of the stack address; setting an enabling bit to be in a locking state, and completing configuration of the monitoring table item of the current bar; and triggering an exception when the value of the SP register exceeds the range from the value of the stack bottom address to the value of the stack top address.
Specifically, the register select bit of the first control register 2013 is set to select the SP register. Setting the condition judgment bit of the first control register 2013 to 9, namely T1 is equal to or more than SP is equal to or less than T2; setting the exception triggering bit of the monitoring register to be 1, namely triggering exception when the conditions are not met; the first threshold register 2012 is set to the bottom of the stack address and the second threshold register 2015 is set to the top of the stack address. The enable bit of the first control register 2013 is set to 1, i.e. the present monitoring entry is opened. During program execution, if the value of SP exceeds the specified range from the bottom of the stack to the top of the stack, the register monitoring module 201 triggers an exception, and at this time, a stack overflow exception, such as a print error message, may be handled by the exception handler and program execution is terminated.
In this embodiment, the chip further includes a plurality of register monitor modules 201 and a plurality of memory monitor modules 202.
In this embodiment, when the second preset abnormal triggering condition is a size relationship, the memory monitoring module 202 includes:
a second obtaining unit 2021, configured to obtain a plurality of monitoring entries, where each monitoring entry monitors a value of one of the memory addresses;
a second control register 2022, configured to configure the current monitoring table entry;
a third threshold register 2023 for setting a third threshold;
a third judging unit 2024, configured to judge the value of the memory address and the third threshold; triggering an exception when the size relationship is satisfied or triggering an exception when the size relationship is not satisfied;
if the size relation is configured to be met, an abnormality occurs, and if the size relation is met, the abnormality is triggered;
if the size relationship is configured not to be satisfied, an exception occurs, and if not, an exception is triggered.
Specifically, 0: an unlocked state. The reset is set to 0 by the hardware, at which point the software can modify the 4 registers of the entry. 1: a locked state. After the software sets the bit to 1, the entry is locked, and the corresponding 4 registers cannot be modified unless the chip is reset.
For selecting the registers to be monitored, a total of 1024 registers can be selected for 10 bits. The specific bit number can be adjusted according to actual conditions, and the number of registers to be monitored can be covered.
In this embodiment, when the second preset abnormal triggering condition is a range relationship, the memory monitoring module 202 further includes:
a fourth threshold register 2025 for setting a fourth threshold;
a fourth judging unit 2026, configured to judge whether the value of the memory address, the third threshold value, and the fourth threshold value are an exception triggered when the range relation is satisfied or an exception triggered when the range relation is not satisfied;
if the range relation is configured to be met, an abnormality occurs, and if the range relation is met, the abnormality is triggered;
if an exception occurs when the range relationship is configured not to be satisfied, then if not, an exception is triggered.
Specifically, different values of the second preset abnormal trigger condition represent different judging conditions, and the two threshold registers are combined to obtain a final condition. The value of the register is denoted by V-! =means not equal. T1 and T2 represent the third threshold value of the third threshold value register 2023 and the fourth threshold value of the fourth threshold value register 2025, respectively, and the different values of the condition judgment bits have the following meanings. The definition of bit number and judging condition can be adjusted according to actual condition in concrete implementation.
The magnitude relation of the second preset abnormal triggering condition is as follows:
V=T1，V<T1，V≤T1，V>T1，V≥T1，V!=T1。
the range relation of the second preset abnormal triggering condition is as follows:
T1<V<T2，T1≤V<T2，T1<V≤T2，T1≤V≤T2。
in this embodiment, the second preset exception triggering condition further includes a relationship and a read-write state for monitoring a value designated bit of the register.
The relationship of the second preset exception triggering condition for monitoring the value designated bit of the register is as follows:
V&T1=T2，V&T1<T2，V&T1≤T2，V&T1>T2，V&T1≥T2，V&T1!=T2，V|T1=T2，V|T1<T2，V|T1≤T2，V|T1>T2，V|T1≥T2，V|T1!=T2。
this allows the monitoring to be accurate in place, and for a certain value, more accurate.
The read-write state of the second preset abnormal trigger condition comprises that a register is read, the register is written and a register value is changed. At this time, the third threshold value and the fourth threshold value do not generate specific threshold values, and only the read-write state can be realized.
Optionally, the above threshold values not only include the third threshold value and the fourth threshold value, but also may be 3, 4, 5 threshold values, etc., and multiple threshold value settings may be added according to the needs of actual situations, which will not be described herein.
Example two
As shown in fig. 4, an embodiment of the present invention provides a chip design method supporting online error correction and debugging, the chip design method including the steps of:
s1, preselecting a designated register, acquiring the value of the designated register in real time, acquiring a first preset abnormal trigger condition according to first preset configuration information, and throwing out an abnormality if the value of the register meets the first preset abnormal trigger condition.
The method comprises the steps of monitoring the value of a selected register in real time in the execution process of a software program by a central processing unit (Central Processing Unit, CPU for short), judging the value of the selected register according to a first preset abnormal triggering condition, triggering an abnormality when the value of the selected register meets the set first preset abnormal triggering condition, and obtaining corresponding register configuration information.
In this embodiment, a plurality of registers are preselected, values of each specified register are obtained in real time, and register configuration information of each specified register is obtained according to a plurality of first preset exception triggering conditions.
In particular, the acquisition is not just data of one register, but values of a plurality of registers can be monitored simultaneously. For example, the register monitoring option is used for monitoring the value of the SP register, so that the stack overflow condition can be well detected. When the value of the SP register exceeds the range of the stack, an exception is triggered, and program breakdown or security problem caused by stack overflow is prevented.
And S2, presetting a designated memory address, acquiring the value of the designated memory address in real time, acquiring a second preset abnormal triggering condition according to second preset configuration information, and throwing out an abnormality if the value of the memory address meets the second preset abnormal triggering condition.
And when the value of the memory address meets the set second preset abnormal triggering condition, triggering an abnormality and obtaining corresponding memory address configuration information.
In this embodiment, a plurality of memory addresses are preset, a value of each specified memory address is obtained in real time, and memory configuration information of each specified memory address is obtained according to a plurality of second preset abnormal triggering conditions.
Specifically, the acquisition is not just a value of a memory address, but may also monitor values of multiple segments of memory space at the same time. For example, the value of a key variable is monitored using a memory address monitoring option, and the condition that the variable is illegally modified can be detected. When the value of the variable in the memory is illegally modified, an exception is triggered, and the security problem caused by the fact that the data is tampered is prevented.
Step S3, after the chip is reset, the first preset configuration information and the second preset configuration information are in an unlocking state, corresponding configuration modification can be carried out on the first preset configuration information and/or the second preset configuration information in the unlocking state, locking is carried out after the configuration modification is finished, and any configuration modification cannot be carried out after the locking.
Specifically, acquiring a value of the specified register in real time, acquiring a first preset abnormal triggering condition according to first preset configuration information, and throwing out an abnormality if the value of the register meets the first preset abnormal triggering condition; acquiring a value of the designated memory address in real time, acquiring a second preset abnormal triggering condition according to second preset configuration information, and throwing an abnormality if the value of the memory address meets the second preset abnormal triggering condition; after the chip is reset, the first preset configuration information and the second preset configuration information are in an unlocking state, corresponding configuration modification can be carried out on the first preset configuration information and/or the second preset configuration information in the unlocking state, locking is carried out after the configuration modification is finished, and any configuration modification cannot be carried out after the locking; therefore, the abnormality can be found and processed in time in the running process of the program, and the reliability and the safety of the program are improved. Meanwhile, when the program execution is problematic, the program execution can directly enter an exception handling process, detailed information of the problem is recorded, and debugging efficiency is improved. The method can monitor the values of any register and memory address, can adapt to different programs and application scenes, and has high flexibility. The implementation can be realized by adding the register monitoring module 201 and the memory monitoring module 202, and the large-scale modification of the existing CPU architecture is not needed, so that the implementation is simple.
In this embodiment, the technical effects and principles achieved by the chip design method supporting online error correction and debugging are the same as those achieved by the chip 200 supporting online error correction and debugging provided in the first embodiment of the present invention, and are not described herein.
Example III
As shown in fig. 5, the present claimed embodiment provides a computer device 300, the computer device including a memory 301, a processor 302, and a chip design program supporting online error correction and debugging stored on the memory 301 and executable on the processor 302, the processor 302 implementing the steps in the chip design method supporting online error correction and debugging as described above when executing the chip design program supporting online error correction and debugging;
step S1, preselecting a designated register, acquiring a value of the designated register in real time, acquiring a first preset abnormal trigger condition according to first preset configuration information, and throwing out an abnormality if the value of the register meets the first preset abnormal trigger condition;
s2, presetting a designated memory address, acquiring a value of the designated memory address in real time, acquiring a second preset abnormal triggering condition according to second preset configuration information, and throwing out an abnormality if the value of the memory address meets the second preset abnormal triggering condition;
step S3, after the chip is reset, the first preset configuration information and the second preset configuration information are in an unlocking state, corresponding configuration modification can be carried out on the first preset configuration information and/or the second preset configuration information in the unlocking state, locking is carried out after the configuration modification is finished, and any configuration modification cannot be carried out after the locking.
The memory 301 may be used to store software programs as well as various data. The memory 301 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like; the storage data area may store data (such as audio data, phonebook, etc.) created according to the use of the handset, etc. In addition, memory 301 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage device.
The processor 302 is a control center of the terminal, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or executing software programs and/or modules stored in the memory 301 and calling data stored in the memory 301, thereby performing overall monitoring of the terminal. Processor 302 may include one or more processing units; preferably, the processor 302 may integrate an application processor that primarily handles operating systems, user interfaces, applications, etc., with a modem processor that primarily handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 302.
It should be noted that, when the computer device 300 is in use, it can achieve the technical effects achieved by the above-mentioned chip design method supporting online error correction and debugging, and the description of the above-mentioned chip design method supporting online error correction and debugging is omitted here.
Example IV
The present invention provides a computer-readable storage medium having stored thereon a chip design program supporting on-line error correction and debugging, which when executed by a processor, implements the steps in the chip design method supporting on-line error correction and debugging as described above.
Wherein the computer readable storage medium is selected from Read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic disk or optical disk.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present invention.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes or direct or indirect application in other related technical fields are included in the scope of the present invention.
Claims (7)
1. The chip supporting online error correction and debugging is characterized by comprising a register monitoring module, a memory monitoring module and a locking module;
the register monitoring module is used for preselecting a designated register, acquiring the value of the designated register in real time, acquiring a first preset abnormal triggering condition according to first preset configuration information, and throwing out an abnormality if the value of the register meets the first preset abnormal triggering condition;
the memory monitoring module is used for presetting a designated memory address, acquiring the value of the designated memory address in real time, acquiring a second preset abnormal triggering condition according to second preset configuration information, and throwing out an abnormality if the value of the memory address meets the second preset abnormal triggering condition;
the locking module is used for being in an unlocking state after the chip is reset, and can carry out corresponding configuration modification on the first preset configuration information and/or the second preset configuration information in the unlocking state, and locking is carried out after the configuration modification is finished, and any configuration modification cannot be carried out after the locking;
when the first preset abnormal triggering condition is a size relation, the register monitoring module comprises:
the first acquisition unit is used for acquiring a plurality of monitoring table entries, and each monitoring table entry monitors the value of one register;
the first control register is used for configuring the current monitoring table item;
a first threshold register for setting a first threshold;
the first judging unit is used for judging whether the value of the register and the first threshold value trigger an exception when the size relation is met or trigger an exception when the size relation is not met;
if the size relation is configured to be met, an abnormality occurs, and if the size relation is met, the abnormality is triggered;
if the size relation is configured to be not met, an abnormality occurs, and if the size relation is not met, the abnormality is triggered;
when the first preset abnormal triggering condition is a range relation, the chip further comprises:
a second threshold register for setting a second threshold;
the second judging unit is used for judging whether the value of the register, the first threshold value and the second threshold value trigger the abnormality when the range relation is met or trigger the abnormality when the range relation is not met;
if the range relation is configured to be met, an abnormality occurs, and if the range relation is met, the abnormality is triggered;
if the range relation is configured to be not satisfied, an abnormality occurs, and if the range relation is not satisfied, the abnormality is triggered;
the second judging unit is further used for setting a register selection bit to be a SP register;
setting the condition judgment bit satisfies the following relationship: the first threshold value is less than or equal to the SP register is less than or equal to the second threshold value;
setting the exception triggering bit to trigger an exception when the following relationship is not satisfied: the first threshold value is less than or equal to the SP register is less than or equal to the second threshold value;
setting a first threshold value register as a stack bottom address, and setting a second threshold value register as a stack top address;
setting an enabling bit to be in a locking state, and completing configuration of the monitoring table item of the current bar;
and triggering an exception when the value of the SP register exceeds the range from the value of the stack bottom address to the value of the stack top address.
2. The chip supporting on-line error correction and debugging according to claim 1, wherein the first preset exception triggering condition further comprises a relationship and a read-write status for monitoring a value-specific bit of the register.
3. The chip supporting online error correction and debugging according to claim 1, wherein when the second preset exception triggering condition is a magnitude relation, the memory monitoring module comprises:
the second acquisition unit is used for acquiring a plurality of monitoring table entries, and each monitoring table entry monitors the value of one memory address;
the second control register is used for configuring the current monitoring table item;
a third threshold register for setting a third threshold;
the third judging unit is used for judging the value of the memory address and a preset third threshold value; triggering an exception when the size relationship is satisfied or triggering an exception when the size relationship is not satisfied;
if the size relation is configured to be met, an abnormality occurs, and if the size relation is met, the abnormality is triggered;
if the size relationship is configured not to be satisfied, an exception occurs, and if not, an exception is triggered.
4. The chip supporting online error correction and debugging according to claim 3, wherein when the second preset exception triggering condition is a range relationship, the memory monitoring module further comprises:
a fourth threshold register for setting a fourth threshold;
a fourth judging module, configured to judge whether the value of the memory address, the third threshold value and a preset fourth threshold value are an exception triggering when the range relation is satisfied or an exception triggering when the range relation is not satisfied;
if the range relation is configured to be met, an abnormality occurs, and if the range relation is met, the abnormality is triggered;
if an exception occurs when the range relationship is configured not to be satisfied, then if not, an exception is triggered.
5. The chip design method supporting online error correction and debugging is characterized by comprising the following steps of:
preselect the appointed register, obtain the value of the appointed register in real time, and obtain the first and presetted exception triggering condition according to the first and presetted configuration information, if the value of the said register meets the said first and presetted exception triggering condition, throw out the exception;
presetting a designated memory address, acquiring the value of the designated memory address in real time, acquiring a second preset abnormal triggering condition according to second preset configuration information, and throwing out an abnormality if the value of the memory address meets the second preset abnormal triggering condition;
after the chip is reset, the first preset configuration information and the second preset configuration information are in an unlocking state, corresponding configuration modification can be carried out on the first preset configuration information and/or the second preset configuration information in the unlocking state, locking is carried out after the configuration modification is finished, and any configuration modification cannot be carried out after the locking;
when the first preset abnormal triggering condition is a size relation, the chip design method further comprises the following sub-steps:
acquiring a plurality of monitoring table entries, wherein each monitoring table entry monitors the value of one register; configuring the monitoring table item of the current bar; setting a first threshold; judging whether the value of the register and the first threshold value trigger an exception when the size relation is met or not;
if the size relation is configured to be met, an abnormality occurs, and if the size relation is met, the abnormality is triggered;
if the size relation is configured to be not met, an abnormality occurs, and if the size relation is not met, the abnormality is triggered;
when the first preset abnormal triggering condition is in a range relation, the chip design method further comprises the following sub-steps:
setting a second threshold; judging whether the value of the register, the first threshold value and the second threshold value meet the range relation or not meet the range relation;
if the range relation is configured to be met, an abnormality occurs, and if the range relation is met, the abnormality is triggered;
if the range relation is configured to be not satisfied, an abnormality occurs, and if the range relation is not satisfied, the abnormality is triggered;
the chip design method further comprises the following steps:
setting a register select bit to select an SP register;
setting the condition judgment bit satisfies the following relationship: the first threshold value is less than or equal to the SP register is less than or equal to the second threshold value;
setting the exception triggering bit to trigger an exception when the following relationship is not satisfied: the first threshold value is less than or equal to the SP register is less than or equal to the second threshold value;
setting a first threshold value register as a stack bottom address, and setting a second threshold value register as a stack top address;
setting an enabling bit to be in a locking state, and completing configuration of the monitoring table item of the current bar;
and triggering an exception when the value of the SP register exceeds the range from the value of the stack bottom address to the value of the stack top address.
6. A computer device comprising a memory, a processor and a chip design program supporting on-line error correction and debugging stored on the memory and executable on the processor, the processor implementing the steps in the chip design method supporting on-line error correction and debugging as claimed in claim 5 when executing the chip design program supporting on-line error correction and debugging.
7. A computer-readable storage medium, on which a chip design program supporting on-line error correction and debugging is stored, which when executed by a processor implements the steps in the chip design method supporting on-line error correction and debugging as claimed in claim 5.
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