CN117453470A - Verification method, device, equipment and medium for memory bank in system-level chip - Google Patents
Verification method, device, equipment and medium for memory bank in system-level chip Download PDFInfo
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Abstract
The invention discloses a method, a device, equipment and a medium for verifying a storage body in a system-in-chip. The method comprises the following steps: obtaining standard parameters corresponding to the memory bank to be tested and modeling and processing the standard parameters to obtain a simulation memory bank corresponding to the memory bank to be tested; acquiring a preset code position corresponding to the analog memory bank, and determining storage data corresponding to the analog memory bank according to the preset code position; and sequentially testing the simulation memory bank to obtain a test result corresponding to the simulation memory bank by using a preset read-write test model and a preset error injection test model according to a set test sequence, and generating a verification result corresponding to the simulation memory bank according to a difference relation between the stored data and the test result. By the technical scheme, the specific functions of the memory bank can be automatically checked, and the research and development period of the chip is reduced.
Description
Technical Field
The present invention relates to the field of memory bank testing technologies, and in particular, to a method, an apparatus, a device, and a medium for verifying a memory bank in a system-in-a-chip.
Background
With the increase of chip design scale, the chip interior is generally composed of a large number of block-shaped memory banks and logic function modules. Where each bank is often composed of several memory cells, complex System on Chip (SoC) typically contains hundreds to thousands of banks in block combination inside. Therefore, if a large-scale memory bank inside the SoC is instantiated, how to guarantee the functional integrity of the memory bank integrated inside the SoC is a very big challenge.
In the prior art, test engineers are often required to expend a great deal of effort in designing test platforms and test cases to ensure the correctness of each instantiated memory bank function and performance. Furthermore, the design engineer checks whether the integrated connection of the memory bank is missed through the code checking tool, and verifies whether the read-write function of the logic function module on the memory bank is correct by creating the test cases related to the memory bank access.
However, if the design code checking tool is used, the specific function of the memory bank cannot be checked, and only static checking can be performed to check whether the connection line is missing. The conventional verification strategy is difficult to cover the read-write and access of each storage unit of the storage body, and engineers need to spend a great deal of time to cover the access of the storage unit, so that the research and development period of the chip is greatly improved. Therefore, how to automatically check the specific functions of the memory bank and reduce the research and development period of the chip is a problem to be solved urgently at present.
Disclosure of Invention
The invention provides a method, a device, equipment and a medium for verifying a memory bank in a system-level chip, which can solve the problems that the specific function of the memory bank cannot be automatically verified and the research and development period of the chip is long.
According to one aspect of the present invention, there is provided a method for verifying a memory bank in a system-on-chip, including:
obtaining standard parameters corresponding to a memory bank to be tested, and modeling and processing the standard parameters to obtain a simulated memory bank corresponding to the memory bank to be tested;
acquiring a preset code position corresponding to an analog memory bank, and determining storage data corresponding to the analog memory bank according to the preset code position;
and sequentially testing the analog memory bank to obtain a test result corresponding to the analog memory bank by using a preset read-write test model and a preset error injection test model according to a set test sequence, and generating a verification result corresponding to the analog memory bank according to a difference relation between the stored data and the test result.
According to another aspect of the present invention, there is provided a verification apparatus for a memory bank in a system-on-chip, including:
the preprocessing module is used for obtaining standard parameters corresponding to the memory bank to be tested and modeling and processing the standard parameters to obtain a simulated memory bank corresponding to the memory bank to be tested;
The data acquisition module is used for acquiring a preset code position corresponding to the analog memory bank and determining storage data corresponding to the analog memory bank according to the preset code position;
and the verification test module is used for sequentially testing and processing the analog memory bank by using a preset read-write test model and a preset error injection test model according to a set test sequence to obtain a test result corresponding to the analog memory bank, and generating a verification result corresponding to the analog memory bank according to the difference relation between the stored data and the test result.
According to another aspect of the present invention, there is provided an electronic apparatus including:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,
the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform a method of verifying a bank in a system-on-chip according to any of the embodiments of the present invention.
According to another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to implement a method for verifying a memory bank in a system-on-a-chip according to any of the embodiments of the present invention when executed.
According to the technical scheme, the standard parameters corresponding to the memory bank to be tested are processed through modeling to obtain the analog memory bank corresponding to the memory bank to be tested, further, storage data corresponding to the analog memory bank is determined according to the preset code positions corresponding to the analog memory bank, finally, the preset read-write test model and the preset error-injection test model are utilized according to the set test sequence, the analog memory bank is processed through sequential testing to obtain the test result corresponding to the analog memory bank, the verification result corresponding to the analog memory bank is generated according to the difference relation between the storage data and the test result, the problem that in the prior art, automatic verification cannot be conducted on specific functions of the memory bank, the research and development period of a chip is long is solved, automatic verification can be conducted on specific functions of the memory bank, and the research and development period of the chip is reduced.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for verifying a memory bank in a system-on-chip according to a first embodiment of the present invention;
FIG. 2 is a flowchart of a method for verifying a memory bank in a system-on-chip according to a second embodiment of the present invention;
FIG. 3 is a flowchart of an alternative method for verifying a memory bank in a system-on-chip according to a second embodiment of the present invention;
FIG. 4 is a schematic diagram of a verification device for a memory bank in a system-on-chip according to a third embodiment of the present invention;
fig. 5 is a schematic structural diagram of an electronic device implementing a method for verifying a memory bank in a system-on-chip according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "target," "preset," and the like in the description and the claims of the present invention and the above drawings are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
Fig. 1 is a flowchart of a method for verifying a memory bank in a system-in-chip according to a first embodiment of the present invention, where the method may be performed by a verification device for a memory bank in a system-in-chip, and the verification device for a memory bank in a system-in-chip may be implemented in hardware and/or software, and the verification device for a memory bank in a system-in-chip may be configured in an electronic device, and may be configured in a computer device, for example. As shown in fig. 1, the method includes:
S110, obtaining standard parameters corresponding to the memory bank to be tested, and modeling and processing the standard parameters to obtain the analog memory bank corresponding to the memory bank to be tested.
The memory bank to be tested may refer to a memory bank that needs to be checked inside the SoC. The standard parameters may refer to descriptive parameters associated with the memory bank to be tested.
In an alternative embodiment, the standard parameters may include: the target key domain segment and the corresponding target key domain value. The target key domain segment may refer to a parameter name related to the memory bank to be tested. Illustratively, the target key domain segment may include: storage type, storage block depth, storage block width, storage block protection type, port description, etc. If the memory bank to be tested is a read port model, the port description may specifically further include: clock signal, chip select signal, read address signal, read data signal, read delay, etc. If the memory bank to be tested is a write port model, the port description may specifically further include: clock signal, chip select signal, write enable, write address signal, write data signal, write delay, etc. If the memory bank to be tested is a check port model, the port description may specifically further include: check enable function, fault injection enable function, fault type, etc.
The target key domain value may refer to an actual parameter value corresponding to the target key domain segment. For example, if the target critical field segment is of a storage type, the target critical field value may be normal memory, parity (parity) protected memory, or corrected error code (Error Correcting Code, ECC) protected memory. If the target key domain segment is the depth of the storage block, the target key domain value may be a numerical value type. If the target key domain segment is the memory block width, the target key domain value may be a numerical type. If the target key domain segment is of a storage block protection type, the target key domain value may be unprotected, odd parity protected, even parity protected or ECC protected.
The modeling process may refer to an operation of performing a simulation model construction according to the target key domain segment in the standard parameter and the corresponding target key domain value. The simulated memory bank may refer to a simulation model corresponding to the memory bank to be tested, which is obtained after the modeling process.
S120, acquiring a preset code position corresponding to the analog memory bank, and determining storage data corresponding to the analog memory bank according to the preset code position.
The preset code position may refer to a preset data storage position. The preset code locations may present a hierarchy of memory banks in the design. Typically, a designer will preset the code location corresponding to the memory bank during the source code design stage. The stored data may refer to data stored in a preset code location. For example, the data stored in the analog memory bank in advance, or the data written later in the test process, etc. may be used.
S130, sequentially testing the analog memory bank to obtain a test result corresponding to the analog memory bank by using a preset read-write test model and a preset error injection test model according to a set test sequence, and generating a verification result corresponding to the analog memory bank according to a difference relation between the stored data and the test result.
The set test sequence may refer to a preset sequence of test flows. The setting may be performed according to actual application requirements, or may be performed according to a priority order of each test flow. The embodiment of the present invention is not limited thereto.
The preset read-write test model may refer to a preset model for testing the read-write function of the analog memory bank. In an alternative embodiment, the preset read-write test model may include: the device comprises a single read-write test unit, a continuous read-write test unit and a concurrent read-write test unit.
The preset error injection test model may refer to a preset model for testing the error injection function of the analog memory bank. In an alternative embodiment, the default fault injection test model may include: a single bit error injection test unit and a multi-bit error injection test unit.
The test result may refer to each model result obtained by integrating after test processing according to a preset read-write test model and a preset error injection test model. The differential relationship may refer to a differential result between the stored data and the corresponding test result. The verification result may refer to a verification determination result generated according to a difference relationship between the stored data and the corresponding test result. The verification result may be verification passing or verification failing, for example.
According to the technical scheme, the standard parameters corresponding to the memory bank to be tested are processed through modeling to obtain the analog memory bank corresponding to the memory bank to be tested, further, storage data corresponding to the analog memory bank is determined according to the preset code positions corresponding to the analog memory bank, finally, the preset read-write test model and the preset error-injection test model are utilized according to the set test sequence, the analog memory bank is processed through sequential testing to obtain the test result corresponding to the analog memory bank, the verification result corresponding to the analog memory bank is generated according to the difference relation between the storage data and the test result, the problem that in the prior art, automatic verification cannot be conducted on specific functions of the memory bank, the research and development period of a chip is long is solved, automatic verification can be conducted on specific functions of the memory bank, and the research and development period of the chip is reduced.
Example two
Fig. 2 is a flowchart of a method for verifying a memory bank in a system-on-chip according to a second embodiment of the present invention, where the method is added based on the above embodiment, and in this embodiment, the adding operation before the obtaining of the standard parameter corresponding to the memory bank to be tested may specifically include: acquiring a target memory bank in a system-in-chip in a target vehicle, and taking the target memory bank as a memory bank to be tested; and adding the operation after generating the verification result corresponding to the simulated memory bank according to the difference relation between the stored data and the test result, wherein the operation specifically comprises the following steps: and generating error assertion corresponding to the memory bank to be tested according to the verification result, and displaying and processing the error assertion. As shown in fig. 2, the method includes:
s210, acquiring a target memory bank in a system-in-chip in a target vehicle, and taking the target memory bank as a memory bank to be tested.
The target vehicle may refer to a vehicle carrying a memory bank that needs to be verified. The target memory bank may refer to a memory bank selected for verification in a system on a chip in the target vehicle.
S220, obtaining standard parameters corresponding to the memory bank to be tested, and modeling and processing the standard parameters to obtain the analog memory bank corresponding to the memory bank to be tested.
Specifically, after the memory bank to be tested is determined, the standard parameters corresponding to the memory bank to be tested can be obtained, and then, the target key domain segments in the standard parameters and the corresponding target key domain values are utilized to carry out simulation model construction, so that the simulation memory bank corresponding to the memory bank to be tested is obtained, and convenience is provided for subsequent verification operation.
S230, acquiring a preset code position corresponding to the analog memory bank, and determining storage data corresponding to the analog memory bank according to the preset code position.
Specifically, after the modeling process obtains the analog memory bank corresponding to the memory bank to be tested, the memory data corresponding to the analog memory bank can be determined according to the preset code position, so that convenience is provided for the subsequent verification operation.
It should be noted that, in the embodiment of the present invention, the acquisition order of the storage data is not limited, and the form of the storage data used in each read-write test and the error-injection test is not particularly limited.
S240, testing and processing the analog memory bank by using a single read-write test unit according to a set test sequence to obtain a single read-write test result corresponding to the analog memory bank.
The single read-write test unit may refer to a unit for verifying a read-write function of the analog memory bank. The single read-write test result may refer to a test result obtained after the analog memory bank is tested and processed by the single read-write test unit.
In particular, since the memory bank may be composed of one line and one line of data. Therefore, the first row of data can be written into the analog memory bank through the single read-write test unit, then the first row of data is read, and for example, the operation is executed on the subsequent rows until all rows in the analog memory bank complete the single read-write test, and each data read respectively is used as a single read-write test result corresponding to the analog memory bank.
S250, if the single read-write test result meets the preset read-write test requirement, the continuous read-write test unit is utilized to test and process the analog memory bank, and the continuous read-write test result corresponding to the analog memory bank is obtained.
The preset read-write test requirement may refer to a preset read-write test evaluation standard. For example, the preset read-write test requirement may be that the write data corresponding to each row in the analog memory bank is the same as the read data corresponding to each row. The continuous read-write test unit may refer to a unit that checks a continuous read-write function of the analog memory bank. The continuous read-write test result may refer to a test result obtained after the analog memory bank is tested and processed by the continuous read-write test unit.
Specifically, the continuous read-write test unit can start writing data to the first row of the analog memory bank until the last row, then, the data is read from the first row of the analog memory bank until the last row, and all the read data are used as continuous read-write test results corresponding to the analog memory bank.
And S260, if the continuous read-write test result meets the preset read-write test requirement, testing and processing the analog memory bank by using the concurrent read-write test unit to obtain a concurrent read-write test result corresponding to the analog memory bank.
The concurrent read/write test unit may refer to a unit that performs verification on a concurrent read/write function of an analog memory bank. The concurrent read/write test result may refer to a test result obtained after the analog memory bank is tested and processed by the concurrent read/write test unit.
Specifically, the data can be written into the first row of the analog memory bank through the concurrent read-write test unit, further, the data is written into the second row of the analog memory bank, meanwhile, the first row of data is read, and for example, the second row of data is required to be read while the data is written into the third row of the analog memory bank until the reading of all rows in the analog memory bank is completed, and all the read data are used as the concurrent read-write test result corresponding to the analog memory bank.
It should be noted that, in the embodiment of the present invention, when the concurrent read/write test unit is used to verify the analog memory bank, it is necessary to ensure that the analog memory bank is a multi-port memory bank.
In an optional implementation manner, after the test processing of the analog memory bank by using the concurrent read-write test unit to obtain a concurrent read-write test result corresponding to the analog memory bank, the method may further include: triggering the analog memory bank according to a preset triggering condition to generate a corresponding triggering result; and judging and processing the self-fault injection function of the analog memory bank according to the existence quantity of fault interrupts in the trigger result.
The preset trigger condition may refer to a preset trigger processing simulation memory bank starting condition. For example, the trigger instruction may be issued according to the actual application requirement. The trigger result may refer to an error report result obtained after the analog memory bank is triggered and processed according to a preset trigger condition. An error interrupt may refer to the cause of an error reported by the bank controller. The presence number may refer to the number of false interrupts in the trigger result. In general, the number of triggers in the preset trigger condition may be compared with the number of false interrupts in the trigger result, to determine whether the analog memory bank has a self-fault injection function. The self-injection function may refer to a function of injecting errors into the memory bank itself.
Specifically, after the concurrent read-write test unit is utilized to test and process the analog memory bank to obtain the concurrent read-write test result corresponding to the analog memory bank, a trigger can be initiated to the analog memory bank, and the corresponding trigger result is obtained, so that whether the analog memory bank has a self-fault injection function can be judged by checking whether a memory bank controller in the analog memory bank reports an error interrupt. An effective basis is provided for subsequent fault injection tests.
S270, testing and processing the analog memory bank by using a single-bit error injection testing unit to obtain a single-bit error injection testing result corresponding to the analog memory bank.
The single-bit fault injection test unit may refer to a unit for testing a single-bit strong line fault injection function of an analog memory bank. The single-bit error injection test result may refer to a test result obtained after the analog memory bank is tested and processed by the single-bit error injection test unit.
Specifically, after the analog memory bank is triggered, if the number of triggering times in the preset triggering condition is the same as the number of existence of error interrupts in the triggering result, the analog memory bank is indicated to have a self-fault injection function, and further, the single-bit fault injection function of the analog memory bank can be tested by using the single-bit fault injection test unit.
In an optional implementation manner, after the testing and processing the analog memory bank by using the single-bit error injection testing unit to obtain a single-bit error injection testing result corresponding to the analog memory bank, the method further includes: and interrupting processing the single-bit fault injection test result.
The interrupt processing may refer to a processing operation of reporting an interrupt to a central processing unit (Central Processing Unit, CPU) after checking an error. For example, interrupt handling operations may be implemented using an interrupt handling model. In the embodiment of the present invention, the interrupt model may be composed of an interrupt register including an interrupt enable register, an interrupt status register, and an interrupt clearing register, and an interrupt programming model including an interrupt enable flow, an interrupt shut-down flow, and an interrupt clearing flow.
Thus, by performing interrupt processing after processing the analog memory bank by the single-bit fault injection test unit, it is possible to realize test for simulating CPU response and interrupt and returning to normal processing flow from the interrupt. The verification function of the analog memory bank is more perfected.
And S280, if the single-bit error injection test result meets the preset error injection test requirement, testing and processing the analog memory bank by utilizing a multi-bit error injection test unit to obtain a multi-bit error injection test result corresponding to the analog memory bank.
The preset error-injection test requirement may refer to a preset error-injection test evaluation standard. For example, the preset error-injection test requirement may be that the error-injection test result is different from the corresponding stored data. The multi-bit fail test unit may refer to a unit that performs a test on a multi-bit fail-safe function of an analog memory bank. The multi-bit error injection test result may refer to a test result obtained after the simulation memory bank is tested and processed by the multi-bit error injection test unit.
Specifically, since the memory controller of the analog memory after the single-bit error injection test may rely on ECC protection to correct errors, only the alarm effect is achieved. And the errors after the multi-bit error injection test cannot be corrected, and at the moment, the vehicle will have faults. Therefore, in order to comprehensively verify the fault injection function of the analog memory bank, the single-bit fault injection test unit can be used for testing and processing the analog memory bank, and then the multi-bit fault injection test unit can be used for testing and processing the analog memory bank.
In an optional implementation manner, after the test processing of the analog memory bank by using the multi-bit error injection test unit to obtain a multi-bit error injection test result corresponding to the analog memory bank, the method further includes: and interrupting processing the multi-bit fault injection test result. Specifically, after the simulation memory bank is tested and processed by the multi-bit fault injection test unit, the simulation CPU response and interrupt can be realized through interrupt processing, and the test of the normal processing flow is resumed from the interrupt. The verification function of the analog memory bank is more perfected.
S290, generating a verification result corresponding to the simulated memory bank according to the difference relation between the stored data and the test result, generating error assertion corresponding to the memory bank to be tested according to the verification result, and displaying and processing the error assertion.
Wherein, the false assertion may refer to an evaluation result of the verification result. For example, the false assertion may include a verification result, and a root cause of the verification result. Specifically, the cause of the test failure may be included.
Specifically, after the read-write test and the error injection test are sequentially performed, the read-write test result including the read data in the read-write test may be compared with the stored data including the write data input in advance, a corresponding verification result may be generated according to the comparison result, or the error injection test result in the error injection test may be compared with the stored data, and a corresponding verification result may be generated according to the comparison result. And generating error assertion corresponding to the memory bank to be tested according to the verification result, displaying and processing the error assertion, and providing effective basis for subsequent operation.
According to the technical scheme of the embodiment of the invention, the target memory bank in the system-in-chip of the target vehicle is used as the memory bank to be tested, the standard parameters corresponding to the memory bank to be tested are modeled and processed, the simulated memory bank corresponding to the memory bank to be tested is obtained, further, the memory data corresponding to the simulated memory bank is determined according to the preset code positions corresponding to the simulated memory bank, finally, the simulated memory bank is tested and processed by the single read-write test unit according to the set test sequence, the single read-write test result corresponding to the simulated memory bank is obtained, if the single read-write test result meets the preset read-write test requirement, the simulated memory bank is tested and processed by the continuous read-write test unit, the continuous read-write test result meets the preset read-write test requirement, the simulated memory bank is tested and processed by the concurrent read-write test unit, the simulated memory bank is obtained, the simulated memory bank is tested and processed by the single bit error test unit, the single bit error test result corresponding to the simulated memory bank is obtained, if the single bit error test result meets the preset test requirement, the multiple bit error test result corresponding to the simulated memory bank is automatically tested, the test result is automatically tested according to the test result is generated, and the error test result can not be verified, and the test result can be automatically verified according to the test result is automatically, and the test result is automatically tested according to the test result is verified, and the test result is automatically according to the test result is tested, the research and development period of the chip is reduced.
Fig. 3 is a flowchart of an alternative method for verifying a memory bank in a system-on-chip according to an embodiment of the present invention. Specifically, firstly, modeling processing is performed on a memory bank to be tested to obtain a simulated memory bank corresponding to the memory bank to be tested, further, storage data corresponding to the simulated memory bank is determined according to a preset code position corresponding to the simulated memory bank, further, a single read-write test is performed on the simulated memory bank by using a single read-write test unit to obtain a single read-write test result corresponding to the simulated memory bank, if the single read-write test result does not meet a preset read-write test requirement, a verification result corresponding to the simulated memory bank is generated according to a difference relation between the storage data containing the write data in the single read-write test process and the single read-write test result, and the verification is ended. And if the single read-write test result meets the preset read-write test requirement, testing and processing the analog memory bank by using the continuous read-write test unit to obtain a continuous read-write test result corresponding to the analog memory bank. If the continuous read-write test result does not meet the preset read-write test requirement, generating a verification result corresponding to the simulated memory bank according to the difference relation between the stored data containing the written data in the continuous read-write test process and the continuous read-write test result, and ending. And if the continuous read-write test result meets the preset read-write test requirement, testing and processing the analog memory bank by using the concurrent read-write test unit to obtain a concurrent read-write test result corresponding to the analog memory bank. If the concurrent read-write test result does not meet the preset read-write test requirement, generating a verification result corresponding to the simulated memory bank according to the difference relation between the memory data containing the written data in the concurrent read-write test process and the concurrent read-write test result, and ending. If the concurrent read-write test result meets the preset read-write test requirement, triggering the processing simulation memory bank according to the preset triggering condition to generate a corresponding triggering result, and judging whether the processing simulation memory bank has a self-fault injection function or not according to the existence number of fault interrupts in the triggering result. If the analog memory bank does not have the self-fault injection function, a check result containing fault failure is generated and ended. If the simulated memory bank has the self-fault injection function, the simulated memory bank is tested and processed by the single-bit fault injection test unit to obtain a single-bit fault injection test result corresponding to the simulated memory bank, and if the single-bit fault injection test result does not meet the preset fault injection test requirement, a check result corresponding to the simulated memory bank is generated according to the difference relation between the stored data and the single-bit fault injection test result, and the check result is ended. If the single-bit error injection test result meets the preset error injection test requirement, interrupting processing of the single-bit error injection test result, and utilizing the multi-bit error injection test unit to test and process the analog memory bank to obtain a multi-bit error injection test result corresponding to the analog memory bank. If the multi-bit error injection test result does not meet the preset error injection test requirement, generating a verification result corresponding to the simulated memory bank according to the difference relation between the stored data and the multi-bit error injection test result, and ending. If the multi-bit error injection test result meets the preset error injection test requirement, interrupting processing of the multi-bit error injection test result. Thereby, the whole checking process of the memory bank to be tested is completed.
Example III
Fig. 4 is a schematic structural diagram of a verification device for a memory bank in a system-on-chip according to a third embodiment of the present invention. As shown in fig. 4, the apparatus includes: a preprocessing module 310, a data acquisition module 320, and a verification test module 330;
the preprocessing module 310 is configured to obtain standard parameters corresponding to a to-be-tested memory bank and perform modeling processing on the standard parameters to obtain a simulated memory bank corresponding to the to-be-tested memory bank;
the data acquisition module 320 is configured to acquire a preset code position corresponding to the analog memory bank, and determine storage data corresponding to the analog memory bank according to the preset code position;
and the verification test module 330 is configured to utilize a preset read-write test model and a preset error injection test model according to a set test sequence, perform sequential test on the analog memory bank to obtain a test result corresponding to the analog memory bank, and generate a verification result corresponding to the analog memory bank according to a difference relationship between the stored data and the test result.
According to the technical scheme, the standard parameters corresponding to the memory bank to be tested are processed through modeling to obtain the analog memory bank corresponding to the memory bank to be tested, further, storage data corresponding to the analog memory bank is determined according to the preset code positions corresponding to the analog memory bank, finally, the preset read-write test model and the preset error-injection test model are utilized according to the set test sequence, the analog memory bank is processed through sequential testing to obtain the test result corresponding to the analog memory bank, the verification result corresponding to the analog memory bank is generated according to the difference relation between the storage data and the test result, the problem that in the prior art, automatic verification cannot be conducted on specific functions of the memory bank, the research and development period of a chip is long is solved, automatic verification can be conducted on specific functions of the memory bank, and the research and development period of the chip is reduced.
Optionally, the verification device for the memory bank in the system-in-chip may further include: the memory bank determining module is used for acquiring a target memory bank in a system-in-chip in a target vehicle before the standard parameters corresponding to the memory bank to be tested are acquired, and taking the target memory bank as the memory bank to be tested;
the verification device of the memory bank in the system-in-chip may further include: and the post-processing module is used for generating error assertion corresponding to the memory bank to be tested according to the verification result after generating the verification result corresponding to the simulated memory bank according to the difference relation between the stored data and the test result, and displaying and processing the error assertion.
Optionally, the preset read-write test model includes: the device comprises a single read-write test unit, a continuous read-write test unit and a concurrent read-write test unit;
the verification test module 330 may specifically include: the device comprises a first test unit, a second test unit and a third test unit;
the first test unit is used for testing and processing the analog memory bank by utilizing the single read-write test unit to obtain a single read-write test result corresponding to the analog memory bank;
the second test unit is used for testing and processing the analog memory bank by using the continuous read-write test unit if the single read-write test result meets the preset read-write test requirement, so as to obtain a continuous read-write test result corresponding to the analog memory bank;
And the third test unit is used for testing and processing the analog memory bank by using the concurrent read-write test unit if the continuous read-write test result meets the preset read-write test requirement, so as to obtain the concurrent read-write test result corresponding to the analog memory bank.
Optionally, the default fault injection test model includes: a single bit error injection test unit and a multi-bit error injection test unit;
the verification test module 330 may specifically include: a fourth test unit and a fifth test unit;
the fourth test unit is used for testing and processing the analog memory bank by utilizing the single-bit error injection test unit to obtain a single-bit error injection test result corresponding to the analog memory bank;
and the fifth test unit is used for testing and processing the analog memory bank by utilizing the multi-bit error injection test unit if the single-bit error injection test result meets the preset error injection test requirement, so as to obtain a multi-bit error injection test result corresponding to the analog memory bank.
Optionally, the verification device for the memory bank in the system-in-chip may further include: the first interrupt processing module is used for interrupting the processing of the single-bit error injection test result after the single-bit error injection test unit is utilized to test and process the analog memory bank to obtain the single-bit error injection test result corresponding to the analog memory bank;
The verification device of the memory bank in the system-in-chip may further include: and the second interrupt processing module is used for interrupting the processing of the multi-bit error injection test result after the multi-bit error injection test unit is used for testing and processing the analog memory bank to obtain the multi-bit error injection test result corresponding to the analog memory bank.
Optionally, the standard parameters include: the target key domain segment and the corresponding target key domain value.
Optionally, the verification device for the memory bank in the system-in-chip may further include: the error injection function verification module is used for triggering and processing the analog memory bank according to a preset triggering condition after the analog memory bank is tested and processed by the concurrent read-write test unit to obtain a concurrent read-write test result corresponding to the analog memory bank, and generating a corresponding triggering result; and judging and processing the self-fault injection function of the analog memory bank according to the existence quantity of fault interrupts in the trigger result.
The verification device for the memory bank in the system-on-chip provided by the embodiment of the invention can execute the verification method for the memory bank in the system-on-chip provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.
Example IV
Fig. 5 shows a schematic diagram of an electronic device 410 that may be used to implement an embodiment of the invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Electronic equipment may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.
As shown in fig. 5, the electronic device 410 includes at least one processor 420, and a memory, such as a Read Only Memory (ROM) 430, a Random Access Memory (RAM) 440, etc., communicatively coupled to the at least one processor 420, wherein the memory stores computer programs executable by the at least one processor, and the processor 420 may perform various suitable actions and processes according to the computer programs stored in the Read Only Memory (ROM) 430 or the computer programs loaded from the storage unit 490 into the Random Access Memory (RAM) 440. In RAM440, various programs and data required for the operation of electronic device 410 may also be stored. The processor 420, ROM 430, and RAM440 are connected to each other by a bus 450. An input/output (I/O) interface 460 is also connected to bus 450.
Various components in the electronic device 410 are connected to the I/O interface 460, including: an input unit 470 such as a keyboard, a mouse, etc.; an output unit 480 such as various types of displays, speakers, and the like; a storage unit 490, such as a magnetic disk, an optical disk, or the like; and a communication unit 4100, such as a network card, modem, wireless communication transceiver, etc. The communication unit 4100 allows the electronic device 410 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunications networks.
Processor 420 may be a variety of general-purpose and/or special-purpose processing components having processing and computing capabilities. Some examples of processor 420 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 420 performs the various methods and processes described above, such as a method of checking memory banks in a system on chip.
The method comprises the following steps:
obtaining standard parameters corresponding to a memory bank to be tested, and modeling and processing the standard parameters to obtain a simulated memory bank corresponding to the memory bank to be tested;
Acquiring a preset code position corresponding to an analog memory bank, and determining storage data corresponding to the analog memory bank according to the preset code position;
and sequentially testing the analog memory bank to obtain a test result corresponding to the analog memory bank by using a preset read-write test model and a preset error injection test model according to a set test sequence, and generating a verification result corresponding to the analog memory bank according to a difference relation between the stored data and the test result.
In some embodiments, the method of verification of memory banks in a system on chip may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as storage unit 490. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 410 via the ROM 430 and/or the communication unit 4100. When the computer program is loaded into RAM 440 and executed by processor 420, one or more steps of the method of verification of memory banks in a system on chip described above may be performed. Alternatively, in other embodiments, processor 420 may be configured to perform the method of verifying the memory banks in the system on chip in any other suitable manner (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.
The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method for verifying a memory bank in a system-on-chip, comprising:
obtaining standard parameters corresponding to a memory bank to be tested, and modeling and processing the standard parameters to obtain a simulated memory bank corresponding to the memory bank to be tested;
acquiring a preset code position corresponding to an analog memory bank, and determining storage data corresponding to the analog memory bank according to the preset code position;
and sequentially testing the analog memory bank to obtain a test result corresponding to the analog memory bank by using a preset read-write test model and a preset error injection test model according to a set test sequence, and generating a verification result corresponding to the analog memory bank according to a difference relation between the stored data and the test result.
2. The method according to claim 1, further comprising, before the obtaining the standard parameters corresponding to the memory bank to be tested:
acquiring a target memory bank in a system-in-chip in a target vehicle, and taking the target memory bank as a memory bank to be tested;
after generating the verification result corresponding to the simulated memory bank according to the difference relation between the stored data and the test result, the method further comprises:
and generating error assertion corresponding to the memory bank to be tested according to the verification result, and displaying and processing the error assertion.
3. The method of claim 1, wherein the pre-set read-write test model comprises: the device comprises a single read-write test unit, a continuous read-write test unit and a concurrent read-write test unit;
and sequentially testing and processing the analog memory bank by using a preset read-write test model to obtain a test result corresponding to the analog memory bank, wherein the method comprises the following steps:
testing and processing the analog memory bank by using a single read-write test unit to obtain a single read-write test result corresponding to the analog memory bank;
if the single read-write test result meets the preset read-write test requirement, testing and processing the analog memory bank by using a continuous read-write test unit to obtain a continuous read-write test result corresponding to the analog memory bank;
And if the continuous read-write test result meets the preset read-write test requirement, testing and processing the analog memory bank by using the concurrent read-write test unit to obtain a concurrent read-write test result corresponding to the analog memory bank.
4. The method of claim 1, wherein the predetermined fault injection test model comprises: a single bit error injection test unit and a multi-bit error injection test unit;
and sequentially testing and processing the simulation memory bank by using a preset fault injection test model to obtain a test result corresponding to the simulation memory bank, wherein the method comprises the following steps:
testing and processing the analog memory bank by using a single-bit error injection testing unit to obtain a single-bit error injection testing result corresponding to the analog memory bank;
and if the single-bit error injection test result meets the preset error injection test requirement, testing and processing the analog memory bank by utilizing a multi-bit error injection test unit to obtain a multi-bit error injection test result corresponding to the analog memory bank.
5. The method according to claim 4, further comprising, after the processing the analog memory bank by the single-bit error injection test unit to obtain a single-bit error injection test result corresponding to the analog memory bank:
interrupting processing the single-bit fault injection test result;
After the multi-bit error injection test unit is used for testing and processing the analog memory bank to obtain a multi-bit error injection test result corresponding to the analog memory bank, the method further comprises the following steps:
and interrupting processing the multi-bit fault injection test result.
6. The method of claim 1, wherein the standard parameters include: the target key domain segment and the corresponding target key domain value.
7. The method according to claim 3, further comprising, after the processing the analog memory bank by the concurrent read/write test unit to obtain a concurrent read/write test result corresponding to the analog memory bank:
triggering the analog memory bank according to a preset triggering condition to generate a corresponding triggering result;
and judging and processing the self-fault injection function of the analog memory bank according to the existence quantity of fault interrupts in the trigger result.
8. A device for verifying a memory bank in a system-on-chip, comprising:
the preprocessing module is used for obtaining standard parameters corresponding to the memory bank to be tested and modeling and processing the standard parameters to obtain a simulated memory bank corresponding to the memory bank to be tested;
the data acquisition module is used for acquiring a preset code position corresponding to the analog memory bank and determining storage data corresponding to the analog memory bank according to the preset code position;
And the verification test module is used for sequentially testing and processing the analog memory bank by using a preset read-write test model and a preset error injection test model according to a set test sequence to obtain a test result corresponding to the analog memory bank, and generating a verification result corresponding to the analog memory bank according to the difference relation between the stored data and the test result.
9. An electronic device, the electronic device comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,
the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the method of checking a memory bank in a system on a chip of any one of claims 1-7.
10. A computer readable storage medium storing computer instructions for causing a processor to perform the method of verifying a memory bank in a system-on-chip of any one of claims 1-7.
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