CN117453035A - Method, device, equipment and storage medium for controlling power consumption of chip - Google Patents

Method, device, equipment and storage medium for controlling power consumption of chip Download PDF

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Publication number
CN117453035A
CN117453035A CN202311412013.5A CN202311412013A CN117453035A CN 117453035 A CN117453035 A CN 117453035A CN 202311412013 A CN202311412013 A CN 202311412013A CN 117453035 A CN117453035 A CN 117453035A
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data
memory
chip
volatile memory
nonvolatile memory
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柯剑平
叶晖
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Guangzhou Particle Microelectronics Co ltd
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Guangzhou Particle Microelectronics Co ltd
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Priority to CN202311412013.5A priority Critical patent/CN117453035A/en
Publication of CN117453035A publication Critical patent/CN117453035A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)

Abstract

The application discloses a power consumption control method, a device, equipment and a storage medium of a chip, aiming at the problem of high power consumption, the following technical scheme is provided, and according to business data interaction information, a time value of data interaction and an interactive data volume are generated; when the time value of data interaction and the data quantity of interaction are within a first preset range, backing up the data in the volatile memory into the nonvolatile memory; powering off the volatile memory; when a wake-up signal is received, acquiring a starting code preset in a nonvolatile memory; backing up data in the nonvolatile memory to the volatile memory by using a starting code; powering down the nonvolatile memory; the service is processed according to the data in the volatile memory and the service code for processing the service. The power-off volatile memory enters a sleep state and the power-off nonvolatile memory enters a working state, so that the power consumption of the chip in the sleep state and the working state is reduced.

Description

Method, device, equipment and storage medium for controlling power consumption of chip
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a method, an apparatus, a device, and a storage medium for controlling power consumption of a chip.
Background
With the development of energy conservation of electronic products, power consumption of chips in the electronic products is a key factor in determining energy consumption of the electronic products. That is, the power consumption of the chip determines the power consumption of the electronic product.
The existing method for reducing the power consumption is that when the system is dormant, data is stored in a nonvolatile memory, and other parts are powered off. When the system wakes up, the system is loaded first and then the service is performed.
However, in the application fields with high requirements for low power consumption, for example, in the field of portable computers, the wake-up time and power consumption cannot meet the application fields with high practical requirements for low power consumption by powering off other parts except the nonvolatile memory under the condition of less workload or more workload.
Disclosure of Invention
Aiming at the defects existing in the prior art, a first object of the application is to provide a power consumption control method of a chip, wherein electric energy in a sleep state is saved through a power-off volatile memory, and electric energy in a low-power wake-up state is saved through the power-off nonvolatile memory.
In order to achieve the above purpose, the present application provides the following technical solutions:
a power consumption control method of a chip comprises the following steps:
acquiring business data interaction information;
generating a time value of data interaction and an interactive data volume according to the business data interaction information;
when the time value of data interaction and the data quantity of interaction are within a first preset range, backing up the data in the volatile memory into the nonvolatile memory;
powering off the volatile memory to cause the chip to enter a first sleep state;
when a wake-up signal is received, acquiring a starting code preset in a nonvolatile memory;
backing up data in the nonvolatile memory to the volatile memory by using a starting code;
powering off the nonvolatile memory to reduce power consumption in the operating state;
the service is processed according to the data in the volatile memory and the service code for processing the service.
Further, when the wake-up signal is received, a start code preset in the nonvolatile memory is acquired, and the method specifically comprises the following steps:
and acquiring a starting code preset in the nonvolatile memory according to the remapping address allocated to the nonvolatile memory.
Further, the method also comprises the following steps:
after the business processing is completed, judging whether adjustment triggering conditions of power distribution strategies of all modules of the chip are met or not according to the time value of data interaction and the data quantity of interaction;
when the adjustment triggering conditions of the power distribution strategies of the modules are met, judging whether the time value of the data interaction and the data quantity of the interaction are within a second preset range or not;
and when the time value of the data interaction and the data quantity of the interaction are in a second preset range, controlling the chip to enter a second sleep state.
Further, when the time value of the data interaction and the data amount of the interaction are within a second preset range, the chip is controlled to enter a second sleep state, and the method specifically comprises the following steps of:
when the time value of data interaction and the data quantity of interaction are within a second preset range, backing up the data in the volatile memory into the nonvolatile memory;
backing up the business execution code to a specific volatile memory;
powering off the non-volatile memory and the non-specific volatile memory to cause the chip to enter a second sleep state;
when a wake-up signal is received, acquiring a service execution code in a specific volatile memory;
the service is processed using the service execution code and the data in the nonvolatile memory.
The interactive data amount in the second preset range is smaller than the interactive data amount in the first preset range, and the sleep time length value in the second preset range is shorter than the sleep time length value in the first preset range.
Further, the volatile memory is: one of static random access memory, dynamic random access memory, synchronous dynamic random access memory.
Further, one of flash memory and eeprom.
Aiming at the defects in the prior art, a second object of the application is to provide a power consumption control device of a chip, which has the advantage of low power consumption.
In order to achieve the above purpose, the present application provides the following technical solutions:
a power consumption control apparatus of a chip, comprising:
the information acquisition unit is used for acquiring business data interaction information;
the time and data production unit is used for generating a time value of data interaction and an interactive data volume according to the business data interaction information;
a data backup first unit for backing up data in the volatile memory to the nonvolatile memory;
the power supply control first unit is used for powering off the volatile memory so as to enable the chip to enter a first sleep state;
a start code acquisition unit for acquiring a start code preset in the nonvolatile memory;
a data backup second unit for backing up the data in the nonvolatile memory to the volatile memory by using the start code;
the power supply controls the second unit to power off the nonvolatile memory so as to reduce the power consumption in the working state;
and the business processing unit is used for processing the business according to the data in the volatile memory and the business code for processing the business.
Further, the start code acquisition unit includes: and the remapping address indicating unit is used for acquiring the starting code preset in the nonvolatile memory according to the remapping address distributed to the nonvolatile memory.
Aiming at the defects existing in the prior art, the third object of the application is to provide equipment with the advantage of low power consumption.
In order to achieve the above purpose, the present application provides the following technical solutions:
an apparatus comprising a processor and a memory;
the processor is configured to execute instructions stored in the memory, so that the device executes the power consumption control method of any one of the chips.
In view of the shortcomings of the prior art, a fourth object of the present application is to provide a computer readable storage medium having the advantage of low power consumption.
In order to achieve the above purpose, the present application provides the following technical solutions:
a computer-readable storage medium comprising instructions that instruct a device to perform the method of controlling power consumption of any one of the chips.
In summary, the present application has the following beneficial effects:
the starting code is arranged in the nonvolatile memory, and in a sleep state, the power consumption of the nonvolatile memory is only required to be kept, so that when the system is awakened, the starting code is only required to be called from the nonvolatile memory, and the system can be awakened. Compared with the method of calling the starting code from the read-only memory, the sleep state has fewer memories for keeping the electric quantity and saves more electric quantity. In addition, after the system is awakened, the volatile memory is powered off in the working state, so that electric energy is saved, and the power consumption in the working state is reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
fig. 1 is a schematic diagram of steps of a power consumption control method of a chip.
Fig. 2 is a schematic diagram illustrating steps after the processing service in fig. 1 is completed.
Fig. 3 is a schematic diagram illustrating a specific step of entering the second sleep state in fig. 2.
Fig. 4 is a schematic diagram of a power consumption control device of a chip.
100. Power consumption control device of chip
1. Information acquisition unit
2. Time and data production unit
3. Data backup first unit
4. Power supply control first unit
5. Start code acquisition unit
51. Remapped address indication unit
6. Data backup second unit
7. Power supply control second unit
8. And a service processing unit.
Detailed Description
For the purposes, technical solutions and advantages of the present application, the technical solutions of the present application will be clearly and completely described below with reference to specific embodiments of the present application and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The application provides a power consumption control method of a chip, referring to fig. 1, comprising the following steps:
s100: and acquiring business data interaction information.
In the application, the chip comprises a non-power-off module, a storage module and a power-off module. The non-powered-off module includes: a timer and a power supply unit. The module capable of being powered off comprises: a Central Processing Unit (CPU), a digital front end unit (Digital Front End, DFE), a radio frequency transceiver (Radio Frequency transceiver, RF transceiver). The memory module includes volatile memory and nonvolatile memory. The volatile memory may be random access memory (RandomAccess Memory, RAM). The nonvolatile Memory may be a Flash Memory (Flash Memory). The business data may be data downloaded when browsing web pages using a computer. The service data may also be an execution instruction sent to the execution device by using the single chip microcomputer. The service data interaction information includes time of service data and the number of service data. The CPU acquires business data interaction information.
S200: and generating a time value of data interaction and the data volume of interaction according to the service data interaction information.
In this application, the time value of data interaction is specifically the time when the data needs to be processed. The amount of data interacted with is in particular the amount of data that needs to be processed.
It will be appreciated that the time value of the interaction by the data may confirm the time range in which the chip is not required to process the data and the time range in which it is required to process. I.e. the time at which the chip is acknowledged to go to sleep and the time at which it wakes up after sleep. The amount of bytes of data processed after the chip wakes up can be confirmed by the amount of data interacted with.
S300: and when the time value of the data interaction and the data quantity of the interaction are within a first preset range, backing up the data in the volatile memory into the nonvolatile memory.
In the present application, the first preset range includes a first sleep time range and a first traffic range. When the time value of the data interaction and the data amount of the interaction are in a first preset range, the time value of the data interaction is in a first sleep time range. The amount of data interacted is within a first traffic range. And the data interaction time is within the first sleep time, the chip does not process data, and the chip can enter a sleep state. And when the data volume is in the first traffic volume range, the chip wakes up after sleeping to process the byte volume of the data.
It will be appreciated that the chip is ready to enter a first sleep state when the time value of the data interaction and the amount of data interacted are within a first preset range. That is, the chip does not process data during sleep. The chip processes data with traffic in a first traffic range after waking up. The volatile memory may be RAM. RAM is typically a temporary storage medium for the operating system or other running programs, and therefore, RAM may be referred to as system memory. RAM is not capable of retaining data when power is turned off. If the data needs to be saved, the data must be written to a non-volatile memory, such as a flash memory.
That is, the volatile memory loses data when it is powered down. The nonvolatile memory does not lose data when power is turned off. And the data in the volatile memory is stored in the nonvolatile memory, so that the data loss caused by the disappearance of the data in the volatile memory during power failure is avoided, and the integrity of the data is ensured.
S400: the volatile memory is powered down to bring the chip into a first sleep state.
In particular, the volatile memory may be a static random access memory (Static RandomAccess Memory, SRAM). The volatile memory, the non-volatile memory, and the powered-down module are powered down in preparation for entering the first sleep state. Only the uninterruptible power supply module operates in a low power mode. In the first sleep state, the current in the chip is 500nA.
It will be appreciated that static random access memory needs to remain powered on to be able to constantly hold stored data. While non-volatile memory is not required to remain powered on to retain data. As can be seen, the power consumption of the volatile memory is greater than that of the nonvolatile memory. Most of electric energy is saved by powering off the volatile memory, and the power consumption of the chip is reduced. In addition, the power is turned off before the sleep state is ready to be entered. That is, when the chip is still in the working state, the power of the volatile memory is cut off before the chip enters the sleep state, and compared with the power cut-off of the volatile memory after the chip enters the sleep state, the power cut-off time is earlier, so that more electric energy is saved, and more power consumption is reduced.
S500: when the wake-up signal is received, a start code preset in the nonvolatile memory is acquired.
Specifically, the wake-up signal is an instruction for switching the chip from the sleep state to the active state. For a computer, the wake-up signal may be a cursor movement signal from a mouse. For a cell phone, the wake-up signal may be a trigger level signal from a switch button. The wake-up signal may also be a level signal sent by a timer when the sleep time has elapsed. The sleep time is derived from the time of the data interaction. The boot code is an instruction for backing up data and service codes in the nonvolatile memory into the volatile memory. The start code is a program set in advance in the nonvolatile memory.
It is understood that a Boot Loader (Boot Loader) solidified in a Read Only Memory (ROM) is loaded into the RAM, and the Boot Loader program is executed, as compared with the Boot chip. On the one hand, in the wake-up process, the program is not required to be called from the read-only memory, so that power supply for the read-only memory is not required, and the power consumption is reduced. On the other hand, the number of memories required to be called during starting is reduced, the wake-up starting step is reduced, the working time is shortened, and therefore the power consumption is reduced.
And the starting code can be flexibly set, a special read-only memory is not needed, and the self-adaption is strong.
In addition, the nonvolatile memory can not lose data under the condition of power failure, so that the starting code is ensured to be successfully called.
Specifically, in a preferred embodiment provided herein, S500: when a wake-up signal is received, a start code preset in a nonvolatile memory is acquired, and the method specifically comprises the following steps:
s501: and acquiring a starting code preset in the nonvolatile memory according to the remapping address allocated to the nonvolatile memory.
In this application, the remapped address is a remapped mapped address for starting power-up. The remapped address is the address of the first instruction read after the chip receives the wake-up signal. The CPU can find the start code in the non-volatile memory based on the remapped address. The nonvolatile memory is in particular a static random access memory.
It will be appreciated that after the chip is powered up, the program basically starts running from the 0 address. That is, the 0 address maps to what memory, and then the start instruction is read from that memory to start normal operation.
Remapping is where the 0 address is originally mapped to read-only memory and is now instead mapped to static random access memory. After remapping to the static random access memory, the wake-up flow of the CPU starts to run from the 0 address, namely, the start code is read from the static random access memory. In other words, in the alternative,
compared with the existing Boot Loader code which is executed and solidified in the read-only memory, the chip is started according to the Boot Loader code. On the one hand, the path for searching the starting code is changed through address remapping, so that the memory for storing the starting code is changed, the memory for storing the starting code can be flexibly configured according to the use condition of the memory, and the applicability of the method is improved. On the other hand, the starting code can be changed, so that the method is suitable for various starting scenes.
S600: and backing up the data in the nonvolatile memory to the volatile memory by using the starting code.
In particular, the volatile memory may be a static random access memory. The nonvolatile memory may be a flash memory.
It can be appreciated that the sram operates faster than the flash memory, so that the efficiency of data processing by the sram is higher and the efficiency of chip processing service is improved. That is, the volatile memory is utilized to perform service data interaction, so that the service processing efficiency is improved.
S700: the non-volatile memory is powered down to reduce power consumption during an operating state.
Specifically, after the nonvolatile memory is powered off, the chip enters a working state.
It can be understood that after waking up, the data is processed by utilizing the volatile memory, the nonvolatile memory is not needed, the nonvolatile memory is powered off, and the power consumption of the working state of the chip is reduced.
S800: the service is processed according to the data in the volatile memory and the service code for processing the service.
In this application, the service code is pre-stored in the nonvolatile memory. By starting the codes, the business codes are backed up to the volatile memory, and the processing of the business can be completed by using the volatile memory, so that the nonvolatile memory is convenient to power off.
Specifically, in a preferred embodiment provided in the present application, referring to fig. 2, the method for controlling power consumption of the chip further includes the following steps:
s900: and after the business processing is completed, judging whether the adjustment triggering conditions of the power distribution strategies of all the modules of the chip are met or not according to the time value of the data interaction and the data quantity of the interaction.
S903: when the adjustment triggering conditions of the power distribution strategies of the modules are met, judging whether the time value of the data interaction and the data quantity of the interaction are within a second preset range.
S904: and when the time value of the data interaction and the data quantity of the interaction are in a second preset range, controlling the chip to enter a second sleep state.
In the application, the chip comprises a non-power-off module, a storage module and a power-off module. The memory module comprises a flash memory and a static random access memory. The individual module power allocation policy is a method of determining which of the uninterruptible power supply module, the flash memory, the static random access memory, and the unpowered power supply module are powered. The adjustment triggering condition means that the current time value of data interaction and the data quantity of interaction are not in the current preset range.
Specifically, the time value of data interaction confirms the sleeping time length of the chip, and the data volume of interaction confirms the data volume which needs to be processed after the chip wakes up. The first sleep time range is preset to be used as a category of long-time sleep. The second sleep time range is preset as a category of short-time sleep. The first data volume range is preset to be used as a category with less workload after waking up. The second data volume range is preset to be used as a category with more workload after waking up.
The first sleep time range and the first data volume range are set as a first preset range to be used as categories with long sleep and little work load after waking up.
The second sleep time range and the first data amount range are set to be a second preset range to be used as categories with short sleep and little work load after waking up.
The first sleep time range and the second data volume range are set to be a third preset range to be used as categories with more work load after long sleep and waking.
And setting a second sleep time range and a second data volume range as a fourth preset range to be used as a category with more work load after short sleep and waking.
The data interaction time and the data volume currently being processed are both within a first preset range, and in this case, the adjustment triggering conditions for meeting the power distribution policy of each module are specifically: and triggering an adjustment program of the power distribution strategy when the data interaction time and the data quantity to be processed are not in the first preset range. The strategy adjustment program specifically comprises the following steps:
s901: and judging whether the time value of the data interaction and the data quantity of the interaction are in a first preset range or not.
S902: and when the time value of the data interaction and the data quantity of the interaction are within a first preset range, entering a first sleep state.
S903: and when the time value of the data interaction and the data volume of the interaction are not in the first preset range, judging whether the time value of the data interaction and the data volume of the interaction are in the second preset range or not.
S904: and when the time value of the data interaction and the data quantity of the interaction are in a second preset range, entering a second sleep state.
S905: and when the time value of the data interaction and the data volume of the interaction are not in the second preset range, judging whether the time value of the data interaction and the data volume of the interaction are in a third preset range or not.
S906: and when the time value of the data interaction and the data quantity of the interaction are in a third preset range, entering a third sleep state.
S907: and when the time value of the data interaction and the data volume of the interaction are not in the third preset range, judging whether the time value of the data interaction and the data volume of the interaction are in a fourth preset range or not.
S908: and when the time value of the data interaction and the data quantity of the interaction are in a fourth preset range, entering a fourth sleep state.
S909: and when the time value of the data interaction and the data quantity of the interaction are not in a fourth preset range, fully waking up the chip.
Specifically, the power allocation policy is to execute a first policy to put the chip into a first sleep state when a time value of data interaction and an amount of data interacted are within a first preset range. And when the time value of the data interaction and the data quantity of the interaction are in a second preset range, executing a second strategy so as to enable the chip to enter a second sleep state. And executing a third strategy when the time value of the data interaction and the data quantity of the interaction are in a third preset range so as to enable the chip to enter a third sleep state. And executing a fourth strategy when the time value of the data interaction and the data quantity of the interaction are in a fourth preset range so as to enable the chip to enter a fourth sleep state.
Specifically, the first strategy comprises the following specific steps: and backing up the data in the volatile memory to the nonvolatile memory. And the volatile memory is powered off, and only the non-powered-off module keeps power to enable the chip to enter a first sleep state. When the wake-up signal is received, a start code preset in the nonvolatile memory is acquired. And backing up the data in the nonvolatile memory to the volatile memory by using the starting code. The non-volatile memory is powered down to reduce power consumption during an operating state. The traffic is processed based on the data in the volatile memory and the code for processing the traffic.
The second strategy comprises the following specific steps: and backing up the data in the volatile memory to the nonvolatile memory. The business execution code is backed up to a specific volatile memory. And powering off the volatile memory and the non-specific volatile memory, wherein only the non-powered-off module and the specific volatile memory remain powered to enable the chip to enter a second sleep state. When a wake-up signal is received, the service execution code in the particular volatile memory is acquired. The service is processed using the service execution code and the data in the nonvolatile memory.
The third strategy comprises the following specific steps: and backing up the data in the volatile memory to the nonvolatile memory. And the volatile memory is powered off, and only the non-powered-off module keeps power to enable the chip to enter a third sleep state. When the wake-up signal is received, the Boot Loader code in the read-only memory is acquired. And starting the system by using the Boot Loader code to restore the working state before sleeping, so as to process the service.
The fourth strategy comprises the following specific steps: setting sleeping time. The static random access device enters a low power consumption state for keeping power consumption so as to enable the chip to enter a fourth sleep state. When the wake-up signal is received, the process of processing the service is executed downwards at the position before sleeping, and the relevant peripheral is awakened to restore the working state before sleeping, so that the service is processed.
In the case of the first strategy, the sleep mode is deep sleep. During sleeping, only the uninterruptible power module in the chip works, and the backup of the register is more, so that the current used in the sleeping process is less.
In the second policy case, the sleep mode is light sleep. During sleeping, the uninterruptible power supply module and the specific volatile memory work in the chip, so that more current is used.
In the third strategy case, the sleep mode is very deep sleep. During sleeping, only the uninterruptible power supply module in the chip works, and the backup of the register is less, so that the current used in the sleeping process is minimum.
In the fourth policy case, the sleep mode is very light sleep. During sleeping, the non-power-off module, the volatile memory, the read-only memory and other parts of the power-off module work in the chip, so that the current is the most used in the sleeping process.
The read-only memory storing the Boot Loader code is a small mask ROM embedded within the processor chip. The mask ROM contains the first code that the processor executes at power-up or reset.
It can be understood that judging the service data time and the service data amount are in which range, and then according to the corresponding power distribution strategy in the range value, adjusting the storage positions of the data and the codes, distributing power to each module of the chip, so that the chip can flexibly and automatically distribute sleep states according to specific service conditions, and has the automatic adaptability of reducing power consumption. And once the wake-up signal is received, the chip rapidly enters a working state, and under the condition of high workload, the system is rapidly waken, so that the working time is reduced, and the power consumption is reduced.
In addition, the selection of at least two sleep states increases the flexible adaptability of the chip sleep state adjustment, so that the application range of the chip is wider.
Specifically, first, whether the first policy is within a first preset range is determined, and when the first policy is within the first preset range, the first policy is executed. And when the second strategy is not in the first preset range, judging whether the second strategy is in a second preset range, and executing the second strategy when the second strategy is in the second preset range. And when the third strategy is not in the second preset range, judging whether the third strategy is in a third preset range, and executing the third strategy when the third strategy is in the third preset range. And finally judging whether the third strategy is in a fourth preset range or not when the third strategy is not in the third preset range, and executing the fourth strategy when the fourth strategy is in the fourth preset range. The first preset range, the second preset range, the third preset range and the fourth preset range jointly cover the whole part of the sleeping condition of the chip.
Specifically, in a preferred embodiment provided in the present application, see fig. 3, S904: when the time value of the data interaction and the data amount of the interaction are in a second preset range, controlling the chip to enter a second sleep state, wherein the method specifically comprises the following steps of:
s9041: and when the time value of the data interaction and the data quantity of the interaction are within a second preset range, backing up the data in the volatile memory into the nonvolatile memory.
S9042: the business execution code is backed up to a specific volatile memory.
S9043: the non-volatile memory and the non-specific volatile memory are powered down to bring the chip into a second sleep state.
S9044: when a wake-up signal is received, the service execution code in the particular volatile memory is acquired.
S9045: the service is processed using the service execution code and the data in the nonvolatile memory.
The interactive data amount in the second preset range is smaller than the interactive data amount in the first preset range, and the sleep time length value in the second preset range is shorter than the sleep time length value in the first preset range.
Specifically, when the volatile memory and the non-specific volatile memory are powered off, only the non-powered-off module and the specific volatile memory remain powered on, and after the power-off step is performed, the chip is controlled to enter a second sleep state. That is, within the second preset range, the system implements the second strategy described above. The service execution code is a program for processing service data.
It can be understood that, after waking up, the service execution code is directly obtained in the specific volatile memory, compared with the mode of obtaining the service execution code by using the Boot Loader code solidified in the read-only memory, the method reduces the starting steps and the starting time, thereby reducing the power consumption during starting.
Specifically, in a preferred embodiment provided in the present application, the volatile memory is: one of static random access memory, dynamic random access memory, synchronous dynamic random access memory.
It can be understood that the method can be used in various volatile memories such as static random access memories, dynamic random access memories, synchronous dynamic random access memories and the like, so that the application range of the method is wider.
Specifically, in a preferred embodiment provided in the present application, the nonvolatile memory is: flash memory, or eeprom.
It can be understood that the method can be used in various nonvolatile memories such as flash memories, EEPROM and the like, so that the application range of the method is wider.
The present application further provides a power consumption control device 100 of a chip, which is adapted to a power consumption control method of a chip, referring to fig. 4, and includes:
an information acquisition unit 1, configured to acquire service data interaction information;
a time and data production unit 2, configured to generate a time value of data interaction and an amount of data to be interacted according to the service data interaction information;
a data backup first unit 3 for backing up data in the volatile memory to the nonvolatile memory;
a power supply control first unit 4 for powering off the volatile memory to bring the chip into a first sleep state;
a start code acquisition unit 5 for acquiring a start code preset in the nonvolatile memory;
a data backup second unit 6 for backing up the data in the nonvolatile memory to the volatile memory by using the start code;
the power supply controls the second unit 7 to power off the nonvolatile memory so as to reduce the power consumption in the working state;
a service processing unit 8 for processing the service according to the data in the volatile memory and the service code for processing the service.
In the application, the chip comprises a non-power-off module, a storage module and a power-off module. The non-powered-off module includes: a timer and a power supply unit. The module capable of being powered off comprises: a Central Processing Unit (CPU), a digital front end unit (Digital Front End, DFE), a radio frequency transceiver (Radio Frequency transceiver, RF transceiver). The memory module includes volatile memory and nonvolatile memory. The volatile memory may be random access memory (RandomAccess Memory, RAM). The nonvolatile Memory may be a Flash Memory (Flash Memory). The business data may be data downloaded when browsing web pages using a computer. The service data may also be an execution instruction sent to the execution device by using the single chip microcomputer. The service data interaction information includes time of service data and the number of service data. The CPU acquires business data interaction information.
In this application, the time value of data interaction is specifically the time when the data needs to be processed. The amount of data interacted with is in particular the amount of data that needs to be processed.
It will be appreciated that the time value of the interaction by the data may confirm the time range in which the chip is not required to process the data and the time range in which it is required to process. I.e. the time at which the chip is acknowledged to go to sleep and the time at which it wakes up after sleep. The amount of bytes of data processed after the chip wakes up can be confirmed by the amount of data interacted with.
In the present application, the first preset range includes a first sleep time range and a first traffic range. When the time value of the data interaction and the data amount of the interaction are in a first preset range, the time value of the data interaction is in a first sleep time range. The amount of data interacted is within a first traffic range. And the data interaction time is within the first sleep time, the chip does not process data, and the chip can enter a sleep state. And when the data volume is in the first traffic volume range, the chip wakes up after sleeping to process the byte volume of the data.
It will be appreciated that the chip is ready to enter a first sleep state when the time value of the data interaction and the amount of data interacted are within a first preset range. That is, the chip does not process data during sleep. The chip processes data with traffic in a first traffic range after waking up. The volatile memory may be RAM. RAM is typically a temporary storage medium for the operating system or other running programs, and therefore, RAM may be referred to as system memory. RAM is not capable of retaining data when power is turned off. If the data needs to be saved, the data must be written to a non-volatile memory, such as a flash memory.
That is, the volatile memory loses data when it is powered down. The nonvolatile memory does not lose data when power is turned off. And the data in the volatile memory is stored in the nonvolatile memory, so that the data loss caused by the disappearance of the data in the volatile memory during power failure is avoided, and the integrity of the data is ensured.
In particular, the volatile memory may be a static random access memory (Static RandomAccess Memory, SRAM). The volatile memory, the non-volatile memory, and the powered-down module are powered down in preparation for entering the first sleep state. Only the uninterruptible power supply module operates in a low power mode. In the first sleep state, the current in the chip is 500nA.
It will be appreciated that static random access memory needs to remain powered on to be able to constantly hold stored data. While non-volatile memory is not required to remain powered on to retain data. As can be seen, the power consumption of the volatile memory is greater than that of the nonvolatile memory. Most of electric energy is saved by powering off the volatile memory, and the power consumption of the chip is reduced. In addition, the power is turned off before the sleep state is ready to be entered. That is, when the chip is still in the working state, the power of the volatile memory is cut off before the chip enters the sleep state, and compared with the power cut-off of the volatile memory after the chip enters the sleep state, the power cut-off time is earlier, so that more electric energy is saved, and more power consumption is reduced.
Specifically, the wake-up signal is an instruction for switching the chip from the sleep state to the active state. For a computer, the wake-up signal may be a cursor movement signal from a mouse. For a cell phone, the wake-up signal may be a trigger level signal from a switch button. The wake-up signal may also be a level signal sent by a timer when the sleep time has elapsed. The sleep time is derived from the time of the data interaction. The boot code is an instruction for backing up data and service codes in the nonvolatile memory into the volatile memory. The start code is a program set in advance in the nonvolatile memory.
It is understood that a Boot Loader (Boot Loader) solidified in a Read Only Memory (ROM) is loaded into the RAM, and the Boot Loader program is executed, as compared with the Boot chip. On the one hand, in the wake-up process, the program is not required to be called from the read-only memory, so that power supply for the read-only memory is not required, and the power consumption is reduced. On the other hand, the number of memories required to be called during starting is reduced, the wake-up starting step is reduced, the working time is shortened, and therefore the power consumption is reduced.
And the starting code can be flexibly set, a special read-only memory is not needed, and the self-adaption is strong.
In addition, the nonvolatile memory can not lose data under the condition of power failure, so that the starting code is ensured to be successfully called.
In particular, the volatile memory may be a static random access memory. The nonvolatile memory may be a flash memory.
It can be appreciated that the sram operates faster than the flash memory, so that the efficiency of data processing by the sram is higher and the efficiency of chip processing service is improved. That is, the volatile memory is utilized to perform service data interaction, so that the service processing efficiency is improved.
Specifically, after the nonvolatile memory is powered off, the chip enters a working state. It can be understood that after waking up, the data is processed by utilizing the volatile memory, the nonvolatile memory is not needed, the nonvolatile memory is powered off, and the power consumption of the working state of the chip is reduced.
In this application, the service code is pre-stored in the nonvolatile memory. By starting the codes, the business codes are backed up to the volatile memory, and the processing of the business can be completed by using the volatile memory, so that the nonvolatile memory is convenient to power off.
Further, the start code acquisition unit 5 includes: the remap address indicating unit 51 is configured to obtain a boot code preset in the nonvolatile memory according to the remap address allocated to the nonvolatile memory.
In the present application, the remapped address is a mapped address that is reassigned by the CPU for power-up. The CPU can find the start code in the non-volatile memory based on the remapped address. The nonvolatile memory is in particular a static random access memory.
It will be appreciated that after the chip is powered up, the program basically starts running from the 0 address. That is, the 0 address maps to what memory, then the instruction is read from that memory and normal operation begins. The remapped address is the address of the first instruction read after the chip wakes up.
Remapping is where the 0 address is originally mapped to read-only memory and is now instead mapped to static random access memory. After remapping to the static random access memory, the wake-up flow of the CPU starts to run from the 0 address, namely, the start code is read from the static random access memory. In other words, the path for finding the boot code is changed by address remapping, thereby changing the memory storing the boot code.
Compared with the existing Boot Loader code which is executed and solidified in the read-only memory, the chip is started according to the Boot Loader code. On one hand, the address for storing the starting code can be flexibly configured, and the applicability of the method is improved. On the other hand, the starting code can be changed, so that the method is applicable to most scenes.
The application also provides a device and a computer readable storage medium, which have the corresponding effects of the power consumption control method of the chip.
An embodiment of the present application provides an apparatus, including a processor and a memory, where the processor is configured to execute instructions stored in the memory, so that the apparatus implements the steps of the power consumption control method of the chip described in any of the embodiments above when the instructions are executed by the apparatus. The device may be a notebook computer, desktop computer, mobile phone. The processor can be a central processor of a computer or a control central system of a mobile phone. The Memory may be a random access Memory (Random Access Memory, RAM), a Flash Memory (Flash).
Embodiments of the present application provide a computer-readable storage medium including instructions that, when executed by a device, instruct the device to implement the steps of the power consumption control method of a chip as described in any of the embodiments above.
In particular, the computer readable storage medium may be random access Memory (RandomAccess Memory, RAM), flash Memory (Flash), read Only Memory (ROM), electrically programmable Read only Memory, electrically erasable programmable Read only Memory, registers, hard disk, removable disk, compact disc Read only Memory (Compact Disc Reads Only Memory, CD ROM), and any other form of storage medium known in the art.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims (10)

1. A method for controlling power consumption of a chip, comprising the steps of:
acquiring business data interaction information;
generating a time value of data interaction and an interactive data volume according to the business data interaction information;
when the time value of data interaction and the data quantity of interaction are within a first preset range, backing up the data in the volatile memory into the nonvolatile memory;
powering off the volatile memory to cause the chip to enter a first sleep state;
when a wake-up signal is received, acquiring a starting code preset in a nonvolatile memory;
backing up data in the nonvolatile memory to the volatile memory by using a starting code;
powering off the nonvolatile memory to reduce power consumption in the operating state;
the service is processed according to the data in the volatile memory and the service code for processing the service.
2. The method for controlling power consumption of a chip according to claim 1, wherein when a wake-up signal is received, a start code preset in a nonvolatile memory is acquired, comprising the steps of:
and acquiring a starting code preset in the nonvolatile memory according to the remapping address allocated to the nonvolatile memory.
3. The method for controlling power consumption of a chip according to claim 1, further comprising the steps of:
after the business processing is completed, judging whether adjustment triggering conditions of power distribution strategies of all modules of the chip are met or not according to the time value of data interaction and the data quantity of interaction;
when the adjustment triggering conditions of the power distribution strategies of the modules are met, judging whether the time value of the data interaction and the data quantity of the interaction are within a second preset range or not;
and when the time value of the data interaction and the data quantity of the interaction are in a second preset range, controlling the chip to enter a second sleep state.
4. The method for controlling power consumption of a chip according to claim 3, wherein when the time value of the data interaction and the data amount of the interaction are within a second preset range, the chip is controlled to enter a second sleep state, comprising the steps of:
when the time value of data interaction and the data quantity of interaction are within a second preset range, backing up the data in the volatile memory into the nonvolatile memory;
backing up the business execution code to a specific volatile memory;
powering off the non-volatile memory and the non-specific volatile memory to cause the chip to enter a second sleep state;
when a wake-up signal is received, acquiring a service execution code in a specific volatile memory;
processing the service using the service execution code and the data in the nonvolatile memory;
the interactive data amount in the second preset range is smaller than the interactive data amount in the first preset range, and the sleep time length value in the second preset range is shorter than the sleep time length value in the first preset range.
5. The method of claim 1, wherein the volatile memory is: one of static random access memory, dynamic random access memory, synchronous dynamic random access memory.
6. The method for controlling power consumption of a chip according to claim 1, wherein the nonvolatile memory is: flash memory, or eeprom.
7. A power consumption control apparatus of a chip, comprising:
the information acquisition unit is used for acquiring business data interaction information;
the time and data production unit is used for generating a time value of data interaction and an interactive data volume according to the business data interaction information;
a data backup first unit for backing up data in the volatile memory to the nonvolatile memory;
the power supply control first unit is used for powering off the volatile memory so as to enable the chip to enter a first sleep state;
a start code acquisition unit for acquiring a start code preset in the nonvolatile memory;
a data backup second unit for backing up the data in the nonvolatile memory to the volatile memory by using the start code;
the power supply controls the second unit to power off the nonvolatile memory so as to reduce the power consumption in the working state;
and the business processing unit is used for processing the business according to the data in the volatile memory and the business code for processing the business.
8. The power consumption control apparatus of the chip according to claim 7, wherein the start code acquisition unit includes: and the remapping address indicating unit is used for acquiring the starting code preset in the nonvolatile memory according to the remapping address distributed to the nonvolatile memory.
9. An apparatus comprising a processor and a memory;
the processor is configured to execute instructions stored in the memory to cause the apparatus to perform the method of any one of claims 1 to 6.
10. A computer readable storage medium comprising instructions that instruct a device to perform the method of any one of claims 1 to 6.
CN202311412013.5A 2023-10-27 2023-10-27 Method, device, equipment and storage medium for controlling power consumption of chip Pending CN117453035A (en)

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