CN117452677A

CN117452677A - Electro-optical modulation chip capable of monolithically integrating active optical device and preparation method

Info

Publication number: CN117452677A
Application number: CN202311361324.3A
Authority: CN
Inventors: 赵子强; 张义
Original assignee: Hangzhou Troy Optoelectronic Technology Co ltd
Current assignee: Hangzhou Troy Optoelectronic Technology Co ltd
Priority date: 2023-10-19
Filing date: 2023-10-19
Publication date: 2024-01-26

Abstract

The invention discloses an electro-optic modulation chip capable of monolithically integrating an active optical device and a preparation method thereof, wherein the electro-optic modulation chip comprises a compound semiconductor active layer, a germanium film layer and an electro-optic material waveguide layer from top to bottom; forming a corresponding waveguide structure by photoetching and etching the electro-optic material waveguide layer; forming a germanium absorption layer and a germanium substrate growth layer on the germanium film layer through photoetching and etching; the germanium film layer is prepared by an ion scissors technology, so that on one hand, high-speed and high-responsivity O/C wave band light detection can be realized, and on the other hand, a lattice-matched growth substrate is provided for a compound semiconductor, and an optical gain semiconductor device can be integrated at the same time.

Description

Electro-optical modulation chip capable of monolithically integrating active optical device and preparation method

Technical Field

The invention belongs to the field of semiconductor photoelectric chips, and particularly relates to an electro-optical modulation chip capable of monolithically integrating active optical devices and a preparation method thereof.

Background

The electro-optic material crystal represented by lithium niobate has larger nonlinear optical coefficient, excellent photorefractive, piezoelectric and acoustic properties, and can be used as a multiple/difference frequency crystal material. The material has excellent physical and mechanical properties, high damage threshold, wide transparent spectrum and low light transmission loss. In addition, the cost of the electro-optic material is relatively reduced, so that the electro-optic material is quite suitable for preparing the light modulator. In comparison with the conventional electro-optical modulation chip represented by silicon (Si) realized based on the CMOS (complementary metal oxide semiconductor) process, in particular, the nonlinear characteristics of the electro-optical material crystal make it exhibit attractive prospects in the research and related applications of the optical frequency comb that has been raised in recent years. With the development of technology, the electro-optic crystal can be integrated on the surface of a 6-inch or larger wafer in a thin film mode. Taking lithium niobate thin film (LNOI) on insulating layer as an example, the problems of low integration density and easy occurrence of polarization crosstalk of the traditional electro-optic material waveguide are solved, and the generation condition of nonlinear effect in the electro-optic material waveguide is further simplified. However, the existing lithium niobate thin film technology is difficult to introduce the preparation of active devices except modulation, and the existing erbium-doped lithium niobate thin film can solve the difficulty of integrating optical gain on a lithium niobate thin film system to a certain extent, but has limitation on the modulation function of the lithium niobate thin film, so the erbium-doped lithium niobate thin film still has great limitation. In combination, there is a need for an electro-optic material system on an insulating layer that can integrate optical gain, optical modulation, and optical detection functions simultaneously on a single chip.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provide an electro-optical modulation chip capable of monolithically integrating an active optical device and a preparation method thereof.

According to a first aspect of the present invention, there is provided an electro-optical modulation chip monolithically integratable with an active optical device, comprising, from top to bottom, a compound semiconductor active layer, a germanium thin film layer, and an electro-optical material waveguide layer; the electro-optic material waveguide layer forms a corresponding waveguide structure through photoetching and etching; the germanium film layer is subjected to photoetching and etching to form a germanium absorption layer and a germanium substrate growth layer;

the electro-optic material waveguide layer is used as a coupling medium of optical signals and forms a waveguide together with the compound semiconductor active layer grown on the germanium substrate growth layer to form an optical gain part of the electro-optic modulation chip;

the electro-optic material waveguide layer is used as a coupling medium of optical signals and forms a waveguide together with the germanium absorption layer to form a light detection part of the electro-optic modulation chip;

the electro-optic material waveguide layer is used as a propagation medium of an optical signal to form an optical modulation part of the electro-optic modulation chip.

According to a second aspect of the present invention, there is provided a method of manufacturing an electro-optical modulation chip monolithically integratable with an active optical device, comprising the steps of:

preparing an electro-optic material wafer with an electro-optic material waveguide layer, etching the electro-optic material waveguide layer to form a waveguide structure, depositing an insulating substrate layer and leveling the surface;

preparing a germanium wafer, and forming a germanium film layer, a germanium defect enrichment layer, a germanium cracking layer and a residual germanium substrate on the surface of the germanium wafer after hydrogen ion implantation;

bonding a germanium wafer to the surface of the upper insulating substrate layer, and only reserving a germanium film layer of the germanium wafer in an annealing and grinding mode;

etching the germanium film layer to form a germanium substrate growth layer of the optical gain part and a germanium absorption layer of the optical detection part respectively; continuing to deposit an insulating substrate layer, and opening a growth window in the optical gain part for growing a compound semiconductor active layer on the germanium substrate growth layer;

and continuing to deposit an insulating substrate layer, and forming a via electrode and a contact electrode.

Further, the impurity doping concentration of the germanium wafer should be 10 ¹⁶ cm ^-3 ～5×10 ¹⁶ cm ^-3 Within the range of (2), the doping type is n-type or p-type, and the surface roughness should be 0.5nm/100 μm ² The following is given.

Further, the preparation process of the germanium wafer specifically comprises the following steps:

cleaning and drying the germanium wafer; depositing an oxide layer film on the germanium wafer to form a protective layer;

hydrogen ion implantation is carried out on the germanium wafer under the room temperature condition, the implantation inclination angle is 7 degrees, and the implantation dosage is 4 multiplied by 10 ¹⁶ cm ^-3 ～1×10 ¹⁷ cm ^-3 The injection energy is 60-250 keV, and the injection beam current is less than or equal to 1000 mu A/cm ² ；

After the implantation is completed, cleaning and drying are performed again to obtain the ready germanium wafer.

Further, the cleaning and drying specifically comprises: adopting a buffer hydrofluoric acid solution or a diluted hydrofluoric acid solution to clean an oxide layer on the surface of the germanium wafer for 3-5 minutes; after the acidic cleaning is completed, cleaning is carried out in deionized ultrapure water to remove residual hydrofluoric acid solution on the surface; after the water washing is finished, the ultrapure water on the surface is removed by adopting a nitrogen blow-drying or vacuum back adsorption and spin-drying mode.

Further, the bonding process of the germanium wafer specifically includes:

the surface of the germanium wafer and the surface of the upper insulating substrate layer are treated, specifically: depositing oxide layer films with the thickness of a plurality of nanometers on the surfaces of the germanium wafer and the upper insulating substrate layer, or activating the surfaces of the germanium wafer and the upper insulating substrate layer by adopting plasma, wherein the gas atmosphere is nitrogen or oxygen taking argon as a carrier;

after surface treatment, pre-bonding the germanium wafer and the upper insulating substrate layer;

the key energy enhancement is carried out on the electro-optic modulation chip formed by pre-bonding;

uniformly heating the germanium wafer in a vacuum environment until the temperature is raised to 300-400 ℃ for annealing operation, and keeping for a long enough time until the germanium cracking layer and the residual germanium substrate are stripped;

removing the germanium defect enrichment layer on the surface in a grinding mode, and reserving the germanium film layer;

and annealing again in a vacuum environment at 500-550 ℃ for 10-60 minutes to further repair residual defects in the germanium film layer.

Further, the bond energy enhancement is specifically: applying 5-20N/cm to the electro-optic modulation chip longitudinally ² Is less than 10 ^-5 Slowly heating up and maintaining for 0.5-2 hours under vacuum atmosphere of mbar and environment temperature of 150-250 ℃ and then slowly reducingTemperature, so that bond energy is enhanced to more than 2J/m ² 。

Further, the annealing mode when the germanium-cleaved layer and the residual germanium substrate are peeled off is as follows: when the size of the electro-optical modulation chip is less than or equal to 6 inches, adopting a furnace tube heating annealing mode; when the size of the electro-optical modulation chip is larger than 6 inches, a laser annealing mode is adopted.

Further, the etched germanium film layer specifically comprises:

for the optical gain part, thinning the thickness of the germanium film layer, and forming a germanium substrate growth layer in a photoetching and etching mode so as to facilitate the growth of the compound semiconductor active layer;

for the light modulation part, the germanium film layer needs to be completely etched;

for the light detection part, the germanium film layer is used as a light absorption layer, the germanium absorption layer is formed by photoetching and etching, and then a pn junction is formed by doping or a photoelectric detector is formed by forming interdigital electrodes.

Further, in the optical gain section, a growth window is opened by etching an upper insulating substrate layer on the germanium substrate growth layer, it is necessary to ensure that no natural oxide is generated on the germanium substrate growth layer after the growth window is opened, and a compound semiconductor active layer is grown.

The beneficial effects of the invention are as follows: the invention provides an electro-optical modulation chip structure capable of integrating optical gain, optical modulation and optical detection simultaneously and a preparation method thereof. The integration of the monocrystalline germanium film layer on the electro-optic material waveguide is realized by the ion scissors technology, so that the preparation of the high-speed and high-responsiveness communication band germanium detector can be realized on the one hand; on the other hand, germanium is used as a growth substrate to be matched with the compound semiconductor in a lattice manner, so that high-quality crystal growth can be realized, and a high-performance optical gain device can be realized.

Drawings

FIG. 1 is a schematic diagram of the structure of an electro-optic modulation chip monolithically integratable with an active optical device provided by the present disclosure;

FIG. 2 is a flow chart of a fabrication process for an electro-optic modulation chip monolithically integratable with an active optical device provided by the present disclosure;

FIG. 3 is a schematic diagram of the structure in preparation step S1 provided by the present disclosure;

fig. 4 is a schematic structural diagram in a preparation step S2 provided in the present disclosure;

fig. 5 is a schematic diagram of a germanium wafer structure in the preparation step S4 provided in the present disclosure;

FIG. 6 is a schematic diagram of the structure after pre-bonding in preparation step S5 provided by the present disclosure;

fig. 7 is a schematic diagram of forming a germanium thin film layer in preparation step S5 provided in the present disclosure;

FIG. 8 is a schematic diagram of the final structure in preparation step S5 provided by the present disclosure;

fig. 9 is a schematic structural view in a preparation step S6 provided in the present disclosure;

FIG. 10 is a schematic diagram of the structure in preparation steps S7-S8 provided by the present disclosure;

fig. 11 is a schematic structural view in a preparation step S9 provided by the present disclosure;

FIG. 12 is a schematic diagram of the structure in the preparation steps S10-S11 provided by the present disclosure;

fig. 13 is a schematic structural view in a preparation step S12 provided in the present disclosure;

in the figure, 100 is an electro-optical modulation chip, 10 is an electro-optical material wafer, 101 is a contact electrode, 102 is a via electrode, 103 is a compound semiconductor active layer, 11 is a germanium wafer, 104 is a germanium thin film layer, 104-a is a germanium cracking layer, 104-b is a germanium defect enrichment layer, 104-c is a residual germanium substrate, 104-1 is a germanium substrate growth layer, 104-2 is a germanium absorption layer, 105 is an electro-optical material waveguide layer, 12 is a waveguide structure, 106a is an upper insulating substrate layer, 106b is a lower insulating substrate layer, 107 is a chip substrate layer, 200 is an optical gain portion, 300 is an optical modulation portion, and 400 is a light detection portion.

Detailed Description

In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present invention is not limited to the specific embodiments disclosed below.

For clarity, the following description of embodiments of the present invention and related structures is primarily directed to single chip structures formed on semiconductor substrates and their fabrication steps. In practice, however, various embodiments may be performed at the wafer level for efficiency considerations.

It should be noted that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Furthermore, the phrase does not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

Generally, terminology is understood, at least in part, based on usage in the context. For example, the term "one or more" as used herein, depending at least in part on the context, may be used to describe any feature, structure, or characteristic in the singular sense or may be used to describe combinations of features, structures, or characteristics in the plural sense. Similarly, terms such as "a," "an," or "the" may again be understood as conveying singular uses or conveying plural uses, depending at least in part on the context. In addition, the term "based on" may be understood as not necessarily intended to convey the exclusive set of factors, but rather may permit the presence of additional factors that are not necessarily clearly described, again, depending at least in part on the context.

It will be readily understood that the meaning of "on … …", "above … …", and "above … …" in this disclosure should be interpreted in the broadest manner such that "on … …" means not only "directly on … … (something), but also" on … … (something) with intermediate features or layers therebetween, and "above … …" or "above … …" means not only "above … … (something) or" above … … (something) "but also" above … … (something) "or" above … … (something) "without intermediate features or layers therebetween (i.e., directly on something).

Furthermore, spatially relative terms, such as "under … …," "below … …," "lower," "above … …," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. In addition to the orientations depicted in the figures, spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "substrate" refers to a material to which subsequent layers of material are added. The substrate itself can be patterned. The material added to the top of the substrate can be patterned or the material added to the top of the substrate can remain unpatterned. In addition, the substrate can comprise a broad range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can be composed of a non-conductive material such as glass, plastic, or sapphire wafers.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entire underlying or overlying structure, or can have a smaller extent than the extent of the underlying or overlying structure. Furthermore, the layer can be a region of homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, the layer can be located between any pair of horizontal planes between the top and bottom surfaces of the continuous structure, between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layers can extend horizontally, vertically, and/or along a tapered surface. The substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereon, and/or thereunder. The layer can comprise a plurality of layers. For example, the interconnect layer can include one or more conductors and contact layers (where interconnect lines, and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term "front side" of a structure refers to the surface of the structure used to form a device or to be subsequently used to form a device.

As used herein, the term "semiconductor" of a structure refers to, but is not limited to, a material having a conductivity value that falls between the conductivity values of a conductor and an insulator. The material may be a simple substance material or a compound material. Semiconductors may include, but are not limited to, elemental, binary, ternary, and quaternary alloys. Structures formed using one or more semiconductors may include a single semiconductor material, two or more semiconductor materials, a single composition semiconductor alloy, two or more discrete compositions of semiconductor alloys, and a semiconductor alloy that is graded from a first semiconductor alloy to a second semiconductor alloy. The semiconductor may be one of undoped (intrinsic), hole doped, electron doped, doped with a first doping level of one type to a third doping level of the same type, and doped with a first doping level of one type to a third doping level of a different type.

Further, the semiconductor may include, but is not limited to, group IV semiconductors such as those between carbon (C), silicon (Si), germanium (Ge), tin (Sn).

Further, the semiconductor may include, but is not limited to, group III-V semiconductors such As those between aluminum (Al), gallium (Ga), indium (In), nitrogen (N), phosphorus (P), arsenic (As), and tin (Sb).

Further, the semiconductor may include, but is not limited to, group II-VI semiconductors such as those between zinc (Zn), cadmium (Cd), mercury (Hg), sulfur (S), selenium (Se), tellurium (Te), and oxygen (O).

As used herein, the term "metal" of the structure refers to, but is not limited to, materials (simple substances, compounds, and alloys) that have good electrical and thermal conductivity as a result of the easy loss of shell electrons. This may include, but is not limited to, gold, chromium, aluminum, silver, platinum, nickel, copper, rhodium, palladium, tungsten, and combinations of such materials.

As used herein, the term structured "optical waveguide," "dielectric waveguide," or "waveguide" refers to, but is not limited to, a dielectric medium or combination of media that supports the propagation of optical signals within a predetermined wavelength range and that is invariant along the propagation direction. The optical waveguide may be at least one of: including at least a core and cladding (e.g., an optical fiber), an isolation structure formed as part of a carrier, formed within a substrate (e.g., a planar lightwave circuit, photonic integrated circuit, integrated optical device), and an optical waveguide. This includes, but is not limited to, flexible optical waveguides formed from pressed glass, pressed doped quartz, pressed chalcogenide glass, and polymers. This further includes, but is not limited to, optical waveguides formed within: quartz on insulator, quartz on silicon, silicon oxynitride on silicon, polymer on polymer, etc.

As used herein, the term "optical waveguide layer" refers to a portion of material that includes regions having a thickness. More specifically, the subsequent processing may have the effect of achieving confinement and conduction of the light waves, including but not limited to one or more layers of waveguide material.

As used herein, the term "dielectric layer" refers to a portion of material that includes a region having a thickness. More particularly, it has the effect of achieving electrical connection or carrier transport, including but not limited to one or more layers of metal or other conductive material.

As used herein, the term "photo-electric layer via structure" refers to a via structure connecting between a dielectric layer and an electro-absorption layer that has the efficacy of conducting an electrical connection in the dielectric layer with an electrical connection in the electro-absorption layer such that light can continue to pass to the dielectric layer for further signal processing after being converted into electrons in the electro-absorption layer. The material of which includes, but is not limited to, the foregoing metallic materials or conductive polymer materials.

As shown in fig. 1, a cross-sectional structural view of an electro-optical modulation chip 100 that can monolithically integrate an active optical device is shown.

Specifically, the electro-optical modulation chip 100 of the monolithically integrated active optical device includes, from top to bottom, a compound semiconductor active layer 103, a germanium thin film layer 104, and an electro-optical material waveguide layer 105. Wherein the electro-optic material waveguide layer 105 is lithographically and etched to form a corresponding waveguide structure 12 to effect propagation of light in the electro-optic material waveguide layer 105. Germanium thin film layer 104 is lithographically and etched to form germanium absorber layer 104-2 and germanium substrate growth layer 104-1.

The electro-optic material waveguide layer 105 is used as a coupling medium of optical signals, and forms a waveguide together with the compound semiconductor active layer 103 grown on the germanium substrate growth layer 104-1, so that the optical signals realize gain amplification effect through the compound semiconductor active layer 103 by means of electric injection, and the optical gain part 200 of the electro-optic modulation chip 100 capable of monolithically integrating the active optical devices is formed.

The electro-optic material waveguide layer 105 is used as a coupling medium for optical signals and forms a waveguide together with the germanium absorbing layer 104-2, and the germanium absorbing layer 104-2 can serve as a light detection medium because germanium has strong absorption to light below 1600nm, and the electro-optic material waveguide layer 105 and the germanium absorbing layer 104-2 together form the light detection part 400 of the electro-optic modulation chip 100 of the monolithically integrated active optical device.

The electro-optic material waveguide layer 105 serves as a propagation medium for an optical signal and constitutes the optical modulating portion 300 of the electro-optic modulation chip 100 that may be monolithically integrated with an active optical device.

Fig. 2 illustrates a process flow of the fabrication of the electro-optic modulation chip 100 that may monolithically integrate an active optical device. The following specifically describes the respective procedures:

s1, preparing an electro-optic material wafer 10;

specifically, as shown in fig. 3, the electro-optic material wafer 10 includes a wafer having lithium niobate, lithium tantalate, and other materials having a linear electro-optic effect as the electro-optic material waveguide layer 105, and having a lower insulating substrate layer 106b and a chip substrate layer 107.

In particular, such wafers may be provided by wafer manufacturers, and the specific manufacturing process is not within the scope of the present patent discussion.

Preferably, the thickness of the electro-optic material waveguide layer 105 in the electro-optic material wafer 10 is 400 nanometers, with a broader range of thicknesses ranging from 300 to 500nm.

S2, etching the waveguide structure 12;

as shown in fig. 4, the waveguide structure 12 is formed on the electro-optic material waveguide layer 105, and the specific design of the waveguide structure is not within the scope of the present invention, but the type of the waveguide structure includes a common bar waveguide, a ridge waveguide, a gap waveguide, a sub-wavelength grating waveguide, and the like.

Preferably, the waveguide structure shown in fig. 4 is a ridge waveguide, which is designed to move the optical waveguide local optical mode up to a region near the top of the waveguide structure 12, to facilitate coupling with subsequent structures, while having lower propagation loss compared to a strip waveguide.

S3, depositing an upper insulating substrate layer 106a and leveling the surface;

after the waveguide etching is completed, an oxide layer deposition is required to form the upper insulating substrate layer 106a, and the geometry of the waveguide structure 12 is gradually transferred to the surface of the upper insulating substrate layer 106a as the deposition process proceeds during the oxide layer deposition, so that the surface of the upper insulating substrate layer 106a needs to be polished and leveled.

In particular, in order to ensure that the waveguide structure 12 can carry its upper layer structure when the optical gain section 200, the optical modulation section 300, and the optical detection section 400 are subsequently configured, it is necessary to limit the spacing between the top surface of the upper insulating substrate layer 106a and the top surface of the waveguide structure 12.

Preferably, the spacing should be guaranteed to be less than 100nm and the optimal spacing should be maintained at 50nm.

S4, preparing a germanium wafer;

conventional group-four semiconductor materials often do not have a linear electro-optic effect, but compound semiconductor materials have a linear electro-optic effect but have too high production and processing costs, and thus are not suitable for manufacturing the electro-optic modulation chip 100 with low cost and high performance.

Common electro-optical materials such as lithium niobate and lithium tantalate are very suitable for preparing the optical modulation portion 300 in the electro-optical modulation chip 100, but because they are generally insulating materials, the integration of the optical gain portion 200 and the optical detection portion 400 cannot be achieved simply by doping and injection. Although in some researches, scientists have developed an integrated optical chip for realizing optical amplification by using erbium-doped lithium niobate material, the preparation process is complex and global, which is unfavorable for monolithic integration.

The present invention employs a germanium wafer 11 as a medium for integrating the optical gain section 200 and the optical detection section 400 of the electro-optical modulation chip 100. Integration of the germanium thin film layer 104, prepared from the germanium wafer 11, on the electro-optic material waveguide layer 105 is achieved by ion-scissors technology. To achieve this, special processing of the germanium wafer 11 is required.

Specifically, the germanium wafer 11 is prepared in advance, and the impurity doping concentration thereof should be 10 ¹⁶ cm ^-3 ～5×10 ¹⁶ cm ^-3 Within the range of (2), the doping type may be n-type or p-type, and the surface Roughness (RMS) should be guaranteed to be 0.5 nm/100. Mu.m ² The following is given.

Subsequently, the germanium wafer 11 is cleaned. Firstly, a 25% buffered hydrofluoric acid solution (BHF) or a diluted hydrofluoric acid solution (DHF) is adopted to clean an oxide layer on the surface of the germanium wafer 11 for 3-5 minutes. After the acidic cleaning is completed, the cleaning is performed in deionized ultrapure water to remove the surface residual hydrofluoric acid solution. After the water washing is completed, the ultrapure water film on the surface of the germanium wafer 11 needs to be uniformly and flatly covered on the surface of the germanium wafer 11, and the purpose of this step is to confirm that the dangling bond structure on the surface of the germanium wafer 11 is a hydrophilic structure. And then, removing the ultrapure water on the surface by adopting a nitrogen blow-drying or vacuum back adsorption and spin-drying mode.

Next, a dense oxide film is deposited on the germanium wafer 11 by vapor deposition to serve as a protective layer for subsequent processes. Preferably, the thickness of the oxide layer film is 100nm, and the material is silicon dioxide. A broader range includes 50nm to 200nm.

Subsequently, the germanium wafer 11 is subjected to hydrogen ions (H ⁺ ) Injection, injection angle of 7 degrees, injection dosage of 4×10 ¹⁶ cm ^-3 ～1×10 ¹⁷ cm ^-3 The injection energy is 60-250 keV, and the injection beam currentLess than or equal to 1000 mu A/cm ² 。

Preferably, in order to prevent the self-heating effect and ensure that a germanium thin film layer 104 of sufficient thickness can be transferred to the surface of the electro-optic material waveguide layer 105 in a subsequent process, the implantation conditions should be: the injection dip angle is 7 degrees, and the injection dosage is 4 multiplied by 10 ¹⁶ cm ^-3 The implantation energy is 80keV, and the implantation beam current is 100 mu A/cm ² 。

After the injection is completed, the surface oxide layer is again washed with BHF or DHF solution for 3 to 5 minutes. After the acidic cleaning is completed, the cleaning is performed in deionized ultrapure water to remove the surface residual hydrofluoric acid solution. After the water washing is completed, the ultrapure water film on the surface of the germanium wafer 11 needs to be uniformly and flatly covered on the surface of the germanium wafer 11, and the purpose of this step is to confirm that the dangling bond structure on the surface of the germanium wafer 11 is still a hydrophilic structure. And then, removing the ultrapure water on the surface by adopting a nitrogen blow-drying or vacuum back adsorption and spin-drying mode, and finally obtaining the prepared germanium wafer 11.

As shown in fig. 5, the surface of the germanium wafer 11 has a germanium thin film layer 104 that has a lower defect density and residual hydrogen ion concentration after ion implantation due to the proximity to the surface of the germanium wafer 11. As the depth increases, a germanium defect-rich layer 104-b is formed at a deeper location on the surface of the germanium wafer 11, and the location and thickness of this layer will vary with the implantation conditions. More specifically, by adjusting the implantation energy and implantation dose, the depth and thickness of the germanium-defect-enriched layer 104-b may be varied, while for a particular implantation condition, germanium defects may form a germanium-cleaved layer 104-a having a certain thickness at a particular depth during enrichment, where there are a large number of germanium lattice defects, and hydrogen ions may passivate dangling bonds on the defects and accumulate as hydrogen molecules at the defect cores. The deeper residual germanium substrate 104-c, because it is much larger than the depth that hydrogen ions can penetrate after acceleration, has basic properties similar to those of the germanium thin film layer 104, and can be considered as single crystal germanium material.

S5, bonding a germanium wafer;

in order to transfer the germanium thin film layer 104 onto the electro-optic material waveguide layer 105, the germanium wafer 11 is first bonded by wafer bonding, so that the upper surface of the germanium wafer 11 and the upper surface of the upper insulating substrate layer 106a formed on the electro-optic modulation chip 100 are tightly bonded together by intermolecular forces. To achieve this, the germanium wafer 11 and the electro-optical modulation chip 100 need to be surface treated.

Specifically, the oxide layer film with a thickness of several nanometers is deposited on the upper surface of the germanium wafer 11, and the material may be silicon oxide, aluminum oxide, etc., and the deposition manner includes vapor deposition enhanced by plasma gas or common vapor deposition, or is formed by an atomic layer deposition device. Similarly, it is also necessary to deposit oxide thin films of several nanometers thick on the electro-optic modulation chip 100. Preferably, the thickness of the oxide layer film is 5 nanometers, and the deposition mode is atomic layer deposition.

Another scheme is to adopt plasma surface activation, and carry out dangling bond activation treatment on the surface by a radio frequency power source with power of hundreds of watts, wherein the gas atmosphere can be other common semiconductor process gases such as nitrogen, oxygen and the like taking argon as a carrier.

After surface treatment, the two are pre-bonded, where the pre-bonding operation does not require fine alignment. Fig. 6 shows a block diagram of the electro-optical modulation chip 100 after pre-bonding the germanium wafer 11. At this time, the germanium thin film layer 104 is pre-transferred onto the upper insulating substrate layer 106a, but the intermolecular bond strength is still weak, and the germanium defect-rich layer 104-b, the germanium-cleaved layer 104-a, and the residual germanium substrate 104-c are not yet removed.

Next, we perform bond energy enhancement on the pre-bonded electro-optic modulation chip 100 by a bonding device. Specifically, 5 to 20N/cm is longitudinally applied to the electro-optical modulation chip 100 ² Is less than 10 ^-5 Slowly heating up and maintaining for 0.5-2 hours under vacuum atmosphere of mbar and environment temperature of 150-250 ℃ and then slowly cooling down so that bond energy is enhanced to be more than 2J/m ² 。

In particular, the pressure and temperature are selected to be adjusted according to the actual size of the electro-optical modulation chip 100 to avoid wafer chipping. In the present invention, the dimensions of the electro-optical modulation chip 100 range from a single chip size (< 1 inch wafer) to a 12 inch wafer size. The dimensions of the corresponding germanium wafer 11 should also be consistent with the dimensions of the electro-optical modulation chip 100.

Next, we need to strip the germanium thin film layer 104, which is called ion-scissor technology, by heating and maintaining for a time sufficient to induce the residual hydrogen ions in the germanium-cracking layer 104-a to cluster and apply microscopic stress to the defect where they are located so that the germanium-cracking layer 104-a breaks widely parallel to the wafer direction, and thus the germanium-cracking layer 104-a and the residual germanium substrate 104-c are stripped together, and only the germanium thin film layer 104 and the germanium defect-enriched layer 104-b remain, as shown in fig. 7.

In particular, the temperature rise process should ensure that its temperature changes slowly and is distributed evenly throughout the wafer to avoid wafer chipping due to stress differences.

Preferably, should be less than 10 ^-5 The wafer is heated uniformly at a rate of 1 c per minute in a vacuum atmosphere of mbar until the temperature rises to 300 c to 400 c for an annealing operation that is maintained for a sufficient period of time until the germanium-cleaving layer 104-a breaks.

Because the fracture process is very rapid, the stress conduction may cause unavoidable fracture of the wafer, and another modified mode of fracture is to use high energy laser induced fracture. In this manner, the laser focus is placed near the germanium-cracking layer 104-a, annealing is performed by continuous single-point scanning, and the cracking of the germanium-cracking layer 104-a is gradually induced everywhere on the chip, and finally small cracking points everywhere are spontaneously connected to each other to form a wide range of cracking effects.

Preferably, when the size of the electro-optical modulation chip 100 is less than or equal to 6 inches, a furnace tube heating annealing mode can be adopted; the laser annealing should be used when the size of the electro-optical modulation chip 100 is greater than 6 inches.

Subsequently, the germanium defect-enriched layer 104-b on the surface is removed by chemical mechanical polishing, and the germanium thin film layer 104 is remained, as shown in fig. 8. Finally, at less than 10 ^-5 Annealing again in vacuum environment of mbar at 500-550 deg.cThe duration of the fire is 10-60 minutes to further repair residual defects in the germanium film layer 104.

S6, etching the germanium film layer;

germanium thin film layer 104, which is a precursor to germanium substrate growth layer 104-1 and germanium absorber layer 104-2, has been transferred to the surface of upper insulating substrate layer 106a as previously described. Next, the optical gain section 200, the optical modulation section 300, and the optical detection section 400 according to the present invention will be separately discussed.

For the optical gain section 200, the germanium thin film layer 104 needs to be reduced in thickness to reduce the absorption region because it has an optical absorption effect on the target band. Since germanium itself is well suited as a precursor substrate for growth of compound semiconductors, and in particular gallium arsenide (GaAs), due to the matching of lattice coefficients, the thickness should be such as to provide a sufficient seed region for growth of the compound semiconductor active layer 103, and the specific growth mode is not discussed in the present invention. In contrast, the present invention focuses on the need to leave the germanium film layer 104 thinner during this step, which typically should be 50nm thick, to form the germanium substrate growth layer 104-1, as shown in FIG. 9. In addition, the grid-like structure array on the germanium substrate growth layer 104-1 can be used as a precursor for the growth of the compound semiconductor.

For the light modulating portion 300, the germanium film layer 104 needs to be completely etched to ensure that it does not affect the insertion loss of the electro-optic material waveguide layer 105 that is too great for light modulation.

For the light detecting section 400, the germanium thin film layer 104 may be used as a light absorbing layer, and the germanium absorbing layer 104-2 is formed by photolithography and etching first, as shown in fig. 9, and then a p-n junction is formed by doping to form a PIN type photodetector, or an MSM type photodetector is formed by forming an interdigital electrode, and its typical thickness should be 200nm.

S7, continuing to deposit an upper insulating substrate layer 106a;

after the preparation of germanium substrate growth layer 104-1 and germanium absorber layer 104-2 is completed, the deposition of insulating substrate layer 106a is continued to ensure passivation of the germanium material, as shown in fig. 10. Since the growth window still needs to be opened later for compound semiconductor growth, the thickness of the insulating substrate layer 106a to be deposited further in this step should not exceed 200nm.

S8, opening a growth window;

the growth window is opened by etching the upper insulating substrate layer 106a on the germanium substrate growth layer 104-1, as shown in fig. 10, which is to ensure that no native oxide is generated on the germanium substrate growth layer 104-1 after the growth window is opened, and thus the sample needs to be vacuum-preserved after the etching is completed.

S9, growing a compound semiconductor;

in the vapor phase epitaxy apparatus, the compound semiconductor active layer 103 is grown on the germanium substrate growth layer 104-1, as shown in fig. 11, the present invention does not protect the compound semiconductor growth environment and layer structure, and only protects the compound semiconductor growth mode using the germanium substrate growth layer 104-1 as a seed layer.

S10, continuing to deposit an upper insulating substrate layer 106a;

as shown in fig. 12, the upper insulating substrate layer 106a is continuously deposited to ensure hermetic protection of the grown compound semiconductor.

S11, forming a via electrode 102;

via structures are formed in the optical gain section 200, the optical modulation section 300, and the optical detection section 400, respectively, by etching, and the via electrodes 102 are formed by filling conductive materials (e.g., metal, transparent conductive oxide, etc.), as shown in fig. 12.

S12, forming a contact electrode 101;

finally, as shown in fig. 13, the contact electrode 101 is formed on the via electrode 102 by etching, plating or stripping, and is generally made of a metal material.

The foregoing is merely a preferred embodiment of the present invention, and the present invention has been disclosed in the above description of the preferred embodiment, but is not limited thereto. Any person skilled in the art can make many possible variations and modifications to the technical solution of the present invention or modifications to equivalent embodiments using the methods and technical contents disclosed above, without departing from the scope of the technical solution of the present invention. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. An electro-optical modulation chip capable of monolithically integrating an active optical device is characterized by comprising a compound semiconductor active layer, a germanium film layer and an electro-optical material waveguide layer from top to bottom; the electro-optic material waveguide layer forms a corresponding waveguide structure through photoetching and etching; the germanium film layer is subjected to photoetching and etching to form a germanium absorption layer and a germanium substrate growth layer;

2. The preparation method of the electro-optical modulation chip capable of monolithically integrating the active optical device is characterized by comprising the following steps of:

3. The method of claim 2, wherein the germanium wafer has an impurity doping concentration of 10 ¹⁶ cm ^-3 ～5×10 ¹⁶ cm ^-3 Within the range of (2), the doping type is n-type or p-type, and the surface roughness should be 0.5nm/100 μm ² The following is given.

4. The method of claim 2, wherein the preparing of the germanium wafer comprises:

5. The method according to claim 4, wherein the washing and drying are specifically: adopting a buffer hydrofluoric acid solution or a diluted hydrofluoric acid solution to clean an oxide layer on the surface of the germanium wafer for 3-5 minutes; after the acidic cleaning is completed, cleaning is carried out in deionized ultrapure water to remove residual hydrofluoric acid solution on the surface; after the water washing is finished, the ultrapure water on the surface is removed by adopting a nitrogen blow-drying or vacuum back adsorption and spin-drying mode.

6. The method of claim 2, wherein the bonding process of the germanium wafer is specifically:

7. The method of claim 6, wherein the bond energy enhancement is specifically: applying 5-20N/cm to the electro-optic modulation chip longitudinally ² Is less than 10 ^-5 Slowly heating up and maintaining for 0.5-2 hours under vacuum atmosphere of mbar and environment temperature of 150-250 ℃ and then slowly cooling down so that bond energy is enhanced to be more than 2J/m ² 。

8. The method of claim 6, wherein the annealing is performed by stripping the germanium-cleaved layer and the residual germanium substrate as follows: when the size of the electro-optical modulation chip is less than or equal to 6 inches, adopting a furnace tube heating annealing mode; when the size of the electro-optical modulation chip is larger than 6 inches, a laser annealing mode is adopted.

9. The method according to claim 2, wherein the etching the germanium thin film layer specifically comprises:

10. The method of manufacturing as claimed in claim 2, wherein the growth window is opened by etching the upper insulating substrate layer on the germanium substrate growth layer in the optical gain section, ensuring that no natural oxide is generated on the germanium substrate growth layer after the growth window is opened, and growing the compound semiconductor active layer.