CN117439596A - Receiving circuit, deserializing circuit chip, electronic equipment and vehicle - Google Patents
Receiving circuit, deserializing circuit chip, electronic equipment and vehicle Download PDFInfo
- Publication number
- CN117439596A CN117439596A CN202310995782.6A CN202310995782A CN117439596A CN 117439596 A CN117439596 A CN 117439596A CN 202310995782 A CN202310995782 A CN 202310995782A CN 117439596 A CN117439596 A CN 117439596A
- Authority
- CN
- China
- Prior art keywords
- field effect
- module
- receiving
- gain
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims description 76
- 230000005540 biological transmission Effects 0.000 claims description 12
- 239000003990 capacitor Substances 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 230000002238 attenuated effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000000881 depressing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The disclosure relates to the technical field of electronic appliances, and provides a receiving circuit, a deserializing circuit chip, electronic equipment and a vehicle. The receiving circuit comprises at least two stages of receiving modules and gain modules which are arranged at intervals with the receiving modules; the first end of the receiving module at the front stage is connected with the first end of the gain module, the second end of the receiving module at the front stage is connected with the second end of the gain module, the third end of the gain module is connected with the first end of the receiving module at the rear stage, and the fourth end of the gain module is connected with the second end of the receiving module at the rear stage; the receiving module at the front stage is configured to suppress the low-frequency gain of the received signal; the gain module is configured to compensate the low-frequency gain to the receiving module at the subsequent stage; the receiving module at the latter stage is configured to equalize a low-frequency gain and a high-frequency gain of the received signal. By adopting the receiving circuit disclosed by the invention, not only can the large-scale equalization be realized, but also the occupied area of a chip can be reduced, and the cost is low.
Description
Technical Field
The disclosure relates to the technical field of electronic and electric appliances, and in particular relates to a receiving circuit, a deserializing circuit chip, electronic equipment and a vehicle.
Background
SERDES (Serializer-Deserializer) is a communication technology in which multiple low-speed parallel signals are converted into high-speed serial signals at a transmitting end, and the high-speed serial signals are reconverted into low-speed parallel signals at a receiving end after passing through a transmission medium. With the continuous popularization and development of high-definition video, the requirements on SERDES circuits are also increased, and the requirements are mainly reflected in the aspect of video transmission speed.
As the process is used more and more advanced, the video transmission speed is improved, but the transmission medium is not well improved, and the voltage margin reserved for the receiving circuit is reduced due to the fact that the internal voltage of the chip is lower and lower. Therefore, it is more difficult to meet the practical requirements of the conventional receiving circuit, and it is difficult to compensate for the high attenuation of the wire. In order to realize low-frequency and high-frequency gain equalization, the related art generally uses an inductor to perform gain compensation on the high frequency, but in this way, the inductor occupies a larger chip area, the process cost is higher, and the method has limitations.
Disclosure of Invention
In view of the above, it is necessary to provide a receiving circuit, a deserializing circuit chip, an electronic device, and a vehicle, which can realize a wide range of equalization, and which can reduce the chip occupation area and the cost.
In a first aspect, an embodiment of the present disclosure provides a receiving circuit, where the receiving circuit includes at least two stages of receiving modules and a gain module spaced from the receiving modules;
the first end of the receiving module at the front stage is connected with the first end of the gain module, the second end of the receiving module at the front stage is connected with the second end of the gain module, the third end of the gain module is connected with the first end of the receiving module at the rear stage, and the fourth end of the gain module is connected with the second end of the receiving module at the rear stage;
the receiving module at the front stage is configured to suppress the low-frequency gain of the received signal; the gain module is configured to compensate low-frequency gain to the receiving module at the subsequent stage; the receiving module at the subsequent stage is configured to equalize a low-frequency gain and a high-frequency gain of the received signal.
Optionally, in some embodiments of the present disclosure, the gain module includes a first field effect transistor, a second field effect transistor, a first current source, a first resistor, and a second resistor;
the first end of the first field effect tube is connected with the first end of the receiving module at the front stage, the second end of the first field effect tube is connected with the first end of the first current source, the second end of the first current source is grounded, the third end of the first field effect tube is respectively connected with the first end of the first resistor and the first end of the receiving module at the rear stage, the second end of the first resistor is connected with a power supply, the first end of the second field effect tube is connected with the second end of the receiving module at the front stage, the second end of the second field effect tube is connected with the first end of the first current source, the third end of the second field effect tube is respectively connected with the first end of the second resistor and the second end of the receiving module at the rear stage, and the second end of the second resistor is connected with the power supply.
Optionally, in some embodiments of the present disclosure, the first field effect transistor and the second field effect transistor are both NMOS transistors;
the first end of the first field effect tube is a grid electrode of the NMOS tube, the second end of the first field effect tube is a source electrode of the NMOS tube, the third end of the first field effect tube is a drain electrode of the NMOS tube, the first end of the second field effect tube is a grid electrode of the NMOS tube, the second end of the second field effect tube is a source electrode of the NMOS tube, and the third end of the second field effect tube is a drain electrode of the NMOS tube.
Optionally, in some embodiments of the disclosure, each of the receiving modules is based on a continuous time linear equalization architecture.
Optionally, in some embodiments of the present disclosure, the receiving module at the front stage includes a third field effect transistor, a fourth field effect transistor, a capacitor, a third resistor, a second current source, a third current source, a fourth resistor, and a fifth resistor;
the first end of the third field effect tube is connected with one path of signal, the second end of the third field effect tube is respectively connected with the first end of the capacitor, the first end of the third resistor and the first end of the second current source, the third end of the third field effect tube is respectively connected with the first end of the fourth resistor and the first end of the gain module, the second end of the second current source is grounded, the second end of the fourth resistor is connected with a power supply, the first end of the fourth field effect tube is connected with another path of signal, the second end of the fourth field effect tube is respectively connected with the second end of the capacitor, the second end of the third resistor and the first end of the third current source, the third end of the fourth field effect tube is respectively connected with the first end of the fifth resistor and the second end of the gain module, and the second end of the fifth resistor is connected with the power supply.
Optionally, in some embodiments of the present disclosure, the third field effect transistor and the fourth field effect transistor are both NMOS transistors;
the first end of the third field effect tube is a grid electrode of the NMOS tube, the second end of the third field effect tube is a source electrode of the NMOS tube, the third end of the third field effect tube is a drain electrode of the NMOS tube, the first end of the fourth field effect tube is a grid electrode of the NMOS tube, the second end of the fourth field effect tube is a source electrode of the NMOS tube, and the third end of the fourth field effect tube is a drain electrode of the NMOS tube.
Optionally, in some embodiments of the disclosure, the receiving module includes a first stage receiving module and a second stage receiving module, and the gain module includes a first gain module disposed after the first stage receiving module and a second gain module disposed after the second stage receiving module.
In a second aspect, an embodiment of the present disclosure provides a deserializing circuit chip, where the deserializing circuit chip includes the receiving circuit of any one of the first aspects.
In a third aspect, an embodiment of the present disclosure provides an electronic device, including a serial circuit chip, a transmission medium, and the deserializing circuit chip of the second aspect, wherein the transmission medium is disposed between the serial circuit chip and the deserializing circuit chip.
In a fourth aspect, embodiments of the present disclosure provide a vehicle comprising the electronic device of the third aspect.
From the above technical solutions, the embodiments of the present disclosure have the following advantages:
according to the receiving circuit, the deserializing circuit chip, the electronic equipment and the vehicle, the low-frequency gain can be improved by arranging the gain modules among the receiving modules, so that the receiving modules at the later stage can be used in more low-frequency gain spaces, the equalizing range is enlarged, the cascade connection can be continued under the condition of bandwidth permission, the equalization in a larger range is realized, meanwhile, inductance is not needed, the occupied area of the chip is reduced, and the cost is greatly reduced.
Drawings
Other features, objects and advantages of the present disclosure will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings:
fig. 1 is a schematic structural diagram of a receiving circuit according to an embodiment of the disclosure;
fig. 2 is a block diagram of a receiving circuit according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of another receiving circuit according to an embodiment of the disclosure;
fig. 4 is a block diagram of a deserializing circuit chip according to an embodiment of the disclosure;
fig. 5 is a block diagram of an electronic device according to an embodiment of the disclosure;
fig. 6 is a block diagram of a vehicle according to an embodiment of the present disclosure.
Detailed Description
In order that those skilled in the art will better understand the present disclosure, a technical solution in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above-described figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the described embodiments of the disclosure may be capable of operation in sequences other than those illustrated or described herein.
Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or modules is not necessarily limited to those steps or modules that are expressly listed or inherent to such process, method, article, or apparatus.
For a better understanding of the present disclosure, the description will now be made in connection with the receiving circuit shown in fig. 1. For example, the receiving circuit provided in the embodiments of the present disclosure is based on a continuous time linear equalization (Continuous Time Linear Equalizer, CTLE) architecture, and it can be seen from fig. 1 that two CTLEs are directly cascaded, and CTLE implements equalization by depressing low frequency gain to boost high frequency gain. Since the received signal of CTLE is usually a high-speed signal transmitted through a long transmission line, the high-frequency signal is greatly attenuated, and the low-frequency signal is also attenuated to some extent, so that the low-frequency gain space left for CTLE to be able to be suppressed is extremely limited. If the low-frequency voltage of the first-stage CTLE is too low, the swing of the low-frequency signal will be small, and if the two-stage CTLE are directly cascaded, the performance of the second-stage CTLE will be greatly limited, and the overall balance effect is seriously affected.
To this end, the embodiment of the disclosure provides a receiving circuit, a deserializing circuit chip, an electronic device and a vehicle. Referring to fig. 2, which is a block diagram of a receiving circuit according to an embodiment of the disclosure, the receiving circuit 10 includes at least two receiving modules 11 and a gain module 12 spaced from the receiving modules 11, and each receiving module 11 may be based on a continuous time linear equalization architecture. Wherein, the first end of the receiving module 11 at the front stage is connected to the first end of the gain module 12, the second end of the receiving module 11 at the front stage is connected to the second end of the gain module 12, the third end of the gain module 12 is connected to the first end of the receiving module 11 at the rear stage, and the fourth end of the gain module 12 is connected to the second end of the receiving module 11 at the rear stage.
Illustratively, the receiving module 11 at the front stage in the receiving circuit 10 of the embodiment of the present disclosure can suppress the low-frequency gain of the received signal, while the gain module 12 can compensate the low-frequency gain for the receiving module 11 at the rear stage, and further the receiving module 11 at the rear stage can equalize the low-frequency gain and the high-frequency gain of the received signal. The advantage of this arrangement is that by arranging the gain modules 12 between the receiving modules 11, the low frequency gain can be increased, so that the receiving modules 11 at the later stage have more low frequency gain space available, the equalization range is enlarged, and the cascade connection can be continued under the condition of bandwidth permission, thereby realizing the equalization of a larger range.
The specific circuit configuration of each constituent block in the reception circuit 10 will be described in detail below with reference to fig. 3. For example, the gain module 12 includes, but is not limited to, a first fet Q1, a second fet Q2, a first current source A1, a first resistor R1, and a second resistor R2, where a first end of the first fet Q1 (corresponding to a first end of the gain module 12) is connected to a first end of the receiving module 11 at a front stage, a second end of the first fet Q1 is connected to the first end of the first current source A1, a second end of the first current source A1 is grounded, a third end of the first fet Q1 (corresponding to a third end of the gain module 12) is connected to the first end of the first resistor R1 and a first end of the receiving module 11 at a rear stage, a second end of the first resistor R1 is connected to a power supply (VDD), a first end of the second fet Q2 (corresponding to a second end of the gain module 12) is connected to a second end of the receiving module 11 at a front stage, a second end of the second fet Q2 is connected to a first end of the first current source A1, a third end of the second fet Q1 (corresponding to a third end of the gain module 12) is connected to a first end of the second resistor R2 at a second end of the second resistor R2 (corresponding to a second end of the second resistor R2).
Optionally, in some embodiments of the present disclosure, the first field effect transistor Q1 and the second field effect transistor Q2 may be NMOS transistors, where a first end of the first field effect transistor Q1 is a gate of the NMOS transistor, a second end of the first field effect transistor Q1 is a source of the NMOS transistor, a third end of the first field effect transistor Q1 is a drain of the NMOS transistor, a first end of the second field effect transistor Q2 is a gate of the NMOS transistor, a second end of the second field effect transistor Q2 is a source of the NMOS transistor, and a third end of the second field effect transistor Q2 is a drain of the NMOS transistor.
For example, the receiving module 11 at the front stage includes, but is not limited to, a third fet Q3, a fourth fet Q4, a capacitor C1, a third resistor R3, a second current source A2, a third current source A3, a fourth resistor R4, and a fifth resistor R5, where a first end (corresponding to rx_p) of the third fet Q3 is connected to a signal, a second end of the third fet Q3 is connected to the first end of the capacitor C1, a first end of the third resistor R3, and a first end of the second current source A2, a third end (corresponding to the first end of the receiving module 11 at the front stage) of the third fet Q3 is connected to a first end of the fourth resistor R4 and a first end of the gain module 12, a second end of the second current source A2 is grounded, a second end of the fourth resistor R4 is connected to a power supply (VDD), a first end (corresponding to rx_n) of the fourth fet Q4 is connected to another signal, and a second end of the fourth fet Q4 is connected to a third end of the third resistor C1, a first end of the third fet Q3 is connected to the first end of the third resistor A3 and a first end of the fourth resistor a 5 at the front stage is connected to the third end of the third resistor R3, and the third end of the fourth resistor Q4 is connected to the first end of the fourth resistor b 3 is connected to the third end of the fourth resistor b 5 at the front end of the fourth resistor b 4.
Optionally, in some embodiments of the present disclosure, the third field effect transistor Q3 and the fourth field effect transistor Q4 may be NMOS transistors, where a first end of the third field effect transistor Q3 is a gate of the NMOS transistor, a second end of the third field effect transistor Q3 is a source of the NMOS transistor, a third end of the third field effect transistor Q3 is a drain of the NMOS transistor, a first end of the fourth field effect transistor Q4 is a gate of the NMOS transistor, a second end of the fourth field effect transistor Q4 is a source of the NMOS transistor, and a third end of the fourth field effect transistor Q4 is a drain of the NMOS transistor.
Optionally, the receiving module 11 in some embodiments of the present disclosure includes, but is not limited to, a first stage receiving module 111 and a second stage receiving module 112, and the gain module 12 includes, but is not limited to, a first gain module 121 disposed after the first stage receiving module 111 and a second gain module 122 disposed after the second stage receiving module 112.
As another aspect, the embodiment of the present disclosure further provides a deserializing circuit chip. As shown in fig. 4, the deserializing circuit chip 20 may include, but is not limited to, the receiving circuit 10 in the corresponding embodiment of fig. 2-3.
As yet another aspect, an embodiment of the present disclosure further provides an electronic device. As shown in fig. 5, the electronic device 30 may include a serial circuit chip 31, a transmission medium 32, and the deserializing circuit chip 20 in the corresponding embodiment of fig. 4. The transmission medium 32 is disposed between the serial circuit chip 31 and the deserializing circuit chip 20, for example, the transmission medium 32 may be a shielded twisted pair (Shielded Twisted Pair, STP) or a Coaxial Cable (COAX).
As yet another aspect, the disclosed embodiments also provide a vehicle. As shown in fig. 6, the vehicle 40 may include the electronic device 30 in the corresponding embodiment of fig. 5.
The embodiment of the disclosure provides a receiving circuit, a deserializing circuit chip, electronic equipment and a vehicle, wherein the receiving circuit can improve low-frequency gain by arranging gain modules among receiving modules, so that the receiving modules at the later stage can be used in more low-frequency gain spaces, the equalizing range is enlarged, and the receiving modules can be continuously cascaded under the condition of bandwidth permission, so that the equalizing in a larger range is realized, meanwhile, inductance is not needed, the occupied area of the chip is reduced, and the cost is greatly reduced.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples merely represent several embodiments of the present disclosure, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the disclosure.
Claims (10)
1. A receiving circuit, characterized in that the receiving circuit comprises at least two stages of receiving modules and gain modules arranged at intervals with the receiving modules;
the first end of the receiving module at the front stage is connected with the first end of the gain module, the second end of the receiving module at the front stage is connected with the second end of the gain module, the third end of the gain module is connected with the first end of the receiving module at the rear stage, and the fourth end of the gain module is connected with the second end of the receiving module at the rear stage;
the receiving module at the front stage is configured to suppress the low-frequency gain of the received signal; the gain module is configured to compensate low-frequency gain to the receiving module at the subsequent stage; the receiving module at the subsequent stage is configured to equalize a low-frequency gain and a high-frequency gain of the received signal.
2. The receive circuit of claim 1, wherein the gain module comprises a first field effect transistor, a second field effect transistor, a first current source, a first resistor, and a second resistor;
the first end of the first field effect tube is connected with the first end of the receiving module at the front stage, the second end of the first field effect tube is connected with the first end of the first current source, the second end of the first current source is grounded, the third end of the first field effect tube is respectively connected with the first end of the first resistor and the first end of the receiving module at the rear stage, the second end of the first resistor is connected with a power supply, the first end of the second field effect tube is connected with the second end of the receiving module at the front stage, the second end of the second field effect tube is connected with the first end of the first current source, the third end of the second field effect tube is respectively connected with the first end of the second resistor and the second end of the receiving module at the rear stage, and the second end of the second resistor is connected with the power supply.
3. The receiving circuit of claim 2, wherein the first field effect transistor and the second field effect transistor are NMOS transistors;
the first end of the first field effect tube is a grid electrode of the NMOS tube, the second end of the first field effect tube is a source electrode of the NMOS tube, the third end of the first field effect tube is a drain electrode of the NMOS tube, the first end of the second field effect tube is a grid electrode of the NMOS tube, the second end of the second field effect tube is a source electrode of the NMOS tube, and the third end of the second field effect tube is a drain electrode of the NMOS tube.
4. A receiving circuit according to any one of claims 1 to 3, wherein each of the receiving modules is based on a continuous time linear equalization architecture.
5. The receiving circuit of claim 4, wherein the receiving module at the front stage comprises a third fet, a fourth fet, a capacitor, a third resistor, a second current source, a third current source, a fourth resistor, and a fifth resistor;
the first end of the third field effect tube is connected with one path of signal, the second end of the third field effect tube is respectively connected with the first end of the capacitor, the first end of the third resistor and the first end of the second current source, the third end of the third field effect tube is respectively connected with the first end of the fourth resistor and the first end of the gain module, the second end of the second current source is grounded, the second end of the fourth resistor is connected with a power supply, the first end of the fourth field effect tube is connected with another path of signal, the second end of the fourth field effect tube is respectively connected with the second end of the capacitor, the second end of the third resistor and the first end of the third current source, the third end of the fourth field effect tube is respectively connected with the first end of the fifth resistor and the second end of the gain module, and the second end of the fifth resistor is connected with the power supply.
6. The receiving circuit of claim 5, wherein the third fet and the fourth fet are NMOS transistors;
the first end of the third field effect tube is a grid electrode of the NMOS tube, the second end of the third field effect tube is a source electrode of the NMOS tube, the third end of the third field effect tube is a drain electrode of the NMOS tube, the first end of the fourth field effect tube is a grid electrode of the NMOS tube, the second end of the fourth field effect tube is a source electrode of the NMOS tube, and the third end of the fourth field effect tube is a drain electrode of the NMOS tube.
7. The receive circuit of claim 6, wherein the receive modules comprise a first stage receive module and a second stage receive module, and wherein the gain module comprises a first gain module disposed after the first stage receive module and a second gain module disposed after the second stage receive module.
8. A deserializing circuit chip, characterized in that it comprises the receiving circuit of any one of claims 1 to 7.
9. An electronic device comprising a serial circuit chip, a transmission medium, and the deserializing circuit chip of claim 8, wherein the transmission medium is disposed between the serial circuit chip and the deserializing circuit chip.
10. A vehicle, characterized in that it comprises the electronic device of claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310995782.6A CN117439596A (en) | 2023-08-09 | 2023-08-09 | Receiving circuit, deserializing circuit chip, electronic equipment and vehicle |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310995782.6A CN117439596A (en) | 2023-08-09 | 2023-08-09 | Receiving circuit, deserializing circuit chip, electronic equipment and vehicle |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117439596A true CN117439596A (en) | 2024-01-23 |
Family
ID=89554307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310995782.6A Pending CN117439596A (en) | 2023-08-09 | 2023-08-09 | Receiving circuit, deserializing circuit chip, electronic equipment and vehicle |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117439596A (en) |
-
2023
- 2023-08-09 CN CN202310995782.6A patent/CN117439596A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7884648B2 (en) | Pseudo-differential interfacing device having a switching circuit | |
| US20110095838A1 (en) | Multichannel interfacing device having a termination circuit | |
| US20060245485A1 (en) | Continuous-time equalizer | |
| GB2415339A (en) | A negative impedance receiver equaliser | |
| US20060291552A1 (en) | Decision feedback equalizer | |
| US8989238B2 (en) | Bi-directional interface circuit having a switchable current-source bias | |
| CN115314069B (en) | Full duplex transmitting and receiving circuit, deserializing circuit chip, electronic equipment and vehicle | |
| US20200036563A1 (en) | Passive continuous-time linear equalizer | |
| WO2008155676A1 (en) | Pseudo-differential interfacing device having a termination circuit | |
| JP4837715B2 (en) | Active connector | |
| US9054902B2 (en) | Apparatus and system for switching equalization | |
| CN117254995A (en) | Receiver front-end device of continuous time linear equalizer based on multiple feedforward | |
| US20130235921A1 (en) | Signal conversion during transmission of serial data streams | |
| US9024659B2 (en) | Method and apparatus for passive equalization and slew-rate control | |
| CN117439596A (en) | Receiving circuit, deserializing circuit chip, electronic equipment and vehicle | |
| WO2023146732A1 (en) | Analog receiver front-end with variable gain amplifier embedded in an equalizer structure | |
| US7902882B2 (en) | Apparatus including a follower output buffer having an output impedance that adapts to a transmission line impedance | |
| CN110838675B (en) | High-speed large-current laser driving circuit and chip thereof | |
| Maeda et al. | An active copper-cable supporting 56-Gbit/s PAM4 and 28-Gbit/s NRZ with continuous time linear equalizer IC for to-meters reach interconnection | |
| US8251721B2 (en) | Active connector | |
| CN110995226B (en) | Serial receiving front-end circuit with wide input range and constant gain | |
| CN117895940A (en) | Receiving circuit compatible with single-end input and double-end input, chip and electronic equipment | |
| CN117040562B (en) | Full duplex transmitting and receiving circuit, serializer, deserializer and vehicle | |
| CN117938192A (en) | Full duplex transmitting and receiving circuit, deserializing circuit chip, electronic equipment and vehicle | |
| US20230246661A1 (en) | Simultaneous Bi-directional Hybrid Transceiver for Single-Ended Voltage Mode Signaling |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |