CN117438476A - Groove type Schottky barrier semiconductor structure and preparation method thereof - Google Patents

Abstract

The application relates to a trench schottky barrier semiconductor structure and a preparation method thereof, wherein the semiconductor structure comprises a substrate, a doped structure formed by a plurality of doped silicon laminated layers, a first trench, a second trench, a trench conductive structure and a trench schottky contact metal. The first groove is filled with groove Schottky contact metal so as to form Schottky contact with the doped silicon layer exposed on the side wall of the first groove; the trench conductive structure fills the second trench. When the device is in reverse bias, two adjacent first well regions at one side of the groove Schottky contact metal can deplete the doped silicon layer between the two first well regions, so that the strongest electric field is close to the body, and leakage current is reduced when in reverse bias. When the device is conducted in the forward direction, due to the arrangement of the groove Schottky contact metal, the Schottky diode is firstly opened to form a plurality of current paths, compared with the prior SBD, the current paths are shortened, the number of the current paths is increased, the reverse leakage current is not increased, the current capacity of the device is improved, and the on resistance is reduced.

Description

Groove type Schottky barrier semiconductor structure and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a groove type Schottky barrier semiconductor structure and a preparation method thereof.

Background

Schottky barrier diodes (SBD, schottky Barrier Diode) are low power consumption, high current, ultra-high speed semiconductor devices that have been widely used in recent years.

In the reverse blocking process of the SBD, the related art generally changes the p+ width at one side of the schottky contact and the spacing between p+ and p+ to reduce the surface electric field of the device, so as to reduce the reverse leakage current of the device, thereby obtaining better blocking characteristics. However, the presence of p+ reduces the current path in forward conduction, reducing the device current capability.

Disclosure of Invention

Based on this, it is necessary to provide a trench schottky barrier semiconductor structure and a method for manufacturing the same, so as to ensure that the reverse leakage current is not increased when the trench schottky barrier semiconductor structure is reverse biased, but the current path can be increased when the trench schottky barrier semiconductor structure is forward conducted, and the current capability is improved.

In order to achieve the purpose of the application, the application adopts the following technical scheme:

a trench schottky barrier semiconductor structure comprising:

a substrate of a first conductivity type;

a doped structure of a first conductivity type formed on the substrate, the doped structure comprising a plurality of doped silicon layers arranged in a stacked manner, wherein the doped silicon layers are formed with a first well region of a second conductivity type, and the second conductivity type is opposite to the first conductivity type in electrical property;

A first trench located in the doping structure and penetrating through the plurality of first well regions, so that the doped silicon layer and the first well regions are alternately exposed at the side wall of the first trench along the depth direction of the first trench;

the second grooves are positioned in the doping structure and are spaced from the first grooves and the plurality of first well regions;

the groove Schottky contact metal fills the first groove and forms Schottky contact with the doped silicon layer exposed on the side wall of the first groove;

and the groove conducting structure fills the second groove.

In one embodiment, the doped silicon layer disposed by the multi-layer stack includes a top doped silicon layer and a middle doped silicon layer disposed between the substrate and the top doped silicon layer, wherein the middle doped silicon layer is further formed with a second well region of the first conductivity type spaced apart from the first well region;

the second trenches are located in the doped structure and penetrate through the plurality of second well regions, so that the doped silicon layers and the second well regions are alternately exposed on the side walls of the second trenches along the depth direction of the second trenches.

In one embodiment, the number of the second grooves is at least two, the number of the first grooves is at least one, and the second grooves and the first grooves are alternately arranged.

In one embodiment, each doped silicon layer is formed with the first well region, and each doped silicon layer in the middle is formed with the second well region.

In one embodiment, the second trench extends into the doped silicon layer adjacent to the substrate, and a bottom wall of the second trench exposes the doped silicon layer adjacent to the substrate or exposes the second well region of the doped silicon layer adjacent to the substrate; or,

the second trench extends to an upper surface of the doped silicon layer adjacent to the substrate, and a bottom wall of the second trench exposes the second well region of the doped silicon layer adjacent to the substrate.

In one embodiment, the first trench extends into the doped silicon layer adjacent to the substrate, and a bottom wall of the first trench exposes the doped silicon layer adjacent to the substrate or exposes the first well region of the doped silicon layer adjacent to the substrate; or,

the first trench extends to an upper surface of the doped silicon layer adjacent to the substrate, and a bottom wall of the first trench exposes the first well region of the doped silicon layer adjacent to the substrate.

In one embodiment, the semiconductor structure is a lateral trench schottky barrier semiconductor structure, the semiconductor structure further comprising:

The anode metal is arranged on the upper surface of the doping structure and is electrically connected with the groove Schottky contact metal;

and the cathode metal is arranged on the upper surface of the doping structure and is electrically connected with the groove conducting structure.

In one embodiment, the semiconductor structure is a vertical trench schottky barrier semiconductor structure, the semiconductor structure further comprising:

a passivation layer covering the trench conductive structure, wherein the potential of the trench conductive structure floats;

a field plate covering a part of the passivation layer and extending to cover a part of the upper surface of the doped structure;

the surface Schottky contact metal is positioned on the doping structure and covers the passivation layer, the field plate and the groove Schottky contact metal;

and the surface conductive structure covers the surface of the substrate, which is away from the doping structure.

A preparation method of a trench Schottky barrier semiconductor structure comprises the following steps:

providing a substrate of a first conductivity type;

forming a doped structure of a first conductivity type on the substrate, wherein the doped structure comprises a doped silicon layer which is formed by stacking a plurality of layers, and a first well region of a second conductivity type is formed on the doped silicon layer, and the second conductivity type is opposite to the first conductivity type in electrical property;

A first groove penetrating through a plurality of first well regions is formed in the doping structure, so that the doped silicon layer and the first well regions are alternately exposed on the side wall of the first groove along the depth direction of the first groove;

forming a second groove which is separated from the first groove and the plurality of first well regions in the doping structure;

filling a groove Schottky contact metal in the first groove, wherein the groove Schottky contact metal forms Schottky contact with the doped silicon layer exposed on the side wall of the first groove;

and filling the second groove with a groove conducting structure.

In one embodiment, the forming a doped structure of a first conductivity type on the substrate, the doped structure including a doped silicon layer disposed by a multi-layer stack, the doped silicon layer being formed with a first well region of a second conductivity type, includes:

forming a doped silicon layer on the substrate through epitaxial growth, and forming a first well region on the upper surface layer of the doped silicon layer through first doping treatment on the doped silicon layer;

and alternately performing epitaxial growth to form a doped silicon layer and forming a first well region on the upper surface layer of the doped silicon layer through first doping treatment so as to form the doped silicon layer arranged by the multi-layer lamination.

In one embodiment, the forming a doped structure of the first conductivity type on the substrate includes a doped silicon layer disposed by stacking a plurality of layers, the doped silicon layer forming a first well region of the second conductivity type, and further includes:

forming a second well region of the first conductivity type spaced from the first well region on the upper surface layer of the doped silicon layer by a second doping process, alternately forming the doped silicon layer by epitaxial growth and the second well region of the first conductivity type on the upper surface layer of the doped silicon layer by the second doping process to form a doped silicon layer in a multi-layer stack arrangement,

the doped silicon layer arranged by the multilayer lamination comprises a doped silicon layer at the top and a doped silicon layer at the middle part between the substrate and the doped silicon layer at the top, and the second well region is formed on the doped silicon layer at the middle part only;

the forming of the second trenches in the doped structure, which are spaced from the first trenches and the plurality of first well regions, further includes:

the second trenches are located in the doped structure and penetrate through the plurality of second well regions, so that the doped silicon layers and the second well regions are alternately exposed at the side walls of the second trenches along the depth direction of the second trenches.

In one embodiment, each of the middle doped silicon layers is formed with the first well region and the second well region.

In one embodiment, the preparation method further comprises:

forming a passivation layer to cover the trench conductive structure;

forming a field plate on the passivation layer, wherein the field plate covers part of the passivation layer and extends to cover part of the upper surface of the doping structure;

forming surface schottky contact metal on the doped structure, wherein the surface schottky contact metal covers the passivation layer, the field plate and the trench schottky contact metal;

and forming a surface conductive structure to cover the surface of the substrate, which is away from the doping structure.

The semiconductor structure comprises a substrate, a doped structure, a first groove, a second groove, a conductive structure and groove Schottky contact metal, wherein the doped structure is formed on the substrate and comprises a doped silicon layer which is formed by multi-layer lamination, a first well region of a second conductivity type is formed on the doped silicon layer, and the doped silicon layer and the first well region are alternately exposed on the side wall of the first groove along the depth direction of the first groove; the first groove is filled with groove Schottky contact metal to form Schottky contact with the doped silicon layer exposed on the side wall of the first groove, and the second groove is filled with the conductive structure. When the device is in reverse bias, two adjacent first well regions at one side of the groove Schottky contact metal can deplete the doped silicon layer between the two first well regions, so that the strongest electric field is close to the body, and leakage current is reduced when in reverse bias. When the device is conducted in the forward direction, the schottky barrier is far lower than the PN junction barrier due to the arrangement of the groove schottky contact metal, so that the schottky diode can be firstly opened to form a plurality of current paths, compared with the prior SBD, the current paths are shortened, the number of the current paths is increased, and therefore the reverse leakage current of the groove schottky barrier semiconductor structure is not increased, and meanwhile the current capacity of the device is improved, and the on resistance is reduced. In addition, the number of the doped silicon layers between two adjacent first well regions at one side of the groove Schottky contact metal can be flexibly adjusted, and the current required by the groove Schottky barrier semiconductor structure can be flexibly met.

Drawings

FIG. 1 is a schematic cross-sectional view of a semiconductor structure according to one embodiment;

FIG. 2 is a schematic diagram of a cross-sectional structure of a semiconductor structure according to an embodiment;

FIG. 3 is a schematic cross-sectional view of a related art semiconductor structure according to one embodiment;

FIG. 4 is a third schematic cross-sectional view of a semiconductor structure according to one embodiment;

FIG. 5 is a schematic diagram showing a cross-sectional structure of a related art semiconductor structure according to a second embodiment;

FIG. 6 is a schematic cross-sectional view of a semiconductor structure according to one embodiment;

FIG. 7 is a schematic diagram of a cross-sectional structure of a semiconductor structure according to an embodiment;

FIG. 8 is a schematic diagram of a cross-sectional structure of a semiconductor structure according to an embodiment;

FIG. 9 is a schematic diagram of a cross-sectional structure of a semiconductor structure according to one embodiment;

FIG. 10 is a schematic diagram of a cross-sectional structure of a semiconductor structure according to an embodiment;

FIG. 11 is a schematic diagram of a cross-sectional structure of a semiconductor structure according to one embodiment;

FIG. 12 is one of the process flow diagrams of a method for fabricating a semiconductor structure according to one embodiment;

FIG. 13 is a second flow chart of a method for fabricating a semiconductor structure according to one embodiment;

FIG. 14 is a third flowchart illustrating a method for fabricating a semiconductor structure according to one embodiment.

Detailed Description

In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that the terms "first," "second," and the like, as used herein, may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element and should not be construed as indicating or implying a relative importance or number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless explicitly defined otherwise.

It is to be understood that the terms "upper," "lower," "vertical," "horizontal," "inner," "outer," and the like indicate orientations or positional relationships based on the methods or positional relationships shown in the drawings, and are merely for convenience in describing the invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the invention.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

In the related art of SBD, an existing SBD is generally to form an epitaxial layer of the same conductivity type on a substrate of a first conductivity type, form a well region of a second conductivity type on the epitaxial layer by implantation, cover a metal layer on the back surface of the substrate to form an ohmic contact, and cover a metal layer on the upper surface of the well region/epitaxial layer to form a schottky contact. During reverse blocking, the surface electric field of the device is reduced by changing the width of the well region at one side of the schottky contact and the distance between two adjacent well regions, so that the reverse leakage current of the device is reduced, and better blocking characteristics are obtained. However, due to the existence of the well region, the current path is reduced when the device is turned on in the forward direction, and the current capability of the device is reduced.

In view of this, the trench schottky barrier semiconductor structure and the method for manufacturing the same provided in the embodiments of the present application can ensure that the strongest electric field is far away from the schottky contact surface and does not increase the reverse leakage current when the trench schottky barrier semiconductor structure is reverse biased, and simultaneously can increase the current path when forward conducting, thereby improving the current capability, shortening the current path, and reducing the on-resistance.

Fig. 1 is a schematic cross-sectional view of a trench schottky barrier semiconductor structure according to an embodiment. As shown in fig. 1 (the number of trenches in fig. 1 is merely an example and is not limited thereto), the trench schottky barrier semiconductor structure includes a substrate 100, a doping structure 200, a first trench 300, a second trench 400, a trench schottky contact metal 500, and a trench conductive structure 600.

In this embodiment, the doped structure 200 of the first conductivity type is formed on the substrate 100, the doped structure 200 includes a doped silicon layer disposed by stacking a plurality of layers, and the doped silicon layer 210 is formed with a first well region 201 of a second conductivity type, which is opposite to the first conductivity type.

The first trenches 300 are located in the doped structure 200 and penetrate the plurality of first well regions 201 such that the doped silicon layers 210 and the first well regions 201 are alternately exposed on the sidewalls of the first trenches 300 along the depth direction of the first trenches 300 on the sidewalls of the first trenches 300; a second trench 400 located in the doped structure 200 and spaced apart from the first trench 300 and the plurality of first well regions 201; the trench schottky contact metal 500 fills the first trench 300 and forms schottky contact with the doped silicon layer 210 exposed at the sidewall of the first trench 300; the trench conductive structure 600 fills the second trench 400.

Wherein one of the first conductivity type and the second conductivity type is P-type, and the other is N-type. In this embodiment, the first conductivity type is N-type, the second conductivity type is P-type, the substrate 100 and the doped structure 200 are both N-type, the first well region 201 is P-type, the doping concentration of the substrate 100 and the doping concentration of the first well region 201 are both greater than the doping concentration of the doped structure 200, for example, the substrate 100 is an N-type substrate, the doped structure 200 includes a plurality of N-type doped silicon layers 210, and the first well region 201 is a p+ type region. In other embodiments, the first conductivity type is P-type and the second conductivity type is N-type.

The doped structure 200 includes a doped silicon layer 210 disposed in a multi-layer stack, and the multi-layer doped silicon layer 210 may be formed by epitaxial growth or by silicon-silicon bonding. The doped silicon layer 210 in the doped structure 200 is formed with a first well region 201 of a second conductivity type, and the first well region 201 may be formed on the doped silicon layer 210 by a doping process, for example, by implanting ions of the second conductivity type at a surface of the doped silicon layer 210 to form the first well region 201. Alternatively, among the plurality of doped silicon layers 210 stacked one on another, each doped silicon layer 210 may be sequentially formed with the first well region 201 by implantation, so that each doped silicon layer 210 is formed with the first well region 201; alternatively, the first well region 201 may be formed in the discontinuous doped silicon layers 210, for example, only one doped silicon layer 210 of every two adjacent doped silicon layers 210 is implanted to form the first well region 201, so that not every doped silicon layer 210 is implanted to form the first well region 201.

The first trenches 300 are located in the doped structure 200 and penetrate through the plurality of first well regions 201, so that the doped silicon layers 210 and the first well regions 201 are alternately exposed at the sidewalls of the first trenches 300 along the depth direction of the first trenches 300. Thus, the first trench 300 can expose the plurality of first well regions 201 and the region of the doped silicon layer 210 between adjacent two of the first well regions 201. Optionally, in a direction perpendicular to the substrate 100, a plurality of first well regions 201 formed in the multi-doped structure 200 are coaxially disposed so as to etch the first trenches 300 in the same axial direction, respectively.

The trench schottky contact metal 500 fills the first trench 300 and forms a schottky contact with the doped silicon layer 210 exposed at the sidewall of the first trench 300, that is, forms a schottky barrier, and the trench schottky contact metal 500 serves as a schottky contact anode. Adjacent two first well regions 201 on one side of the trench schottky contact metal 500 can deplete the doped silicon layer 210 between the two first well regions 201, so that the strongest electric field is close to the body and the leakage current is reduced during reverse bias. When the device is conducted in the forward direction, the schottky barrier is far lower than the PN junction barrier due to the arrangement of the groove schottky contact metal 500, so that the schottky diode can be firstly opened to form a plurality of current paths, compared with the prior SBD, the current paths are shortened, the number of the current paths is increased, and therefore the reverse leakage current of the groove schottky barrier semiconductor structure is not increased, the current capacity of the device is improved, and the on resistance is reduced. In addition, the number of the doped silicon layers between two adjacent first well regions at one side of the groove Schottky contact metal can be flexibly adjusted, and the current required by the groove Schottky barrier semiconductor structure can be flexibly met.

The description is given with the first well region 201 as p+ and the doped silicon layer 210 as N-: the P + around the trench schottky contact metal 500 helps deplete the N-between P + and P + during reverse bias, bringing the strongest electric field closer to the body, and thus reducing leakage current during reverse bias. When the positive electrode is conducted, current is formed between the N-electrode and the cathode electrode, a current path is shortened, a circuit path is increased, current capacity is improved, and on-resistance is reduced. Meanwhile, since the depth and width of the p+ can determine the depletion degree of the doped silicon layer 210, the number, depth and width of the p+ can be set according to the practical application requirement of the depletion degree of the device, so that N-near one side of the schottky contact of the trench schottky contact metal 500 or N-between adjacent p+ and p+ is just depleted by p+ at two sides to be a further alternative embodiment, so as to further reduce the leakage current when the device is reverse biased.

In some embodiments, as shown in fig. 2, on the basis of fig. 1, the doped silicon layer 210 of the multi-layer stack arrangement includes a top doped silicon layer 210 and a middle doped silicon layer 210 located between the substrate 100 and the top doped silicon layer 210, the middle doped silicon layer 210 further forming a second well region 202 of the first conductivity type spaced apart from the first well region 201.

The second well region 202 may be formed on the doped silicon layer 210 at the middle thereof by a doping process, for example, by implanting ions of the first conductivity type at the surface of the doped silicon layer 210 to form the second well region 202. Alternatively, among the plurality of middle doped silicon layers 210 stacked one on another, each doped silicon layer 210 may be sequentially formed with the second well region 202 by implantation, so that each doped silicon layer 210 is formed with the second well region 202; alternatively, the second well region 202 may be formed in the discontinuous doped silicon layers 210, for example, only one doped silicon layer 210 of every two adjacent doped silicon layers 210 in the middle may be implanted to form the second well region 202, so that not every doped silicon layer 210 is implanted to form the second well region 202. Alternatively, the first well region 201 and the second well region 202 may not be formed in the same doped silicon layer, for example, only one doped silicon layer 210 of every two adjacent middle doped silicon layers 210 is formed with the first well region 201, and the other doped silicon layer 210 is formed with the second well region 202.

The second trenches 400 are located in the doped structure 200 and penetrate through the plurality of second well regions 202, so that the doped silicon layers 210 and the second well regions 202 are alternately exposed at the sidewalls of the second trenches 400 along the depth direction of the second trenches 400. The plurality of second well regions 202 in the plurality of doped silicon layers 210 may be spaced apart or integrally connected in a direction perpendicular to the substrate 100. The depth and width of the second well region 202 can determine the resistance of the device, and the depth and width of the second well region 202 can be set according to the actual application requirement of the device resistance, and the corresponding depth and width requirement can be achieved by controlling the implantation parameters in the formation process of the second well region 202.

In some embodiments, the trench schottky barrier semiconductor structure is a lateral trench schottky barrier semiconductor structure, the trench conductive structure 600 is a metal material, the trench conductive structure 600 forms an ohmic contact with the doped silicon layer 210, and the trench conductive structure 600 serves as an ohmic contact cathode; the trench schottky contact metal 500 forms a schottky contact with the doped silicon layer 210 and the trench schottky contact metal 500 acts as a schottky contact anode.

Referring to fig. 3 and fig. 4 in an auxiliary manner, fig. 3 is a lateral SBD of the related art, and fig. 4 is a lateral trench schottky barrier semiconductor structure according to an embodiment of the present application, wherein a region of the doped silicon layer 210 between the trench conductive structure 600 and two adjacent second well regions 202 forms an ohmic contact, and the trench conductive structure 600 serves as an ohmic contact cathode; the trench schottky contact metal 500 forms schottky contacts with the regions of the doped silicon layer 210 between two adjacent first well regions 201; the trench schottky contact metal 500 acts as a schottky contact anode.

With continued assistance in fig. 3 and 4, the lateral SBD of the related art shown in fig. 3 has fewer current paths and long current paths (as indicated by the arrow in the figure) when it is turned on in the forward direction. In the lateral trench schottky barrier semiconductor structure of the embodiment shown in fig. 4, taking the first well region 201 as p+ and the second well region 202 as n+ and the doped silicon layer 210 as N-as an example, the second well region 202 can reduce the ohmic contact resistance on the cathode side (n+ refers to a highly doped N-type region, and the highly doped N-type region contacts with the trench conductive structure 600 to form ohmic contact, and its resistance is very small and negligible). Compared with the lateral SBD in the related art of fig. 3, in the lateral trench schottky barrier semiconductor structure of the embodiment of the present application shown in fig. 4, since the schottky barrier is lower than the PN junction barrier in forward conduction, the N-doped silicon layer 210 on one side of each anode flows out of the cathode, so that N-between p+ and p+ is equivalent to parallel connection, the current paths are increased, the current paths are greatly shortened, and the current capability of the trench schottky barrier semiconductor structure is improved; and meanwhile, the N+ greatly reduces the on-resistance of the device. That is, the trench schottky contact metal of the lateral trench schottky barrier semiconductor structure of the present application serves as a schottky contact anode, and the first well region 201 (p+) on one side of the schottky contact anode helps to deplete the doped silicon layer 210 (N-doped silicon layer) between the first well region 201 (p+) and the first well region 201 (p+) during reverse bias, so that the strongest electric field is close to the body, and the leakage current is reduced during reverse bias. Meanwhile, as the deep trench Schottky barrier semiconductor structure is additionally provided with the deep trench Schottky barrier semiconductor structure, compared with the transverse trench Schottky barrier semiconductor structure in the related art, the transverse current path is greatly shortened, the current capacity of the trench Schottky barrier semiconductor structure can be effectively improved, and the on-resistance is reduced.

In some embodiments, the lateral trench schottky barrier semiconductor structure further comprises: an anode metal and a cathode metal. An anode metal disposed on the upper surface of the doped structure 200 and electrically connected to the trench schottky contact metal 500; and a cathode metal disposed on the upper surface of the doped structure 200 and electrically connected to the trench conductive structure 600. Wherein, the anode metal is used as the extraction electrode of the groove Schottky contact metal 500, the cathode metal is used as the extraction electrode of the groove conductive structure 600, when the device is in forward conduction, the anode metal has higher voltage, the cathode metal is applied with lower voltage, and a current path is formed from the cathode metal to the anode metal through the groove conductive structure 600 and the groove Schottky contact metal 500; when reverse bias is applied, two adjacent first well regions 201 on one side of the trench schottky contact metal 500 deplete the doped silicon layer 210 between the two first well regions 201, so that the strongest electric field is close to the body, and the leakage current is reduced when reverse bias is applied.

In some embodiments, the trench schottky barrier semiconductor structure is a vertical trench schottky barrier semiconductor structure. As shown in fig. 5 and 6, fig. 5 is a longitudinal SBD of the related art, and fig. 6 is a longitudinal trench schottky barrier semiconductor structure of the present embodiment. The vertical trench schottky barrier semiconductor structure further includes: passivation layer 700, field plate 800, surface schottky contact metal 900 and surface conductive structure 1000. The passivation layer 700 covers the trench conductive structure 600, and the potential of the trench conductive structure 600 floats; the field plate 800 covers a portion of the passivation layer 700 and extends to cover a portion of the upper surface of the doped structure 200; a surface schottky contact metal 900 is located on the doped structure 200 and covers the passivation layer 700, the field plate 800, and the trench schottky contact metal 500. Wherein the passivation layer 700 covers the trench conductive structure 600 to isolate the trench conductive structure 600 from the surface schottky contact metal 900; the field plate 800 covers a portion of the passivation layer 700 and extends over a portion of the upper surface of the top doped silicon layer 210 to assist in depleting the region of the doped silicon layer 210 located on the surface of the top doped silicon layer 210 during device reverse bias. Due to the existence of the field plate 800 and the first well region 201, the strongest electric field is close to the body when the device is reversely biased, and the surface electric field is reduced, so that the reverse leakage current of the device is not increased, and the device performance is improved. The surface schottky contact metal 900 contacts the top epitaxial doped silicon layer 210 region not covered by the field plate 800, passivation layer 700 to form a schottky contact, and the surface schottky contact metal 900 and the trench schottky contact metal 500 act as a schottky contact anode. The surface conductive structure 1000 covers the lower surface of the substrate 100 facing away from the doped silicon layer 210 to form an ohmic contact with the lower surface of the substrate 100, the surface conductive structure 1000 acting as an ohmic contact cathode.

In some embodiments, the surface schottky contact metal 900 and the trench schottky contact metal 500 may be integrally formed or may be formed in two times.

In some embodiments, a second well region 202 is also formed in the top doped silicon layer 210 spaced apart from the first well region 201, and the passivation layer 700 also covers the second well region 202 in the top doped silicon layer 210 to isolate the second well region 202 from the surface schottky contact metal 900.

With continued assistance in fig. 5 and 6, the longitudinal SBD of the related art shown in fig. 5 has fewer current paths and long current paths (as indicated by the arrow-headed current paths) when it is turned on in the forward direction; in fig. 6, the trench conductive structure 600 contacts the doped silicon layer 210 region between two adjacent second well regions 202, and the trench conductive structure 600 and the second well regions 202 can reduce the on-resistance of the device at the same time; the trench schottky contact metal 500 forms a schottky contact with the region of the doped silicon layer 210 between two adjacent first well regions 201. Taking the first well region 201 as p+ and the second well region 202 as n+ and the doped silicon layer 210 as N-, it is obvious that in the longitudinal trench schottky barrier semiconductor structure of the embodiment of the present application, since the schottky barrier is lower than the PN junction barrier when conducting in the forward direction, the N-doped silicon layer 210 on one side of each anode will flow out of the current to the cathode, so the N-between p+ and p+ is equivalent to parallel connection, the current path is increased, and the current path is shortened, thereby improving the current capability of the trench schottky barrier semiconductor structure; simultaneously, the conducting structures 600 and N+ of the grooves simultaneously reduce the on-resistance of the device greatly. And additionally arranging a field plate 800 in the longitudinal groove type Schottky barrier semiconductor structure, and because of the existence of the field plate 800, the field plate 800 can further enable the strongest electric field to be close to the body when the device is reversely biased, so that the surface electric field is reduced, and further the reverse leakage current of the device is not increased.

In some embodiments, each doped silicon layer 210 is formed with a first well region 201 and each middle doped silicon layer 210 is formed with a second well region 202. Thus, the doped silicon layer 210 can be depleted to a greater extent during reverse bias, so that the strongest electric field is close to the body, and leakage current is reduced during reverse bias; and the on-resistance of the device is reduced to a greater extent.

In some embodiments, the second well region 202 spaced apart from the first well region 201 may be further formed in the top doped silicon layer 210, wherein for the lateral trench schottky barrier semiconductor structure, no additional capping process is required for the second well region 202 in the top doped silicon layer 210; for a vertical trench schottky barrier semiconductor structure, the second well region 202 in the top doped silicon layer 210 needs an additional capping process through a passivation layer to isolate the second well region 202 from the surface schottky contact metal and ensure that the potential of the trench conductive structure 600 floats. Optionally, in a direction perpendicular to the substrate 100, the plurality of second well regions 202 in the plurality of doped silicon layers 210 are coaxially arranged so as to etch the second trenches 400 in the same axial direction, respectively.

In some embodiments, the middle doped silicon layer 210 is at least two layers, and the middle doped silicon layers 210 of the multiple layers are stacked in sequence in a direction away from the substrate 100. Optionally, the second well region 202 and the first well region 201 of each middle doped silicon layer 210 are formed by implantation on the surface of the doped silicon layer 210; the first well region 201 of the top doped silicon layer 210 is formed by surface implantation of the doped silicon layer 210.

In some embodiments, please refer to fig. 7-8 (fig. 7-8 only show schematic views before the first trench 300 and the second trench 400 are not formed), the first well region 201 of the doped silicon layer 210 formed in advance is diffused into the adjacent doped silicon layer 210 formed in advance; the second well regions 202 of the previously formed doped silicon layer 210 each diffuse into the subsequently formed adjacent doped silicon layer 210. That is, based on the diffusion characteristic of the ion high temperature, the first well region 201 and the second well region 202 are further diffused to the side with high temperature after being formed, and each doped silicon layer 210 may have a certain high temperature process during the formation process. Thus, the second well region 202 and the first well region 201 of the previously formed doped silicon layer 210 will back-diffuse towards the adjacent subsequently formed doped silicon layer 210, whereby the second well region 202 and the first well region 201 will extend into the subsequently formed doped silicon layer 210. It can be appreciated that the depth and width of the second well region 202 and the first well region 201 can be increased by the high temperature during the preparation of the doped silicon layer 210 formed later, so that the resistance of the device can be further reduced and the leakage current in reverse bias can be further reduced without additional steps.

It should be noted that, during the formation of the doped silicon layer 210, the depth of extension of the second well region 202 and the first well region 201 of the previously formed doped silicon layer 210 may be controlled by controlling the temperature during the high temperature process; the junction depths of the second well region 202 and the first well region 201 formed by the surface implantation of the later-formed doped silicon layer 210 can be controlled in the subsequent step at the same time, so as to ensure that the first well region 201 formed in advance is spaced from the adjacent first well region 201 formed in later, and the second well region 202 formed in advance and the adjacent second well region 202 formed in later can be spaced from each other or can be connected into a whole in a diffusion manner.

In some embodiments, as shown in fig. 9 (fig. 9 illustrates a structure in which the first well region 201 and the second well region 202 undergo back diffusion, which is only illustrative and not limiting), only the sidewalls of the first trench 300 on the side close to the second trench 400 expose the plurality of first well regions 201, and only the sidewalls of the second trench 400 on the side close to the first trench 300 expose the plurality of second well regions 202. So that in the side of the first trench 300 near the second trench 400, the contact interface between the doped silicon layer 210 region between two adjacent first well regions 201 and the trench schottky contact metal 500 can create a current path to the cathode at that side, the current path increasing; in a side of the second trench 400 adjacent to the first trench 300, the region of the doped silicon layer 210 between two adjacent second well regions 202 is in contact with the trench conductive structure 600 to reduce the ohmic contact resistance of the device.

In some embodiments, as shown in fig. 10 (fig. 10 illustrates a structure in which the first well region 201 and the second well region 202 undergo back diffusion, which is only illustrative and not limiting), each first well region 201 exposed by the sidewall of the first trench 300 surrounds the sidewall of the first trench 300, and each second well region 202 exposed by the sidewall of the second trench 400 surrounds the sidewall of the second trench 400. Therefore, the doped silicon layer 210 region between two adjacent first well regions 201 also surrounds the first trench 300 and contacts the trench schottky contact metal 500, and the contact interface between the doped silicon layer 210 region and the trench schottky contact metal 500 can generate current paths flowing to the cathode to the periphery, so that the current paths are further increased; the region of doped silicon layer 210 between two adjacent second well regions 202 will also surround the second trench 400 and be in contact with the trench conductive structure 600 such that the device resistance is further reduced.

In some embodiments, the orthographic projections of the plurality of first well regions 201 distributed along the sidewalls of the first trench 300 coincide on the substrate 100, and the orthographic projections of the plurality of second well regions 202 distributed along the sidewalls of the second trench 400 coincide on the substrate 100. The orthographic projection is coincident, which means that the width dimensions and the positions of the plurality of well regions distributed along the same trench are the same, so that on one hand, the preparation process of forming each well region can be further simplified, and meanwhile, the second trench 400 and the first trench 300 are also conveniently opened at the positions corresponding to the well regions respectively.

In some embodiments, the number of the second trenches 400 and the number of the first trenches 300 are only one, so that one trench schottky barrier semiconductor structure is formed, and only one side wall of the first trench 300 is close to the second trench 400, so as shown in fig. 9, the first well region 201 may be distributed only on the side, and when the first trench 300 is etched, one side of the first well region 201 facing away from the second trench 400 may be completely etched; similarly, when etching the second trench 400, a side of the second well region 202 facing away from the first trench 300 may be completely etched away.

In some embodiments, the number of the second trenches 400 is at least two, the number of the first trenches 300 is at least one, and the second trenches 400 and the first trenches 300 are alternately arranged to form a plurality of trench schottky barrier semiconductor structures, at least two sides of the first trenches 300 are provided with corresponding second trenches 400, the at least two sides can be correspondingly distributed with the first well regions 201, and when the first trenches 300 are etched, only the first well regions 201 at two sides of the first trenches 300 can be reserved, or only the middle regions of the first well regions 201 are etched; similarly, when etching the second trench 400, only the second well region 202 on both sides of the second trench 400 may remain, or only the middle region of the second well region 202 may be etched away. It should be noted that, when the number of the second trenches 400 is two, the number of the first trenches 300 may be one, as shown in fig. 10.

It will be appreciated that the depth of the second well region 202 in the above embodiment may be the same as or different from the depth of the first well region 201, the width of the second well region 202, and the width of the first well region 201, the depth and width of the second well region 202 formed by surface implantation of the different doped silicon layers 210 may be the same as or different from each other, and likewise the depth and width of the first well region 201 formed by surface implantation of the different doped silicon layers 210 may be the same as or different from each other. Optionally, the depths and widths of the plurality of first well regions 201 formed by implanting on the surface of the different doped silicon layers 210 are respectively corresponding to the same, so that the same photolithography plate, the same implantation energy and implantation dosage can be adopted to form the first well regions 201 of the different doped silicon layers 210, so that the process is simple and easy to operate; the second well region 202 is similar. Optionally, the depth and width of the plurality of first well regions 201 formed by surface implantation of the different doped silicon layers 210 are different, so that each first well region 201 can be formed by using a different photolithography plate, different implantation energy and implantation dosage, so that each step has independent operability; the second well region 202 is similar.

In some embodiments, the first trench 300 extends into the doped silicon layer 210 adjacent to the substrate 100, the bottom wall of the first trench 300 exposing either the doped silicon layer 210 adjacent to the substrate 100 (as shown in fig. 11) or; or the first trench 300 extends to the upper surface of the doped silicon layer 210 adjacent to the substrate 100, and the bottom wall of the first trench 300 exposes the first well region 201 (as shown in fig. 10) in the doped silicon layer 210 adjacent to the substrate 100.

When the bottom wall of the first trench 300 exposes the doped silicon layer 210 adjacent to the substrate 100, the trench schottky contact metal 500 can also contact the doped silicon layer 210 region of the bottom wall of the first trench 300 to form a schottky contact, so that the current path can be further increased, and for a vertical trench schottky barrier semiconductor structure, the current path thereat can be greatly shortened.

In some embodiments, the second trench 400 extends into the doped silicon layer 210 adjacent to the substrate 100, the bottom wall of the second trench 400 exposing the doped silicon layer 210 adjacent to the substrate 100 (as shown in fig. 11) or exposing the second well region 202 in the doped silicon layer 210 adjacent to the substrate 100; optionally, the second trench 400 extends to an upper surface of the doped silicon layer 210 adjacent to the substrate 100, and a bottom wall of the second trench 400 exposes the second well region 202 (shown in fig. 10) in the doped silicon layer 210 adjacent to the substrate 100.

When the second trench 400 extends into the doped silicon layer 210 adjacent to the substrate 100, the bottom wall of the second trench 400 exposes the doped silicon layer 210 adjacent to the substrate 100, and the second trench 400 penetrates the second well region 202 in each doped silicon layer 210, so that the bottom wall of the second trench 400 is surrounded by the doped silicon layer 210 adjacent to the substrate 100, and only the second well regions 202 distributed on the sidewalls of the second trench 400 can reduce the device resistance. When the bottom wall of the second trench 400 exposes the second well region 202 in the doped silicon layer 210 adjacent to the substrate 100, the bottom wall of the second trench 400 is surrounded by the second well region 202, and the second well region 202 distributed on the side wall of the second trench 400 and the second well region 202 on the bottom wall of the second trench 400 can reduce the device resistance, so that the device resistance is further reduced.

In the above embodiment, the number of the doped silicon layers 210 and the thickness of the doped silicon layers 210 are not limited. The number of doped silicon layers 210 may be determined according to the amount of current required by the device, and may be 3-4 layers, for example; the thickness of the doped silicon layer 210 is only required to ensure that the adjacent two first well regions 201 can be spaced apart, so that the existence of the doped silicon layer 210 region between the adjacent two first well regions 201 in the direction perpendicular to the substrate 100 is ensured, and the schottky contact between the doped silicon layer 210 region and the trench schottky contact metal 500 is ensured. It is understood that the doped silicon layer 210 and the well region formed on each doped silicon layer 210 formed by stacking multiple layers in the present application may be understood as one doped silicon layer 210 and a plurality of well regions formed by surface implantation multiple times at intervals, and the implantation position, the implantation depth and the implantation width of each well region are controlled by controlling the implantation energy, the implantation temperature and the like of each surface implantation.

It should be noted that the materials for preparing the above layers are not limited, and conventional materials in the art may be used, for example, the trench schottky contact metal 500 may be a metal such as aluminum, titanium, tungsten, gold, or an alloy of the above metals that may form a schottky contact with the doped silicon layer 210.

Fig. 12 illustrates a method of fabricating a trench schottky barrier semiconductor structure according to an embodiment, including steps 101-106.

In step 101, a substrate of a first conductivity type is provided.

Step 102, forming a doped structure of a first conductivity type on a substrate, wherein the doped structure comprises a doped silicon layer arranged by stacking a plurality of layers, and the doped silicon layer is formed with a first well region of a second conductivity type, and the second conductivity type is opposite to the first conductivity type.

Step 103, first trenches penetrating through the plurality of first well regions are formed in the doped structure, so that the doped silicon layer and the first well regions are alternately exposed on the side walls of the first trenches along the depth direction of the first trenches.

Step 104, a second trench is formed in the doped structure and is spaced apart from the first trench and the plurality of first well regions.

And 105, filling the first groove with groove Schottky contact metal, and forming Schottky contact between the groove Schottky contact metal and the doped silicon layer exposed on the side wall of the first groove.

And 106, filling the second groove with the groove conductive structure.

The description of the substrate, the doped silicon layer, the first well region, the first trench, the second trench, the trench conductive structure and the trench schottky contact metal is assisted by the related description in the above embodiments, and will not be repeated here.

According to the preparation method provided by the embodiment, when the device is in reverse bias, two adjacent first well regions at one side of the groove Schottky contact metal can deplete the doped silicon layer between the two first well regions, so that the strongest electric field is close to the body, and leakage current is reduced when the device is in reverse bias. When the device is conducted in the forward direction, the schottky barrier is far lower than the PN junction barrier due to the arrangement of the groove schottky contact metal, so that the schottky diode can be firstly opened to form a plurality of current paths, compared with the prior SBD, the current paths are shortened, the number of the current paths is increased, and therefore the reverse leakage current of the groove schottky barrier semiconductor structure is not increased, and meanwhile the current capacity of the device is improved, and the on resistance is reduced. In addition, the number of the doped silicon layers between two adjacent first well regions at one side of the groove Schottky contact metal can be flexibly adjusted, and the current required by the groove Schottky barrier semiconductor structure can be flexibly met. .

In some embodiments, step 102 comprises: step 1021, forming a doped silicon layer on the substrate through epitaxial growth, forming a first well region on the doped silicon layer through first doping treatment on the upper surface layer of the doped silicon layer, and alternately forming a doped silicon layer through epitaxial growth and forming a first well region on the upper surface layer of the doped silicon layer through first doping treatment to form the doped silicon layer in a multi-layer laminated arrangement.

The first well region is formed in each of the successive multi-layer doped silicon layers by alternately forming a doped silicon layer by epitaxial growth and forming a first well region in an upper surface layer of the doped silicon layer by a first doping process.

Optionally, forming a doped silicon layer by epitaxial growth and forming a first well region on the upper surface layer of the doped silicon layer by first doping treatment, repeating for 3 to 4 times, forming three to four doped silicon layers on the basis of repeating for 3 to 4 times, and forming the first well region in each doped silicon layer at the same time, so as to shorten the preparation time, ensure that the thickness of the formed doped structure is moderate, and simultaneously ensure that the reverse leakage current is not increased when the trench schottky barrier semiconductor structure is reversely biased, but the current path can be increased when the trench schottky barrier semiconductor structure is positively conducted, and the current capacity is improved.

It will be appreciated that in other embodiments, the doped silicon layers and the first well regions may be formed in other alternating ways, for example, by alternating the formation of two doped silicon layers by epitaxial growth and the formation of the first well region on top of one doped silicon layer by a first doping process. In other embodiments, each doped silicon layer may also be formed in other ways, for example, in a silicon-silicon bonded manner.

In some embodiments, step 102 further comprises: and 1022, forming a second well region of the first conductivity type, which is spaced from the first well region, on the upper surface layer of the doped silicon layer through a second doping process, alternately forming a doped silicon layer through epitaxial growth and forming a second well region of the first conductivity type on the upper surface layer of the doped silicon layer through a second doping process, so as to form a doped silicon layer in a multi-layer stack arrangement, wherein the doped silicon layer in the multi-layer stack arrangement comprises a top doped silicon layer and a middle doped silicon layer positioned between the substrate and the top doped silicon layer, and the second well region is formed only in the middle doped silicon layer.

In some embodiments, step 104 further comprises: in step 1041, the second trench is located in the doped structure and penetrates through the plurality of second well regions, so that the doped silicon layer and the second well regions are alternately exposed at the sidewalls of the second trench along the depth direction of the second trench.

The alternately performing the formation of a doped silicon layer by epitaxial growth and the formation of a second well region on the upper surface layer of the doped silicon layer by the second doping process may be understood as forming a second well region in the doped silicon layer by the second doping process every time after the formation of a doped silicon layer by epitaxial growth, thereby forming a second well region in each of the successive multi-layer doped silicon layers.

It will be appreciated that in other embodiments, the doped silicon layers and the second well regions may be formed in other alternating ways, for example, by alternating the formation of two doped silicon layers by epitaxial growth and the formation of the second well region on top of one doped silicon layer by a second doping process.

The first well region, the second trench, the top doped silicon layer, the middle doped silicon layer, and the trench conductive structure are described in the above embodiments, and will not be described herein.

The first doping treatment may be doping implantation with ions of the second conductivity type to form a first well region having the second conductivity type; the second doping process may be a doping implantation with ions of the first conductivity type to form a second well region having the first conductivity type. When the first doping treatment and the second doping treatment are performed, the dose, the implantation angle and the implantation energy of each first well region and each second well region can be set according to actual process requirements. Optionally, under the condition of ensuring that two adjacent first well regions are arranged at intervals, a high-temperature push-well process can be performed under a certain atmosphere so as to enable the implanted ions to be diffused to the required depth, and the process temperature and the process time of the push-well process can be adjusted according to the actual process requirements.

In some embodiments, the first well region and the second well region are formed in each middle epitaxial layer doped silicon layer, so that the doped silicon layer can be depleted to a greater extent during reverse bias, the strongest electric field is close to the body, and leakage current is reduced during reverse bias; and the on-resistance of the device is reduced to a greater extent.

In some embodiments, during the formation of the later-formed doped silicon layer, the first well region and the second well region of the adjacent earlier-formed doped silicon layer diffuse toward the later-formed doped silicon layer to extend into the later-formed doped silicon layer. Therefore, the depth and the width of the second well region and the first well region can be increased in an auxiliary mode through the high temperature during preparation of the later-formed doped silicon layer, and accordingly the resistance of the device can be further reduced and leakage current during reverse bias can be further reduced on the basis that no additional steps are needed.

In some embodiments, the semiconductor structure is a lateral trench schottky barrier semiconductor structure, the trench conductive structure forms an ohmic contact with the doped silicon layer as an ohmic contact cathode; the trench schottky contact metal forms a schottky contact with the doped silicon layer as a schottky contact anode. As shown in fig. 13, the preparation method further includes: step 107 and step 108.

Step 107, forming anode metal electrically connected with the groove Schottky contact metal on the upper surface of the doped structure; and 108, forming cathode metal electrically connected with the trench conductive structure on the upper surface of the doped structure. The anode metal and the cathode metal are referred to for assistance in the description of the above embodiments, and are not described herein.

In some embodiments, the semiconductor structure is a vertical trench schottky barrier semiconductor structure, as shown in fig. 14, and the method further comprises: step 109-step 112.

In step 109, a passivation layer is formed to cover the trench conductive structure, and the potential of the trench conductive structure floats.

At step 110, a field plate is formed over the passivation layer, the field plate covering a portion of the passivation layer and extending over a portion of the upper surface of the top doped structure.

And 111, forming surface Schottky contact metal on the doped structure, wherein the surface Schottky contact metal covers the passivation layer, the field plate and the groove Schottky contact metal.

At step 112, a surface conductive structure is formed overlying a surface of the substrate facing away from the doped structure.

The passivation layer, the field plate, the surface schottky contact metal and the surface conductive structure are referred to in the above embodiments for assistance in description, and are not described herein.

It is to be understood that the forming process, the preparation material, etc. of the doped silicon layer, the first well region, the second well region, the first trench, the second trench, the trench conductive structure, the trench schottky contact metal, the passivation layer, the field plate, the surface schottky contact metal, the surface conductive structure, etc. in the above embodiment are not further limited in this embodiment, and all possible forming processes, preparation materials may be used.

It should be understood that, although the steps in the flowcharts of fig. 12-14 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in fig. 12-14 may include multiple steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor do the order in which the steps or stages are performed necessarily performed in sequence, but may be performed alternately or alternately with at least a portion of the steps or stages in other steps or other steps.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The foregoing examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.

Claims (13)

1. A trench schottky barrier semiconductor structure comprising:

a substrate of a first conductivity type;

a doped structure of a first conductivity type formed on the substrate, the doped structure comprising a plurality of doped silicon layers arranged in a stacked manner, wherein the doped silicon layers are formed with a first well region of a second conductivity type, and the second conductivity type is opposite to the first conductivity type in electrical property;

A first trench located in the doping structure and penetrating through the plurality of first well regions, so that the doped silicon layer and the first well regions are alternately exposed at the side wall of the first trench along the depth direction of the first trench;

the second grooves are positioned in the doping structure and are spaced from the first grooves and the plurality of first well regions;

the groove Schottky contact metal fills the first groove and forms Schottky contact with the doped silicon layer exposed on the side wall of the first groove;

and the groove conducting structure fills the second groove.

2. The semiconductor structure of claim 1, wherein the multi-layer stack of doped silicon layers comprises a top doped silicon layer and a middle doped silicon layer between the substrate and the top doped silicon layer, the middle doped silicon layer further forming a second well region of the first conductivity type spaced apart from the first well region;

the second trenches are located in the doped structure and penetrate through the plurality of second well regions, so that the doped silicon layers and the second well regions are alternately exposed on the side walls of the second trenches along the depth direction of the second trenches.

3. The semiconductor structure of claim 2, wherein the number of second trenches is at least two, the number of first trenches is at least one, and the second trenches and the first trenches are alternately arranged.

4. The semiconductor structure of claim 2, wherein each of the doped silicon layers is formed with the first well region and each of the middle doped silicon layers is formed with the second well region.

5. The semiconductor structure of claim 2, wherein the second trench extends into the doped silicon layer adjacent to the substrate, a bottom wall of the second trench exposing the doped silicon layer adjacent to the substrate or exposing the second well region of the doped silicon layer adjacent to the substrate; or,

the second trench extends to an upper surface of the doped silicon layer adjacent to the substrate, and a bottom wall of the second trench exposes the second well region of the doped silicon layer adjacent to the substrate.

6. The semiconductor structure of any of claims 1-5, wherein the first trench extends into the doped silicon layer adjacent to the substrate, a bottom wall of the first trench exposing the doped silicon layer adjacent to the substrate or exposing the first well region of the doped silicon layer adjacent to the substrate; or,

The first trench extends to an upper surface of the doped silicon layer adjacent to the substrate, and a bottom wall of the first trench exposes the first well region of the doped silicon layer adjacent to the substrate.

7. The semiconductor structure of any of claims 1-5, wherein the semiconductor structure is a lateral trench schottky barrier semiconductor structure, the semiconductor structure further comprising:

the anode metal is arranged on the upper surface of the doping structure and is electrically connected with the groove Schottky contact metal;

and the cathode metal is arranged on the upper surface of the doping structure and is electrically connected with the groove conducting structure.

8. The semiconductor structure of any of claims 1-5, wherein the semiconductor structure is a vertical trench schottky barrier semiconductor structure, the semiconductor structure further comprising:

a passivation layer covering the trench conductive structure, wherein the potential of the trench conductive structure floats;

a field plate covering a part of the passivation layer and extending to cover a part of the upper surface of the doped structure;

the surface Schottky contact metal is positioned on the doping structure and covers the passivation layer, the field plate and the groove Schottky contact metal;

And the surface conductive structure covers the surface of the substrate, which is away from the doping structure.

9. A method for fabricating a trench schottky barrier semiconductor structure, comprising:

providing a substrate of a first conductivity type;

forming a doped structure of a first conductivity type on the substrate, wherein the doped structure comprises a doped silicon layer which is formed by stacking a plurality of layers, and a first well region of a second conductivity type is formed on the doped silicon layer, and the second conductivity type is opposite to the first conductivity type in electrical property;

a first groove penetrating through a plurality of first well regions is formed in the doping structure, so that the doped silicon layer and the first well regions are alternately exposed on the side wall of the first groove along the depth direction of the first groove;

forming a second groove which is separated from the first groove and the plurality of first well regions in the doping structure;

filling a groove Schottky contact metal in the first groove, wherein the groove Schottky contact metal forms Schottky contact with the doped silicon layer exposed on the side wall of the first groove;

and filling the second groove with a groove conducting structure.

10. The method of manufacturing of claim 9, wherein forming a doped structure of a first conductivity type on the substrate, the doped structure comprising a doped silicon layer disposed in a multi-layer stack, the doped silicon layer formed with a first well region of a second conductivity type, comprises:

Forming a doped silicon layer on the substrate through epitaxial growth, forming a first well region on the doped silicon layer through first doping treatment on the upper surface layer of the doped silicon layer, and alternately performing epitaxial growth to form the doped silicon layer and first well region on the upper surface layer of the doped silicon layer through first doping treatment to form the doped silicon layer arranged in the multilayer stack.

11. The method of manufacturing of claim 9, wherein forming a doped structure of a first conductivity type on the substrate, the doped structure comprising a doped silicon layer disposed in a multi-layer stack, the doped silicon layer formed with a first well region of a second conductivity type, further comprises:

forming a second well region of a first conductivity type spaced from the first well region on the upper surface layer of the doped silicon layer by a second doping process, alternately performing the forming of the doped silicon layer by epitaxial growth and the forming of the second well region of the first conductivity type on the upper surface layer of the doped silicon layer by the second doping process to form a doped silicon layer in a multi-layer stack arrangement, wherein the doped silicon layer in the multi-layer stack arrangement comprises a top doped silicon layer and a middle doped silicon layer located between the substrate and the top doped silicon layer, and the second well region is formed only in the middle doped silicon layer;

The forming of the second trenches in the doped structure, which are spaced from the first trenches and the plurality of first well regions, further includes:

the second trenches are located in the doped structure and penetrate through the plurality of second well regions, so that the doped silicon layers and the second well regions are alternately exposed at the side walls of the second trenches along the depth direction of the second trenches.

12. The method of claim 11, wherein each of the middle doped silicon layers is formed with the first well region and the second well region.

13. The method of any one of claims 9-12, wherein the method further comprises:

forming a passivation layer to cover the trench conductive structure, wherein the potential of the trench conductive structure floats;

forming a field plate on the passivation layer, wherein the field plate covers part of the passivation layer and extends to cover part of the upper surface of the doping structure;

forming surface schottky contact metal on the doped structure, wherein the surface schottky contact metal covers the passivation layer, the field plate and the trench schottky contact metal;

and forming a surface conductive structure to cover the surface of the substrate, which is away from the doping structure.