CN117438420A

CN117438420A - Semiconductor device and method of forming the same

Info

Publication number: CN117438420A
Application number: CN202311009778.4A
Authority: CN
Inventors: 许家豪; 洪建玮; 丁国强; 叶松峯
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-09-07
Filing date: 2023-08-11
Publication date: 2024-01-23

Abstract

Die structures and methods of forming the same are described. In an embodiment, a device includes: a lower integrated circuit die; a first upper integrated circuit die surface-to-surface bonded to the lower integrated circuit die, the first upper integrated circuit die comprising a first semiconductor substrate and a first substrate via; a gap fill dielectric located around the first upper integrated circuit die, a top surface of the gap fill dielectric being substantially coplanar with a top surface of the first semiconductor substrate and substantially coplanar with a top surface of the first substrate via; and an interconnect structure including a first dielectric layer disposed on the top surface of the gap-fill dielectric and the top surface of the first semiconductor substrate and a first conductive via extending through the first dielectric layer to contact the top surface of the first substrate via. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Description

Semiconductor device and method of forming the same

Technical Field

Embodiments of the present application relate to semiconductor devices and methods of forming the same.

Background

The semiconductor industry has experienced rapid growth due to the ever increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, the increase in integration density results from an iterative decrease in the minimum feature size, which allows more elements to be integrated into a given area. As the demand for shrinking electronic devices increases, there is a need for smaller and more innovative semiconductor die packaging techniques.

Disclosure of Invention

Some embodiments of the present application provide a semiconductor device including: a lower integrated circuit die; a first upper integrated circuit die surface-to-surface bonded to the lower integrated circuit die, the first upper integrated circuit die comprising a first semiconductor substrate and a first substrate via; a gap-fill dielectric located around the first upper integrated circuit die, a top surface of the gap-fill dielectric being substantially coplanar with a top surface of the first semiconductor substrate and substantially coplanar with a top surface of the first substrate via; and an interconnect structure including a first dielectric layer disposed on the top surface of the gap-fill dielectric and the top surface of the first semiconductor substrate and a first conductive via extending through the first dielectric layer to contact the top surface of the first substrate via.

Other embodiments of the present application provide a semiconductor device comprising: a lower integrated circuit die; an upper integrated circuit die surface-to-surface bonded to the lower integrated circuit die, the upper integrated circuit die comprising a semiconductor substrate and a substrate via protruding from a surface of the semiconductor substrate; a dielectric member located around the upper integrated circuit die, the dielectric member comprising: a first nitride liner on sidewalls of the upper integrated circuit die; an oxide liner on the first nitride liner; a second nitride liner on the oxide liner, a top surface of the second nitride liner disposed below the surface of the semiconductor substrate; and an oxide liner on the second nitride liner, wherein a top surface of the oxide liner, and a top surface of the first nitride liner are disposed over the surface of the semiconductor substrate.

Still further embodiments of the present application provide a method of forming a semiconductor device, comprising: bonding a first front side of a first integrated circuit die to a second front side of a second integrated circuit die, the first integrated circuit die comprising a semiconductor substrate and a through substrate via; forming a gap fill dielectric on the first integrated circuit die and on the second integrated circuit die; planarizing the gap-fill dielectric until the gap-fill dielectric, the semiconductor substrate, and the substrate via have substantially coplanar top surfaces; depositing a first dielectric layer on the gap-fill dielectric, the semiconductor substrate, and the top surface of the substrate via; and forming a conductive via in the first dielectric layer, the conductive via extending through the first dielectric layer to contact the top surface of the substrate via.

Drawings

The various aspects of the disclosure are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a cross-sectional view of an integrated circuit die.

Fig. 2-11 are cross-sectional views at intermediate stages in the fabrication of a die structure, according to some embodiments.

Fig. 12-14 are cross-sectional views of die structures according to some embodiments.

Fig. 15-17 are cross-sectional views at intermediate stages in the fabrication of a die structure, according to some embodiments.

Fig. 18-20 are cross-sectional views of die structures according to some embodiments.

Fig. 21-26 are cross-sectional views at intermediate stages in the fabrication of a die structure, according to some embodiments.

Fig. 27-30 are cross-sectional views of die structures according to some embodiments.

Fig. 31-35 are cross-sectional views of die structures according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the present disclosure. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as "under …," "under …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

According to various embodiments, a die structure is formed by bonding integrated circuit dies in a face-to-face manner. The upper integrated circuit die of the die structure includes a semiconductor substrate and Through Substrate Vias (TSVs), and the backside interconnect structure for the die structure is electrically coupled to the integrated circuit die through the TSVs. The backside interconnect structure includes an additional conductive via layer in contact with the TSV. The use of an additional conductive via layer may avoid the process for recessing the semiconductor substrate of the upper integrated circuit die. Omitting recessing the semiconductor substrate may help reduce pinhole defects in the die structure.

Fig. 1 is a cross-sectional view of an integrated circuit die 50. The integrated circuit die 50 will be bonded to other dies in subsequent processing to form a die structure. The integrated circuit die 50 may be a logic die (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a system on a chip (SoC), an Application Processor (AP), a microcontroller, etc.), a memory die (e.g., a Dynamic Random Access Memory (DRAM) die, a Static Random Access Memory (SRAM) die, etc.), a power management die (e.g., a Power Management Integrated Circuit (PMIC) die), a Radio Frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a Digital Signal Processing (DSP) die), a front end die (e.g., an Analog Front End (AFE) die), etc., or a combination thereof.

The integrated circuit die 50 may be formed in a wafer that may include different device regions that are singulated in subsequent steps to form a plurality of integrated circuit die. The integrated circuit die 50 may be processed according to applicable manufacturing processes to form an integrated circuit. For example, the integrated circuit die 50 includes an active layer of a semiconductor substrate 52 (such as silicon, doped or undoped) or a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 52 may comprise other semiconductor materials such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor comprising SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP and/or GaInAsP; or a combination thereof. Other substrates, such as multi-layer or gradient substrates, may also be used. The semiconductor substrate 52 has an active surface (e.g., the surface facing upward in fig. 1), sometimes referred to as the front side, and a non-active surface (e.g., the surface facing downward in fig. 1), sometimes referred to as the back side.

Devices (not separately shown) are provided at the active surface of the semiconductor substrate 52. The devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. Interconnect structure 54 is disposed over the active surface of semiconductor substrate 52. Interconnect structures 54 interconnect devices of semiconductor substrate 52 to form an integrated circuit. Interconnect structure 54 may be formed from, for example, metallization pattern 56 in dielectric layer 58. Dielectric layer 58 may be, for example, a low-k dielectric layer 58. The metallization pattern 56 includes metal lines and vias that may be formed in the dielectric layer 58 by a damascene process, such as a single damascene process, a dual damascene process, or the like. The metallization pattern 56 may be formed of a suitable conductive material such as copper, tungsten, aluminum, silver, gold, combinations thereof, and the like, which may be formed by, for example, plating or the like. The metallization pattern 56 is electrically coupled to the devices of the semiconductor substrate 52.

Optionally, conductive vias 60 extend into interconnect structure 54 and/or semiconductor substrate 52. The conductive vias 60 are electrically coupled to the metallization pattern 56 of the interconnect structure 54. As an example of forming the conductive vias 60, recesses may be formed in the interconnect structure 54 and/or the semiconductor substrate 52 by, for example, etching, milling, laser techniques, combinations thereof, and the like. The thin barrier layer may be conformally deposited in the grooves, such as by Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), thermal oxidation, combinations thereof, and the like. The barrier layer may be formed of an oxide, nitride, combinations thereof, or the like. A conductive material may be deposited over the barrier layer and in the recess. The conductive material may be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, or the like. Examples of conductive materials include copper, tungsten, aluminum, silver, gold, combinations thereof, and the like. Excess conductive material and barrier layer are removed from the surface of interconnect structure 54 or semiconductor substrate 52 by, for example, chemical Mechanical Polishing (CMP). The barrier layer and the remaining portion of the conductive material in the recess form a conductive via 60. After its initial formation, the conductive via 60 may be buried in the semiconductor substrate 52. Semiconductor substrate 52 may be thinned in subsequent processing to expose conductive vias 60 at the non-active surface of semiconductor substrate 52. After the exposure process, the conductive vias 60 are through-substrate vias (TSVs), such as through-silicon vias, that extend through the semiconductor substrate 52.

In this embodiment, the conductive via 60 is formed by a medium via process such that the conductive via 60 extends through a portion of the interconnect structure 54 (e.g., a subset of the dielectric layer 58) and into the semiconductor substrate 52. Conductive vias 60 formed by the medium via process are connected to the medium metallization pattern 56 of the interconnect structure 54. In another embodiment, the conductive via 60 is formed by a via-first process such that the conductive via 60 extends into the semiconductor substrate 52 but not into the interconnect structure 54. Conductive vias 60 formed by a via-first process are connected to the lower metallization pattern 56 of the interconnect structure 54. In yet another embodiment, the conductive via 60 is formed by a post via process such that the conductive via 60 extends through the entire interconnect structure 54 (e.g., each of the dielectric layers 58) and into the semiconductor substrate 52. Conductive vias 60 formed by a post via process are connected to the upper metallization pattern 56 of the interconnect structure 54.

Dielectric layer 62 is located over interconnect structure 54 at the front side of integrated circuit die 50. The dielectric layer 62 may be formed of: oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), tetraethylorthosilicate (TEOS) -based oxides, and the like; nitrides, such as silicon nitride and the like; polymers such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB) based polymers, and the like; combinations thereof; etc. The dielectric layer 62 may be formed, for example, by CVD, spin coating, lamination, or the like. In some embodiments, dielectric layer 62 is formed from TEOS-based silicon oxide. Optionally, one or more passivation layers (not separately shown) are disposed between dielectric layer 62 and interconnect structure 54.

Die attach 64 extends through dielectric layer 62. The die connectors 64 may include conductive posts, pads, etc. that may make external connections. In some embodiments, die connectors 64 include bond pads at the front side of integrated circuit die 50 and include bond pad vias that connect the bond pads to upper metallization pattern 56 of interconnect structure 54. In such embodiments, the die connectors 64 (including the bond pads and bond pad vias) may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like. The die connectors 64 may be formed of a suitable conductive material, such as copper, tungsten, aluminum, silver, gold, combinations thereof, and the like, which may be formed by, for example, plating, and the like.

Optionally, during formation of the integrated circuit die 50, solder regions (not separately shown) may be formed on the die connectors 64. The solder regions may be used to perform Chip Probe (CP) testing on the integrated circuit die 50. For example, the solder regions may be solder balls, solder bumps, or the like, which are used to attach the chip probes to the die connectors 64. Chip probing tests may be performed on the integrated circuit die 50 to determine if the integrated circuit die 50 is a Known Good Die (KGD). Thus, only the integrated circuit die 50, which is KGD, is subjected to subsequent processing, and then no die that fails the chip probe test is processed. After testing, the solder areas may be removed. In some embodiments, a planarization process is utilized, such as a Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, and the like.

In some embodiments, integrated circuit die 50 is a stacked device that includes a plurality of semiconductor substrates 52. For example, the integrated circuit die 50 may be a memory device including a plurality of memory dies, such as a hybrid memory multi-dimensional dataset (HMC) device, a High Bandwidth Memory (HBM) device, or the like. In such an embodiment, the integrated circuit die 50 includes a plurality of semiconductor substrates 52 interconnected by TSVs. Each of the semiconductor substrates 52 may (or may not) have a separate interconnect structure 54.

Fig. 2-11 are cross-sectional views at intermediate stages in the fabrication of a die structure 100 according to some embodiments. The die structure 100 is a stack of integrated circuit dies 50 (including a lower integrated circuit die 50A and an upper integrated circuit die 50B). The die structure 100 will be formed by bonding the upper integrated circuit die 50B to a wafer 102 that includes the lower integrated circuit die 50A. One upper integrated circuit die 50B is shown in one device region 102D of the bonding wafer 102, but it should be understood that the wafer 102 may have any number of device regions and that any number of upper integrated circuit die 50B may be bonded in each device region. The device region 102D will be singulated to form the die structure 100.

The die structure 100 is a component that may be subsequently packaged to form an integrated circuit package. The integrated circuit die 50 of the die structure 100 may be a heterogeneous die. Packaging the die structure 100 instead of individually packaging the dies may allow heterogeneous dies to be integrated with smaller footprints. The die structure 100 may be an integrated system-on-chip (SoIC) device, but other types of devices may be formed.

In fig. 2, a wafer 102 is obtained. Wafer 102 includes lower integrated circuit die 50A in device region 102D, which device region 102D will be singulated in subsequent processing for inclusion in die structure 100. The lower integrated circuit die 50A has a similar structure to that described with respect to fig. 1, except that the lower integrated circuit die 50A does not include conductive vias that extend into the semiconductor substrate 52A of the lower integrated circuit die 50A. In some embodiments, the lower integrated circuit die 50A is a logic die (previously described).

In fig. 3, an upper integrated circuit die 50B is attached to a lower integrated circuit die 50A (e.g., to wafer 102). The upper integrated circuit die 50B has a similar structure to that described with respect to fig. 1. In some embodiments, upper integrated circuit die 50B is a memory die, a power management die, or the like (previously described). The functionality of the upper integrated circuit die 50B may (or may not) be different from the functionality of the lower integrated circuit die 50A. The lower integrated circuit die 50A and the upper integrated circuit die 50B may be formed in the process of the same technology node or may be formed in the process of different technology nodes. For example, the lower integrated circuit die 50A may be an advanced process node than the upper integrated circuit die 50B. The lower integrated circuit die 50A is wider than the upper integrated circuit die 50B.

The upper integrated circuit die 50B may be attached to the lower integrated circuit die 50A by placing the upper integrated circuit die 50B on the lower integrated circuit die 50A (e.g., on the wafer 102) and then bonding the upper integrated circuit die 50B to the lower integrated circuit die 50A. The upper integrated circuit die 50B may be placed by, for example, a pick and place process. The bonding process may include fusion bonding, dielectric bonding, metal bonding, combinations thereof (e.g., combinations of dielectric-to-dielectric bonding and metal-to-metal bonding), and the like. As an example of a bonding process, the upper integrated circuit die 50B may be bonded to the lower integrated circuit die 50A by a combination of dielectric-to-dielectric bonding and metal-to-metal bonding. The dielectric layer 62B of the upper integrated circuit die 50B is directly bonded to the dielectric layer 62A of the lower integrated circuit die 50A by a dielectric-to-dielectric bond without the use of any adhesive material (e.g., die attach film). The die connectors 64B of the upper integrated circuit die 50B are directly bonded to the corresponding die connectors 64A of the lower integrated circuit die 50A by metal-to-metal bonding without the use of any eutectic material (e.g., solder). Bonding may include pre-bonding and annealing. During pre-bonding, less pressure is applied to press upper integrated circuit die 50B (e.g., dielectric layer 62B) against lower integrated circuit die 50A (e.g., dielectric layer 62A). The pre-bonding is performed at a low temperature, such as about room temperature, and after the pre-bonding, the dielectric layer 62A is bonded to the dielectric layer 62B. The bond strength is then increased in a subsequent annealing process in which the dielectric layers 62A, 62B and die connectors 64A, 64B are annealed. After annealing, a direct bond, such as a fusion bond, is formed, bonding dielectric layer 62A to dielectric layer 62B. For example, the bond may be a covalent bond between the material of dielectric layer 62A and the material of dielectric layer 62B. Die connectors 64A are connected to die connectors 64B in a one-to-one correspondence. The die connectors 64A and 64B may be in physical contact after pre-bonding or may be expanded to be in physical contact during annealing. Furthermore, during annealing, the materials (e.g., copper) of die attach 64A and die attach 64B mix, thereby also forming a metal-to-metal bond. Thus, the resulting bond between the lower integrated circuit die 50A and the upper integrated circuit die 50B includes a dielectric-to-dielectric bond and a metal-to-metal bond.

The upper integrated circuit die 50B is attached to the lower integrated circuit die 50A in a face-to-face manner. In some embodiments, upper integrated circuit die 50B is bonded face-to-face to lower integrated circuit die 50A. Thus, the front side of the lower integrated circuit die 50A faces the front side of the upper integrated circuit die 50B. The backside of the lower integrated circuit die 50A faces away from the backside of the upper integrated circuit die 50B.

The semiconductor substrate 52B of the upper integrated circuit die 50B is optionally thinned, which may help reduce the overall thickness of the die structure 100. The thinning process may be, for example, a Chemical Mechanical Polishing (CMP), grinding process, etchback process, etc., which is performed at the backside of the upper integrated circuit die 50B. The thinning process reduces the thickness of the semiconductor substrate 52B. After this thinning process, the conductive vias 60B of the upper integrated circuit die 50B remain buried by the semiconductor substrate 52B. Thinning semiconductor substrate 52B during this processing step may help reduce the cost of exposing conductive vias 60B during subsequent processing steps.

In fig. 4, gap filler medium 106 is formed around upper integrated circuit die 50B and on lower integrated circuit die 50A. Initially, the gap fill dielectric 106 may be formed over the upper integrated circuit die 50B and the lower integrated circuit die 50A such that the gap fill dielectric 106 buries in or covers the upper integrated circuit die 50B. Thus, the top surface of the gap-fill dielectric 106 may initially be located above the top surface of the upper integrated circuit die 50B. Gap filler medium 106 is disposed over a portion of lower integrated circuit die 50A adjacent to upper integrated circuit die 50B (e.g., wafer 102) and may contact the top surface of lower integrated circuit die 50A. The gap fill dielectric 106 is a dielectric filler (or dielectric component) that fills (and may overfill) the gap between the upper integrated circuit die 50B and the upper integrated circuit die 50B in other device regions (not separately shown). The gap fill dielectric 106 may be formed of one or more dielectric materials. Acceptable gap fill dielectric materials include oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), tetraethylorthosilicate (TEOS) based oxides, and the like; nitrides such as silicon nitride and the like; combinations thereof; etc., which may be formed by a suitable deposition process, such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), etc.

In some embodiments, the gap-fill dielectric 106 is multi-layered, including one or more liner layers and a main layer. In this embodiment, the gap-fill dielectric 106 includes a first liner 106A, a second liner 106B, a third liner 106C, and a main filler 106D. The gap fill dielectric 106 may have a nitride-oxide-nitride-oxide (NONO) structure, wherein the first liner 106A and the third liner 106C are formed of nitride (previously described), and wherein the second liner 106B and the main fill 106D are formed of oxide (previously described). For example, the first liner 106A and the third liner 106C may be nitride liners formed of silicon nitride, the second liner 106B may be oxide liners formed of silicon oxide, and the main filler 106D may be oxide filler formed of silicon oxide. The use of the NONO structure may reduce the risk of damaging the integrated circuit die 50 when forming the gap-fill dielectric 106. For example, when forming a NONO structure, cracking of the gap fill dielectric 106 along the edges of the upper integrated circuit die 50B may be avoided.

In fig. 5, portions of gap fill dielectric 106 that overlie upper integrated circuit die 50B may optionally be removed to form openings 108. The portion of the gap fill dielectric 106 that is located over the upper integrated circuit die 50B may be removed by suitable photolithography and etching techniques. The opening 108 may expose the backside of the upper integrated circuit die 50B. Removing portions of the gap-fill dielectric 106 by etching may reduce pattern loading effects during subsequent processes for planarizing the gap-fill dielectric 106.

In fig. 6, a removal process is performed to bring the surface of the gap-fill dielectric 106 flush with the backside of the upper integrated circuit die 50B (e.g., the non-active surface of the semiconductor substrate 52B). The remaining portion of gap fill dielectric 106 that is located over upper integrated circuit die 50B is removed. In some embodiments, a planarization process is utilized, such as a Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, and the like.

In addition, the semiconductor substrate 52B is thinned to expose the conductive via 60B. Portions of the gap fill dielectric 106 may also be removed by a thinning process. The thinning process may be, for example, a Chemical Mechanical Polishing (CMP), grinding process, etch back process, etc., or a combination thereof, which is performed at the back side of the integrated circuit die 50B. The planarization process may be performed until the gap-fill dielectric 106 and the top surface of the upper integrated circuit die 50B (including the surfaces of the semiconductor substrate 52B and the conductive vias 60B) are substantially coplanar (within process variations). The thinning process for semiconductor substrate 52B may (or may not) be different from the removal process for gap-fill dielectric 106. After the exposure process, conductive via 60B is a through-substrate via (TSV) that extends through semiconductor substrate 52B.

As described later with respect to fig. 7-9, backside interconnect structures 110 (see fig. 9) will be formed on the gap-fill dielectric 106 and the coplanar top surface of the upper integrated circuit die 50B. The backside interconnect structure 110 includes a dielectric layer and conductive features in the dielectric layer. The conductive features are interconnects of devices electrically coupled to the integrated circuit die 50 (including the lower integrated circuit die 50A and the upper integrated circuit die 50B). Specifically, the conductive features of the backside interconnect structure 110 are coupled to the integrated circuit die 50 through conductive vias 60B.

The lower portion 110A (e.g., a portion of a small feature) of the backside interconnect structure 110 will be formed by a single damascene process. The upper portion 110B (e.g., a portion of a large feature) of the backside interconnect structure 110 will be formed by a dual damascene process. The conductive features of the lower portion 110A of the backside interconnect structure 110 are smaller than the conductive features of the upper portion 110B of the backside interconnect structure 110.

In fig. 7, a dielectric layer 112 is formed over the gap-fill dielectric 106 and the coplanar top surface of the upper integrated circuit die 50B. The dielectric layer 112 may be formed of a dielectric material. Acceptable dielectric materials include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), and the like, which may be formed by CVD, ALD, and the like. Dielectric layer 112 may be formed of a low-k dielectric material having a k value of less than about 3.0. Dielectric layer 112 may be formed of an ultra low k (ELK) dielectric material having a k value less than 2.5.

Conductive vias 114 are formed in the dielectric layer 112. Conductive via 114 extends through dielectric layer 112 to contact conductive via 60B. The conductive via 114 may be formed by a damascene process, in particular, a single damascene process. As an example of forming the conductive via 114, the dielectric layer 112 is patterned using photolithography and etching techniques to form an opening corresponding to a desired pattern of the conductive via 114. The openings may then be filled with a conductive material. Suitable conductive materials include copper, silver, gold, tungsten, aluminum, combinations thereof, and the like, which may be formed by electroplating or the like. A removal process may be performed to remove excess conductive material from the surface of the dielectric layer 112. In some embodiments, a planarization process is utilized, such as a Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, and the like. The remaining conductive material forms a conductive via 114 in the opening.

A plurality of conductive vias 114 are electrically and physically coupled to each conductive via 60B. Each conductive via 114 is smaller (e.g., narrower) than the underlying conductive via 60B. More specifically, the critical dimension (e.g., width) of conductive via 114 is less than the critical dimension (e.g., width) of conductive via 60B. In some embodiments, the critical dimension of conductive via 114 is in the range of 0.2 μm to 2 μm and the critical dimension of conductive via 60B is in the range of 1 μm to 5 μm. In some embodiments, the width of each conductive via 114 is less than half the width of the underlying conductive via 60B. Forming conductive via 114 smaller than conductive via 60B helps to reduce the risk of conductive via 114 contacting semiconductor substrate 52B. Thus, the conductive via 114 is spaced apart from the semiconductor substrate 52B by the dielectric material.

Instead of recessing semiconductor substrate 52B, conductive via 114 is formed over conductive via 60B such that conductive via 60B protrudes from the non-active surface of semiconductor substrate 52B. Accordingly, vertical connection to the upper wiring can be achieved without recessing the semiconductor substrate 52B. When the gap-fill dielectric 106 has a nitride-oxide-nitride-oxide structure, omitting recessing the semiconductor substrate 52B may avoid etching the first liner 106A and the third liner 106C (e.g., nitride), thereby reducing pinhole defects in the die structure 100. Reducing pinhole defects may improve the yield and reliability of the die structure 100.

In fig. 8, a dielectric layer 116 is formed over the conductive via 114 and the dielectric layer 112. The dielectric layer 116 may be formed of a dielectric material. Acceptable dielectric materials include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), and the like, which may be formed by CVD, ALD, and the like. Dielectric layer 116 may be formed of a low-k dielectric material having a k value of less than about 3.0. Dielectric layer 116 may be formed of an ultra low k (ELK) dielectric material having a k value less than 2.5.

Conductive lines 118 are formed in the dielectric layer 116. The conductive line 118 extends through the dielectric layer 116 to contact the conductive via 114 and along the dielectric layer 112. The conductive line 118 may be formed by a damascene process, in particular, a single damascene process. As an example of forming the conductive lines 118, the dielectric layer 116 is patterned using photolithography and etching techniques to form openings corresponding to the desired pattern of the conductive lines 118. The openings may then be filled with a conductive material. Suitable conductive materials include copper, silver, gold, tungsten, aluminum, combinations thereof, and the like, which may be formed by electroplating or the like. A removal process may be performed to remove excess conductive material from the surface of the dielectric layer 116. In some embodiments, a planarization process is utilized, such as a Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, and the like. The remaining conductive material forms a conductive line 118 in the opening.

In fig. 9, a dielectric layer 128 is formed over the conductive line 118 and the dielectric layer 116. The dielectric layer 128 may be formed of a dielectric material. Acceptable dielectric materials include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), and the like, which may be formed by CVD, ALD, and the like. Dielectric layer 128 may be formed of a low-k dielectric material having a k value of less than about 3.0. The dielectric layer 128 may be formed of an ultra low k (ELK) dielectric material having a k value less than 2.5.

Conductive features 130 are formed in the dielectric layer 128. The conductive features 130 may include conductive lines and vias in the dielectric layer 128, wherein each combination of conductive vias and overlying conductive lines extend through the dielectric layer 128. Conductive feature 130 extends through dielectric layer 128 to contact wire 118. The conductive feature 130 may be formed by a damascene process, in particular, a dual damascene process. As an example of forming the conductive feature 130, the dielectric layer 128 is patterned using photolithography and etching techniques to form interconnect openings (including trenches and via openings) corresponding to the desired pattern of the conductive feature 130. The interconnect openings may then be filled with a conductive material. Suitable conductive materials include copper, silver, gold, tungsten, aluminum, combinations thereof, and the like, which may be formed by electroplating or the like. A removal process may be performed to remove excess conductive material from the surface of the dielectric layer 128. In some embodiments, a planarization process is utilized, such as a Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, and the like. The remaining conductive material forms conductive features 130 in the interconnect openings.

The backside interconnect structure 110 may include any desired number of conductive feature layers. In this embodiment, the lower portion 110A of the backside interconnect structure 110 includes one of the dielectric layers 112, 116 and a via layer (e.g., conductive via 114 and conductive line 118). Similarly, the upper portion 110B of the backside interconnect structure 110 includes one wire and via layer (e.g., conductive feature 130) in the dielectric layer 128. In another embodiment (described later with respect to fig. 12), the lower portion 110A and/or the upper portion 110B of the backside interconnect structure 110 includes a plurality of conductive lines and via layers.

As previously noted, the conductive features of the lower portion 110A of the backside interconnect structure 110 are formed by a single damascene process, while the conductive features of the upper portion 110B of the backside interconnect structure 110 are formed by a dual damascene process. Forming the conductive via 114 using a single damascene process may increase the accuracy of the conductive via 114 that falls on the conductive via 60B. The use of a dual damascene process to form conductive feature 130 may reduce manufacturing costs. Other variations are also contemplated. In another embodiment, the lower portion 110A and the upper portion 110B of the backside interconnect structure 110 are both formed by a dual damascene process.

In fig. 10, one or more passivation layers 132 are formed on the backside interconnect structure 110. The passivation layer 132 may be formed of: one or more suitable dielectric materials such as silicon oxynitride, silicon nitride, low-k dielectrics such as carbon-doped oxides, very low-k dielectrics such as porous carbon-doped silicon oxide, and the like; polymers such as polyimide, solder resist, polybenzoxazole (PBO), benzocyclobutene (BCB) based polymers, molding compounds, and the like; combinations thereof; etc. The passivation layer 132 may be formed by CVD, spin coating, lamination, or the like or a combination thereof.

Conductive pads 134 are formed that extend through passivation layer 132 to electrically and physically couple to upper conductive features 130 of backside interconnect structure 110. The conductive pads 134 may be formed by a damascene process, such as a single damascene process. The conductive pads 134 may be formed of a suitable conductive material, such as copper, tungsten, aluminum, silver, gold, combinations thereof, and the like, which may be formed by, for example, plating, and the like. In some embodiments, the conductive pads 134 are formed of a low cost conductive material (e.g., aluminum).

A dielectric layer 136 is formed over the conductive pad 134 and the passivation layer 132. The dielectric layer 136 may bury or cover the conductive pads 134. The dielectric layer 136 may be formed of: polymers such as PBO, polyimide, BCB-based polymers, and the like; nitrides, such as silicon nitride and the like; oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), tetraethylorthosilicate (TEOS) based oxides; etc., or a combination thereof. The dielectric layer 136 may be formed, for example, by spin coating, lamination, CVD, or the like.

In fig. 11, a dicing process is performed along scribe line regions, for example, between the device region 102D and an adjacent device region (not separately shown). The singulation process may include performing a sawing process, a laser dicing process, etc. on the wafer 102, gap-fill dielectric 106, backside interconnect structures 110, passivation layer 132, and dielectric layer 136. The singulation process separates the device region 102D (including the lower integrated circuit die 50A) from adjacent device regions of the wafer 102. The resulting singulated die structure 100 is from the device region 102D. After the singulation process, the lower integrated circuit die 50A, the gap-fill dielectric 106, the backside interconnect structure 110, the passivation layer 132, and the dielectric layer 136 are laterally co-terminated.

The die structure 100 is a component that may be subsequently implemented in an integrated circuit package. The integrated circuit die 50 of the die structure 100 may be a heterogeneous die. Packaging the die structure 100 instead of or in addition to individually packaging the die may allow heterogeneous dies to be integrated with smaller footprints. In some embodiments, the integrated circuit package is formed by encapsulating the die structure 100 and forming redistribution lines on the encapsulant to fan out the connections from the die structure 100. In some embodiments, the integrated circuit package is formed by attaching the die structure 100 to additional components such as an interposer, a package substrate, and the like.

The die structure 100 may include additional features for attaching the die structure 100 to additional components. In this embodiment, the die structure 100 further includes one or more dielectric layers 142, die connectors 144, and conductive connectors 146. Conductive connections 146 may be used to connect the die structure 100 (e.g., die connections 144) to additional components. The dielectric layer 142, die connectors 144, and conductive connectors 146 may be formed before or after singulating the die structure 100.

Dielectric layer 142 may be formed on dielectric layer 136. The dielectric layer 142 may be formed of: one or more suitable dielectric materials such as silicon oxynitride, silicon nitride, low-k dielectrics such as carbon doped oxides, very low-k dielectrics such as porous carbon doped silicon oxide; polymers such as polyimide, solder resist, polybenzoxazole (PBO), benzocyclobutene (BCB) based polymers, molding compounds, and the like; or a combination thereof. Dielectric layer 142 may be formed by Chemical Vapor Deposition (CVD), spin coating, lamination, or the like, or a combination thereof. In some embodiments, dielectric layer 142 includes a lower dielectric layer 142A formed of nitride (e.g., silicon nitride) and an upper dielectric layer 142B formed of polymer (e.g., polyimide).

Die attach 144 may be formed through dielectric layer 142 and dielectric layer 136 to contact conductive pads 134. The die attach 144 may include conductive posts, pads, etc. that may make external connections. The die connectors 144 may be formed of a conductive material, such as a metal, such as copper, aluminum, etc., which may be formed by plating, for example.

As an example of forming die attach 144, dielectric layer 142 and dielectric layer 136 are patterned using photolithography and etching techniques to form openings corresponding to the desired pattern of die attach 144. In some embodiments, dielectric layer 142 serves as a masking layer during patterning of the openings. For example, the upper dielectric layer 142B may be patterned by an acceptable process, such as by exposing the upper dielectric layer 142B to light when the upper dielectric layer 142B is a photosensitive material, or by etching using, for example, anisotropic etching. If the upper dielectric layer 142B is a photosensitive material, the upper dielectric layer 142B may be developed after exposure. The lower dielectric layer 142A may then be patterned by etching the lower dielectric layer 142A using the upper dielectric layer 142B as an etch mask. The lower dielectric layer 142A may then be used as an etch mask (e.g., a hard mask) to etch the dielectric layer 136. The openings may then be filled with a conductive material (previously described) to form die connectors 144 in the openings.

Conductive connections 146 may be formed on die connections 144. The conductive connectors 146 may be Ball Grid Array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) or the like. The conductive connector 146 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or combinations thereof. In some embodiments, the conductive connection 146 is formed by initially forming a layer of reflowable material (e.g., solder) by evaporation, plating, printing, solder transfer, ball placement, and the like. Once the solder layer is formed on the structure, reflow may be performed to shape the material into the desired bump shape.

Fig. 12 is a cross-sectional view of a die structure 100 according to some embodiments. This embodiment is similar to the embodiment of fig. 11 except that the lower portion 110A of the backside interconnect structure 110 also includes dielectric layers 120, 124 and additional layers of conductive lines and vias. Specifically, the lower portion 110A of the backside interconnect structure 110 includes two of the dielectric layers 112, 116, 120, 124 and a via layer (e.g., conductive vias 114, 122 and conductive lines 118, 126).

Fig. 13 is a cross-sectional view of a die structure 100 according to some embodiments. This embodiment is similar to the embodiment of fig. 11 except that the gap fill dielectric 106 includes an epoxy material instead of a nitride-oxide-nitride-oxide (NONO) structure. The epoxy material may be a molding compound, an underfill, or the like. When a molding compound is used, it may be applied by compression molding, transfer molding, or the like. When an underfill is used, it may be applied by capillary flow processes, deposition processes, and the like.

Fig. 14 is a cross-sectional view of a die structure 100 according to some embodiments. This embodiment is similar to the embodiment of fig. 11 except that a plurality of upper integrated circuit dies 50B are bonded to a lower integrated circuit die 50A. The gap fill dielectric 106 fills the gap between the upper integrated circuit die 50B. The upper integrated circuit die 50B may be interconnected at least in part by some of the wires 118.

Fig. 15-17 are cross-sectional views at intermediate stages in the fabrication of a die structure 100 according to some embodiments. In this embodiment, the die structure 100 includes dielectric vias (TDVs) extending through the dielectric material to facilitate connection of the lower integrated circuit die 50A to the conductive features of the backside interconnect structure 110. The TDV may be formed during formation of the backside interconnect structure 110.

In fig. 15, the structure of fig. 7 is obtained. Conductive vias 154 are formed through gap-fill dielectric 106 and dielectric layer 112. Conductive via 154 may be formed after conductive via 114. Each conductive via 154 contacts a die connection 64A. Conductive via 154 is a dielectric via (TDV) that extends through the dielectric material.

As an example of forming the conductive via 154, the gap-fill dielectric 106 and the dielectric layer 112 are patterned using photolithography and etching techniques to form openings corresponding to the desired pattern of the conductive via 154. The openings expose a subset of die connectors 64A of the lower integrated circuit die 50A. A seed layer is formed over dielectric layer 112 and over the portions of die attach 64A exposed by the openings. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sub-layers formed of different materials. In a particular embodiment, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A conductive material is formed on the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, and the like. The seed layer and excess portions of the conductive material are then removed from the surface of the gap-fill dielectric 106. In some embodiments, a planarization process is utilized, such as a Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, and the like. The seed layer and the remaining portion of the conductive material in the opening form a conductive via 154.

In fig. 16, a dielectric layer 116 is formed over conductive via 154, conductive via 114, and dielectric layer 112. The dielectric layer 116 may be formed in a similar manner as previously described with respect to fig. 8. Conductive lines 118 are then formed in dielectric layer 116. The subset of wires 118 are electrically and physically coupled to the conductive vias 154. The wire 118 may be formed in a similar manner as previously described with respect to fig. 8.

In fig. 17, appropriate processing is performed as previously described with respect to fig. 9-11 to complete the die structure 100. In the die structure 100 of this embodiment, conductive vias 154 connect the lower integrated circuit die 50A to conductive features of the backside interconnect structure 110. Conductive vias 154 extend through dielectric layer 112 and each layer of gap-fill dielectric 106.

Fig. 18 is a cross-sectional view of a die structure 100 according to some embodiments. This embodiment is similar to the embodiment of fig. 17 except that the lower portion 110A of the backside interconnect structure 110 also includes dielectric layers 120, 124 and additional layers of conductive lines and vias. Specifically, the lower portion 110A of the backside interconnect structure 110 includes two of the dielectric layers 112, 116, 120, 124 and a via layer (e.g., conductive vias 114, 122 and conductive lines 118, 126).

Fig. 19 is a cross-sectional view of a die structure 100 according to some embodiments. This embodiment is similar to the embodiment of fig. 17 except that the gap fill dielectric 106 includes an epoxy material instead of a nitride-oxide-nitride-oxide (NONO) structure. The epoxy material may be a molding compound, an underfill, or the like. When a molding compound is used, it may be applied by compression molding, transfer molding, or the like. When an underfill is used, it may be applied by capillary flow processes, deposition processes, and the like.

Fig. 20 is a cross-sectional view of a die structure 100 according to some embodiments. This embodiment is similar to the embodiment of fig. 17, except that a plurality of upper integrated circuit dies 50B are bonded to a lower integrated circuit die 50A. The gap fill dielectric 106 fills the gap between the upper integrated circuit die 50B. The upper integrated circuit die 50B may be interconnected at least in part by some of the wires 118. In addition, some of the conductive vias 154 may be used to interconnect the upper integrated circuit die 50B. For example, conductive vias 154 may be used to connect the backside of an upper integrated circuit die 50B to the front side of another upper integrated circuit die 50B through die connectors 64A of the lower integrated circuit die 50A.

Embodiments may realize advantages. Forming conductive via 114 on conductive via 60B allows vertical connection to wire 118 to be accomplished without recessing semiconductor substrate 52B. When the gap-fill dielectric 106 has a nitride-oxide-nitride-oxide structure, omitting recessing the semiconductor substrate 52B may avoid etching the first liner 106A and the third liner 106C (e.g., nitride), thereby reducing pinhole defects in the die structure 100. Reducing pinhole defects may improve the yield and reliability of the die structure 100.

Other techniques may be used to reduce pinhole defects in the die structure 100. As described in more detail later, the gap fill dielectric 106 may be formed in a manner that allows the semiconductor substrate 52B to be recessed while avoiding liner damage to the gap fill dielectric 106. Thus, pinhole defects in the die structure 100 may be reduced even if the semiconductor substrate 52B is recessed such that the conductive vias 60B protrude from the non-active surface of the semiconductor substrate 52B.

Fig. 21-26 are cross-sectional views at intermediate stages in the fabrication of the die structure 100, according to some embodiments. In this embodiment, the main filler 106D is formed to cover the third pad 106C. Accordingly, the main filler 106D may protect the third liner 106C during recessing the semiconductor substrate 52B.

In fig. 21, the structure of fig. 3 is obtained. Then, spacer layers, such as a first spacer 106A, a second spacer 106B, and a third spacer 106C, are formed around the upper integrated circuit die 50B and on the lower integrated circuit die 50A to gap fill the dielectric 106. The first pad 106A, the second pad 106B, and the third pad 106C may be formed in a similar manner as previously described with respect to fig. 4.

In fig. 22, the third liner 106C is patterned such that the third liner 106C is recessed. The third liner 106C may be patterned by etching the third liner 106C to remove horizontal portions of the third liner 106C. Any acceptable etching process, such as dry etching, wet etching, or the like, or combinations thereof, may be performed to pattern the third liner 106C. The etching may be anisotropic. When the third liner 106C is etched, the second liner 106B may serve as an etch stop layer such that a horizontal portion of the second liner 106B is exposed by patterning the third liner 106C. The third liner 106C (when etched) has vertical portions left on the sidewalls of the second liner 106B. The remaining vertical portion of the third pad 106C is along the edge of the upper integrated circuit die 50B. Thus, the gap fill dielectric 106 still has a nitride-oxide-nitride-oxide structure along the edges of the upper integrated circuit die 50B.

In this embodiment, the third liner 106C is patterned such that the top surface of the third liner 106C is an inclined top surface. Specifically, each top surface of the third liner 106C forms an acute angle with the inner sidewall of the third liner 106C and an obtuse angle with the outer sidewall of the third liner 106C. In another embodiment (described later with respect to fig. 30), the top surface of the third liner 106C is a flat top surface.

As will be described in greater detail later, semiconductor substrate 52B will be recessed such that conductive vias 60B protrude from the inactive surface of semiconductor substrate 52B. The third liner 106C is patterned such that the top surface of the third liner 106C is below the top surface of the conductive via 60B. Therefore, when the semiconductor substrate 52B is subsequently recessed to expose the conductive via 60B, the third pad 106C is not etched.

In fig. 23, a main layer of gap-fill dielectric 106 (e.g., main filler 106D) is formed on liner layers of gap-fill dielectric 106 (e.g., third liner 106C and second liner 106B). The main fill 106D may be formed in a similar manner as previously described with respect to fig. 4.

In fig. 24, a removal process is performed to bring the surface of the gap-fill dielectric 106 flush with the backside of the upper integrated circuit die 50B (e.g., the non-active surface of the semiconductor substrate 52B). The removal process may be performed in a similar manner as previously described with respect to fig. 6. The removal process may include removing portions of the gap fill dielectric 106 that are located over the upper integrated circuit die 50B by etching in a similar manner as previously described with respect to fig. 5. Further, semiconductor substrate 52B may be thinned to expose conductive vias 60B in a similar manner as previously described with respect to fig. 6. After the removal process, the third liner 106C remains buried and covered by the main filler 106D. The main filler 106D extends along the outer sidewall and the top surface of the third liner 106C.

In fig. 25, an isolation layer 156 is optionally formed around the conductive vias 60B of the upper integrated circuit die 50B. Isolation layer 156 may help electrically isolate conductive vias 60B from each other, thereby avoiding shorting, and may also be used in subsequent bonding processes. In addition, isolation layer 156 helps protect the inactive surface of semiconductor substrate 52B. As an example of forming isolation layer 156, semiconductor substrate 52B is recessed such that conductive via 60B protrudes from the non-active surface of semiconductor substrate 52B. The recess exposes a portion of the sidewall of the conductive via 60B. The recessing may be performed by an etching process, such as dry etching, wet etching, or a combination thereof. A dielectric material may then be formed in the recess. The dielectric material may be an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), tetraethylorthosilicate (TEOS) -based oxide, etc., which may be formed by a suitable deposition process such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), etc. Other suitable dielectric materials may also be utilized, such as low temperature polyimide materials, PBO, encapsulants, combinations of these materials, and the like. A planarization process, such as CMP, grinding or etchback, may be performed to remove excess portions of the dielectric material over the conductive vias 60B. The remaining portion of the dielectric material in the recess forms an isolation layer 156. Isolation layer 156 laterally surrounds portions of the sidewalls of the corresponding conductive vias 60B.

As previously noted, the third liner 106C is recessed such that it is buried and covered by the main filler 106D. The top surface of the third liner 106C is located below the inactive surface of the semiconductor substrate 52B. The top surfaces of the first liner 106A, the second liner 106B, and the main fill 106D are located above the inactive surface of the semiconductor substrate 52B and are substantially coplanar (within process variations) with the top surfaces of the conductive via 60B and the isolation layer 156. Thus, the third liner 106C is not etched during recessing of the semiconductor substrate 52B, thereby reducing pinhole defects in the die structure 100. Reducing pinhole defects may improve the yield and reliability of the die structure 100.

In fig. 26, appropriate processing is performed as previously described with respect to fig. 8-11 to complete the die structure 100. Since in this embodiment, the conductive via 60B protrudes from the inactive surface of the semiconductor substrate 52B, the conductive via 114 and the dielectric layer 112 may be omitted. Thus, the wire 118 extends through the dielectric layer 116 to contact the conductive via 60B. The width of conductive via 60B is less than the width of wire 118 contacting conductive via 60B.

Fig. 27 is a cross-sectional view of a die structure 100 according to some embodiments. This embodiment is similar to the embodiment of fig. 26 except that the lower portion 110A of the backside interconnect structure 110 also includes dielectric layers 120, 124 and additional layers of conductive lines and vias. Specifically, the lower portion 110A of the backside interconnect structure 110 further includes conductive vias 122 and wires 126 in the dielectric layers 120, 124.

Fig. 28 is a cross-sectional view of a die structure 100 according to some embodiments. This embodiment is similar to the embodiment of fig. 26 except that a plurality of upper integrated circuit dies 50B are bonded to a lower integrated circuit die 50A. The gap fill dielectric 106 fills the gap between the upper integrated circuit die 50B. The upper integrated circuit die 50B may be interconnected at least in part by some of the wires 118. In addition, some of the conductive vias 154 may be used to interconnect the upper integrated circuit die 50B. For example, conductive vias 154 may be used to connect the backside of an upper integrated circuit die 50B to the front side of another upper integrated circuit die 50B through die connectors 64A of the lower integrated circuit die 50A.

Fig. 29 is a cross-sectional view of a die structure 100 according to some embodiments. This embodiment is similar to the embodiment of fig. 26 except that the gap-fill dielectric 106 includes a first liner 106A, a second liner 106B, a third liner 106C, a fourth liner 106D, a fifth liner 106E, and a main fill 106F. The fifth liner 106E may be formed in a similar manner to the third liner 106C, e.g., recessed, such that it is buried and covered by the main filler 106 DF.

Fig. 30 is a cross-sectional view of a die structure 100 according to some embodiments. This embodiment is similar to the embodiment of fig. 26 except that the top surface of the third liner 106C is a flat top surface. Specifically, each top surface of the third liner 106C forms a right angle with the inner sidewall of the third liner 106C and forms a right angle with the outer sidewall of the third liner 106C.

Fig. 31-35 are cross-sectional views of a die structure 100 according to some embodiments. These embodiments are similar to the embodiments of fig. 26-30, except that die structure 100 includes dielectric vias (TDVs) extending through the dielectric material to facilitate connection of the lower integrated circuit die 50A to the conductive features of the backside interconnect structure 110. The TDV may be formed during formation of the backside interconnect structure 110 in a similar manner as previously described with respect to fig. 21-26.

In an embodiment, a device includes: a lower integrated circuit die; a first upper integrated circuit die surface-to-surface bonded to the lower integrated circuit die, the first upper integrated circuit die comprising a first semiconductor substrate and a first substrate via; a gap fill dielectric located around the first upper integrated circuit die, a top surface of the gap fill dielectric being substantially coplanar with a top surface of the first semiconductor substrate and substantially coplanar with a top surface of the first substrate via; and an interconnect structure including a first dielectric layer disposed on the top surface of the gap-fill dielectric and the top surface of the first semiconductor substrate and a first conductive via extending through the first dielectric layer to contact the top surface of the first substrate via. In some embodiments of the device, the interconnect structure further includes a second dielectric layer disposed on the first dielectric layer and a first conductive line extending through the second dielectric layer to contact each of the first conductive vias. In some embodiments of the device, the interconnect structure further includes a third dielectric layer disposed on the second dielectric layer and a conductive feature including a second wire and a second conductive via in the third dielectric layer. In some embodiments of the device, the width of each of the first conductive vias is less than half the width of the first substrate via. In some embodiments of the device, each of the first conductive vias is spaced apart from the first semiconductor substrate. In some embodiments of the device, the gap fill dielectric comprises a nitride-oxide-nitride-oxide structure. In some embodiments of the device, the gap-fill dielectric comprises an epoxy material. In some embodiments, the device further comprises: a second upper integrated circuit die bonded to the lower integrated circuit die, a gap-fill dielectric disposed around the second upper integrated circuit die, the second upper integrated circuit die including a second semiconductor substrate and a second substrate via, a top surface of the gap-fill dielectric being substantially coplanar with a top surface of the second semiconductor substrate and a top surface of the second substrate via; wherein the interconnect structure further includes a second conductive via extending through the first dielectric layer to contact a top surface of the second substrate via. In some embodiments, the device further comprises: a dielectric via extending through the first dielectric layer of the interconnect structure and through the gap-fill dielectric, wherein the interconnect structure further includes a wire contacting the dielectric via.

In an embodiment, a device includes: a lower integrated circuit die; an upper integrated circuit die surface-to-surface bonded to the lower integrated circuit die, the upper integrated circuit die comprising a semiconductor substrate and a substrate via protruding from a surface of the semiconductor substrate; a dielectric member positioned around the upper integrated circuit die, the dielectric member comprising: a first nitride liner on sidewalls of the upper integrated circuit die; an oxide liner on the first nitride liner; a second nitride liner on the oxide liner, a top surface of the second nitride liner being disposed below a surface of the semiconductor substrate; and an oxide liner on the second nitride liner, wherein a top surface of the oxide liner, and a top surface of the first nitride liner are disposed over a surface of the semiconductor substrate. In some embodiments, the device further comprises: an isolation layer located around the through substrate via, a top surface of the isolation layer being substantially coplanar with a top surface of the oxide fill, a top surface of the oxide liner, and a top surface of the first nitride liner; a dielectric layer on the isolation layer and the dielectric member; and a wire extending through the dielectric layer to contact the through substrate via, the through substrate via having a width less than a width of the wire. In some embodiments of the device, the lower integrated circuit die includes a first die connector and a first dielectric layer, the upper integrated circuit die further includes a second die connector and a second dielectric layer, the first die connector is directly bonded to the second die connector, and the first dielectric layer is directly bonded to the second dielectric layer. In some embodiments of the device, the top surface of the second nitride liner is an inclined top surface. In some embodiments of the device, the top surface of the second nitride liner is a planar top surface.

In an embodiment, a method comprises: bonding a first front side of a first integrated circuit die to a second front side of a second integrated circuit die, the first integrated circuit die including a semiconductor substrate and a through substrate via; forming a gap fill dielectric over the first integrated circuit die and over the second integrated circuit die; planarizing the gap-fill dielectric until the gap-fill dielectric, the semiconductor substrate, and the substrate via have substantially coplanar top surfaces; depositing a first dielectric layer on top of the gap-fill dielectric, the semiconductor substrate, and the substrate via; and forming a conductive via in the first dielectric layer, the conductive via extending through the first dielectric layer to contact a top surface of the substrate via. In some embodiments of the method, forming the gap-fill dielectric includes forming an oxide-nitride-oxide structure on the first integrated circuit die and on the second integrated circuit die. In some embodiments of the method, forming the gap-fill dielectric includes forming an epoxy material on the first integrated circuit die and on the second integrated circuit die. In some embodiments, the method further comprises: forming a dielectric via extending through the first dielectric layer and through the gap-fill dielectric; depositing a second dielectric layer over the dielectric via, the conductive via, and the first dielectric layer; and forming a wire in the second dielectric layer, the wire extending through the second dielectric layer to contact the dielectric via and the conductive via. In some embodiments, the method further comprises: depositing a second dielectric layer over the conductive via and the first dielectric layer; forming a wire in the second dielectric layer, the wire extending through the second dielectric layer to contact the conductive via; depositing a third dielectric layer over the conductive lines and the second dielectric layer; and forming a conductive feature in the third dielectric layer, wherein the conductive via and the wire are each formed in a single damascene process, and wherein the conductive feature is formed in a dual damascene process. In some embodiments of the method, bonding the first front side of the first integrated circuit die to the second front side of the second integrated circuit die includes bonding the first integrated circuit die to a wafer including the second integrated circuit die, the gap-fill charging medium is formed on the wafer, and the method further comprises: the wafer is singulated, wherein after singulating the wafer, the second integrated circuit die, the gap-fill dielectric, and the first dielectric layer are laterally co-terminated.

89 the foregoing outlines features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising:

a lower integrated circuit die;

a first upper integrated circuit die surface-to-surface bonded to the lower integrated circuit die, the first upper integrated circuit die comprising a first semiconductor substrate and a first substrate via;

a gap-fill dielectric located around the first upper integrated circuit die, a top surface of the gap-fill dielectric being substantially coplanar with a top surface of the first semiconductor substrate and substantially coplanar with a top surface of the first substrate via; and

an interconnect structure includes a first dielectric layer disposed on the top surface of the gap-fill dielectric and the top surface of the first semiconductor substrate and a first conductive via extending through the first dielectric layer to contact the top surface of the first substrate via.

2. The semiconductor device of claim 1, wherein the interconnect structure further comprises a second dielectric layer disposed on the first dielectric layer and a first conductive line extending through the second dielectric layer to contact each of the first conductive vias.

3. The semiconductor device of claim 2, wherein the interconnect structure further comprises a third dielectric layer disposed on the second dielectric layer and a conductive feature comprising a second conductive line and a second conductive via in the third dielectric layer.

4. The semiconductor device of claim 1, wherein a width of each of the first conductive vias is less than half a width of the first substrate via.

5. The semiconductor device of claim 1, wherein each of the first conductive vias is spaced apart from the first semiconductor substrate.

6. The semiconductor device of claim 1, wherein the gap-fill dielectric comprises a nitride-oxide-nitride-oxide structure.

7. The semiconductor device of claim 1, wherein the gap-fill dielectric comprises an epoxy material.

8. The semiconductor device of claim 1, further comprising:

a second upper integrated circuit die bonded to the lower integrated circuit die, the gap-fill dielectric disposed about the second upper integrated circuit die, the second upper integrated circuit die including a second semiconductor substrate and a second substrate via, the top surface of the gap-fill dielectric being substantially coplanar with the top surfaces of the second semiconductor substrate and the second substrate via;

wherein the interconnect structure further includes a second conductive via extending through the first dielectric layer to contact the top surface of the second substrate via.

9. A semiconductor device, comprising:

a lower integrated circuit die;

an upper integrated circuit die surface-to-surface bonded to the lower integrated circuit die, the upper integrated circuit die comprising a semiconductor substrate and a substrate via protruding from a surface of the semiconductor substrate;

a dielectric member located around the upper integrated circuit die, the dielectric member comprising:

a first nitride liner on sidewalls of the upper integrated circuit die;

an oxide liner on the first nitride liner;

A second nitride liner on the oxide liner, a top surface of the second nitride liner disposed below the surface of the semiconductor substrate; and

and an oxide liner on the second nitride liner, wherein a top surface of the oxide liner, and a top surface of the first nitride liner are disposed over the surface of the semiconductor substrate.

10. A method of forming a semiconductor device, comprising:

bonding a first front side of a first integrated circuit die to a second front side of a second integrated circuit die, the first integrated circuit die comprising a semiconductor substrate and a through substrate via;

forming a gap fill dielectric on the first integrated circuit die and on the second integrated circuit die;

planarizing the gap-fill dielectric until the gap-fill dielectric, the semiconductor substrate, and the substrate via have substantially coplanar top surfaces;

depositing a first dielectric layer on the gap-fill dielectric, the semiconductor substrate, and the top surface of the substrate via; and

a conductive via is formed in the first dielectric layer, the conductive via extending through the first dielectric layer to contact the top surface of the substrate via.