CN117437966A

CN117437966A - Semiconductor memory device and memory system including the same

Info

Publication number: CN117437966A
Application number: CN202310594310.XA
Authority: CN
Inventors: 宋侑贞; 金成来; 姜吉荣; 金惠兰; 吴致成
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2022-07-20
Filing date: 2023-05-24
Publication date: 2024-01-23

Abstract

A semiconductor memory device and a memory system including the semiconductor memory device are provided. The semiconductor memory device includes a memory cell array, an on-chip Error Correction Code (ECC) engine, and control logic. The on-chip ECC engine includes a first latch and a second latch. The control logic circuit sets the semiconductor memory device to a test mode in response to a first mode register set command. In a test mode, the on-chip ECC engine cuts off connection with the memory cell array, receives test data, stores the test data in a first latch, performs ECC decoding on the test data stored in the first latch and test parity data stored in a second latch in response to a read command, and provides a severity signal to the external device, the severity signal indicating whether the test data and the test parity data include at least one error bit and whether the at least one error bit is correctable.

Description

Semiconductor memory device and memory system including the same

The present application claims priority from korean patent application No. 10-2022-0089304 filed on the korean intellectual property office at 7 months 20 of 2022 and korean patent application No. 10-2022-0128271 filed on the korean intellectual property office at 10 months 7 of 2022, the disclosures of which are incorporated herein by reference in their entirety.

Technical Field

The present disclosure relates to memories, and more particularly, to semiconductor memory devices and memory systems including semiconductor memory devices.

Background

Semiconductor memory devices may be classified into nonvolatile memory devices (such as flash memory devices) and volatile memory devices (such as DRAMs). The high speed operation and cost effectiveness of DRAM makes DRAM available for system memory. As the manufacturing design rules of DRAM continue to shrink, bit errors of memory cells in DRAM may increase rapidly and the yield of DRAM may decrease. Therefore, there is a need for reliability of semiconductor memory devices.

Disclosure of Invention

Some example embodiments provide a semiconductor memory device capable of enhancing test coverage.

Some example embodiments provide a memory system capable of enhancing test coverage.

According to an example embodiment, a semiconductor memory device includes a memory cell array, an on-chip Error Correction Code (ECC) engine, and control logic. The memory cell array includes a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines. The on-chip ECC engine includes a first latch and a second latch. The control logic controls the on-chip ECC engine. The control logic circuit sets the semiconductor memory device to a test mode in response to a first mode register set command from an external device. In the test mode, the on-chip ECC engine cuts off an electrical connection with the memory cell array, receives test data accompanied by a write command from the external device, stores the test data in the first latch, performs ECC decoding on the test data stored in the first latch and the test parity data selectively including a specific error bit stored in the second latch in response to a read command from the external device, and provides a severity signal to the external device based on a result of the ECC decoding, the severity signal indicating whether the test data and the test parity data include at least one error bit and indicating whether the at least one error bit is correctable.

According to an example embodiment, a memory system includes a semiconductor memory device and a memory controller for controlling the semiconductor memory device. The semiconductor memory device includes a memory cell array, an on-chip Error Correction Code (ECC) engine, and control logic. The memory cell array includes a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines. The on-chip ECC engine includes a first latch and a second latch. The control logic controls the on-chip ECC engine. The control logic circuit sets the semiconductor memory device to a test mode in response to a first mode register set command from the memory controller. In a test mode, the on-chip ECC engine cuts off electrical connection with the memory cell array, receives test data accompanied by a write command from the memory controller, stores the test data in the first latch, performs ECC decoding on the test data stored in the first latch and test parity data stored in the second latch that selectively includes a particular error bit in response to a read command from the memory controller, and provides a severity signal to the memory controller based on a result of the ECC decoding, the severity signal indicating whether the test data and the test parity data include at least one error bit and indicating whether the at least one error bit is correctable.

According to an example embodiment, a semiconductor memory device includes a memory cell array, an on-chip Error Correction Code (ECC) engine, and control logic. The memory cell array includes a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines. The on-chip ECC engine includes a first latch and a second latch. The control logic controls the on-chip ECC engine. The control logic circuit sets the semiconductor memory device to a test mode in response to a first mode register set command from an external device. In the test mode, the on-chip ECC engine cuts off an electrical connection with the memory cell array, receives test data accompanied by a write command from the external device, stores the test data in the first latch, performs ECC decoding on the test data stored in the first latch and the test parity data selectively including a specific error bit stored in the second latch in response to a read command from the external device, and provides a severity signal to the external device based on a result of the ECC decoding, the severity signal indicating whether the test data and the test parity data include at least one error bit and indicating whether the at least one error bit is correctable. The on-chip ECC engine includes encoding/decoding logic, a data corrector, a parity error pattern generator, and a severity signal generator. The encoding/decoding logic generates a syndrome by performing ECC decoding on the test data stored in the first latch and the test parity data stored in the second latch in the test mode. The data corrector outputs corrected test data by correcting selected error bits in the test data in the test mode. The parity error pattern generator applies a parity error pattern including error bits to the background parity data stored in the second latch based on the error bit selection signal. The severity signal generator generates a severity signal based on the syndrome.

Accordingly, in the test mode, the semiconductor memory device cuts off the electrical connection with the memory cell array, determines whether the test parity data includes an error bit, and selects a position of the parity bit including the error bit by setting the test mode register, injects at least one error bit in the test parity data and the test data, performs ECC decoding based on the test data and the test parity data without receiving the test parity data from the memory controller, and transmits a result of the ECC decoding to the memory controller. Accordingly, the semiconductor memory device can test the on-chip ECC engine for various error modes without disclosing the parity check matrix and without cutting off the connection with the memory cell array, and thus enhance the test coverage.

Drawings

Example embodiments will be described in more detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a memory system according to an example embodiment.

Fig. 2 is a block diagram illustrating an example of a memory controller in the memory system of fig. 1 according to an example embodiment.

Fig. 3 illustrates data sets corresponding to a plurality of burst lengths in the memory system of fig. 1 according to an example embodiment.

FIG. 4 illustrates an error injection register set, a data buffer, and a test data generator in the memory controller of FIG. 2 according to an example embodiment.

Fig. 5 shows a second data bit that may be stored in the error injection register set of fig. 4.

Fig. 6 and 7 illustrate various error modes that may be represented by an error injection register set according to example embodiments.

Fig. 8 is a block diagram illustrating an example of a semiconductor memory device in the memory system of fig. 1 according to an example embodiment.

Fig. 9 illustrates an example of a first bank array in the semiconductor memory device of fig. 8 according to an example embodiment.

Fig. 10 illustrates an example of a test mode register among the mode registers included in the semiconductor memory of fig. 8 according to an example embodiment.

Fig. 11 is a block diagram illustrating an example of an on-chip ECC engine in the semiconductor memory device of fig. 8 according to an example embodiment.

FIG. 12 illustrates an example of encoding/decoding logic in the on-die ECC engine of FIG. 11, according to an example embodiment.

Fig. 13 illustrates an example of a data corrector in the on-chip ECC engine of fig. 11 according to an example embodiment.

Fig. 14 shows a command sequence received by the semiconductor memory device in the test mode.

FIG. 15 illustrates operation of the memory system of FIG. 1 in a test mode according to an example embodiment.

FIG. 16 illustrates operation of the on-chip ECC engine of FIG. 11 in a test mode according to an example embodiment.

Fig. 17 illustrates data input/output to/from the on-chip ECC engine of fig. 11 in a test mode according to an example embodiment.

Fig. 18 illustrates data input/output to/from the on-chip ECC engine of fig. 11 in a test mode according to an example embodiment.

Fig. 19 shows a portion of the semiconductor memory device of fig. 8 for explaining a write operation in a normal mode.

Fig. 20 shows a portion of the semiconductor memory device of fig. 8 for explaining a read operation of a normal mode.

Fig. 21 is a flowchart illustrating a method of operating a semiconductor memory device according to an example embodiment.

Fig. 22 is a block diagram illustrating a semiconductor memory device according to an example embodiment.

Fig. 23 is a diagram illustrating a semiconductor package including stacked memory devices according to an example embodiment.

Detailed Description

Various example embodiments are described more fully hereinafter with reference to the accompanying drawings, in which example embodiments are shown.

Referring to fig. 1, a memory system 20 may include a memory controller 100 and a semiconductor memory device 200.

The memory controller 100 may control the overall operation of the memory system 20. The memory controller 100 may control the overall data exchange between the external host and the semiconductor memory device 200. For example, the memory controller 100 may write data into the semiconductor memory device 200 or read data from the semiconductor memory device 200 in response to a request from a host. The memory controller 100 may be referred to as an external device.

In addition, the memory controller 100 may issue an operation command to the semiconductor memory device 200 to control the semiconductor memory device 200.

In some embodiments, semiconductor memory device 200 is a memory device including dynamic memory cells, such as Dynamic Random Access Memory (DRAM) or graphic double data rate 7 (GDDR 7) Synchronous DRAM (SDRAM).

The memory controller 100 may transmit a command CMD and an address (signal) ADDR to the semiconductor memory device 200, may transmit main data MD to the semiconductor memory device 200 in a normal mode, may transmit test data TD to the semiconductor memory device 200 in a test mode, and may receive a severity signal SEV from the semiconductor memory device 200 in the test mode.

Memory controller 100 may include a Central Processing Unit (CPU) 110 and an error log register 160.

The semiconductor memory device 200 may include a memory cell array 310 storing main data MD and test data TD, an on-chip Error Correction Code (ECC) engine 400, and a control logic circuit 210.

The control logic 210 may control access to the memory cell array 310 and may control the on-chip ECC engine 400 based on the command CMD and the address ADDR. The memory cell array 310 may include a normal cell area and a parity cell area.

In the test mode, the on-chip ECC engine 400 may disconnect from the memory cell array 310, may receive test data TD accompanying a write command from the memory controller 100, may store the test data TD in a first latch in the on-chip ECC engine 400, may perform ECC decoding on the test data TD stored in the first latch and test parity data stored in a second latch in the on-chip ECC engine 400 in response to the read command from the memory controller 100, and may provide a severity signal SEV to the memory controller 100 indicating whether the test data TD and the test parity data include at least one error bit and indicating whether the at least one error bit is correctable based on a result of the ECC decoding. The test data TD and the test parity data may optionally include specific error bits.

The memory controller 100 may determine whether the on-chip ECC engine 400 is operating normally based on the severity signal SEV, and may record error information of the on-chip ECC engine 400 associated with various error patterns of the test data TD and the test parity data.

Referring to fig. 2, the memory controller 100 may include a CPU 110, a data buffer 120, a test data generator 130, an error injection register set 140, a Multiplexer (MUX) 170, a command buffer 180, and an address buffer 190.

The CPU 110 may receive the request REQ and the data DTA from the host, and may provide the data DTA to the data buffer 120.CPU 110 may control data buffer 120, test data generator 130, error injection register set 140, multiplexer 170, command buffer 180, and address buffer 190.

The data buffer 120 buffers the data DTA to supply the main data MD to the test data generator 130 and the multiplexer 170. The error injection register set 140 may store an error bit set including at least one error bit, and the error bit set may be associated with test data TD to be provided to the semiconductor memory device 200.

The test data generator 130 may generate test data TD based on the main data MD and the error bit set, and may provide the test data TD to the multiplexer 170.

In response to the mode signal MS from the CPU 110, the multiplexer 170 may receive the main data MD and the test data TD, may select the main data MD to provide the main data MD to the semiconductor memory device 200 in the normal mode, and may select the test data TD to provide the test data TD to the semiconductor memory device 200 in the test mode.

Under the control of the CPU 110, the command buffer 180 may store a command CMD corresponding to the request REQ, and may transmit the command CMD to the semiconductor memory device 200. The address buffer 190 may store the address ADDR under the control of the CPU 110, and may transmit the address ADDR to the semiconductor memory device 200.

Referring to fig. 3, a data set dq_bl corresponding to a plurality of burst lengths is input to/output from the semiconductor memory device 200. The data set dq_bl includes data segments dq_bl_sg1 to dq_bl_ SGk, each of which corresponds to each of a plurality of burst lengths, where k is an integer greater than three. For example, each data segment may include a plurality of data bits DQ1 through DQk. The data sets dq_bl corresponding to the plurality of burst lengths may be stored in the memory cell array 310 of the semiconductor memory device 200. The data set dq_bl may include main data MD and test data TD.

Referring to FIG. 4, error injection register set 140 may include a register write circuit 150 and a plurality of error injection registers 141-14 k. The data buffer 120 may include a plurality of data input registers 121-12 k. Each of the data input registers 121 to 12k may store a corresponding one of the first data bits dq_bl_sg1 to dq_bl_ SGk of the first unit corresponding to the burst length of the semiconductor memory device 200 in the data set dq_bl. Each of the data input registers 121 to 12k may provide a corresponding one of the first data bits dq_bl_sg1 to dq_bl_ SGk of the first unit of the data set dq_bl to the test data generator 130.

Each of the error injection registers 141 to 14k may store a corresponding one of the second data bits eb_bl_sg1 to eb_bl_ SGk of the second unit corresponding to each of the data input registers 121 to 12k and each of the first data bits dq_bl_sg1 to dq_bl_ SGk of the first unit. The size of the first unit may be the same as the size of the second unit.

Based on the control of the CPU 110, the register write circuit 150 may maintain the second data bits stored in the error injection registers 141 to 14k at a default level (first logic level, i.e., logic low level), or may change at least one of the second data bits to the second logic level.

Test data generator 130 may include a plurality of exclusive-or gates 131-13 k.

The plurality of exclusive or gates 131 to 13k may perform exclusive or operations on the first data bits dq_blsg1 to dq_bl_ SGk of the first unit and the second data bits eb_blsg1 to eb_bl_ SGk of the second unit, respectively, to generate the test data td_sg1 to td_ SGk.

Referring to fig. 5, the second data bit V having the first logic level as the default logic level may be stored in the error injection registers 141 to 14k in the error injection register set 140. The register write circuit 150 may change at least one of the second data bits V to a second logic level so that test data td_sg1 to td_ SGk representing various error modes may be provided to the semiconductor memory device 200.

Fig. 6 shows a single bit error.

Referring to fig. 6, only one of the second data bits eb_bl_sg1 to eb_bl_ SGk has a logic high level. Thus, it should be noted that the error pattern of FIG. 6 represents a single bit error.

Figure 7 shows a double bit error.

Referring to fig. 7, two of the second data bits eb_bl_sg1 to eb_bl_ SGk have a logic high level. Thus, it should be noted that the error pattern of FIG. 7 represents a double bit error.

Referring to fig. 8, a semiconductor memory device 200 may include a control logic circuit 210, an address register 220, a bank control logic 230, a refresh counter 245, a row address multiplexer (RA MUX) 240, a Column Address (CA) latch 250, a row decoder 260, a column decoder 270, a memory cell array 310, a sense amplifier unit 285, an input/output (I/O) gating circuit 290, an on-chip ECC engine 400, a data I/O buffer 295, and a signal buffer 297.

The memory cell array 310 may include first to eighth bank arrays 310a to 310h. The row decoder 260 may include first to eighth row decoders 260a to 260h coupled to the first to eighth bank arrays 310a to 310h, respectively, the column decoder 270 may include first to eighth column decoders 270a to 270h coupled to the first to eighth bank arrays 310a to 310h, respectively, and the sense amplifier unit 285 may include first to eighth sense amplifiers 285a to 285h coupled to the first to eighth bank arrays 310a to 310h, respectively.

The first to eighth bank arrays 310a to 310h, the first to eighth row decoders 260a to 260h, the first to eighth column decoders 270a to 270h, and the first to eighth sense amplifiers 285a to 285h may form first to eighth banks. Each of the first to eighth bank arrays 310a to 310h may include a plurality of volatile memory cells MC formed at intersections of a plurality of word lines WL and a plurality of bit lines BTL.

The address register 220 may receive an address ADDR including a BANK address bank_addr, a ROW address row_addr, and a column address col_addr from the memory controller 100. Address register 220 may provide a received BANK address BANK ADDR to BANK control logic 230, a received ROW address ROW ADDR to ROW address multiplexer 240, and a received column address COL ADDR to column address latch 250.

The BANK control logic 230 may generate the BANK control signal in response to the BANK address BANK ADDR. One of the first to eighth row decoders 260a to 260h corresponding to the BANK address bank_addr may be activated in response to a BANK control signal, and one of the first to eighth column decoders 270a to 270h corresponding to the BANK address bank_addr may be activated in response to a BANK control signal.

The ROW address multiplexer 240 may receive the ROW address ROW ADDR from the address register 220 and may receive the refresh ROW address REF ADDR from the refresh counter 245. The ROW address multiplexer 240 may selectively output the ROW address row_addr or the refresh ROW address ref_addr as the ROW address RA. The row address RA output from the row address multiplexer 240 may be applied to the first to eighth row decoders 260a to 260h.

The refresh counter 245 may sequentially increase or decrease the refresh row address ref_addr under the control of the control logic circuit 210.

When the command CMD from the memory controller 100 corresponds to an auto-refresh command or a self-refresh entry command, the control logic 210 may control the refresh counter 245 to sequentially output the refresh row address ref_addr.

One of the first through eighth row decoders 260a through 260h activated by the bank control logic 230 may decode the row address RA output from the row address multiplexer 240, and may activate a word line corresponding to the row address RA. For example, an activated row decoder may apply a word line drive voltage to a word line corresponding to a row address RA.

The column address latch 250 may receive the column address col_addr from the address register 220 and may temporarily store the received column address col_addr. In some embodiments, in burst mode, column address latch 250 may generate column address col_addr' incremented from received column address col_addr. The column address latch 250 may apply the temporarily stored or generated column address col_addr' to the first to eighth column decoders 270a to 270h.

The activated one of the first to eighth column decoders 270a to 270h may activate the sense amplifier corresponding to the BANK address bank_addr and the column address col_addr' through the I/O gating circuit 290.

The I/O gating circuit 290 may include a circuit for gating input/output data, and further includes input data mask logic, read data latches for storing data output from the first to eighth bank arrays 310a to 310h, and write drivers for writing data to the first to eighth bank arrays 310a to 310 h.

The codeword CW read from one of the first to eighth bank arrays 310a to 310h may be sensed by a sense amplifier coupled to one bank array from which data is to be read and may be stored in a read data latch. After ECC decoding is performed by the on-chip ECC engine 400 on the codeword CW stored in the read data latch, the codeword CW may be provided to the memory controller 100 via the data I/O buffer 295.

The main data MD to be written into one of the first through eighth bank arrays 310a through 310h may be provided from the memory controller 100 to the data I/O buffer 295, may be provided from the data I/O buffer 295 to the on-chip ECC engine 400, the on-chip ECC engine 400 may perform ECC encoding on the main data MD to generate parity data, the on-chip ECC engine 400 may provide the main data MD and the parity data to the I/O gating circuit 290, and the I/O gating circuit 290 may write the main data MD and the parity data into a sub-page of a target page in one of the bank arrays through a write driver.

The data I/O buffer 295 may provide the main data MD from the memory controller 100 to the on-chip ECC engine 400 in a normal mode write operation of the semiconductor memory device 200, and may provide test data TD selectively including at least one error bit in a test mode write operation of the semiconductor memory device 200.

In the write operation of the normal mode, the on-chip ECC engine 400 may receive the main data MD accompanied by the write command, may perform ECC encoding on the main data MD to generate parity data, and may store the main data MD and the parity data included in the codeword CW in the normal cell area and the parity cell area of the target bank, respectively, through the I/O gating circuit 290.

In the test mode, the on-chip ECC engine 400 may update the test data TD in a first latch in the on-chip ECC engine 400, may perform ECC decoding on the test data TD stored in the first latch and the test parity data stored in a second latch in response to a read command, may generate a severity signal SEV based on a result of the ECC decoding, and may provide the severity signal SEV to the memory controller 100 through the signal buffer 297. In one example, the on-chip ECC engine 400 may perform ECC decoding on test data TD including one error bit and test parity data having no parity error bits, and may provide a severity signal indicating that at least one error bit is correctable to an external device based on a result of the ECC decoding. In another example, the on-chip ECC engine 400 may perform ECC decoding on the test data TD without error bits and the test parity data including one parity error bit, and may provide a severity signal indicating that at least one error bit is correctable to an external device based on a result of the ECC decoding. In yet another example, the on-chip ECC engine 400 may perform ECC decoding on test data TD including one error bit and test parity data including one parity error bit, and may provide a severity signal indicating that at least one error bit is uncorrectable to an external device based on a result of the ECC decoding. In yet another example, the on-chip ECC engine 400 may perform ECC decoding on test data TD including two or more error bits and test parity data without parity error bits, and may provide a severity signal indicating that at least one error bit is uncorrectable to an external device based on a result of the ECC decoding.

The control logic circuit 210 may control the operation of the semiconductor memory device 200. For example, the control logic circuit 210 may generate control signals for the semiconductor memory device 200 in order to perform a write operation, a read operation, and an operation in a test mode. The control logic circuit 210 may include a command decoder 211 that decodes a command CMD received from the memory controller 100 and a mode register 212 that sets an operation mode of the semiconductor memory device 200.

For example, the command decoder 211 may generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, or the like.

The control logic circuit 210 may generate a first control signal CTL1 for controlling the I/O gating circuit 290 and a second control signal CTL2 for controlling the on-chip ECC engine 400 by decoding the command CMD.

Referring to fig. 9, the first bank array 310a may include a plurality of word lines WL0 to WLm-1 (where m is an even number equal to or greater than two), a plurality of bit lines BTL0 to BTLn-1 (where n is an even number equal to or greater than 2), and a plurality of memory cells MC disposed at intersections between the word lines WL0 to WLm-1 and the bit lines BTL0 to BTLn-1.

The word lines WL 0-WLm-1 may extend in a first direction D1, and the bit lines BTL 0-BTLn-1 may extend in a second direction D2.

Each of the memory cells MC includes an access (cell) transistor coupled to one of the word lines WL0 to WLm-1 and one of the bit lines BTL0 to BTLn-1, and a storage (cell) capacitor coupled to the cell transistor. That is, each of the memory cells MC has a DRAM cell structure.

In addition, the memory cells MC may have different arrangements depending on whether the memory cells MC are coupled to even word lines (e.g., WL 0) or odd word lines (e.g., WL 1). That is, bit lines coupled to adjacent memory cells may differ depending on whether a word line selected by an access address is an even word line or an odd word line.

Referring to FIG. 10, the test mode register MRx may store a plurality of operation codes OP [6:0].

The first operation code OP [6] of the plurality of operation codes OP [6:0] can set whether to enter an ECC Error Injection mode ECC_error_injection. When the first operation code OP [6] has a first logic level (i.e., a logic low level), the semiconductor memory device 200 may perform a normal operation, and when the first operation code OP [6] has a second logic level (i.e., a logic high level), the semiconductor memory device 200 may enter a test mode and may operate in an ECC error injection mode.

When the operation mode of the semiconductor memory device 200 is set to the ECC Error injection mode by the first operation code OP [6], the type error_pattern of the background data stored in the first latch (423 in FIG. 11) is set by the second operation code OP [5] of the plurality of operation codes OP [6:0 ]. Background data having a first type associated with a first codeword CW0 may be stored in the first latch 423 when the second opcode OP [5] has a first logic level and background data having a second type associated with a second codeword CW1 may be stored in the first latch 423 when the second opcode OP [5] has a second logic level.

The high level bit may indicate an error bit because all data bits in the background data having the first type have a low level, and the low level bit may indicate an error bit because all data bits in the background data having the second type have a high level.

When the operation mode of the semiconductor memory device 200 is set to the ECC Error injection mode, a third operation code OP [4] of the plurality of operation codes OP [6:0] can set whether the test Parity data includes an Error bit Party_error. When the third operation code OP [4] has the first logic level, the test parity data does not include an error bit, and when the third operation code OP [4] has the second logic level, the test parity data includes an error bit (i.e., a parity error).

When the operation mode of the semiconductor memory device 200 is set to the ECC error injection mode and the test Parity data is set to include error bits, the fourth through seventh operation codes OP [3:0] of the plurality of operation codes OP [6:0] may set (i.e., may select) a position, as represented by parity_sel, of Parity bits including the error bits from among the Parity bits of the test Parity data. For example, the fourth through seventh opcodes OP [3:0] may correspond to a 16-bit error mask (i.e., party_sel4b→error_mask 16 b).

If the test parity data includes 16-bit parity bits and the fourth through seventh opcodes OP [3:0] correspond to [0000], then the error mask corresponds to [1000000000000000]. The test parity data may be generated by performing an exclusive or (XOR) operation on the error mask and the background data by a second latch (427 in fig. 11).

Thus, in test mode, the test mode register MRx according to example embodiments may set the type of background data, whether the test parity data includes an error bit, and the location of the error bit in the test parity data. Thus, in addition to testing the case in which the test data includes the error bit, the memory controller 100 may also test the case in which the test parity data includes the error bit, and thus may enhance the test coverage.

Referring to fig. 11, the on-chip ECC engine 400 may include a demultiplexer 411, a first multiplexer 413, a second multiplexer 415, a third multiplexer 417, a first register 421, a first latch 423, a second register 425, a second latch 427, a parity error pattern generator 430, encoding/decoding logic 440, a data corrector 470, a severity signal generator 480, and a buffer circuit 490.

The buffer circuit 490 may include buffers 491, 492, 493, and 494. Buffers 491, 492, 493, and 494 may be controlled by a buffer control signal BCTL.

In the normal mode, in response to the first selection signal SS1, the demultiplexer 411 may receive the main data MD and may provide the main data MD to the second multiplexer 415 and the memory cell array 310 through a buffer 491 in the buffer circuit 490. In response to the first selection signal SS1, in the test mode, the demultiplexer 411 may receive the test data TD and may provide (i.e., update) the test data TD to the first latch 423.

In response to the first selection signal SS1, in the normal mode, the first multiplexer 413 may receive the main data MD from the memory cell array 310 through the buffer 492 and may output the main data MD to the second multiplexer 415 and the data corrector 470. In response to the first selection signal SS1, in the test mode, the first multiplexer 413 may receive the test data TD stored in the first latch 423 and output the test data TD to the second multiplexer 415 and the data corrector 470.

In response to the second selection signal SS2, the second multiplexer 415 may provide the main data MD to the encode/decode logic 440 in the write operation of the normal mode, and may provide the output of the first multiplexer 413 to the encode/decode logic 440 in the test mode.

In response to the first selection signal SS1, the third multiplexer 417 may provide the parity data PRT from the memory cell array 310 to the encoding/decoding logic 440 through the buffer 494 in the normal mode, and may provide the test parity data TPRT received from the second latch 427 to the encoding/decoding logic 440 in the test mode.

The first register 421 may store the first type of background data BD0 and the second type of background data BD1, and may provide one of the first type of background data BD0 and the second type of background data BD1 to the first latch 423 as the background data based on the first register control signal RCTL1 set by the second operation code OP [5] in the test mode.

In the test mode, the first latch 423 may store one of the first type of background data BD0 and the second type of background data BD1, may be updated by the test data TD, and may provide the test data TD to the first multiplexer 413 under the first latch control signal LCTL 1.

The second register 425 may store the first type of background parity data P0 and the second type of background parity data P1, and may provide one of the first type of background parity data P0 and the second type of background parity data P1 to the second latch 427 based on the second register control signal RCTL2 set by the second operation code OP [5] in the test mode.

In the test mode, the second latch 427 may store one of the first type of background parity data P0 and the second type of background parity data P1, may be inserted with an error bit through the parity error mode PEP, and may provide the test parity data TPRT to the third multiplexer 417 under the second latch control signal LCTL 2.

The parity error pattern generator 430 may apply a parity error pattern PEP including error bits to the background parity data stored in the second latch 427 based on the error bit selection signals eb_sel corresponding to the fourth through seventh operation codes OP [3:0 ]. The error bit selection signal eb_sel may set a position of an error bit included in the parity error pattern PEP, the parity error pattern generator 430 may provide the parity error pattern PEP to the second latch 427, and the second latch 427 may generate the test parity data TPRT by performing an XOR operation on background parity data corresponding to one of the first type of background parity data P0 and the second type of background parity data P1 and the parity error pattern PEP.

The encode/decode logic 440 may receive the main data MD from the second multiplexer 415 in a write operation of a normal mode, may generate the parity data PRT by performing ECC encoding on the main data MD, and may provide the parity data PRT to the memory cell array 310 through the buffer 493. In the read operation of the normal mode, the encoding/decoding logic 440 may receive the main data MD from the second multiplexer 415, may receive the parity data PRT from the third multiplexer 417, may generate the syndrome SDR by performing ECC decoding on the main data MD and the parity data PRT, and may provide the syndrome SDR to the data corrector 470 and the severity signal generator 480.

In a read operation of the test mode, the encoding/decoding logic 440 may receive the test data TD from the second multiplexer 415, may receive the test parity data TPRT from the third multiplexer 417, may generate a syndrome SDR by performing ECC decoding on the test data TD and the test parity data TPRT, and may provide the syndrome SDR to the data corrector 470 and the severity signal generator 480.

In the read operation of the normal mode, the data corrector 470 may receive the main data MD and may output the correction data c_md by correcting one error bit in the main data MD based on the syndrome SDR. In a read operation of the test mode, the data corrector 470 may receive the test data TD and may output corrected test data c_td by correcting one error bit in the test data TD based on the syndrome SDR. In one example, in a test mode, the data corrector 470 may output test data by avoiding correcting two or more error bits (i.e., two or more error bits included in the test data and the test parity data are uncorrectable) in response to the test data and the test parity data including two or more error bits.

The severity signal generator 480 may generate a severity signal SEV indicating whether the main data MD or the test data TD includes an error bit and whether the error bit is correctable.

The first selection signal SS1, the second selection signal SS2, the buffer control signal BCTL, the first register control signal RCTL1, the second register control signal RCTL2, the first latch control signal LCTL1, the second latch control signal LCTL2, and the error bit selection signal eb_sel in fig. 11 may be included in the second control signal CTL2 in fig. 8.

Fig. 12 illustrates an example of encoding/decoding logic in the on-chip ECC engine of fig. 11, according to an example embodiment.

Referring to fig. 12, encoding/decoding logic 440 may include a parity generator 441, a check bit generator 443, a syndrome generator 450, and a memory 445.

Parity generator 441 may be connected to ECC 447 in memory 445 and may generate parity data PRT based on main data MD using an array of exclusive or gates.

The check bit generator 443 may be connected to the ECC 447 in the memory 445 and may generate check bits CHB based on the main data MD in a read operation in a normal mode and may generate check bits CHB based on the test data TD in a read operation in a test mode. The syndrome generator 450 may generate the syndrome data SDR based on the "parity data PRT from the buffer 494 of fig. 11" and the "parity bit CHB based on the main data MD", and may generate the syndrome data SDR based on the "test parity data TPRT from the second latch 427" and the "parity bit CHB based on the test data TD". The syndrome generator 450 may generate the syndrome SDR based on whether each of the check bits CHB is equal to a corresponding one of the bits of the parity data PRT or the test parity data TPRT.

The syndrome SDR may include a plurality of syndrome bits, and each of the plurality of syndrome bits may indicate whether each of the parity bits CHB is equal to a corresponding one of the bits of the parity data PRT or the test parity data TPRT. Thus, the syndrome SDR may indicate the location of the erroneous bits and the number of erroneous bits.

Referring to fig. 13, the data corrector 470 may include a syndrome decoder 471, a bit inverter 473, and a selection circuit 475 implemented by a multiplexer.

The syndrome decoder 471 may decode the syndrome SDR to generate the decoded signal DS and the third selection signal SS3. The decoding signal DS may indicate a location of at least one error, and the third selection signal SS3 may have a logic level according to the number of at least one error bit. The bit inverter 473 may invert the at least one erroneous bit in response to the decoding signal DS. The selection circuit 475 may select one of the main data MD and the output of the bit inverter 473 in response to the third selection signal SS3 to provide the corrected main data c_md in the normal mode, and may select one of the test data TD and the output of the bit inverter 473 in response to the third selection signal SS3 to provide the corrected test data c_td in the test mode.

Fig. 14 illustrates a command sequence received by the semiconductor memory device in a test mode, and fig. 15 illustrates an operation of the memory system of fig. 1 in the test mode according to an example embodiment.

Referring to fig. 1, 10, 11, 14 and 15, the memory controller 100 applies a first mode register set command MRS1 to the semiconductor memory device 200 (operation S110) so that the semiconductor memory device 200 enters a test mode (operation S115) and a plurality of operation codes OP [6:0] in the test mode register MRx may be set to an error injection mode (operation S120). For example, the first mode register set command MRS1 may correspond to a test mode register set command. In response to the plurality of operation codes OP [6:0] being set to the error injection mode, the first latch 423 stores one of the first type of background data BD0 and the second type of background data BD1, and the second latch 427 stores one of the first type of background parity data P0 and the second type of background parity data P1.

The memory controller 100 applies the first write command WR1 and the first test data TD1 to the semiconductor memory device 200 (operation S125), and the on-chip ECC engine 400 updates the first latch 423 by storing the first test data TD1 in the first latch 423 (operation S130), and updates the second latch 427 by applying the parity error pattern PEP to the second latch 427.

The memory controller 100 applies the first read command RD1 to the semiconductor memory device 200 (operation S135), and the on-chip ECC engine 400 performs ECC decoding on the first test data TD1 stored in the first latch 423 and the test parity data TPRT stored in the second latch 427 (operation S140), generates a severity signal SEV1 based on a result of the ECC decoding, and transmits the severity signal SEV1 to the memory controller 100 (operation S145).

The memory controller 100 applies the second write command WR2 and the second test data TD2 to the semiconductor memory device 200 (operation S150), and the on-chip ECC engine 400 updates the first latch 423 by storing the second test data TD2 in the first latch 423 (operation S155).

The memory controller 100 applies the second read command RD2 to the semiconductor memory device 200 (operation S160), and the on-chip ECC engine 400 performs ECC decoding on the second test data TD2 stored in the first latch 423 and the test parity data TPRT stored in the second latch 427 (operation S165), generates the severity signal SEV2 based on the result of the ECC decoding, and transmits the severity signal SEV2 to the memory controller 100 (operation S170).

The above-described process is repeated for various test data and various test parity data, the memory controller 100 applies the second mode register set command MRS2 to the semiconductor memory device 200 (operation S175), and the semiconductor memory device 200 exits the test mode in response to the second mode register set command MRS2 (operation S180).

In fig. 16, according to the setting by the test mode register MRx, it is assumed that the first latch 423 stores the first type of background data BD0 and the second latch 427 stores the first type of background parity data P0.

Referring to fig. 16, the buffer circuit 490 cuts off the connection between the on-chip ECC engine 400 and the memory cell array 310 based on the buffer control signal BCTL in the test mode.

Test data TD accompanied by a write command from the memory controller 100 is stored in the first latch 423 and the first latch is updated. The parity error pattern PEP based on the error bit selection signal eb_sel is stored in the second latch 427, and the second latch 427 is updated.

The encode/decode logic 440 generates a syndrome SDR by performing ECC decoding on the test data TD stored in the first latch 423 and the test parity data TPRT stored in the second latch 427 in response to a read command from the memory controller 100, and the severity signal generator 480 generates a severity signal SEV based on the syndrome SDR. The data corrector 470 outputs corrected test data c_td by correcting one error bit in the test data TD based on the syndrome SDR.

In fig. 17, according to the setting by the test mode register MRx, it is assumed that the first latch 423 stores the first type of background data BD0 and the second latch 427 stores the first type of background parity data P0.

In fig. 17, the error pattern input may correspond to the test data TD in fig. 16, the error pattern output may correspond to the corrected test data c_td in fig. 16, the parity error may correspond to the test parity data TPRT in fig. 16, the SEV result may correspond to the severity signal SEV in fig. 16, and the expected SEV may correspond to the expected severity signal expected by the CPU 110 with respect to various error patterns. A logic high in the error mode input and the error mode output may indicate an error bit.

In fig. 17, it is assumed that each of the error pattern input and the error pattern output includes 256 bits and the parity error includes 16 bits.

Referring to fig. 17, when the error pattern input and the parity error do not include an error bit, the severity signal generator 480 in fig. 16 transmits a severity signal SEV indicating that an error bit (NE) is not detected to the memory controller 100, and the CPU 110 determines whether the on-chip ECC engine 400 operates normally based on a comparison of the severity signal SEV indicating that the error bit (NE) is not detected with an expected severity signal.

When one of the error pattern input and the parity error includes one error bit, the severity signal generator 480 in fig. 16 transmits a severity signal SEV indicating that one error bit is correctable (or Corrected) (CE) to the memory controller 100, and the CPU 110 determines whether the on-chip ECC engine 400 is operating normally based on a comparison of the severity signal SEV indicating that one error bit is Corrected (CE) with an expected severity signal.

When the error pattern input includes two or more error bits and the parity error does not include an error bit or each of the error pattern input and the parity error includes an error bit, the severity signal generator 480 in fig. 16 transmits a severity signal SEV indicating that the error bit is Uncorrectable (UE) to the memory controller 100, and the CPU 110 determines whether the on-chip ECC engine 400 operates normally based on a comparison of the severity signal SEV indicating that the error bit is Uncorrectable (UE) with an expected severity signal.

When the severity signal SEV is different from the expected severity signal, the CPU 110 determines that the on-chip ECC engine 400 is operating abnormally.

In fig. 18, according to the setting by the test mode register MRx, it is assumed that the first latch 423 stores the second type of background data BD1 and the second latch 427 stores the second type of background parity data P1.

In fig. 18, the error pattern input may correspond to the test data TD in fig. 16, the error pattern output may correspond to the corrected test data c_td in fig. 16, the parity error may correspond to the test parity data TPRT in fig. 16, the SEV result may correspond to the severity signal SEV in fig. 16, and the expected SEV may correspond to the expected severity signal expected by the CPU 110 with respect to various error patterns. A logic low in the error mode input and the error mode output may indicate an error bit.

In fig. 18, it is assumed that each of the error pattern input and the error pattern output includes 256 bits and the parity error includes 16 bits.

Referring to fig. 18, when the error pattern input and the parity error do not include an error bit, the severity signal generator 480 in fig. 16 transmits a severity signal SEV indicating that an error bit (NE) is not detected to the memory controller 100, and the CPU 110 determines whether the on-chip ECC engine 400 operates normally based on a comparison of the severity signal SEV indicating that the error bit (NE) is not detected with an expected severity signal.

In FIG. 19, control logic 210, first bank array 310a, I/O gating circuit 290, and on-chip ECC engine 400 are shown.

Referring to fig. 19, the first bank array 310a includes a normal cell area NCA and a redundant cell area RCA.

The normal cell area NCA includes a plurality of first memory blocks MB0 to MB15 (i.e., 311 to 313), and the redundant cell area RCA includes at least a second memory block 314. The first memory blocks 311 to 313 are memory blocks for determining or for determining the memory capacity of the semiconductor memory device 200. The second memory block 314 is used for ECC and/or redundancy repair. Since the second memory block 314 for ECC and/or redundancy repair is used for ECC, data line repair, and block repair to repair "faulty" cells generated in the first memory blocks 311 to 313, the second memory block 314 is also referred to as an EDB block. Each of the first memory blocks 311 to 313 includes memory cells coupled to a word line WL and a bit line BTL, and the second memory block 314 includes memory cells coupled to a word line WL and a redundancy bit line RBTL. The redundant cell area RCA may be referred to as a parity cell area.

The I/O gating circuit 290 includes a plurality of switching circuits (MUXs) 291a to 291d connected to the first memory blocks 311 to 313 and the second memory block 314, respectively.

The on-chip ECC engine 400 may be connected to the switching circuits 291a to 291d through a first data line GIO and a second data line EDBIO. The control logic circuit 210 may receive the command CMD and the address ADDR, and may decode the command CMD to generate a first control signal CTL1 for controlling the switching circuits 291a to 291d and a second control signal CTL2 for controlling the on-chip ECC engine 400.

When the command CMD is a write command, the control logic circuit 210 provides a second control signal CTL2 to the on-chip ECC engine 400. The on-chip ECC engine 400 performs ECC encoding on the main data MD to generate parity data associated with the main data MD, and provides a codeword CW including the main data MD and the parity data to the I/O gating circuit 290.

The control logic circuit 210 provides the first control signal CTL1 to the I/O gating circuit 290 such that the codeword CW is to be stored in a sub-page of the target page in the first bank array 310 a.

Fig. 20 shows a portion of the semiconductor memory device of fig. 8 for explaining a read operation of a normal mode. A description repeated with fig. 19 will be omitted.

Referring to fig. 20, when the command CMD is a read command for designating a read operation, the control logic circuit 210 supplies a first control signal CTL1 to the I/O gating circuit 290 so that the (read) codeword RCW stored in a sub-page of the target page in the first bank array 310a is supplied to the on-chip ECC engine 400.

The on-chip ECC engine 400 performs ECC decoding on the main data and the parity data in the codeword RCW and corrects error bits in the codeword RCW to output corrected main data c_md.

Referring to fig. 1 through 18 and 21, a method of operating a semiconductor memory device 200 is provided, the semiconductor memory device 200 including a memory cell array 310, an on-chip ECC engine 400, and a control logic circuit 210.

According to the method, a (test) mode register MRx associated with an error injection mode in the control logic circuit 210 is set to a test mode in response to a first mode register set command from the memory controller (operation S210).

The plurality of operation codes OP [6:0] of the test mode register MRx may set whether to enter the ECC Error Injection mode ecc_error_injection, may determine the type of background data stored in the first latch 423, may determine whether the test parity data includes Error bits, and may select the positions of the parity bits including the Error bits.

The on-chip ECC engine 400 cuts off connection with the memory cell array 310, the first latch 423 stores the test data TD in response to a write command from the memory controller 100 (operation S220), and the parity error pattern PEP is applied to the second latch 427.

In response to a read command from the memory controller 100, the encoding/decoding logic 440 performs ECC decoding on the test data TD stored in the first latch 423 and the test parity data TPRT stored in the second latch 427 (operation S230), and the severity signal generator 480 generates a severity signal SEV based on syndrome SDR corresponding to the result of the ECC decoding (operation S240).

The semiconductor memory device 200 transmits the severity signal SEV to the memory controller 100 (operation S250). The CPU 110 of the memory controller 100 determines whether the on-chip ECC engine 400 is operating normally based on the severity signal SEV.

Accordingly, in a test mode, the semiconductor memory device according to example embodiments cuts off a connection with the memory cell array, determines whether test parity data includes an error bit, and selects a position of the parity bit including the error bit by setting a test mode register, injects at least one error bit in the test parity data and the test data, performs ECC decoding based on the test data and the test parity data without receiving the test parity data from the memory controller, and transmits a result of the ECC decoding to the memory controller. Accordingly, the semiconductor memory device can test the on-chip ECC engine for various error modes without disclosing the parity check matrix and without cutting off the connection with the memory cell array, and thus enhance the test coverage.

Referring to fig. 22, a semiconductor memory device 600 may include a plurality of memory dies 620-1 through 620-p and at least one buffer die 610 that provide soft error analysis and correction functions in a stacked chip structure. Here, p is an integer greater than three.

The plurality of memory dies 620-1 through 620-p stacked on the at least one buffer die 610 transfer data through a plurality of Through Silicon Via (TSV), also referred to as through silicon via, lines.

Each of the memory dies 620-1 through 620-p may include a cell core 621, a cell core ECC engine 624, and a control logic circuit CLC 623, the cell core 621 including an array of memory cells, the cell core ECC engine 624 generating transmit parity data (i.e., transmit parity data) based on transmit data to be transmitted to the at least one buffer die 610. The cell core ECC engine 624 may employ the on-chip ECC engine 400 of FIG. 11. The control logic 623 may include a test mode register, and the test mode register may determine the type of background data, may determine whether the test parity data includes an error bit, and may select a position of the parity bit including the error bit through a plurality of opcodes.

The at least one buffer die 610 may include a pass (via) ECC engine 612, the pass ECC engine 612 correcting transmission errors using transmission parity data when transmission errors are detected from transmission data received over TSV lines, and generating error corrected data.

The semiconductor memory device 600 may be a stacked chip type memory device or a stacked memory device transmitting data and control signals through TSV lines. The TSV line may also be referred to as a "through electrode (through electrode)".

The data TSV line group 632 formed at one memory die 620-p may include TSV lines L1, L2 through Lp, and the parity TSV line group 634 may include TSV lines L10 through Lq.

The TSV lines L1, L2-Lp of the data TSV line set 632 and the parity TSV lines L10-Lq of the parity TSV line set 634 may be connected to the micro bumps MCB correspondingly formed in the memory dies 620-1-620-p.

Each of the memory dies 620-1 through 620-p can include DRAM cells that each include at least one access transistor and one storage capacitor.

The semiconductor memory device 600 may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with a host through the data bus B10. At least one buffer die 610 may be connected to the memory controller through a data bus B10.

Whether a transmission error occurs at the transmission data received through the data TSV line set 632 may be determined by the ECC engine 612 based on the transmission parity data received through the parity TSV line set 634. When a transmission error is detected, the transmission parity data may be used by the ECC engine 612 to correct the transmission error on the transmission data. When the transmission error is uncorrectable, information indicating the occurrence of the uncorrectable data error may be output by the ECC engine 612.

Referring to fig. 23, a semiconductor package 900 may include one or more stacked memory devices 910 and a Graphics Processor (GPU) 920.GPU 920 may include a memory Controller (CONT) 925.

The stacked memory device 910 and GPU 920 may be mounted on an interposer 930, and the interposer on which the stacked memory device 910 and GPU 920 are mounted may be mounted on a package substrate 940. Package substrate 940 may be mounted on solder balls 950. Memory controller 925 may employ memory controller 100 in fig. 1.

Each of the stacked memory devices 910 may be implemented in various forms, and may be a memory device in the form of a High Bandwidth Memory (HBM) in which multiple layers are stacked. Thus, each of the stacked memory devices 910 may include at least one buffer die and a plurality of memory dies. Each of the memory dies may include an array of memory cells, an on-chip ECC engine, and control logic circuitry.

The plurality of stacked memory devices 910 may be mounted on an interposer 930, and the GPU 920 may communicate with the plurality of stacked memory devices 910. For example, each of stacked memory device 910 and GPU 920 may include a physical region, and communication may be performed between stacked memory device 910 and GPU 920 through the physical region.

As described above, according to example embodiments, in a test mode, a semiconductor memory device cuts off a connection with a memory cell array, determines whether test parity data includes an error bit, and selects a position of a parity bit including the error bit by setting a test mode register, injects at least one error bit in the test parity data and the test data, performs ECC decoding based on the test data and the test parity data without receiving the test parity data from a memory controller, and transmits a result of the ECC decoding to the memory controller. Accordingly, the semiconductor memory device can test the on-chip ECC engine for various error modes without disclosing the parity check matrix and without cutting off the connection with the memory cell array, and thus enhance the test coverage.

Aspects of the present disclosure may be applied to systems using semiconductor memory devices employing an on-chip ECC engine and a plurality of volatile memory cells. For example, aspects of the present invention may be applied to systems (such as smartphones, navigation systems, notebook computers, desktop computers, and game consoles) that use semiconductor memory devices as working memory.

The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of this disclosure. Accordingly, all such modifications are intended to be included within the scope of this disclosure as defined in the claims.

Claims

1. A semiconductor memory device, comprising:

a memory cell array including a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines;

an on-chip error correction code ECC engine comprising a first latch and a second latch; and

control logic configured to control the on-chip ECC engine,

wherein the control logic circuit is configured to set the semiconductor memory device to a test mode in response to a first mode register set command from an external device, and

Wherein, in the test mode, the on-chip ECC engine is configured to perform operations comprising:

cutting off electrical connection to the memory cell array;

receiving test data and a write command from an external device;

storing the test data in a first latch;

performing ECC decoding on the test data stored in the first latch and the test parity data stored in the second latch in response to a read command from an external device; and

providing a severity signal to the external device based on a result of the ECC decoding, wherein the severity signal indicates whether the test data and the test parity data include at least one error bit and indicates whether the at least one error bit is correctable.

2. The semiconductor memory device according to claim 1, wherein the first mode register set command corresponds to a test mode register set command.

3. The semiconductor memory device according to claim 1,

wherein the control logic circuit includes a test mode register configured to indicate a test mode;

wherein the test mode register is configured to store a plurality of opcodes;

wherein a first opcode of the plurality of opcodes indicates whether to enter an ECC error injection mode;

Wherein when the first operation code indicates to enter the ECC error injection mode,

a second opcode of the plurality of opcodes indicates a type of background data stored in the first latch, an

A third opcode of the plurality of opcodes indicates whether the test parity data includes parity error bits, an

Wherein when the third operation code indicates that the test parity data includes a parity error bit, the fourth operation code, the fifth operation code, the sixth operation code, and the seventh operation code of the plurality of operation codes indicate a position of a parity bit including the parity error bit among the parity bits of the test parity data.

4. The semiconductor memory device of claim 3, wherein, in response to the second opcode indicating that the type of background data is one of the first type and the second type, the on-chip ECC engine is configured to perform operations comprising:

updating test data including an error bit in the first latch;

performing ECC decoding on the test data including the one error bit and the test parity data having no parity error bit; and

based on the results of the ECC decoding, a severity signal is provided to the external device indicating that the at least one error bit is correctable.

5. The semiconductor memory device of claim 3, wherein, in response to the second opcode indicating that the type of background data is one of the first type and the second type, the on-chip ECC engine is configured to perform operations comprising:

updating the test data without the erroneous bits in the first latch;

performing ECC decoding on test data without error bits and test parity data including one parity error bit; and

6. The semiconductor memory device of claim 3, wherein, in response to the second opcode indicating that the type of background data is one of the first type and the second type, the on-chip ECC engine is configured to perform operations comprising:

updating test data including an error bit in the first latch;

performing ECC decoding on the test data including the one error bit and the test parity data including the one parity error bit; and

based on the results of the ECC decoding, a severity signal is provided to the external device indicating that the at least one error bit is uncorrectable.

7. The semiconductor memory device of claim 3, wherein, in response to the second opcode indicating that the type of background data is one of the first type and the second type, the on-chip ECC engine is configured to perform operations comprising:

updating test data comprising two or more erroneous bits in a first latch;

performing ECC decoding on test data including the two or more error bits and test parity data having no parity error bits; and

based on the ECC decoding, a severity signal is provided to the external device indicating that the at least one error bit is uncorrectable.

8. The semiconductor memory device according to claim 3,

wherein, in response to the background data being of the first type, a high level bit in the test data indicates an erroneous bit, and

wherein, in response to the background data being of the second type, a low level bit in the test data indicates an erroneous bit.

9. The semiconductor memory device of any one of claims 1 to 8, wherein the on-chip ECC engine comprises:

a demultiplexer configured to: providing main data from an external device to the memory cell array in a normal mode in response to the first selection signal, and configured to provide test data to the first latch in a test mode;

Encoding/decoding logic configured to perform operations comprising:

generating parity data by performing ECC encoding on the main data in a write operation in a normal mode;

generating a syndrome by performing ECC decoding on the main data and the parity data in a read operation in a normal mode; and

generating a syndrome by performing ECC decoding on the test data and the test parity data in the test mode;

a data corrector configured to output correction data by correcting one error bit in the main data based on the syndrome in the normal mode and by correcting one error bit in the test data based on the syndrome in the test mode;

a buffer circuit configured to supply main data and parity data to the memory cell array in a normal mode, and configured to cut off electrical connection with the memory cell array in a test mode;

a parity error pattern generator configured to apply a parity error pattern including error bits to the background parity data stored in the second latch based on the error bit selection signal; and

a severity signal generator configured to generate a severity signal based on the syndrome.

10. The semiconductor memory device according to claim 9,

wherein the parity error pattern generator is configured to apply a parity error pattern including an error pattern in a position specified by the error bit selection signal to the second latch; and is also provided with

Wherein the second latch is configured to generate test parity data by performing an exclusive or operation on the background parity data and the parity error pattern.

11. The semiconductor memory device of claim 9, wherein the encoding/decoding logic comprises:

a check bit generator electrically connected to the memory cell array storing the ECC, the check bit generator configured to generate check bits based on the test data in the test mode; and

and a syndrome generator configured to generate a syndrome based on whether each of the check bits is equal to a corresponding one of the bits of the test parity data.

12. The semiconductor memory device according to claim 9, wherein the data corrector is configured to perform operations comprising:

in the test mode, outputting correction data by correcting the one error bit in response to the test data and the test parity data including the one error bit; and

In the test mode, the test data is output by avoiding correcting the two or more erroneous bits in response to the test data and the test parity data including the two or more erroneous bits.

13. The semiconductor memory device of claim 9, wherein the on-chip ECC engine further comprises:

a first register configured to provide background data in a test mode;

a first multiplexer configured to output main data supplied from the memory cell array in a normal mode and configured to output test data stored in the first latch in a test mode in response to a first selection signal;

a second multiplexer configured to supply the main data to the encoding/decoding logic in a write operation of the normal mode and configured to supply an output of the first multiplexer to the encoding/decoding logic in the test mode in response to the second selection signal;

a second register configured to provide background parity data to the second latch in the test mode; and

and a third multiplexer configured to supply parity data from the memory cell array to the encoding/decoding logic in a normal mode and configured to supply test parity data stored in the second latch to the encoding/decoding logic in a test mode in response to the first selection signal.

14. The semiconductor memory device according to any one of claims 1 to 8, wherein the control logic circuit is configured to exit the test mode in response to a second mode register set command from the external device applied after the read command.

15. The semiconductor memory device according to any one of claims 1 to 8, comprising:

at least one buffer die; and

a plurality of memory dies stacked on the at least one buffer die and configured to transfer data through a plurality of Through Silicon Via (TSV) lines,

wherein each of the plurality of memory dies includes an array of memory cells, control logic circuitry, and an on-chip ECC engine.

16. A memory system, comprising:

a semiconductor memory device; and

a memory controller configured to control the semiconductor memory device,

wherein the semiconductor memory device includes:

control logic configured to control the on-chip ECC engine,

Wherein the control logic circuit is configured to set the semiconductor memory device to a test mode in response to a first mode register set command from the memory controller, and

cutting off electrical connection to the memory cell array;

receiving test data and a write command from a memory controller;

storing the test data in a first latch;

performing ECC decoding on the test data stored in the first latch and the test parity data stored in the second latch in response to a read command from the memory controller; and

providing a severity signal to the memory controller based on a result of the ECC decoding, wherein the severity signal indicates whether the test data and the test parity data include at least one error bit and indicates whether the at least one error bit is correctable.

17. The memory system of claim 16, wherein the memory controller comprises:

a central processing unit CPU configured to determine whether the on-chip ECC engine is operating normally based on the severity signal in a test mode,

Wherein the memory controller is included in the graphics processor.

18. The memory system of claim 17,

wherein the control logic circuit includes a test mode register configured to set a test mode;

wherein the CPU is configured to perform operations comprising:

setting a test mode register such that at least one of the test data and the test parity data includes an error bit; and

whether the on-chip ECC engine is operating properly is determined based on a comparison of the severity signal and the expected severity signal.

19. The memory system of claim 17,

wherein the test mode register is configured to store a plurality of opcodes;

wherein when the first opcode indicates to enter an ECC error injection mode, a second opcode of the plurality of opcodes indicates a type of background data stored in the first latch;

wherein a third opcode of the plurality of opcodes indicates whether the test parity data includes an error bit; and is also provided with

Wherein when the third opcode indicates that the test parity data includes an error bit, a fourth opcode, a fifth opcode, a sixth opcode, and a seventh opcode of the plurality of opcodes indicate a position of a parity bit including the error bit among the parity bits of the test parity data.

20. A semiconductor memory device, comprising:

control logic configured to control the on-chip ECC engine,

cutting off electrical connection to the memory cell array;

receiving test data and a write command from an external device;

storing the test data in a first latch;

Providing a severity signal to the external device based on the results of the ECC decoding, wherein the severity signal indicates whether the test data and the test parity data include at least one error bit and indicates whether the at least one error bit is correctable, and

wherein, the on-chip ECC engine includes:

encoding/decoding logic configured to generate a syndrome by performing ECC decoding on the test data stored in the first latch and the test parity data stored in the second latch in the test mode;

a data corrector configured to output correction test data by correcting selected error bits in the test data in a test mode;