CN117437945A

CN117437945A - Clock multiplexing circuit, pulse generator and memory device

Info

Publication number: CN117437945A
Application number: CN202310822112.4A
Authority: CN
Inventors: 郑镕芸; 郑东赫; 俞昌植; 金基汉
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2022-07-22
Filing date: 2023-07-06
Publication date: 2024-01-23

Abstract

A clock multiplexing circuit, a pulse generator and a memory device are disclosed. The clock multiplexing circuit includes a first transistor between a first input terminal receiving a first input clock signal and an output terminal outputting an output pulse signal and operating based on a logic level of a second input terminal receiving a second input clock signal, and a second transistor between the output terminal and a first voltage node and operating based on a logic level of the second input terminal. The first input clock signal and the second input clock signal have the same period and different phases. The output pulse signal transitions to a first logic level at a first time when the first input clock signal transitions to the first logic level and transitions to a second logic level at a second time when the second input clock signal transitions to the first logic level.

Description

Clock multiplexing circuit, pulse generator and memory device

Cross Reference to Related Applications

The present application claims priority from korean patent application No.10-2022-0091304 filed in the korean intellectual property office at 22 nd 7 th year 2022 and korean patent application No. 10-2022-0124038 filed in 29 nd 9 th year 2022, the disclosures of which are incorporated herein by reference in their entireties.

Technical Field

The present disclosure relates to a clock multiplexing circuit. More particularly, the present disclosure relates to a clock multiplexing circuit that receives clock signals of different phases and generates a pulse signal that switches (toggling) in response to edges of the received clock signal.

Background

The memory device may include various circuits for generating, processing, or storing data. For example, a memory device may include various circuits for storing or outputting data based on a clock signal, a data signal, and a command signal. Nowadays, as the amount of data to be processed in a memory device increases, the frequency of a clock signal increases in order to increase the speed of data transmission. However, in the case where the frequency of the clock signal increases, the reliability of the operation of the memory device that operates in response to the clock signal may decrease.

Disclosure of Invention

Embodiments of the present disclosure provide a clock multiplexing circuit with a simpler structure.

According to some embodiments, the clock multiplexing circuit may include a first transistor between a first input terminal configured to receive the first input clock signal and an output terminal configured to output the output pulse signal and operating based on a logic level of a second input terminal configured to receive the second input clock signal, and a second transistor between the output terminal and the first voltage node and configured to operate based on a logic level of the second input terminal. The first input clock signal and the second input clock signal may have the same period and have different phases. The output pulse signal may transition to a first logic level at a first time when the first input clock signal transitions to the first logic level and may transition to a second logic level at a second time when the second input clock signal transitions to the first logic level.

According to some embodiments, the pulse generator may include a phase shifter outputting four-phase clock signals including first to fourth clock signals having phases different from each other, and a clock multiplexer including first to fourth clock multiplexing circuits. The first to fourth clock multiplexing circuits may output first to fourth pulse signals having different phases from each other, respectively, based on the four-phase clock signals. The first clock multiplexing circuit may include a first transistor between a first input node configured to receive the first clock signal and an output node configured to output the first pulse signal at the output node and operating based on a logic level of a second input node configured to receive the second clock signal, and a second transistor between the first output node and the first voltage node and configured to operate based on a logic level of the second input node.

According to some embodiments, a memory device may include a clock multiplexer configured to generate first to nth pulse signals (n is a natural number greater than or equal to 4) based on n-phase clock signals including the first to nth clock signals, a memory cell array configured to output first to mth data in parallel (m is a natural number equal to or greater than 4), and a serializer configured to sequentially output the first to mth data to a first data pad in response to the first to nth pulse signals. The clock multiplexer may include first to nth clock multiplexing circuits configured to generate first to nth clock signals, respectively. The first clock multiplexing circuit may include a first transistor between the first input node and the first output node and a second transistor between the first output node and the first voltage node. The first transistor is configured to output a first pulse signal and is configured to operate based on a logic level of a second input node that receives a second clock signal, and the second transistor is configured to operate based on a logic level of the second input node.

Drawings

The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments thereof with reference to the accompanying drawings.

Fig. 1 is a block diagram illustrating a pulse generator according to some embodiments of the present disclosure.

Fig. 2 is a block diagram illustrating the clock multiplexer of fig. 1 in detail.

Fig. 3 is a block diagram illustrating the clock multiplexing circuit of fig. 1.

Fig. 4 is a timing diagram illustrating output pulse signals that are switched in response to different types of edges of a first input clock signal and a second input clock signal.

Fig. 5 is a circuit diagram illustrating the clock multiplexing circuit of fig. 3, according to some embodiments.

Fig. 6 is a circuit diagram illustrating the clock multiplexing circuit of fig. 3, according to some embodiments.

Fig. 7 is a circuit diagram illustrating the clock multiplexing circuit of fig. 3, according to some embodiments.

Fig. 8 is a timing diagram illustrating the relationship between the first and second input clock signals and the output pulse signal associated with the clock multiplexing circuits of fig. 5-7.

Fig. 9 is a timing chart showing a relationship between the clock signal and the pulse signal of fig. 1 when the clock multiplexing circuit of fig. 1 is implemented with the clock multiplexing circuit of fig. 7.

Fig. 10 is a circuit diagram illustrating the clock multiplexing circuit of fig. 3 according to some embodiments of the present disclosure.

Fig. 11 is a timing diagram illustrating a relationship between first and second input clock signals and an output pulse signal associated with the clock multiplexing circuit of fig. 10.

Fig. 12 is a timing chart showing a relationship between the clock signal and the pulse signal of fig. 1 when the clock multiplexing circuit of fig. 1 is implemented with the clock multiplexing circuit of fig. 10.

Fig. 13 is a timing diagram illustrating a relationship between first and second input clock signals and an output pulse signal associated with the clock multiplexing circuit of fig. 7.

Fig. 14 is a timing chart showing a relationship between the clock signal and the pulse signal of fig. 1 when the clock multiplexing circuit of fig. 1 is implemented with the clock multiplexing circuit of fig. 7.

Fig. 15 is a block diagram illustrating a memory system according to some embodiments of the present disclosure.

Fig. 16 is a block diagram illustrating the memory device of fig. 15 in detail.

Fig. 17 is a block diagram illustrating the input/output circuit of fig. 16 in detail.

Fig. 18 is a timing chart showing data output to the data pad based on the pulse signal of fig. 17.

Fig. 19 is a block diagram showing a memory module to which the memory device of fig. 15 to 18 is applied.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described in detail and clearly to enable one skilled in the art to easily practice the present disclosure. In the following description, specific details such as detailed components and structures are provided merely to aid in a thorough understanding of embodiments of the present disclosure. It will therefore be apparent to those skilled in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the invention. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness. In the following figures and/or detailed description, components may be connected with any other components in addition to the components shown in the figures or described in the detailed description. The terms described in the specification are terms defined in consideration of functions in the present disclosure, and are not limited to specific functions. The definition of terms should be determined based on the contents of the entire specification.

Components described in the detailed description with reference to the terms "circuit," "block," and the like will be implemented in software, hardware, or a combination thereof. For example, the software may be machine code, firmware, embedded code, and/or application software. For example, the hardware may include electrical circuitry, electronic circuitry, processors, computers, integrated circuit cores, pressure sensors, microelectromechanical systems (MEMS), passive components, or combinations thereof.

Fig. 1 is a block diagram illustrating a pulse generator according to some embodiments of the present disclosure. Referring to fig. 1, the pulse generator PG may include a phase shifter PS and a clock multiplexer 100.

The phase shifter PS may receive the reference clock RCLK. The phase shifter PS may generate an n-phase clock signal based on the reference clock RCLK. For example, the phase shifter PS may output the first to nth clock signals CLK1 to CLKn generated by delaying the reference clock RCLK by different phases. That is, the n-phase clock signals may include the first to n-th clock signals CLK1 to CLKn.

In some embodiments, the first clock signal CLK1 to the n-th clock signal CLKn may have the same period and may have different phases.

In some embodiments, "n" may be an integer of 4 or greater. For example, when "n" is 4, the n-phase clock signals may include the first to fourth clock signals CLK1 to CLK4. In this case, two clock signals adjacent to each other among the first to fourth clock signals CLK1 to CLK4 may have a phase difference of 90 degrees. That is, the second clock signal CLK2 may lag the first clock signal CLK1 by up to 90 degrees; the third clock signal CLK3 may lag the first clock signal CLK1 by up to 180 degrees; the fourth clock signal CLK4 may lag the first clock signal CLK1 by up to 270 degrees. In the following, some embodiments where "n" is 4 will be representatively described for the sake of brief description. However, the present disclosure is not limited thereto. For example, "n" may be an integer of 8, 16, etc. In particular, some embodiments in which "n" is 8 will be described in detail with reference to fig. 13 and 14.

In some embodiments, "n" may be an integer of 4 or greater.

In some embodiments, the pulse generator PG may be included in a memory device. Further, the pulse generator PG may receive the reference clock RCLK from the outside. That is, the reference clock RCLK may be provided from outside the memory device or from outside the memory device. For example, the reference clock RCLK may be provided from a memory controller.

The clock multiplexer 100 may include first to nth clock multiplexing circuits (clock multiplexing circuits # 1) 110_1 to (clock multiplexing circuits # n) 110_n. The first to nth clock multiplexing circuits 110_1 to 110—n may multiplex n-phase clock signals to output the first to nth pulse signals PUL1 to PULn.

Each of the first to nth clock multiplexing circuits 110_1 to 110—n may generate a pulse signal based on two different clock signals of the first to nth clock signals CLK1 to CLKn. For example, each of the first to nth clock multiplexing circuits 110_1 to 110—n may generate a pulse signal based on two clock signals adjacent to each other among clock signals included in the n-phase clock signals. In detail, the kth clock multiplexing circuit 110—k, which is one of the first through (n-1) th clock multiplexing circuits 110_1 through 110_n-1, may generate the kth pulse signal PULk based on the kth clock signal CLKk and the (k+1) th clock signal clkk+1. The nth clock multiplexing circuit 110—n may generate the nth pulse signal PULn based on the nth clock signal CLKn and the first clock signal CLK 1. The configuration of the clock multiplexer 100 and the operation of each of the first to nth clock multiplexing circuits 110_1 to 110—n will be described in detail with reference to the following drawings.

In some embodiments, clock signals having a phase difference of 360/n degrees among clock signals included in n-phase clock signals may be described as being adjacent to each other. For example, clock signals having a phase difference of 90 degrees among clock signals included in n-phase clock signals may be described as being adjacent to each other.

Fig. 2 is a block diagram illustrating the clock multiplexer of fig. 1 in detail. Referring to fig. 1 and 2, the clock multiplexer 100 may include first to nth clock multiplexing circuits 110_1 to 110—n.

The clock multiplexer 100 may include first to nth input nodes IN1 to INn. The clock multiplexer 100 may receive the first to nth clock signals CLK1 to CLKn through the first to nth input nodes IN1 to INn. For example, the first clock signal CLK1 may be provided to the first input node IN1, and the n-th clock signal CLKn may be provided to the n-th input node INn.

Each of the first to nth clock multiplexing circuits 110_1 to 110—n may generate the pulse signal based on two clock signals adjacent to each other among the clock signals included in the n-phase clock signals. In other words, each of the clock multiplexing circuits 110_1 to 110—n may generate a pulse signal based on two clock signals whose phases are shifted from each other by 90 degrees. For example, a kth clock multiplexing circuit 110—k, which is one of the first through (n-1) th clock multiplexing circuits 110_1 through 110_n-1, may be connected to the kth input node INk and the (k+1) th input node INk +1. The nth clock multiplexing circuit 110_n may be connected to the nth input node INn and the first input node IN 1.

Each of the first to nth clock multiplexing circuits 110_1 to 110—n may receive clock signals of different phases from an input node connected thereto. Each of the first to nth clock multiplexing circuits 110_1 to 110—n may generate a pulse signal based on the received clock signal. For example, the first clock multiplexing circuit 110_1 may receive the first clock signal CLK1 through the first input node IN1 and the second clock signal CLK2 through the second input node IN 2. In this case, the first clock multiplexing circuit 110_1 may generate the first pulse signal PUL1 based on the first clock signal CLK1 and the second clock signal CLK2. The operation of each of the first to nth clock multiplexing circuits 110_1 to 110—n will be described in detail with reference to the following drawings.

Fig. 3 is a block diagram illustrating the clock multiplexing circuit of fig. 1. Referring to fig. 1 and 3, the clock multiplexing circuit 110 may receive a first input clock signal ICLKa and a second input clock signal ICLKb. The clock multiplexing circuit 110 may output the output pulse signal OPUL based on the first input clock signal ICLKa and the second input clock signal ICLKb.

The clock multiplexing circuit 110 may correspond to one or more of the first to nth clock multiplexing circuits 110_1 to 110—n. For example, the first clock multiplexing circuit 110_1 may be the clock multiplexing circuit 110. In this case, the first input clock signal ICLKa may correspond to the first clock signal CLK1, and the second input clock signal ICLKb may correspond to the second clock signal CLK2. The output pulse signal OPUL may correspond to the first pulse signal PUL1 from fig. 2.

In some embodiments, the first input clock signal ICLKa may precede the second input clock signal ICLKb. That is, the first input clock signal ICLKa may be ahead of the second input clock signal ICLKb, and the second input clock signal ICLKb may lag behind the first input clock signal ICLKa. For example, the first input clock signal ICLKa and the second input clock signal ICLKb may be clock signals having different phases (or adjacent to each other) among clock signals included in n-phase clock signals. In detail, the first input clock signal ICLKa and the second input clock signal ICLKb may have a phase difference of 360/n degrees. The first input clock signal ICLKa and the second input clock signal ICLKb may have the same frequency or period but have different phases. However, the present disclosure is not limited thereto.

The output pulse signal OPUL may be switched in response to edges of the first input clock signal ICLKa and/or the second input clock signal ICLKb. For example, the output pulse signal OPUL may be switched in response to different types of edges among edges of the first input clock signal ICLKa and/or the second input clock signal ICLKb. In some embodiments, the output pulse signal OPUL may be switched in response to the same type of edges among the edges of the first input clock signal ICLKa and/or the second input clock signal ICLKb.

The clock multiplexing circuit 110 that generates the output pulse signal OPUL switched in response to different types of edges among edges of the input clock signal will be described in detail with reference to fig. 4.

The clock multiplexing circuit 110 that generates the output pulse signal OPUL switched in response to the same type of edges among the edges of the input clock signal will be described in detail with reference to fig. 5 to 14.

In some embodiments, the clock multiplexing circuit 110 may include a first input terminal, a second input terminal, and an output terminal. In this case, the clock multiplexing circuit 110 may receive the first input clock signal ICLKa through the first input terminal, may receive the second input clock signal ICLKb through the second input terminal, and may output the output pulse signal OPUL through the output terminal.

In some embodiments, clock multiplexing circuit 110 may include two transistors of different channel types. The clock multiplexing circuit 110 including two transistors having different channel types will be described in detail with reference to fig. 7 and 10.

Fig. 4 is a timing diagram illustrating output pulse signals that are switched in response to different types of edges of a first input clock signal and a second input clock signal. In fig. 4, the horizontal axis represents time, and the vertical axis represents the logic level of the signal.

For a more concise description, the output pulse signal OPUL switched in response to the rising edge of the second input clock signal ICLKb and the falling edge of the first input clock signal ICLKa will be representatively described below. In addition, some embodiments in which the first input clock signal ICLKa and the second input clock signal ICLKb are included in a four-phase clock signal will be representatively described below. However, the present disclosure is not limited thereto.

The first input clock signal ICLKa and the second input clock signal ICLKb may have the same period. For example, each of the first input clock signal ICLKa and the second input clock signal ICLKb may have a period Tp.

The second input clock signal ICLKb may lag the first input clock signal ICLKa by up to 90 degrees (i.e., up to 360/n degrees when "n" is 4). For example, the first input clock signal ICLKa may transition from a logic low level to a logic high level at the 0 th time t 0. That is, the first input clock signal ICLKa may have a rising edge at the 0 th time t 0. The second input clock signal ICLKb may transition from a logic low level to a logic high level at a first time t 1 later than a 0 th time t 0. That is, the second input clock signal ICLKb may have a rising edge at the first time t 1. In this case, the time interval from the 0 th time t0 to the first time t 1 may be 1/4 of the period Tp.

The first input clock signal ICLKa may transition from a logic high level to a logic low level at the second time t 2. That is, the first input clock signal ICLKa may have a falling edge at the second time t 2. In this case, the time interval from the 0 th time t0 to the second time t2 may be 1/2 of the period Tp.

The output pulse signal OPUL may transition from a logic low level to a logic high level at a first time t 1. That is, the output pulse signal OPUL may transition to a logic high level in response to a rising edge of the second input clock signal ICLKb. The output pulse signal OPUL may transition from a logic high level to a logic low level at the second time t 2. That is, the output pulse signal OPUL may transition to a logic low level in response to a falling edge of the first input clock signal ICLKa.

In some embodiments, the output pulse signal OPUL may have the same period as the first input clock signal ICLKa and the second input clock signal ICLKb. For example, in the next cycle of the first input clock signal ICLKa and the second input clock signal ICLKb, the logic level of the output pulse signal OPUL may be transitioned in a similar manner to that described above.

In some embodiments, the clock multiplexing circuit 110 implemented to perform a logic operation such as an AND, NAND, OR NOR operation may output the output pulse signal OPUL based on the first input clock signal ICLKa AND the second input clock signal ICLKb. In this case, a time interval from the first time t 1 when the output pulse signal OPUL transitions from the logic low level to the logic high level to the second time t2 when the output pulse signal OPUL transitions from the logic high level to the logic low level may be determined based on the rising edge time point of the second input clock signal ICLKb and the falling edge time point of the first input clock signal ICLKa. Thus, for fine (or accurate) operation of the clock multiplexing circuit 110, it may be necessary to accurately determine both the falling edge time point and the rising edge time point of the clock signal. However, technically, it may be very difficult to generate a high frequency n-phase clock signal that is accurate at both the rising edge time point and the falling edge time point.

Accordingly, instead of the structure in which the clock multiplexing circuit 110 generates the output pulse signal OPUL switched in response to different types of edges of the input clock signal, the clock multiplexing circuit 110 may be implemented to generate the output pulse signal OPUL switched in response to the same type of edges among the edges of the input clock signal. Accordingly, an embodiment in which the clock multiplexing circuit 110 generates the output pulse signal OPUL switched in response to the same type of edges among the edges of the input clock signal will be described with reference to fig. 5 to 14.

Fig. 5 is a circuit diagram illustrating the clock multiplexing circuit of fig. 3, according to some embodiments. Referring to fig. 3 and 5, the clock multiplexing circuit 11a may include a delay matching circuit dmea and a NAND gate NAND.

The delay matching circuit DMCa may receive the first input clock signal ICLKa and may provide a signal having the same phase as the first input clock signal ICLKa to the first input terminal of the NAND gate NAND. For example, the delay matching circuit DMCa may supply the first input clock signal ICLKa to the first input terminal of the NAND gate NAND through an inverter string including an even number of inverters INV.

The delay matching circuit DMCa may receive the second input clock signal ICLKb and may provide a signal having a phase opposite to that of the second input clock signal ICLKb to the second input terminal of the NAND gate NAND. For example, the delay matching circuit DMCa may supply the second input clock signal ICLKb to the second input terminal of the NAND gate NAND through an inverter string including an odd number of inverters INV.

The delay matching circuit DMCa may delay the first input clock signal ICLKa and the second input clock signal ICLKb by as much as the same time length so as to be supplied to the input terminals of the NAND gate NAND, respectively. For example, the delay between the first input clock signal ICLKa and the signal supplied to the first input terminal of the NAND gate NAND may be the same as the delay between the second input clock signal ICLKb and the signal supplied to the second input terminal of the NAND gate NAND.

The NAND gate NAND may perform a NAND (NAND) operation on the signal received from the delay matching circuit dmea. The NAND gate NAND may provide the result of the NAND operation to the inverter INV. The inverter INV receiving the nand operation result may output the output pulse signal OPUL.

In this case, the output pulse signal OPUL may be switched in response to edges of the input clock signal having the same type. For example, the output pulse signal OPUL may transition from a logic low level to a logic high level at a rising edge time point of the first input clock signal ICLKa, and may transition from a logic high level to a logic low level at a rising edge time point of the second input clock signal ICLKb. The output pulse signal OPUL switched in response to the input clock signal having the same type of edges will be described in detail with reference to fig. 8.

However, according to the embodiment of fig. 5, a plurality of inverters INV may be required to delay the second input clock signal ICLKb for the same length of time as the first input clock signal ICLKa, and the phase of the second input clock signal ICLKb is inverted. In this case, the size of the clock multiplexing circuit 11a may become larger, and the power consumption of the clock multiplexing circuit 11a may increase. Also, since the inverter strings of different numbers are configured to cause delays of the same length, the yield of the pulse generator PG may be reduced.

Fig. 6 is a circuit diagram illustrating the clock multiplexing circuit of fig. 3, according to some embodiments. Referring to fig. 3 and 6, the clock multiplexing circuit 11b may include a delay matching circuit DMCb and a NAND gate NAND.

The delay matching circuit DMCb may receive the first input clock signal ICLKa and may provide a signal having the same phase as the first input clock signal ICLKa to the first input terminal of the NAND gate NAND. For example, the delay matching circuit DMCb may supply the first input clock signal ICLKa to the first input terminal of the NAND gate NAND through an inverter string including an even number of inverters INV.

The delay matching circuit DMCb may receive the second input clock signal ICLKb and may provide a signal having a phase opposite to that of the second input clock signal ICLKb to the second input terminal of the NAND gate NAND. For example, the delay matching circuit DMCb may supply the second input clock signal ICLKb to the second input terminal of the NAND gate NAND through the inverter string including the odd number of inverters INV and the transmission gate TG.

In some embodiments, the transmission gate TG may include a p-channel metal oxide semiconductor (PMOS) transistor PT and an n-channel metal oxide semiconductor (NMOS) transistor NT connected in parallel. The gate terminal of the PMOS transistor PT may be connected to a ground voltage, and the gate terminal of the NMOS transistor may be connected to a power supply voltage VDD.

The inverter INV may be connected to an output terminal of the NAND gate NAND of the clock multiplexing circuit 11 b. The function of the NAND gate NAND and the inverter INV of the clock multiplexing circuit 11b is similar to that described above, and thus additional description will be omitted to avoid redundancy.

In some embodiments related to fig. 6, as in the description given with reference to fig. 5, the output pulse signal OPUL may be switched in response to edges of the input clock signal having the same type. The output pulse signal OPUL switched in response to the input clock signal having the same type of edges will be described in detail with reference to fig. 8.

However, according to the embodiment of fig. 6, the transmission gate TG may be used to cause inverter delays of the same length without reversing the phase of the pass signal. In this case, since the clock signal passes through the transmission gate TG, the slopes of the rising edge and the falling edge of the clock signal may decrease. Thus, the accuracy of the operation of the electronic device operating based on the clock signal may be reduced.

Fig. 7 is a circuit diagram illustrating the clock multiplexing circuit of fig. 3, according to some embodiments. Referring to fig. 7, the clock multiplexing circuit 110a may receive the first input clock signal ICLKa through the first node N1. The clock multiplexing circuit 110a may receive the second input clock signal ICLKb through the second node N2.

In some embodiments, the first node N1 may be connected to a first input terminal of the clock multiplexing circuit 110 of fig. 3, the second node N2 may be connected to a second input terminal of the clock multiplexing circuit 110 of fig. 3, and the third node N3 may be connected to an output terminal of the clock multiplexing circuit 110 of fig. 3.

The clock multiplexing circuit 110a may include a first transistor TRa and a second transistor TRb. The channel of the first transistor TRa may be different in type from the channel of the second transistor TRb. For example, the first transistor TRa may be a PMOS transistor and the second transistor TRb may be an NMOS transistor. However, the present disclosure is not limited thereto.

The first transistor TRa may be connected between the first node N1 and the third node N3. The first transistor TRa may operate in response to a logic level of the second node N2. For example, the first transistor TRa may operate in response to a logic level of the second input clock signal ICLKb input to the second node N2.

In detail, when the second input clock signal ICLKb is at a logic low level, the first transistor TRa may be turned on. In this case, the logic level of the third node N3 may be set to the logic level of the first node N1 (i.e., the logic level of the first input clock signal ICLKa). In contrast, when the second input clock signal ICLKb is at a logic high level, the first transistor TRa may be turned off.

The second transistor TRb may be connected between the third node N3 and the ground voltage. The second transistor TRb may operate in response to a logic level of the second node N2. For example, the second transistor TRb may operate in response to a logic level of the second input clock signal ICLKb input to the second node N2.

In detail, when the second input clock signal ICLKb is at a logic high level, the second transistor TRb may be turned on. In this case, the logic level of the third node N3 may be set to a logic level (i.e., a logic low level) corresponding to the ground voltage. In contrast, when the second input clock signal ICLKb is at a logic low level, the second transistor TRb may be turned off.

The logic level of the output pulse signal OPUL may correspond to the logic level of the third node N3. That is, when the second input clock signal ICLKb is at a logic high level, the logic level of the output pulse signal OPUL may be at a logic low level. When the second input clock signal ICLKb is at a logic low level, the logic level of the output pulse signal OPUL may be the same as that of the first input clock signal ICLKa.

That is, according to the embodiment of fig. 7, as in the description given with reference to fig. 5 and 6, the clock multiplexing circuit 110a may generate the output pulse signal OPUL that is switched in response to the input clock signal having the same type of edges. The output pulse signal OPUL switched in response to the input clock signal having the same type of edges will be described in detail with reference to fig. 8.

In particular, according to the embodiment of fig. 7, the clock multiplexing circuit 110a can generate the output pulse signal OPUL that transitions at the same timing as the output pulse signal shown in fig. 5 and 6 without including a plurality of inverters INV, transmission gates TG, and NAND gates NAND. That is, according to some embodiments of the present disclosure, a clock multiplexing circuit including a smaller number of transistors that performs the same function may be provided. In the clock multiplexing circuit 110a according to some embodiments of the present disclosure, the complexity of the circuit may be reduced, the cost required to manufacture the circuit may be reduced, the circuit area may be reduced, the power consumption of the circuit may be reduced, and the heat generation of the circuit may be reduced.

Fig. 8 is a timing diagram illustrating the relationship between the first and second input clock signals and the output pulse signal associated with the clock multiplexing circuits of fig. 5-7. In fig. 8, the horizontal axis represents time, and the vertical axis represents the logic level of the signal.

In fig. 8, some embodiments in which the first input clock signal ICLKa and the second input clock signal ICLKb are included in a four-phase clock signal will be described. That is, the first input clock signal ICLKa and the second input clock signal ICLKb may have a phase difference of 90 degrees (i.e., 360/n degrees when "n" is 4).

Each of the clock multiplexing circuits 11a, 11b, and 110a of fig. 5 to 7 may generate the output pulse signal OPUL switched in response to rising edges of the first input clock signal ICLKa and the second input clock signal ICLKb. The logic levels of the first input clock signal ICLKa and the second input clock signal ICLKb in the period Tp and at the 0 th time t0, the first time t 1, the second time t2, and the fourth time t4 are similar to those described with reference to fig. 4, and thus, additional description will be omitted to avoid redundancy.

The second input clock signal ICLKb may transition from a logic high level to a logic low level at a third time t 3. In this case, the time interval from the third time t3 to the second time t2 may be 1/4 of the period Tp.

Referring to fig. 7 and 8, the logic level of the output pulse signal OPUL may correspond to the logic level of the third node N3. That is, when the second input clock signal ICLKb is at a logic high level, i.e., in a period of time between the first time t 1 and the third time t3, the output pulse signal OPUL may be at a logic low level. When the second input clock signal ICLKb is at a logic low level, i.e., in a period of time between the 0 th time t0 and the first time t 1 and between the third time t3 and the fourth time t4, the logic level of the output pulse signal OPUL may be the same as that of the first input clock signal ICLKa. For example, the output pulse signal OPUL may be at a logic high level in a period between the 0 th time t0 and the first time t 1, and may be at a logic low level in a period between the third time t3 and the fourth time t 4.

That is, according to the embodiment of fig. 7, the output pulse signal OPUL may transition to a logic high level at the 0 th time t0 in response to the rising edge of the first input clock signal ICLKa. Further, the output pulse signal OPUL may transition to a logic low level at the first time t 1 in response to a rising edge of the second input clock signal ICLKb. When the rising edge time point of the clock signal is accurately determined (i.e., even if an error occurs at the falling edge time point), the clock multiplexing circuit 110 can operate correctly.

Fig. 9 is a timing chart showing a relationship between the clock signal and the pulse signal of fig. 1 when the clock multiplexing circuit of fig. 1 is implemented with the clock multiplexing circuit of fig. 7. In fig. 9, some embodiments where "n" is 4 (i.e., clock multiplexer 100 operates based on four-phase clock signals) will be representatively described. In fig. 9, the horizontal axis represents time, and the vertical axis represents the logic level of the signal.

Referring to fig. 1 and 7 to 9, the first to fourth clock signals CLK1 to CLK4 may have the same period Tp and may have different phases. For example, the first clock signal CLK1 may transition to a logic high level at a 0 th time t0, the second clock signal CLK2 may transition to a logic high level at a first time t 1, the third clock signal CLK3 may transition to a logic high level at a second time t2, and the fourth clock signal CLK4 may transition to a logic high level at a third time t 3.

Each of the first to fourth clock multiplexing circuits 110_1 to 110_4 may be implemented as the same as the clock multiplexing circuit 110a of fig. 7. Each of the first to fourth clock multiplexing circuits 110_1 to 110_4 may receive two adjacent clock signals and may generate an output pulse. For example, the first clock multiplexing circuit 110_1 may receive the first clock signal CLK1 and the second clock signal CLK2 and may generate the first pulse signal PUL1. In this case, the first pulse signal PUL1 may be at a logic low level in a period from t 1 to t3 in which the second clock signal CLK2 is at a logic high level. In the period in which the second clock signal CLK2 is at the logic low level, i.e., in the period from t0 to t 1 and the period from t3 to t4, the logic level of the first pulse signal PUL1 may be the same as that of the first clock signal CLK 1. For example, the first pulse signal PUL1 may be at a logic high level in a period from t0 to t 1 and may be at a logic low level in a period from t3 to t 4.

As in the above description, the second to fourth clock multiplexing circuits 110_2 to 110_4 may generate the second to fourth pulse signals PUL2 to PUL4, respectively. In this case, two pulse signals adjacent to each other among the first to fourth pulse signals PUL1 to PUL4 may have a phase difference of 90 degrees. For example, from the 0 th time t0 to the first time t 1, the first pulse signal PUL1 may be at a logic high level, from the first time t 1 to the second time t2, the second pulse signal PUL2 may be at a logic high level, from the second time t2 to the third time t3, the third pulse signal PUL3 may be at a logic high level, and from the third time t3 to the fourth time t4, the fourth pulse signal PUL4 may be at a logic high level.

In some embodiments, the first to fourth pulse signals PUL1 to PUL4 may be used as control signals for electronic circuits placed outside the pulse generator PG. For example, the first to fourth pulse signals PUL1 to PUL4 may be used for the operation of the input/output circuits of the memory device. Some embodiments of the operation of the pulse signal of the present disclosure for the input/output circuit of the memory device will be described in detail with reference to fig. 15 to 19.

Fig. 10 is a circuit diagram illustrating the clock multiplexing circuit of fig. 3 according to some embodiments of the present disclosure. Referring to fig. 10, the clock multiplexing circuit 110b may receive the first input clock signal ICLKa through the fourth node N4. The clock multiplexing circuit 110b may receive the second input clock signal ICLKb through the fifth node N5.

In some embodiments, the fourth node N4 may be connected to the first input terminal of the clock multiplexing circuit 110 of fig. 3, the fifth node N5 may be connected to the second input terminal of the clock multiplexing circuit 110 of fig. 3, and the sixth node N6 may be connected to the output terminal of the clock multiplexing circuit 110 of fig. 3.

The clock multiplexing circuit 110B may include a third transistor TRc and a fourth transistor TRd. The channel of the third transistor TRc can be different in type from the channel of the fourth transistor TRd. For example, the third transistor TRc may be an NMOS transistor and the fourth transistor TRd may be a PMOS transistor. However, the present disclosure is not limited thereto.

The third transistor TRc can be connected between the fourth node N4 and the sixth node N6. The third transistor TRc can operate in response to a logic level of the fifth node N5. For example, the third transistor TRc may operate in response to a logic level of the second input clock signal ICLKb input to the fifth node N5.

In detail, when the second input clock signal ICLKb is at a logic high level, the third transistor TRc can be turned on. In this case, the logic level of the sixth node N6 may be set to the logic level of the fourth node N4 (i.e., the logic level of the first input clock signal ICLKa). In contrast, when the second input clock signal ICLKb is at a logic low level, the third transistor TRc can be turned off.

The fourth transistor TRd may be connected between the sixth node N6 and the power supply voltage VDD. The fourth transistor TRd may operate in response to a logic level of the fifth node N5. For example, the fourth transistor TRd may operate in response to a logic level of the second input clock signal ICLKb input to the fifth node N5.

In detail, when the second input clock signal ICLKb is at a logic low level, the fourth transistor TRd may be turned on. In this case, the logic level of the sixth node N6 may be set to a logic level (i.e., a logic high level) corresponding to the power supply voltage VDD. In contrast, when the second input clock signal ICLKb is at a logic high level, the fourth transistor TRd may be turned off.

The logic level of the output pulse signal OPUL may correspond to the logic level of the sixth node N6. That is, when the second input clock signal ICLKb is at a logic low level, the logic level of the output pulse signal OPUL may be at a logic high level. When the second input clock signal ICLKb is at a logic high level, the logic level of the output pulse signal OPUL may be the same as that of the first input clock signal ICLKa.

That is, the output pulse signal OPUL may be switched in response to edges of the input clock signal having the same type. For example, the output pulse signal OPUL may transition from a logic high level to a logic low level at a falling edge time point of the first input clock signal ICLKa, and may transition from a logic low level to a logic high level at a falling edge time point of the second input clock signal ICLKb.

In some embodiments, an inverter may also be connected to the sixth node N6 of the clock multiplexing circuit 110 b. In this case, the signal output through the inverter may be referred to as an "inverted output pulse signal". Next, the inverted output pulse signal will be described in detail with reference to fig. 11.

Fig. 11 is a timing diagram illustrating a relationship between first and second input clock signals and an output pulse signal associated with the clock multiplexing circuit of fig. 10. In fig. 11, the horizontal axis represents time, and the vertical axis represents the logic level of a signal.

The logic levels of the first and second input clock signals ICLKa and ICLKb in the period Tp and at the 0 th to fourth times t0 to t4 are similar to those described with reference to fig. 4, and thus, additional description will be omitted to avoid redundancy.

Referring to fig. 10 and 11, the logic level of the output pulse signal OPUL may correspond to the logic level of the sixth node N6. When the second input clock signal ICLKb is at a logic low level, i.e., in a period of time between the 0 th time t0 and the first time t 1 and between the third time t3 and the fourth time t4, the output pulse signal OPUL may be at a logic high level. When the second input clock signal ICLKb is at a logic high level, i.e., in a period between the first time t 1 and the third time t3, the logic level of the output pulse signal OPUL may be the same as that of the first input clock signal ICLKa. For example, the output pulse signal OPUL may be at a logic high level in a period between the first time t 1 and the second time t2, and may be at a logic low level in a period between the second time t2 and the third time t 3.

That is, according to the embodiment of fig. 10, the output pulse signal OPUL may transition to a logic low level at the second time t2 in response to the falling edge of the first input clock signal ICLKa. Further, the output pulse signal OPUL may transition to a logic high level at the third time t3 in response to a falling edge of the second input clock signal ICLKb.

In some embodiments, the logic level of the inverted output pulse signal opul_bar may be opposite to the logic level of the output pulse signal OPUL. For example, the inverted output pulse signal opul_bar may transition to a logic high level at the second time t2 in response to a falling edge of the first input clock signal ICLKa. Further, the inverted output pulse signal opul_bar may transition to a logic low level at the third time t3 in response to a falling edge of the second input clock signal ICLKb.

Fig. 12 is a timing chart showing a relationship between the clock signal and the pulse signal of fig. 1 when the clock multiplexing circuit of fig. 1 is implemented with the clock multiplexing circuit of fig. 10. In fig. 12, the horizontal axis represents time, and the vertical axis represents the logic level of a signal.

In fig. 12, some embodiments where "n" is 4 (i.e., clock multiplexer 100 operates based on four-phase clock signals) will be representatively described. Referring to fig. 1 and 10 to 12, the first to fourth clock signals CLK1 to CLK4 may have the same period Tp and may have different phases. The logic levels of the first to fourth clock signals CLK1 to CLK4 at the 0 th to fourth times t0 to t4 are similar to those described with reference to fig. 4, and thus, additional description will be omitted to avoid redundancy.

Each of the first to fourth clock multiplexing circuits 110_1 to 110_4 may be implemented as the same as the clock multiplexing circuit 110b of fig. 10. Each of the first to fourth clock multiplexing circuits 110_1 to 110_4 may receive two adjacent clock signals and may generate an output pulse. For example, the first clock multiplexing circuit 110_1 may receive the first clock signal CLK1 and the second clock signal CLK2 and may generate the first pulse signal PUL1. In this case, when the second input clock signal ICLKb is at a logic low level, i.e., in a period of time between the 0 th time t0 and the first time t 1 and between the third time t3 and the fourth time t4, the first pulse signal PUL1 may be at a logic high level. When the second input clock signal ICLKb is at a logic high level, i.e., in a period of time between the first time t 1 and the third time t3, the logic level of the first pulse signal PUL1 may be the same as that of the first input clock signal ICLKa. For example, the first pulse signal PUL1 may be at a logic high level in a period from t 1 to t2, and may be at a logic low level in a period from t2 to t 3.

As in the above description, the second to fourth clock multiplexing circuits 110_2 to 110_4 may generate the second to fourth pulse signals PUL2 to PUL4, respectively. In this case, two pulse signals adjacent to each other among the first to fourth pulse signals PUL1 to PUL4 may have a phase difference of 90 degrees. For example, from the second time t2 to the third time t3, the first output signal PUL1 may be at a logic low level, from the third time t3 to the fourth time t4, the second output signal PUL2 may be at a logic low level, from the 0 th time t0 to the first time t 1, the third output signal PUL3 may be at a logic low level, and from the first time t 1 to the second time t2, the fourth output signal PUL4 may be at a logic low level.

In some embodiments, the first to fourth pulse signals PUL1 to PUL4 may be used as control signals of electronic circuits placed outside the pulse generator PG (i.e., outside the pulse generator PG). For example, the first to fourth pulse signals PUL1 to PUL4 may be used for the operation of the input/output circuits of the memory device. However, the present disclosure is not limited thereto. For example, signals whose phases are opposite to those of the first to fourth pulse signals PUL1 to PUL4 may be used for the operation of the input/output circuits of the memory device.

Fig. 13 is a timing diagram illustrating a relationship between first and second input clock signals and an output pulse signal associated with the clock multiplexing circuit of fig. 7. In fig. 13, the horizontal axis represents time, and the vertical axis represents the logic level of a signal.

In fig. 13, some embodiments in which the first input clock signal ICLKa and the second input clock signal ICLKb are included in eight-phase clock signals will be described. That is, the first input clock signal ICLKa and the second input clock signal ICLKb may have a phase difference of 45 degrees (i.e., 360/n degrees when "n" is 8).

For example, referring to fig. 7 and 13, the first input clock signal ICLKa and the second input clock signal ICLKb may have a period Tp. In detail, the first input clock signal ICLKa may transition from a logic low level to a logic high level at a tenth time t 10 and may transition from a logic low level to a logic high level at an eighteenth time t 18. In this case, the time interval from the tenth time t 10 to the eighteenth time t 18 may be the same as the period Tp.

The second input clock signal ICLKb may transition from a logic low level to a logic high level at an eleventh time t 11. In this case, the time interval from the tenth time t 10 to the eleventh time t 11 may be 1/8 of the period Tp.

The output pulse signal opll may be switched in response to rising edges of the first input clock signal ICLKa and the second input clock signal ICLKb (i.e., a logic level of the output pulse signal opll may be transitioned in response to rising edges of the first input clock signal ICLKa and the second input clock signal ICLKb). For example, the output pulse signal opll may transition from a logic low level to a logic high level at a tenth time t 10 when the first input clock signal ICLKa transitions from a logic low level to a logic high level, and may transition from a logic high level to a logic low level at an eleventh time t 11 when the second input clock signal ICLKb transitions from a logic low level to a logic high level.

The output pulse signals generated based on two adjacent clock signals included in the four-phase clock signal are described with reference to fig. 8, and the output pulse signals generated based on two adjacent clock signals included in the eight-phase clock signal are described with reference to fig. 13. However, the present disclosure is not limited thereto. The clock multiplexing circuit 110 according to some embodiments of the present disclosure may generate an output pulse signal based on both an n-phase clock signal ("n" is any integer) and a four-phase clock signal. In detail, the clock multiplexing circuit 110 may generate an output pulse signal based on two adjacent clock signals (i.e., clock signals having a phase difference of 360/n degrees) included in the n-phase clock signals.

In fig. 14, some embodiments where "n" is 8 (i.e., the clock multiplexer 100 operates based on eight-phase clock signals) will be representatively described.

Referring to fig. 1, 7, 13 and 14, the first to eighth clock signals CLK1 to CLK8 may have the same period Tp and may have different phases. For example, the first to eighth clock signals CLK1 to CLK8 may transition to a logic high level at tenth to seventeenth times t 10 to t 17, respectively.

Each of the first to eighth clock multiplexing circuits 110_1 to 110_8 may be implemented as the same as the clock multiplexing circuit 110a of fig. 7. Each of the first to eighth clock multiplexing circuits 110_1 to 110_8 may receive two adjacent clock signals and may generate an output pulse. For example, the first clock multiplexing circuit 110_1 may receive the first clock signal CLK1 and the second clock signal CLK2 and may generate the first pulse signal PUL1. In this case, the first pulse signal PUL1 may be at a logic low level in a period of time t 11 to t 15 in which the second clock signal CLK2 is at a logic high level. In the period in which the second clock signal CLK2 is at the logic low level, that is, in the period from t 10 to t 11 and the period from t 15 to t 18, the logic level of the first pulse signal PUL1 may be the same as that of the first clock signal CLK 1. For example, the first pulse signal PUL1 may be at a logic high level in a period from t 10 to t 11, and may be at a logic low level in a period from t 15 to t 18.

As in the above description, the second to eighth clock multiplexing circuits 110_2 to 110_2 may generate the second to eighth pulse signals PUL2 to PUL8, respectively. In this case, two pulse signals adjacent to each other among the first to eighth pulse signals PUL1 to PUL8 may have a phase difference of 45 degrees. The period in which each of the first to eighth pulse signals PUL1 to PUL8 is at the logic high level is determined in a similar manner to the above, and thus, an additional description will be omitted to avoid redundancy.

Fig. 15 is a block diagram illustrating a memory system according to some embodiments of the present disclosure. Referring to fig. 15, a memory system 1000 may include a memory device 1100 and a memory controller 1200.

The memory controller 1200 may include a clock generator 1210. The clock generator 1210 may generate the reference clock RCLK.

The memory controller 1200 may send the reference clock RCLK and the command/address CA to the memory device 1100. In response to the command/address CA, the memory device 1100 may store data provided from the memory controller 1200 or may provide data to the memory controller 1200.

In some embodiments, the memory device 1100 may be a Dynamic Random Access Memory (DRAM), and the memory controller 1200 and the memory device 1100 may communicate with each other based on a Double Data Rate (DDR) interface. However, the present disclosure is not limited thereto. The memory device 1100 may be one of various memory devices such as a Static Random Access Memory (SRAM), a Synchronous Dynamic Random Access Memory (SDRAM), a Magnetic Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM), and a resistive random access memory (ReRAM), and the memory device 1100 and the memory controller 1200 may communicate with each other based on various interfaces such as a low power double data rate (lpdddr) interface, a Universal Serial Bus (USB) interface, a multimedia card (MMC) interface, a Peripheral Component Interconnect (PCI) interface, a peripheral component interconnect express (PCI-e) interface, an Advanced Technology Attachment (ATA) interface, a Serial Advanced Technology Attachment (SATA) interface, a Parallel Advanced Technology Attachment (PATA) interface, a Small Computer System Interface (SCSI), and an Enhanced Small Disk Interface (ESDI).

The memory device 1100 may include a pulse generator PG. The pulse generator PG may generate n-phase clock signals based on the reference clock RCLK. That is, the pulse generator PG may generate first to nth clock signals having phases different from each other based on the reference clock RCLK.

In some embodiments, the first to nth clock signals generated by the pulse generator PG may have the same period as the reference clock RCLK.

The pulse generator PG may include first to nth clock multiplexing circuits 1161_1 to 1161—n. The pulse generator PG may generate first to nth pulse signals based on the n-phase clock signal. For example, the first to nth clock multiplexing circuits 1161_1 to 1161—n may generate the first to nth pulse signals, respectively, based on the n-phase clock signals.

Each of the first to nth clock multiplexing circuits 1161_1 to 1161—n may receive two clock signals adjacent to each other among clock signals included in the n-phase clock signals, and may generate a pulse signal. Each of the first to nth clock multiplexing circuits 1161_1 to 1161—n may generate a pulse signal switched in response to edges of two clock signals having the same type.

In some embodiments, the pulse generator PG may be implemented similar to the pulse generator PG described with reference to fig. 1 and 2. Further, each of the first to nth clock multiplexing circuits 1161_1 to 1161—n may be implemented by the clock multiplexing circuit 110a described with reference to fig. 7 or the clock multiplexing circuit 110b described with reference to fig. 10. Hereinafter, in order to describe more briefly, some embodiments for realizing each of the first to nth clock multiplexing circuits 1161_1 to 1161—n using the clock multiplexing circuit 110a described with reference to fig. 7 will be representatively described. However, the present disclosure is not limited thereto.

Fig. 16 is a block diagram illustrating the memory device of fig. 15 in detail. Referring to fig. 15 and 16, the memory device 1100 may include a pulse generator PG, a command/address (CA) decoder 1110, a control logic circuit 1120, a memory cell array 1130, a sense amplifier and write driver 1140, and an input/output circuit 1150.

The pulse generator PG may include a phase shifter PS and a clock multiplexer 1160. The phase shifter PS may receive the reference clock RCLK from the memory controller 1200 through the reference clock PAD pad_rclk. The phase shifter PS may generate an n-phase clock signal based on the reference clock RCLK. The configuration and operation of the pulse generator PG and the phase shifter PS are similar to those described with reference to fig. 1, and thus, additional description will be omitted to avoid redundancy.

The clock multiplexer 1160 may include first to nth clock multiplexing circuits 1161_1 to 1161—n. The first to nth clock multiplexing circuits 1161_1 to 1161—n may output the first to nth pulse signals PUL1 to PULn, respectively, based on the n-phase clock signals.

In detail, each of the first to nth clock multiplexing circuits 1161_1 to 1161—n may receive two clock signals adjacent to each other among clock signals included in the n-phase clock signals and may generate a pulse signal. For example, the first clock multiplexing circuit 1161_1 may generate the first pulse signal PUL1 based on the first clock signal CLK1 and the second clock signal CLK 2. As described above, the kth clock multiplexing circuit 1161—k (k is an integer of 1 or more and (n-1) or less) may generate the kth pulse signal PULk based on the kth clock signal CLKk and the (k+1) th clock signal clkk+1. The nth clock multiplexing circuit 1161—n may generate the nth pulse signal PULn based on the nth clock signal CLKn and the first clock signal CLK 1.

The configuration and operation of the clock multiplexer 1160 and the clock multiplexing circuits 1161_1 to 1161—n are similar to those of the clock multiplexer 100 and the clock multiplexing circuit 110 described with reference to fig. 1 to 14, and thus, additional description will be omitted to avoid redundancy.

The command/address decoder 1110 may receive the command/address CA from the memory controller 1200 through the command/address PAD pad_ca and may decode the received command/address CA.

Control logic 1120 may control the overall operation of memory device 1100 in response to decoded command/address CA. For example, when the command/address CA decoded by the command/address decoder 1110 corresponds to a read command, the control logic circuit 1120 may control the sense amplifier and the write driver 1140 such that the first to mth data D1 to Dm are output in parallel (e.g., simultaneously) from the memory cell array 1130.

The input/output circuit 1150 may receive the first through mth data D1 through Dm. The input/output circuit 1150 may supply the first to mth DATA D1 to Dm to the memory controller 1200 through the DATA PAD pad_data based on the first to nth pulse signals PUL1 to PULn.

The input/output circuit 1150 may include a serializer 1151. The serializer 1151 may sequentially (or serially) supply the first to m-th DATA D1 to Dm to the memory controller 1200 through the DATA PAD pad_data in response to the first to n-th pulse signals PUL1 to PULn. The configuration of the serializer 1151 operating based on the first through n-th pulse signals PUL1 through PULn will be described in detail with reference to fig. 17 and 18.

Fig. 17 is a block diagram illustrating the input/output circuit of fig. 16 in detail. Referring to fig. 15 to 17, the input/output circuit 1150 may include a serializer 1151 and an output data buffer 1152.

The output data buffer 1152 may receive the first through mth data D1 through Dm in parallel. For example, the output data buffer 1152 may receive the first data D1 to m-th data Dm from different sub memory cell arrays of the memory cell array 1130, respectively. That is, the output data buffer 1152 may simultaneously receive the first data D1 to the m-th data Dm. The output data buffer 1152 may temporarily store the first through mth data D1 through Dm thus received. The output data buffer 1152 may supply the stored first to mth data D1 to Dm to the serializer 1151.

The serializer 1151 may include first to nth serial circuits 1151_1 to 1151—n. The first to nth serial circuits 1151_1 to 1151—n may receive the first to nth pulse signals PUL1 to PULn, respectively. Each of the first to nth serial circuits 1151_1 to 1151—n may operate in response to the received pulse signal. For example, when the received pulse signal is at a logic high level, each of the first to nth serial circuits 1151_1 to 1151—n may supply the DATA stored in the output DATA buffer 1152 to the DATA PAD pad_data. In detail, the first serial circuit 1151_1 may supply one of the DATA (e.g., the first DATA D1) stored in the output DATA buffer 1152 to the DATA PAD pad_data in response to the first pulse signal PUL1 of a logic high level. How the serializer 1151 operates according to the logic level of the pulse signal will be described in detail with reference to fig. 18.

Fig. 18 is a timing chart showing DATA output to the DATA PAD pad_data based on the pulse signal of fig. 17. For a more concise description, some embodiments in which "n" and "m" are 4 will be representatively described below. However, the present disclosure is not limited thereto. For example, "n" may be 8. In some embodiments, "n" may be any integer of 4 or greater.

Referring to fig. 17 and 18, DATA supplied to the DATA PAD pad_data, the first clock signal CLK1, and the first to fourth pulse signals PUL1 to PUL4 are shown. In fig. 18, the horizontal axis represents time, and the vertical axis represents the kind of logic state or data.

The first clock signal CLK1 and the first to fourth pulse signals PUL1 to PUL4 may have a period Tp. The first pulse signal PUL1 may be at a logic high level during the first period Ta; the second pulse signal PUL2 may be at a logic high level during the second period Tb; the third pulse signal PUL3 may be at a logic high level during a third period Tc; the fourth pulse signal PUL4 may be at a logic high level during the fourth period Td. In this case, the sum of the lengths of the first to fourth periods Ta to Td may be the same as the length of the period Tp. The transition timings of the logic levels of the first to fourth pulse signals PUL1 to PUL4 are similar to those described with reference to fig. 7 to 9, and thus, additional description will be omitted to avoid redundancy.

The first serial circuit 1151_1 may operate in response to the first pulse signal PUL 1. For example, during the first period Ta in which the first pulse signal PUL1 is at the logic high level, the first serial circuit 1151_1 may output the first DATA D1 to the DATA PAD pad_data. That is, in this case, the first data D1 may be provided to the memory controller 1200 during the first period Ta.

As described above, the second data D2 may be provided to the memory controller 1200 during the second period Tb, the third data D3 may be provided to the memory controller 1200 during the third period Tc, and the fourth data D4 may be provided to the memory controller 1200 during the fourth period Td.

In some embodiments, "m" may be an integer of 4 or greater. In this case, a plurality of data may be serially output through the serial circuit. In some embodiments, "m" may be an integer of 4 or greater.

For a more concise description, in fig. 18, an example case where "n" and "m" are equal is representatively described. However, the present disclosure is not limited thereto. For example, "m" may be an integer multiple of "n". In this case, the first to mth DATA D1 to Dm simultaneously supplied to the output DATA buffer 1152 may be output to the DATA PAD pad_data during the period "m/n".

Fig. 19 is a block diagram showing a memory module to which the memory device of fig. 15 to 18 is applied. Referring to fig. 15 to 19, the memory module 2000 may include a Register Clock Driver (RCD) 2100, a plurality of DRAM devices 2200a to 2200h, and a plurality of data buffers DB. The RCD 2100 may receive a command/address CA and a clock CK from an external device (e.g., a host or a memory controller). In response to the received signal, the RCD 2100 may transmit a command/address CA to the plurality of DRAM devices 2200a to 2200h and may control the plurality of data buffers DB.

The plurality of DRAM devices 2200a to 2200h may be connected to the plurality of data buffers DB through the memory data lines MDQ, respectively. In some embodiments, each of the plurality of DRAM devices 2200 a-2200 h may be implemented with the memory device 1100 of fig. 15-18, and may include a serializer 1151 that operates in response to a pulse signal generated by the clock multiplexing circuit of fig. 7 or 10. The plurality of data buffers DB may transmit and receive data to and from an external device (e.g., a host or a memory controller) through the plurality of data lines DQ.

In some embodiments, the memory module 2000 shown in fig. 19 may have a reduced load dual inline memory module (LRDIMM) form factor. However, the inventive concept is not limited thereto. For example, the memory module 2000 may have a form factor of a Registered DIMM (RDIMM) that does not include a plurality of data buffers DB therein.

According to some embodiments of the present disclosure, a clock multiplexing circuit having a simple structure may be provided. In detail, according to some embodiments of the present disclosure, the manufacturing cost of the clock multiplexing circuit may be reduced, and the clock multiplexing circuit may operate at lower power.

Although the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure as set forth in the following claims.

Claims

1. A clock multiplexing circuit, comprising:

a first transistor between a first input terminal configured to receive a first input clock signal and an output terminal configured to output an output pulse signal, wherein the first transistor is configured to operate based on a logic level of a second input terminal configured to receive a second input clock signal; and

a second transistor located between the output terminal and a first voltage node, wherein the second transistor is configured to operate based on a logic level of the second input terminal,

Wherein the first input clock signal and the second input clock signal have the same period and have different phases, an

Wherein the output pulse signal transitions to a first logic level at a first time when the first input clock signal transitions to the first logic level and transitions to a second logic level at a second time when the second input clock signal transitions to the first logic level.

2. The clock multiplexing circuit of claim 1, wherein the first transistor comprises an n-channel metal oxide semiconductor transistor, the second transistor comprises a p-channel metal oxide semiconductor transistor, and the first voltage node is at a supply voltage.

3. The clock multiplexing circuit of claim 2, wherein the first logic level is lower than the second logic level.

4. The clock multiplexing circuit of claim 1, wherein the first transistor comprises a p-channel metal oxide semiconductor transistor, the second transistor comprises an n-channel metal oxide semiconductor transistor, and the first voltage node is at ground voltage.

5. A clock multiplexing circuit according to claim 3 wherein the first logic level is higher than the second logic level.

6. The clock multiplexing circuit of claim 1, wherein a phase difference between the first input clock signal and the second input clock signal corresponds to a time interval from the first time to the second time.

7. A pulse generator, comprising:

a phase shifter configured to output four-phase clock signals including a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, which are different in phase from each other; and

a clock multiplexer including a first clock multiplexing circuit, a second clock multiplexing circuit, a third clock multiplexing circuit, and a fourth clock multiplexing circuit,

wherein the first clock multiplexing circuit, the second clock multiplexing circuit, the third clock multiplexing circuit, and the fourth clock multiplexing circuit output a first pulse signal, a second pulse signal, a third pulse signal, and a fourth pulse signal having phases different from each other, respectively, based on the four-phase clock signal,

Wherein the first clock multiplexing circuit comprises:

a first transistor located between a first input node configured to receive the first clock signal and an output node, wherein the first transistor is configured to output the first pulse signal at the output node and is configured to operate based on a logic level of a second input node configured to receive the second clock signal; and

a second transistor located between the first output node and a first voltage node, wherein the second transistor is configured to operate based on a logic level of the second input node.

8. The pulse generator of claim 7, wherein the second clock signal lags the first clock signal by 90 degrees,

wherein the third clock signal lags the first clock signal by 180 degrees, an

Wherein the fourth clock signal lags the first clock signal by 270 degrees.

9. The pulse generator of claim 7, wherein the first clock multiplexing circuit is configured to generate the first pulse signal based on the first clock signal and the second clock signal,

Wherein the second clock multiplexing circuit is configured to generate the second pulse signal based on the second clock signal and the third clock signal,

wherein the third clock multiplexing circuit is configured to generate the third pulse signal based on the third clock signal and the fourth clock signal, and

wherein the fourth clock multiplexing circuit is configured to generate the fourth pulse signal based on the fourth clock signal and the first clock signal.

10. The pulse generator of claim 9, wherein the second clock multiplexing circuit comprises:

a third transistor located between the second input node and a second output node, wherein the third transistor is configured to output the second pulse signal and is configured to operate based on a logic level of a third input node configured to receive the third clock signal; and

a fourth transistor located between the second output node and the first voltage node, wherein the fourth transistor is configured to operate based on a logic level of the third input node,

wherein the third clock multiplexing circuit includes:

A fifth transistor located between the third input node and a third output node, wherein the fifth transistor is configured to output the third pulse signal and is configured to operate based on a logic level of a fourth input node configured to receive the fourth clock signal; and

a sixth transistor located between the third output node and the first voltage node, wherein the sixth transistor is configured to operate based on a logic level of the fourth input node, and

wherein the fourth clock multiplexing circuit comprises:

a seventh transistor between the fourth input node and a fourth output node, wherein the seventh transistor is configured to output the fourth pulse signal and is configured to operate based on a logic level of the first input node; and

an eighth transistor located between the fourth output node and the first voltage node, wherein the eighth transistor is configured to operate based on a logic level of the first input node.

11. The pulser of claim 7, wherein the first transistor comprises an n-channel metal oxide semiconductor transistor, the second transistor comprises a p-channel metal oxide semiconductor transistor, and the first voltage node is at a supply voltage.

12. The pulse generator of claim 11, wherein the first pulse signal transitions to a logic low level in response to the first clock signal transitioning to the logic low level and transitions to a logic high level in response to the second clock signal transitioning to the logic low level.

13. The pulser of claim 7, wherein the first transistor comprises a p-channel metal oxide semiconductor transistor, the second transistor comprises an n-channel metal oxide semiconductor transistor, and the first voltage node is at a ground voltage.

14. The pulse generator of claim 13, wherein the first pulse signal transitions to a logic high level in response to the first clock signal transitioning to the logic high level and transitions to a logic low level in response to the second clock signal transitioning to the logic high level.

15. A memory device, comprising:

a clock multiplexer configured to generate first to nth pulse signals based on n-phase clock signals including the first to nth clock signals, where n is a natural number equal to or greater than 4;

A memory cell array configured to output first data to mth data in parallel, wherein m is a natural number equal to or greater than 4; and

a serializer configured to sequentially output the first to mth data to a first data pad in response to the first to nth pulse signals,

wherein the clock multiplexer includes first to nth clock multiplexing circuits configured to generate the first to nth clock signals, respectively,

wherein the first clock multiplexing circuit comprises:

a first transistor between a first input node and a first output node, wherein the first transistor is configured to output the first pulse signal and is configured to operate based on a logic level of a second input node that receives a second clock signal from among the first to nth clock signals; and

16. The memory device according to claim 15, wherein the kth clock multiplexing circuit is configured to generate the kth pulse signal based on the kth clock signal and the (k+1) th clock signal, wherein k is a natural number of 1 or more and (n-1) or less, and

Wherein the nth clock multiplexing circuit is configured to generate the nth pulse signal based on the nth clock signal and the first clock signal.

17. The memory device of claim 16, wherein the kth clock multiplexing circuit comprises:

a (2 k-1) th transistor located between a kth input node and a kth output node, wherein the (2 k-1) th transistor is configured to output the kth pulse signal and is configured to operate based on a logic level of a (k+1) th input node that receives the (k+1) th clock signal; and

a 2 k-th transistor located between the k-th output node and the first voltage node, wherein the 2 k-th transistor is configured to operate based on a logic level of the (k+1) -th input node,

wherein the nth clock multiplexing circuit includes:

a (2 n-1) th transistor located between an n-th input node and an n-th output node, wherein the (2 n-1) th transistor is configured to output the n-th pulse signal and is configured to operate based on a logic level of the first input node configured to receive the first clock signal; and

a 2 n-th transistor located between the n-th output node and the first voltage node, wherein the 2 n-th transistor is configured to operate based on a logic level of the first input node.

18. The memory device of claim 15, wherein the first transistor comprises a p-channel metal oxide semiconductor transistor, the second transistor comprises an n-channel metal oxide semiconductor transistor, and the first voltage node is at a ground voltage, and

wherein the first pulse signal transitions to a logic high level in response to the first clock signal transitioning to the logic high level and transitions to a logic low level in response to the second clock signal transitioning to the logic high level.

19. The memory device of claim 18, wherein the serializer comprises:

an output data buffer configured to receive the first data to the mth data in parallel; and

first to nth serial circuits configured to receive the first to nth pulse signals, respectively,

wherein each of the first to nth serial circuits is configured to: one of the first to m-th data is transferred from the output data buffer to the first data pad during a period in which a corresponding one of the first to n-th pulse signals is at the logic high level.

20. The memory device of claim 19, wherein m is an integer multiple of n.