CN117436401B

CN117436401B - Data processing method, device, equipment and storage medium of power state table

Info

Publication number: CN117436401B
Application number: CN202311752591.3A
Authority: CN
Inventors: 刘子奇
Original assignee: Innoda Chengdu Electronic Technology Co ltd
Current assignee: Innoda Chengdu Electronic Technology Co ltd
Priority date: 2023-12-19
Filing date: 2023-12-19
Publication date: 2024-03-12
Anticipated expiration: 2043-12-19
Also published as: CN117436401A

Abstract

The application discloses a data processing method, a device, equipment and a storage medium of a power state table, wherein the method comprises the following steps: creating a characterization power line and selecting a target power line from the design power lines; traversing the design power line, and mapping the related power line corresponding to the target power line obtained by traversing into the characterization power line, wherein the related power line is the design power line belonging to the same physical wiring with the target power line. The identification scheme of the design power line with the same power supply characteristic can quickly identify the design power lines with different names but the same power supply characteristic under different levels, and provides possibility for quick acquisition of the subsequent power supply state.

Description

Data processing method, device, equipment and storage medium of power state table

Technical Field

The application belongs to the technical field of integrated circuit design, and particularly relates to a data processing method, device and equipment of a power state table and a storage medium.

Background

Since the voltage has a quadratic relation to the power effect, reducing the operating voltage when designing a chip with low power consumption is one of the common methods for reducing the power consumption of the chip.

To accurately express the low power design intent of chip designers, unified power format (Unified Power Format, UPF) files were introduced in the related art. It allows the designer to create power networks and power domains and associate their corresponding voltages and voltage ranges at each power domain. In the case where high-speed operation is not required, the corresponding power domain may be operated at a lower voltage, and if operation is not required for a specific period of time, the power domain may be placed in a shutdown or sleep mode.

The precise control of each power domain is independent of the design power lines (upf _net) in each level in each power domain, but in practical application, it is often difficult to identify the design power lines with the same power characteristics at different levels.

Disclosure of Invention

The embodiment of the application provides a data processing method, device and equipment of a power state table and a computer readable storage medium, aiming at providing an identification scheme of a design power line with the same power supply characteristics.

In one aspect, an embodiment of the present application provides a data processing method of a power state table, where the method includes:

creating a characterization power line and selecting a target power line from the design power lines;

traversing the design power line, and mapping the traversed associated power line corresponding to the target power line into the representation power line, wherein the associated power line is the design power line belonging to the same entity wiring with the target power line.

Optionally, the characterization power line is attribute information describing a physical trace to which the design power line belongs.

Optionally, the characterization power line is configured in the mapped attributes of the design power lines, and the characterization power line is attribute information describing the physical routing to which the design power line belongs.

Optionally, after traversing the design power line, the method further includes:

and adding the characterization power line in the attribute of the associated power line corresponding to the target power line.

Optionally, after mapping the traversed associated power line corresponding to the target power line into the characterization power line, the method further includes:

and configuring the attribute of the design power line corresponding to the mapping through the characterization power line.

Optionally, the associated power line is a design power line connected to the same port as the target power line.

Optionally, the associated power line includes:

the design power line is directly connected with the target power line at the same port;

and the design power line indirectly connected with the target power line via the port.

And storing the characterization power line and the associated power line mapped by the characterization power line into a cache.

and assigning the characterization power line as the associated power line with the highest design level.

The step of traversing the design power line and mapping the associated power line corresponding to the target power line obtained by traversing into the representation power line comprises the following steps:

mapping the target power line as the associated power line into the characterization power line;

sequentially searching first power lines in one-by-one layers along the direction close to the top design layer, and mapping the first power lines in one-by-one layers as the associated power lines into the characterization power lines, wherein the first power lines are design power lines connected with the associated power lines in the direction close to the top design layer;

and sequentially searching second power lines in one-by-one layers along the direction close to the design bottom layer, and mapping the second power lines in one-by-one layers into the characterization power lines as associated power lines, wherein the second power lines are design power lines connected with the first power lines in the design top layer in the direction close to the design bottom layer.

Optionally, the sequentially searching the first power lines in the successive layers along the direction close to the top layer of the design, and mapping the first power lines in the successive layers as the associated power lines into the characterization power lines includes:

determining a first power line in a previous level adjacent to the level where an associated power line is located through a first port, wherein the first port is a port which is connected with the associated power line and is close to a top design layer, and the first power line is a design power line which is adjacent to the associated power line and is connected with the first port;

mapping the first power line into the characterization power line as a new associated power line;

starting with a new associated power line, determining the next adjacent first power line through a first port along the direction of the top layer of the design, and mapping the determined first power line serving as the associated power line into the characterization power line until the first power line in the top layer of the design serving as the associated power line is mapped into the characterization power line.

Optionally, after determining, through the first port, the first power line in the previous level adjacent to the level where the associated power line is located, the method further includes:

Stopping searching the first power lines in the hierarchy-by-hierarchy mode under the condition that the mapped target representation power lines exist in the first power lines, and configuring the searched attribute of the related power lines according to the target representation power lines

In the case that the first power line does not have a mapped target representation power line, performing the steps of: the first power line is mapped into the characterization power line as a new associated power line.

Optionally, the sequentially searching for the second power lines in the successive layers along the direction close to the bottom layer of the design, and mapping the second power lines in the successive layers as associated power lines into the characterization power lines, including:

determining a second power line in the next adjacent level of the level where the current associated power line is located through a second port, wherein the second port is a port which is connected with the associated power line and is close to the design bottom layer, and the second power line is a design power line which is connected with the first power line in the design top layer in the direction close to the design bottom layer, is adjacent to the associated power line and is connected with the second port;

mapping the second power line into the characterization power line as a new associated power line;

Starting with a new associated power line, determining a next adjacent second power line through a second port along the direction of the design bottom layer, and mapping the determined second power line serving as the associated power line into the characterization power line until the second power line at the design bottom layer serving as the associated power line is mapped into the characterization power line.

Optionally, after the mapping the first power line within the hierarchy-by-hierarchy as the associated power line into the characterization power line, the method further includes:

stopping traversing the design power line under the condition that the first power line in the design top layer belongs to the characterization power line, and configuring the searched attribute of the related power line according to the first power line in the design top layer;

in case the first power supply line within the design top layer does not belong to the characterization power supply line, the steps are performed: and sequentially searching second power lines in the successive layers along the direction close to the bottom layer of the design, and mapping the second power lines in the successive layers into the characterization power lines as associated power lines.

Storing the target power line into an empty stack;

executing a spring stack operation to obtain spring stack elements;

under the condition that the design power line connected with the spring stack element and not traversed is searched, searching a first power line which is close to the direction which is closer to the top layer of the design than the spring stack element from the design power lines connected with the spring stack element and not traversed;

mapping the first power line into the characterization power line as a new associated power line, storing the first power line into a stack, and returning to continue to execute the spring stack operation;

and returning to continue to execute the spring stack operation until the spring stack element cannot be obtained under the condition that the design power line connected with the spring stack element and not traversed is not found.

Optionally, the traversing the design power line and mapping the traversed associated power line corresponding to the target power line into the characterization power line includes:

storing the target power line into an empty stack;

executing a spring stack operation to obtain spring stack elements;

under the condition that the layer level of the spring stack element is higher than the value of the representation power line, the representation power line is assigned to be the spring stack element, and search operation is carried out;

Executing the search operation under the condition that the level of the spring stack element is not higher than the value of the representation power line;

under the condition that the design power line which is connected with the spring stack element and is not traversed is searched, the design power line which is connected with the spring stack element and is not traversed is used as an associated power line corresponding to the target power line to be stored in a stack, and the spring stack operation is returned to be continuously executed, so that a new spring stack element is obtained;

and returning to continue to execute the spring stack operation under the condition that the design power line connected with the spring stack element and not traversed is not found, so as to obtain a new spring stack element until the spring stack element cannot be obtained.

storing the target power line into an empty stack;

executing a spring stack operation to obtain spring stack elements;

storing the design power line which is connected with the spring stack element and is not traversed into a stack under the condition of searching the design power line which is connected with the spring stack element and is not traversed, and returning to continue to execute spring stack operation to obtain a new spring stack element;

Returning to continue to execute the spring stack operation under the condition that the design power line connected with the spring stack element and not traversed is not found, so as to obtain a new spring stack element until the spring stack element cannot be obtained;

and assigning the design power line with the highest level in all the pop stack elements obtained by the pop stack operation to the representation power line, and mapping all the pop stack elements obtained by the pop stack operation as the associated power lines corresponding to the target power line to the representation power line.

Optionally, before the creating the characterization power line, the method further includes:

responding to a query request of a user, and determining a query target corresponding to the query request, wherein the query target comprises at least two design power lines;

under the condition that the characterization power line corresponding to the query target is not queried, executing the steps of: a characterization power line is created.

Optionally, after the determining the query target corresponding to the query request, the method further includes:

and under the condition that the characterization power line corresponding to the query target is queried, reading the characterization power line corresponding to the query target from a cache.

Optionally, the method further comprises:

Acquiring power state tables corresponding to a plurality of design power lines respectively mapped by the characterization power lines;

and combining different power supply state information in the power supply state table by taking the characterization power supply line as an index to obtain a target power supply state table.

Optionally, the merging processing is performed on different power state information in the power state table by using the characterization power line as an index to obtain a target power state table, including:

in the same power state table, taking the representation power line as a first index, and carrying out combination processing on the power state information corresponding to the first index to obtain an updated power state table;

and combining the power state information corresponding to the second index by taking the characterization power line as the second index among different power state tables to obtain the target power state table.

Optionally, after taking the characterization power line as the first index in the same power state table, the method further includes:

checking the power state information corresponding to the first index;

feeding back error reporting information to the user under the condition that the power state information corresponding to the first index is not matched;

And executing the steps under the condition that the power state information corresponding to the first index is matched: and merging the power state information corresponding to the first index to obtain the updated power state table.

Optionally, the merging processing is performed on the power state information corresponding to the second index by taking the characterization power line as the second index between different power state tables to obtain the target power state table, including:

extracting two power state tables from different power state tables;

taking the characterization power line as a second index, and combining the extracted power state information corresponding to the second index in the two power state tables to obtain an intermediate power state table;

in the case that no remaining power state tables exist in different power state tables, the intermediate power state table is the target power state table;

and under the condition that the rest power state tables exist in different power state tables, continuously extracting two power state tables from the different power state tables and the middle power state table, continuously executing the step of taking the characterization power line as a second index, and combining the power state information corresponding to the second index in the extracted two power state tables to obtain the middle power state table.

Optionally, the merging processing is performed on the power state information corresponding to the second index in the extracted two power state tables by using the characterization power line as the second index to obtain an intermediate power state table, including:

taking the characterization power line as a second index, and checking the extracted power state information corresponding to the second index in the two power state tables;

feeding back error reporting information to the user under the condition that the power state information corresponding to the second index is not matched;

and executing the steps under the condition that the power state information corresponding to the second index is matched: and merging the extracted power state information corresponding to the second index in the two power state tables to obtain an intermediate power state table.

Optionally, after the obtaining the intermediate power state table, the method further includes:

storing the intermediate power state table into a cache;

the continuing extracts two power state tables from the different power state tables and the intermediate power state table, including:

in case the extracted two power state tables comprise the intermediate power state table, the intermediate power state table is read from the cache.

Optionally, after the obtaining the target power state table, the method further includes:

and according to the target power state table and the characterization power line, checking the correctness of the chip design to obtain a checking result.

and screening out the power state information irrelevant to the query target in the target power state table.

In another aspect, an embodiment of the present application provides a data processing apparatus of a power state table, where the apparatus may include:

the creation module is used for creating the characterization power line;

a selection module for selecting a target power line from the design power lines;

the traversing module is used for traversing the design power line;

and the mapping module is used for mapping the related power line corresponding to the target power line obtained through traversing into the representation power line, wherein the related power line is the design power line belonging to the same entity wiring with the target power line.

In yet another aspect, an embodiment of the present application provides a data processing apparatus of a power state table, including:

a processor and a memory storing computer program instructions;

The steps of a data processing method of a power state table implementing the above aspects when the processor executes computer program instructions.

In yet another aspect, embodiments of the present application provide a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the steps of the data processing method of the power state table of the above aspect.

In yet another aspect, embodiments of the present application provide a computer program product comprising a computer program which, when executed by a processor, implements the steps of the data processing method of the power state table of the above aspect.

The embodiment of the application comprises the steps of creating a characterization power line and selecting a target power line from design power lines; traversing the design power line, and mapping the related power line corresponding to the target power line obtained by traversing into the representation power line, wherein the related power line is the design power line belonging to the same entity wiring with the target power line. The concept of the representation power line is introduced, the associated power line corresponding to the target power line obtained by traversing the design power line can be mapped into the representation power line, the design power line which belongs to one entity wiring is obtained by means of mapping management of the representation power line, an operation object corresponding to the entity wiring is formed in practical application, namely, the design power lines with different names but the same power characteristics under different levels can be quickly identified by setting the representation power line, and the possibility is provided for quick acquisition of the subsequent power state.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described, and it is possible for a person skilled in the art to obtain other drawings according to these drawings without inventive effort.

FIG. 1 is a flow chart of a data processing method of a power state table according to one embodiment of the present application;

FIG. 2 is a schematic diagram of a design involved in a data processing method of a power state table according to an embodiment of the present application;

FIG. 3 is another flow chart of a data processing method of a power state table according to one embodiment of the present application;

FIG. 4 is a flow chart of a data processing method of a power state table according to one embodiment of the present application;

FIG. 5 is a detailed flowchart of a method for processing data in a power state table according to an embodiment of the present application, where a design power line is traversed, and an associated power line corresponding to a target power line obtained by the traversing is mapped to a characterization power line;

FIG. 6 is a schematic diagram of an alternative flow path traversing in a direction approaching a top layer of a design in a data processing method of a power state table according to one embodiment of the present application;

FIG. 7 is a schematic diagram of an optional refinement flow of S530 in a data processing method of a power state table according to an embodiment of the present application;

FIG. 8 is a schematic diagram of an optional refinement flow in the data processing method of the power state table according to an embodiment of the present application, in which the first power lines are sequentially searched in a hierarchical level by hierarchical level, and the first power lines in the hierarchical level by hierarchical level are mapped as associated power lines into the characterization power lines;

FIG. 9 is a schematic diagram of an optional refinement flow in a data processing method of a power state table according to an embodiment of the present application, where a design power line is traversed, and an associated power line corresponding to a target power line obtained by the traversing is mapped to a characterization power line;

FIG. 10 is a schematic diagram of an optional refinement flow in a data processing method of a power state table according to an embodiment of the present application, where a design power line is traversed, and an associated power line corresponding to a target power line obtained by the traversing is mapped to a characterization power line;

FIG. 11 is an exemplary design hierarchy chart of a power domain V3 after enlargement when a target power state table is used for checking the correctness of chip design in a data processing method of a power state table according to an embodiment of the present application;

FIG. 12 is a target power state table referred to by the example design hierarchy diagram of FIG. 11;

FIG. 13 is a schematic diagram of a process of merging power state information corresponding to a first index to obtain an updated power state table according to a data processing method of a power state table according to an embodiment of the present application, wherein the first index is a representation power line mapped by a design power line;

FIG. 14 is a schematic diagram illustrating a process of merging power state information corresponding to a second index by using a characterization power line as the second index among different power state tables in a data processing method of a power state table according to an embodiment of the present disclosure;

FIG. 15 is a detailed flowchart of a target power state table obtained by merging power state information corresponding to a second index, which represents a power line between different power state tables in the data processing method of a power state table according to an embodiment of the present application;

FIG. 16 is a schematic diagram illustrating a process of merging the power state tables corresponding to the intermediate power state table V3@V4 and the power domain V2 after the intermediate power state table V3@V4 is obtained in the data processing method of the power state table according to one embodiment of the present application;

FIG. 17 is an exemplary diagram of a power state table in which a power state conflict is found when merging power state information in a data processing method according to one embodiment of the present application;

FIG. 18 is a schematic diagram of a data processing apparatus according to another embodiment of the present application;

fig. 19 is a schematic structural view of a data processing apparatus according to still another embodiment of the present application.

Description of the reference numerals:

1801-create a module; 1802-select module; 1803-traversing module; 1804-a mapping module;

1901-a processor; 1902-a memory; 1903-communication interface; 1910-bus.

Detailed Description

Features and exemplary embodiments of various aspects of the present application are described in detail below to make the objects, technical solutions and advantages of the present application more apparent, and to further describe the present application in conjunction with the accompanying drawings and the detailed embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative of the application and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by showing examples of the present application.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

Chips (chips) are small in size and are widely used in computers and other electronic devices. The chip is a silicon chip that connotes an integrated circuit (Integrated Circuit, IC). In which an integrated circuit is formed by integrating a number of commonly used electronic components, such as resistors, capacitors, and transistors, and the wiring therebetween, through a semiconductor process.

To implement the design of an integrated circuit, designers typically require the use of computer aided design (CAD-Computer Aided Design, CAD) software and/or electronic design automation (Electronic Design Automation, EDA) software.

During the design of an integrated circuit, a designer may create a high-level behavioral description of the integrated circuit device using a hardware description language (Hardware Description Language, HDL), which may include Verilog HDL and VHDL, for example.

To illustrate an integrated circuit design using EDA software, EDA software may generally receive HDL data for an integrated circuit device and convert the HDL data to netlists at various levels of abstraction.

In order to conveniently perform low-Power design and verification of the chip, the industry provides a Power supply design definition which cannot be described by the HDL data by introducing UPF files on the basis of the HDL data, and describes the low-Power design intention (Power Intent) of a user by using some standard sentences.

It should be noted that, the UPF file may refer to a Power consumption management file written in IEEE Standard for Design and Verification of Low-Power, energy Aware Electronic System, which is also called a unified Power source format file. The UPF file may describe the low power consumption intent in the chip design.

The introduction of a UPF file enables chip designers to create power networks and power domains while associating voltages and their voltage ranges with the individual power domains and defining correlations between the individual power domains. In addition, UPF files also support the creation of various low power policies, such as retention, quarantine, and level shifting.

With the coordination and support of the UPF file, an integrated circuit designer can verify the low-power management strategy related to the power state control of the RTL (Register Transfer Level ) code file and the UPF file at the same time in the verification stage of HDL, so that the power management problem can be found timely in early design, the design accuracy can be ensured, the development period can be shortened, and the design iteration can be reduced.

In this design format, the voltage is associated with a particular power domain through the concept of "supply status". The "supply status" of the different power domains is correlated by a power status table (Power State Table, PST).

The PST thus plays a key role in low power design behavior control, which gathers all legal voltage state combinations in the hardware design, and the chip designer can analyze the PST with implementation tools to effectively determine whether isolation and level shifting in the design meets specifications or requirements.

In the prior art, the UPF file is used to precisely control each power domain, and besides the function of the power state table, the power domain of the UPF file is not separated from the design power line (UPF _net) belonging to each level, but in actual application, it is often difficult to identify the design power lines with the same power characteristics at different levels.

Accordingly, in order to solve the above-mentioned technical problems, the present application proposes a data processing method, apparatus, device and computer readable storage medium of a power state table, and the data processing method of the power state table of the embodiments of the present application is described first with reference to the accompanying drawings.

Referring to fig. 1, fig. 1 is a schematic flow chart of an optional method for processing data in a power state table according to an embodiment of the present application. In this example, the method may include:

s110, creating a representation power line and selecting a target power line from design power lines;

and S120, traversing the design power line, and mapping the traversed associated power line corresponding to the target power line into the representation power line, wherein the associated power line is the design power line belonging to the same entity wiring with the target power line.

The above method may be applied to an integrated circuit design terminal, for example, the integrated circuit design terminal may be a computer, and for example, the integrated circuit design terminal may be loaded with at least one of EDA software and CAD software. The EDA software is hereinafter exemplified as being loaded with the above-described integrated circuit design terminal.

In data processing, EDA software may read the UPF file, for example, by executing a read_ UPF command to read the UPF file, thereby obtaining design power lines at different design level ranges (Scope). In some examples, corresponding individual power state tables created based on these design power lines may also be obtained.

One design power line can be randomly selected from the obtained design power lines to serve as a target power line, the target power line is mainly used for subsequent traversal searching of the associated power line, and the target power line can be included in the associated power line or can serve as a traversal starting power line.

In addition, before and after reading the UPF file, a characterization power line can be created, and it should be noted that, at this time, the characterization power line does not map any design power line, and its mapping relationship is null.

And traversing the obtained design power lines to obtain all the design power lines belonging to the same physical wiring with the target power line, and mapping all the design power lines belonging to the same physical wiring obtained by traversing into the created characterization power lines after the traversing is completed or in the traversing process.

It should be noted that, according to the scheme, the related power lines are obtained by traversing the design power lines, so that traversing operations in different design hierarchy ranges are realized, the relation among the design power lines distributed in different designs is found, and mapping record is carried out by means of the concept of the introduced characterization power lines. Therefore, any current design power line can be inquired, and the corresponding representation power line can be found when the current design power line is used as an associated power line, so that all design power lines which have association relations with the current design power line under different levels and belong to the same entity wiring can be obtained quickly, and therefore the design power lines with different names but the same power characteristics under different levels can be identified quickly. On the other hand, by creating the representation power line and managing the mapping of the representation power line, an operation object corresponding to the actual physical wiring is formed, and unified management and operation of the power state are facilitated.

It should be noted that, in some alternative examples, the above-mentioned characterizing power line is attribute information describing a physical trace to which the design power line belongs.

In this example, by defining the characterization power line as attribute information describing the physical routing to which the design power line belongs, and combining with creating the characterization power line, mapping the traversed associated power line corresponding to the target power line to the characterization power line, attribute information about the physical routing to which the characterization power line belongs is configured for each existing design power line in the UPF file, and when precise control of each power domain is achieved, the design power line belonging to the same physical routing with the same power characteristic can be quickly and conveniently identified from the mapping recorded by the characterization power line.

Illustratively, the characterization power line may be stored in the form of a database or file.

Alternatively, the above-described characterization power line may be configured directly in the attribute of the several design power lines to which the characterization power line maps, with reference to other attributes of the design power lines, as an example. That is, the characterization power line can be configured in the mapped attributes of the design power lines, and the characterization power line is the attribute information describing the physical routing to which the design power line belongs.

In these examples, the characterization power supply lines are directly configured in the attribute information of each mapped design power supply line by introducing the characterization power supply lines as attribute information, so that the entity wiring information of each design power supply line is conveniently and quickly read by means of the characterization power supply lines recorded in the attribute.

In some optional examples, after traversing the design power line, the characterization power line may be further added to the attribute of the associated power line corresponding to the target power line.

This example may be performed where the associated power line has been configured with attributes, e.g., a mapped characterization power line may be added to the attributes of one associated power line after each traversal. The attribute of the characterization power line can be added to the attribute of each associated power line after all the associated power lines are obtained through traversing.

In these examples, after traversing the design power line, adding the characterization power line to the attribute of all the associated power lines corresponding to the target power line is obtained by traversing, so as to update the attribute information of each associated power line, so that the attribute information of each associated power line obtained by traversing is added and has the attribute information capable of describing the entity trace to which the corresponding design power line belongs, thereby facilitating the subsequent unified operation, management and identification of the design power line with the entity trace association relationship.

In other alternative examples, after step S120 is performed, the attribute of the corresponding mapped design power line may also be configured by the characterization power line.

This example may be performed in the case where the associated power line is not configured with an attribute. For example, the traversed associated power line may be mapped into the characterization power line, and then the characterization power line may be used to configure the properties of the design power line for the traversed associated power line, whereby the characterization power line may be configured among the mapped properties of several of the design power lines.

In these examples, with the configuration of attribute information including characterizing the power lines, an operational object corresponding to the physical trace of the entity is created, facilitating subsequent unified operation, management, and identification of the design power lines having physical trace associations.

It should also be noted that the above-mentioned associated power line may be further configured as a design power line connected to the same port as the target power line.

It will be appreciated that each associated power line corresponding to a target power line has the same physical routing, and that each associated power line mapped with the same characterization power line is electrically connected to each other at the physical level, so in an integrated circuit design terminal on which EDA-like software is loaded, the definition of an associated power line can also be understood as a design power line connected to the same port as the target power line.

The connection may be a direct connection or an indirect connection, for example.

Illustratively, the above-described associated power line may include:

and the design power line is indirectly connected with the target power line through the port.

The design power line indirectly connected to the target power line through the above-mentioned port may be understood as a design power line indirectly connected to the same port as the target power line, and the indirect connection may be understood as a design power line which can be finally connected to the same port through a combination of the design power line and the port which are sequentially arranged.

For example, referring to fig. 2, where V1 to V4 are different power domains, assuming that the selected target power line is N210, the design power line directly connected to the same port as the target power line N210 may include N110 in the V1 power domain and N310 in the V3 power domain.

The design power lines indirectly connected to the target power line via the above-described ports may include N220 in the V2 power domain, N320 in the V3 power domain, and N410 in the V4 power domain.

In these examples, further explanation and definition of attributing to the same physical routing as the target power line is made in terms of different connection relationships corresponding to the target power line, helping to find all associated power lines by traversal, perfecting the search and management of design power lines with the same power characteristics.

In some alternative examples, referring to fig. 3, after mapping the traversed associated power line corresponding to the target power line into the characterization power line in step S120, step S130 may also be performed.

And S130, storing the characterization power line and the associated power line mapped by the characterization power line into a cache.

It should be noted that, after the relevant power line corresponding to the target power line is obtained through traversing, and the relevant power line obtained through traversing is mapped to the characterization power line, the characterization power line and the relevant power line mapped by the characterization power line may also be stored in a storage module of the integrated circuit design terminal, where the storage module may be a cache (cache), or may be other memories or storage units.

Illustratively, taking S130 as an example, a temporary cache list may be created in the EDA software cache, and the target power line, the traversed associated power line corresponding to the target power line, and the representation power line of the associated power line map may be stored in the cache list.

In these examples, by storing the results of the traversal in a cache, e.g., forming a temporary cache list, to facilitate subsequent data lookup processing based on characterizing the power line, a quick response can be achieved, helping to save computation time to arrive at the final power state table.

In some alternative examples, referring to fig. 4, after mapping the traversed associated power line corresponding to the target power line into the characterization power line in step S120, step S140 may also be performed.

And step S140, assigning the characterization power line as the associated power line with the highest design level.

The present example further defines the actual parameter values that characterize the power lines mapped by the associated power lines. It should be noted that the associated power line with the highest design level is the source of all the design power lines with the same power characteristics, similar to the starting position of the corresponding physical trace. The associated power line is used as the assignment for representing the power line, so that the attribute of the design power line which is attributed to each different entity wiring can be clearly distinguished.

In some optional examples of S120, the associated power line corresponding to the target power line may be obtained by traversing in a stack manner, or may be obtained by traversing in a manner of searching for the power lines one by one along the top and bottom design layer directions, or may be obtained by traversing in a manner of combining the stack and the searching for the design layer.

For example, referring to fig. 5, traversing the design power line and mapping the traversed associated power line corresponding to the target power line into the characterization power line may include:

s510, mapping the target power line into the characterization power line as the associated power line;

and S520, sequentially searching first power lines in the successive layers along the direction close to the top layer of the design, and mapping the first power lines in the successive layers as the associated power lines into the characterization power lines.

The first power line is a design power line connected with the associated power line in a direction approaching to the top design layer. It should be noted that, the design top layer refers to a design level at the top layer, i.e. a design level without a parent instance.

And S530, sequentially searching second power lines in the successive layers along the direction close to the bottom layer of the design, and mapping the second power lines in the successive layers as associated power lines into the characterization power lines.

The second power line is a design power line connected with the first power line in the design top layer in the direction close to the design bottom layer.

The above design base layer is also called a leaf level, and refers to a design base layer without sub-instances. In the IEEE written association specification, the association of leaf levels is defined as "leaf-level cell: an instance that has no descendants, or an instance that is a soft or hard macro".

The present example may select an arbitrary hierarchy of design power lines as the target power line and then map the target power line as the associated power line into the created characterization power line. And further obtaining the design power lines connected with the target power line in different hierarchical ranges in the UPF file in an upward and/or downward traversing mode, and mapping the design power lines connected with the target power line into the representation power lines.

It should be noted that the selection of the upward traversal, the downward traversal, or the upward traversal first and then the downward traversal is related to the position of the target power line and the characterization of whether the power line is already present.

For example, when the selected target power line is at the top level of the design, only a downward traversal may be required.

For another example, when the selected target power line is located at the bottom layer of the design, and the design power line connected with the target power line at the top layer of the design already has a corresponding characterization power line, mapping of all associated power lines can be completed only by an upward traversal manner.

In this example, before or after mapping the target power line as the associated power line to the characterization power line, whether the current target power line is at the top design level may be determined, if the current target power line is not at the top design level, the method may traverse to a higher design level until the associated power line in the top design level is found, and then traverse to a lower design level based on the associated power line in the top design level. Otherwise, if the current target power line is at the top design level, the current target power line can be traversed directly to the lower design level.

In this example, by first traversing the design layers one by one in the direction of the top design layer, the design power lines connected to the target power line are searched, that is, the first power lines of the design layers one by one are obtained, and the first power lines are mapped as associated power lines into the characterization power lines. Then under the condition of traversing to obtain the first power lines of the top design layer, sequentially searching the design power lines connected with the first power lines in the top design layer in the direction close to the bottom design layer in a layer-by-layer manner, namely traversing along the direction of the bottom design layer to obtain the second power lines of the layer-by-layer design.

In the traversal process, the mapping of the characterization power line is continuously updated, and finally, a set of design power lines with the same power characteristics is formed, so that the characterization power line which is finally mapped can be used as attribute information for describing the physical wiring to which the design power line belongs, and an operation object corresponding to the physical wiring is formed in actual application. In addition, the present example also provides an alternative implementation scheme of traversing the design power line and mapping the traversed associated power line corresponding to the target power line to the characterization power line.

The scheme of traversing one by one to obtain the associated power lines corresponding to the target power lines can be realized by means of ports connected between the design power lines of different design layers.

For example, referring to fig. 6, in traversing in a direction approaching the top layer of the design, the following steps S610 to S630 may be performed.

S610, determining a first power line in a layer adjacent to the layer where the associated power line is located through the first port.

The first port is a port which is connected with the associated power line and is close to the top design layer, and the first power line is a design power line which is adjacent to the associated power line and is connected with the first port.

And S620, mapping the first power line into the characterization power line as a new associated power line.

S630, starting with a new associated power line, determining the next adjacent first power line through a first port along the direction of the top design layer, and mapping the determined first power line as the associated power line into the characterization power line until the first power line in the top design layer is mapped as the associated power line into the characterization power line.

I.e., after performing a traversal lookup at any design level, a traversal lookup to a higher design level may be performed. When the current design level is used for explanation, the first port can be determined firstly during traversing and searching of a design level higher than the current design level, then the first power line connected with the associated power line of the current design level is determined through the first port, and the determined design power line is used as a new associated power line to be mapped into the representation power line.

And the new associated power line can be taken as an initial line, the design level of the new associated power line is updated to the current design level, and then the traversal search operation to the higher design level is continuously executed until the first power line in the design top layer is used as the associated power line to be mapped into the characterization power line, at the moment, all the associated power lines in the direction along the design top layer are obtained, the mapping operation of the associated power lines in the direction of the design top layer is completed, and the mapping relation of the characterization power lines is expanded.

Optionally, after determining, in S610, the first power line in the previous level adjacent to the level where the associated power line is located through the first port, the method may further include:

s640, judging whether the first power line has a mapped target representation power line or not; if yes, go to step S650; if not, step S620 is performed.

S650, stopping searching the first power lines in the layers one by one, and configuring the searched attribute of the related power line according to the target characteristic power line.

In this example, since the first power line obtained by previous traversal is connected to the current first power line through the first port, that is, has the same power characteristic, belongs to the same physical trace on the chip, and the attribute information of the current first power line or the cache records the target representation power line mapped by the current first power line, the first power line obtained by previous traversal should also be mapped to the target representation power line mapped by the current first power line, that is, the target representation power line may be configured as the attribute of all the found associated power lines.

It should be noted that, in this case, the situation of updating a part of the power domain or a part of the design power line is considered, when the mapped target representation power line of the first power line is found, the operation of continuing to find the first power line in the design hierarchy one by one is stopped, and then the attribute of all the related power lines found at this time is configured by using the found target representation power line, so that the found design power line and the part of the design power line mapped by the previous target representation power line can be related, and the mapping management of the target representation power line is perfected.

If the attribute information of the current first power line or the target representation power line of the mapping is not recorded in the cache, that is, the representation power line describing the entity routing information to which the current first power line belongs does not exist in all the recorded representation power lines, the attribute information of the entity routing to which the current first power line belongs needs to be defined, so that the traversal can be continued.

In the examples, after the first power line is searched each time, according to the result of whether the mapping target representation power line exists in the current first power line or not, whether the current first power line has attribute information capable of describing the physical wiring to which the current first power line belongs is quickly confirmed, so that under the condition that the target representation power line exists, attribute configuration of all the searched associated power lines is quickly and conveniently carried out through the target representation power line, the mapping of the associated power lines in all the design level ranges is not required to be completed, the overall data processing speed is improved, and the updating of the mapping relation between the representation power lines and the design power lines is also realized.

In still other alternative examples, referring to fig. 7 together with fig. 5, S530 described above may include S710 through S730.

S710, determining a second power line in the next adjacent level of the level where the current associated power line is located through the second port.

The second port is a port connected with the associated power line and close to the design bottom layer, and the second power line is a design power line which is connected with the first power line in the design top layer in the direction close to the design bottom layer, is adjacent to the associated power line and is connected with the second port.

And S720, mapping the second power line into the characterization power line as the new associated power line.

And S730, starting with a new associated power line, determining a next adjacent second power line through a second port along the direction of the design bottom layer, and mapping the determined second power line as the associated power line into the characterization power line until the second power line at the design bottom layer is mapped as the associated power line into the characterization power line.

The associated power line includes a target power line and a design power line directly connected to the target power line through a port, and also includes the design power line indirectly connected to the target power line through the port. Therefore, the second power lines of other power domains/other design layers connected by the first power line of the design top layer also belong to the associated power lines, and after the first power line of the design top layer is found, the second power lines are searched by traversing in a direction close to the design bottom layer by taking the associated power line of the design top layer as a starting point, and finally, each second power line from the design top layer to the design bottom layer is mapped into the representation power line, so that the mapping management of the representation power lines in each design layer is completed.

For example, please continue to refer to fig. 2, where V1 to V4 are different power domains, assuming that the selected target power line is N210, on the basis of determining that the associated power line in the top layer of the design is N110, a second power line may be searched for in the direction of the bottom layer of the design, and finally the second power lines that may be determined through the second port include N220, N320, N410, and N420, where N220, N320, N410, and N420 may be mapped into the created characterization power lines.

In these examples, after the first power line in the top layer of the design is found, the second power lines are continuously found through the second ports one by one along the direction close to the bottom layer of the design, so that the finding of the associated power lines in all design layers can be realized, and the finding is comprehensive and has wide coverage range.

In still other alternative examples, after mapping the first power line within the hierarchy as the associated power line into the characterization power line, the method may further include the steps of:

and stopping traversing the design power line under the condition that the first power line in the design top layer belongs to the characterization power line, and configuring the searched attribute of the related power line according to the first power line in the design top layer.

And under the condition that the first power lines in the top layer of the design do not belong to the characterization power lines, sequentially searching the second power lines in the successive layers along the direction close to the bottom layer of the design, and mapping the second power lines in the successive layers as associated power lines into the characterization power lines.

The present example may find whether or not there is a characterization power line assigned to the first power line in the top layer of the design from all the recorded characterization power lines, if the characterization power line assigned to the first power line in the top layer of the design is found, it indicates that the first power line in the top layer of the design belongs to the characterization power line, and all the second power lines connected to the first power line in a direction close to the bottom layer of the design have completed attribute configuration related to the attributed physical routing, and may not need to traverse to the direction of the bottom layer of the design. Otherwise, if the characterization power line assigned as the first power line in the top layer of the design is not found from all the recorded characterization power lines, the created characterization power line and the attribute configuration related to the physical routing to which the power signal lines are not attributed are indicated, and the second power line can be continuously found in the layer-by-layer along the direction close to the bottom layer of the design.

In these examples, under the condition that the first power line of the design top layer is found, by firstly confirming whether the first power line of the design top layer belongs to the characterization power line and then deciding whether to continue to traverse to the design bottom layer to find the second power line, the attribute configuration of the entity trace to which the design power line belongs can be efficiently completed, meanwhile, the data processing flow is simplified as a whole, and resources are saved.

It will be appreciated that in addition to the above-mentioned approach of traversing the lookup associated power lines along a design level by design level, traversing may also be implemented using a stack technique.

Illustratively, referring to fig. 8, the stack technique may be applied in the process of searching for the first power line, that is, the process of sequentially searching for the first power line in a hierarchical level and mapping the first power line in the hierarchical level as the associated power line into the characterization power line along the direction close to the top layer of the design may include:

and S810, storing the target power line into an empty stack.

S820, executing a spring stack operation to obtain spring stack elements.

And S830, searching a first power line in a direction closer to a top layer of the design than the bullet stack element from the design power lines which are connected with the bullet stack element and are not traversed under the condition that the design power lines which are connected with the bullet stack element and are not traversed are searched.

And S840, mapping the first power line into the characterization power line as a new associated power line, storing the first power line into a stack, and returning to continue to execute the pop operation.

S850, returning to continue to execute the spring stack operation until the spring stack element cannot be obtained under the condition that the design power line connected with the spring stack element and not traversed is not found.

The stack is a last-in first-out data structure, an empty stack can be prepared in the initial condition, a selected target power line is stored in the stack, and the stack flicking operation can be sequentially executed subsequently. The pop operation in this example acts to pop the associated power line at the top of the stack, which is the pop element.

It should be noted that, in this example, the first power line near the top layer of the design is mainly searched by means of the stack technology. When a spring stack operation is performed to obtain a spring stack element, a design power line connected with the spring stack element can be searched. For example, the search of the design power line can be realized through the port connected with the spring stack element, and the specific search process can refer to the foregoing, which is not repeated herein.

In the case of finding out the design power lines to which the spring stack elements are connected, the design power lines that have not been found out before can be screened out of these. If all the design power lines are searched, returning to continue to execute the spring stack operation until the spring stack operation cannot obtain the spring stack element.

If the design power lines which are not searched for before can be screened out from the design power lines, a design power line with the highest design level can be selected from the design power lines which are not searched for and traversed, and the design power line is used as a first power line which is connected with the spring stack element and is close to the top layer direction of the design.

The first power line may be further mapped as a new associated power line into the characterization power line, while a push operation may also be performed to store the first power line. And continuing to perform new pop operation by means of a stack technology until the pop operation cannot obtain the pop element.

Illustratively, continuing with fig. 2 as an example, the target power line may be stored in an empty stack, and after the first pop operation, a pop element N210 may be obtained. The design power lines N310 and N110 to which the spring stack element N210 is connected may then be obtained by a lookup operation. Before the searching operation, both N310 and N110 are not searched or traversed, where the first power line near the top-level direction of the design is N110, N110 may be stored as a new associated power line in the stack, and the pop element N110 is popped through the second pop operation.

At this time, the design power lines connected to the pop element N110 are N210 and N220 through the search operation, where the N210 has been traversed, the non-traversed design power line is N220, but the pop element N110 is closer to the top-level direction than the design power line N220, at this time, the first power line is not found, the pop element N110 is actually the design power line on the top-level, and the execution of the pop operation can be continued, and the cycle ends because the stack is empty. In addition, the attribute of the characterization power line is assigned as N110, and the characterization power line N110 is configured in all the searched attributes of the first power lines.

In this example, a process of searching for the first power line in the hierarchy by the stack technique and mapping the first power line to the characterization power line is presented, and mapping management of the design power line having the same power characteristic in the direction near the top layer of the design can be rapidly realized.

The stack technique may also be applied, for example, in the lookup process of all associated power lines. For example, referring to fig. 9, the process of traversing the design power line and mapping the traversed associated power line corresponding to the target power line into the characterization power line may include:

S910, storing the target power line in an empty stack.

S920, performing a spring stack operation to obtain spring stack elements.

And S930, assigning the representation power line as the spring stack element and executing the search operation under the condition that the layer level of the spring stack element is higher than the value of the representation power line.

And S940, executing the searching operation under the condition that the level of the bullet stack element is not higher than the value of the representation power line.

And S950, under the condition that the design power line which is connected with the spring stack element and is not traversed is searched, storing the design power line which is connected with the spring stack element and is not traversed into a stack as an associated power line corresponding to the target power line, and returning to continue to execute spring stack operation to obtain a new spring stack element.

S960, returning to continue to execute the spring stack operation under the condition that the design power line connected with the spring stack element and not traversed is not found, and obtaining a new spring stack element until the spring stack element cannot be obtained.

The main differences between this example and the example shown in fig. 8 are as follows:

1. after the pop operation is performed to obtain the pop element, the level of the pop element is compared with the current value of the characterization power line, and the purpose is to update the current value of the characterization power line through the comparison result in the process of searching all the design power lines connected with the target power line, and finally assign the characterization power line to the design power line with the highest design level, so that the assignment of the characterization power line can be accurately performed.

2. In this example, the first power line and the second power line are not distinguished, but after the search operation, all the design power lines which are connected by all the spring stack elements and have not been traversed are stored in the stack, so that the search of all the design power lines related to the target power line can be completed at one time without distinguishing the traversing direction.

It should be noted that, when there are multiple design power lines connected to the spring stack element and not traversed, that is, there are multiple associated power lines, the sequence of storing the multiple design power lines in the stack may be random storage, or may be sequential storage according to the level of the associated power lines.

To better illustrate the implementation of the present example, the traversal scheme provided by the present example is still illustrated by way of example in fig. 2. If the target power line selected from the design power lines is N210, the current characterization power line can be assigned as N210, and then N110 and N310 which are connected with N210 and are not traversed can be searched from the design power lines, and N110 and N310 are stored in a stack.

If N110 and N310 are stored in the stack sequentially, the new stack element obtained by performing the stack pop operation is N310, and the search operation may be performed according to the stack element N310. Because the level where N310 is located is the design bottom layer, and N210 connected to the stack element N310 has been traversed, when N310 is used as a stack element, there is no design power line connected to it and not traversed, and the stack operation can be continuously performed, so as to obtain a new stack element N110.

The new spring stack element N110 is located at a higher layer level than the current value N210 of the characterization power line, so that the characterization power line can be reassigned to N110, and the search operation can be continuously performed according to N110.

The design power line connected with the spring stack element N110 and not traversed can be found to be N220, because the level of N220 is lower than the value N110 of the current characterization power line, the characterization power line keeps the current assignment, and the push operation can be performed to store the design power line N220 in the stack.

After the pop operation is performed again, a new pop element N220 may be obtained. Because the level of the spring stack element N220 is not higher than the current value N110 representing the power line, the value representing the power line is not updated, and a search operation can be performed according to the spring stack element N220 to find the design power lines N320 and N410 which are connected with the spring stack element N220 and are not traversed.

Design power lines N320 and N410 are at a lower level than the value N110 representing the power line, so the value of the representing power line is also maintained as N110, and N320 and N410 are actually design power lines in the design base layer, so no non-traversed design power line connected with N320/N410 exists, namely the value of the final representing power line is N110, and the associated power lines representing the power line mapping are all the design power lines stored in the stack.

In these examples, the process of finding the associated power lines in a hierarchy by hierarchy and determining the assignments characterizing the power lines is presented by introducing a stack technique that does not need to distinguish between traversal directions, enabling mapping management of design power lines having the same power characteristics in different design hierarchies to be quickly implemented.

For example, referring to fig. 10, a stacking technique may be applied in a process of searching all associated power lines, for example, traversing the design power line, and mapping the traversed associated power line corresponding to the target power line into the characterization power line, where the method includes:

s1010, storing the target power line into an empty stack.

S1020, executing a spring stack operation to obtain spring stack elements.

And S1030, storing the design power line which is connected with the spring stack element and is not traversed into a stack under the condition that the design power line which is connected with the spring stack element and is not traversed is found, and returning to continue to execute the spring stack operation to obtain a new spring stack element.

S1040, returning to continue to execute the spring stack operation under the condition that the design power line connected with the spring stack element and not traversed is not found, and obtaining a new spring stack element until the spring stack element cannot be obtained.

S1050, assigning a design power line with the highest level in all bullet stack elements obtained by bullet stack operation to the representation power line, and mapping all bullet stack elements obtained by bullet stack operation as associated power lines corresponding to the target power line to the representation power line.

The main difference between this example and the process shown in fig. 9 is that: the present example is simple and convenient in that the values characterizing the power lines are determined and the mapping operations characterizing the power lines are performed after the pop-up of all elements in the stack is completed, as compared to the previous example, which enables all mapping management operations to be completed at once.

In these examples, a process of traversing the design power line by using a stacking technology and mapping the traversed associated power line corresponding to the target power line into the characterization power line is given, so that the design power line which belongs to one entity wiring is obtained by means of mapping management of the characterization power line, an operation object corresponding to the entity wiring is formed in actual application, namely, the design power lines with different names but the same power characteristics under different levels can be quickly identified by setting the characterization power line, and possibility is provided for quick acquisition of a subsequent power state.

In still other optional examples, before creating the characterization power line in S110, the method may further include:

responding to a query request of a user, and determining a query target corresponding to the query request, wherein the query target comprises at least two design power lines; and executing step S110 when the characteristic power line corresponding to the query target is not queried.

It will be appreciated that the foregoing examples may be applied to all the design power line identification schemes of the same power supply feature, and the present example proposes a use scenario based thereon, i.e. using the attribute of characterizing the power line in query merging of a power supply state table and/or checking of power supply state information.

It should be noted that, in addition to being able to read the design power line, the UPF file defines the interrelationship between the power domains, so as to support various low-power policies, such as the creation of policies of retention, isolation, and level conversion. In these low power strategies, voltages are associated with specific power domains through different supply states. The supply states of the different power domains are related to each other by a power state table (Power State Table, PST).

The power state table plays a key role in low-power consumption design, and comprises a combination of all legal voltage states in the hardware circuit design, and a chip designer can analyze the power state table so as to effectively determine whether the power consumption intention in the chip design meets the specification or the requirement.

Currently, there is a corresponding power state table for each power domain of a Chip, such as a System On Chip (SOC). When a state relation query is performed, the related art generally calculates all power state tables and creates a global power state table, thereby providing query state information for a low power inspection tool.

However, for design files with numerous power domains, a solution that forms a global power state table using all power state tables may contain millions of states, resulting in significant run time and memory consumption when performing inspections using low power inspection tools, sometimes even exceeding the upper endurance limit of a single device.

Therefore, when the low-power consumption inspection is performed, the query of the power state information can be performed independently of the global power state table, and the query of the power state information corresponding to the query target can be selectively provided, so that the use of the global power state table is reduced, and the running time and the memory of EDA software are reduced.

When providing the query power state information corresponding to the query target, firstly, a query request of a user can be received, and the query target is determined in response to the query request of the user, wherein the query target can be an interested target selected by the user independently, for example, can be a design power line for requesting to provide related power state information, and the query target generally comprises at least two design power lines, for example, the query target can be between two design power lines and four design power lines.

After the query targets are determined, the application of the characterization power lines corresponding to the query targets can be considered later, but if any query target does not have the corresponding characterization power line, the characterization power line can be created through S110, and the characterization power line corresponding to the query target can be obtained through traversal.

In these examples, an alternative use scenario is presented that characterizes the power line, which can provide a fast and convenient technical means for querying the power state information in the low power inspection.

It should be noted that, in the foregoing example, after mapping the associated power line corresponding to the target power line obtained by traversing into the characterization power line, the characterization power line is also stored in a storage module similar to a cache.

The characterization power line can be used as attribute information for describing the physical routing to which the design power line belongs, so that once the mapped characterization power lines exist in all the design power lines in the query target according to the attribute information of the query target, the characterization power lines corresponding to the query target can be directly read from the storage module similar to the cache.

That is, in an example, after determining the query target corresponding to the query request, the following steps may be performed:

and under the condition that the characterization power line corresponding to the query target is not queried, creating the characterization power line.

In these examples, the characterization power line is only required to be created once in the initial link and to perform mapping relation searching and calculating once, so that the characterization power line can be quickly responded and read from the cache in low-power consumption inspection, and the operation time and the memory overhead of the characterization power line are greatly saved.

In still other alternative examples, the above method may further comprise:

acquiring power state tables corresponding to a plurality of design power lines respectively mapped by the characterization power lines; and combining different power supply state information in the power supply state table by taking the characterization power supply line as an index to obtain a target power supply state table.

The method can be executed after the creation and mapping of the characterization power line are completed, and can also be executed according to the characterization power line corresponding to the query target after the query request of the user is received.

As described in the foregoing, when it is required to obtain an effective supply state corresponding to a certain set of power supplies, the related art usually combines different single power state tables, but combines different power state tables, so that the final forming of a complete power state table is a very time-consuming process, which includes a large number of repeated operations or redundant computations unrelated to PST queries, and the final combined power state table occupies excessive storage space.

In order to minimize the time required to obtain the power state information and control the size of the final target power state table, the present example incorporates the generation of the target power state table based on the design power lines associated with the power state information to be obtained.

In the process of generating the target power state table, all design power lines with the same power characteristics as the design power lines related to the power state information can be found according to the representation power lines mapped by the design power lines related to the power state information to be searched, and the power state table under the power domain of the power state table is determined according to all the found design power lines.

The power state table described above may be created prior to acquisition, for example, the power state table may be created prior to creation of the characterization power line. For example, a user may create a specified power state table and define a power consumption intent using the create_pst command.

Illustratively, tables 1 and 2 below show power state tables for the power domain pd_memory and the power domain pd_pro in the UPF file.

Wherein table 1 provides three modes of operation of the power domain, pd_memory, and the effective state voltage combinations between the power lines VDD, vdd_2 and VSS are designed in the three modes of operation.

Table 2 below provides three modes of operation for the power domain, PD_pro, and the effective state voltage combinations between the design power lines VDD, VDD_2 and VSS in the three modes of operation.

TABLE 1 Power State Table of Power Domain PD_memory

TABLE 2 Power State Table of Power Domain PD_pro

It should be noted that, the design power lines under different power domains may have different power state information under different situations, but if they belong to the same physical wiring, they should have consistent power state characteristics, and should be able to combine the power state information, so that the unified mapping management of the design power lines with the same power characteristics by means of the characterization power lines can be performed, with the characterization power lines as indexes, and the power state information corresponding to the design power lines mapped by the indexes is combined to obtain the target power state table corresponding to the characterization power lines.

Still referring to the above table 2, it is assumed that the above table 2 is included in the power state table corresponding to the design power lines mapped by the characterization power lines, and the power vdd and vdd_1 in the power domain pd_pro have the same attribute of the characterization power lines, so that the corresponding characterization power line rep1 may be added after the table heads of the table 2, i.e. the power vdd and the power vdd_1, and the power state information of the two design power lines may be combined with this as an index. And the like, and the target power state table can be obtained after the power state information of the plurality of design power lines which are mapped based on the power state information is combined.

In these examples, the representation power lines mapped by the design power lines to be queried are used as indexes, incremental combination of the power state information is realized, and the finally formed target power state table only comprises the power state information related to the result, namely the finally formed target power state table is smaller, and the calculation of the global power state can be avoided, so that the calculation time consumption in the combination process is shortened.

In some examples, after the target power state table is obtained, power state information in the target power state table that is not related to the query target may be filtered out.

For example, assuming that one query request wants to know the valid states of the design power lines "v1" and "v2", while in performing the merge calculation, there are other power state information characterizing the design power lines mapped by the power lines in some power state tables, so after the incremental merge forms the target power state table, only those power state information related to all the design power lines where "v1" and "v2" belong to the same physical trace may be retained, and for other power states in the target power state table that are not related to the design power lines "v1" and "v2", they may be deleted.

In the examples, the power state information of all design power lines interested by a user in the low-power consumption inspection can be screened out by screening out the power state information which is irrelevant to the query target in the target power state table, so that the adaptation degree and the correlation between the final target power state table and the query request are enhanced, the intake of irrelevant information is reduced, and the memory occupation of the target power state table is reduced.

In still other examples, after the target power state table is obtained, or after the power state information irrelevant to the query target in the target power state table is screened out, the correctness of the chip design is checked according to the target power state table and the characterization power line, so as to obtain a check result.

In this example, a Final target power state table (Final-PST) may be output in response to the aforementioned query request of the user, and the chip design correctness may be checked using the Final target power state table and the characterization power line corresponding to the user query request and the check result may be output.

For example, referring to fig. 11, fig. 11 is an exemplary design hierarchy diagram of the power domain V3 after being enlarged when the chip design correctness checking is performed using the target power state table, it can be found that a logic line is disposed between the instances L1 and L2, so that L1 changes the state of L2.

However, in the target power state table of fig. 12, the power supply of L1 is OFF in three states s43@s33, S23, and S13, but the power supply of L2 is FULL-ON, at this time, the low power inspection tool of the EDA software inspects the design of fig. 11 according to the final output target power state table, and then issues a warning, for example, the inspection result outputs IsoMissingStrat, to indicate that the power states are unequal, and that the design of fig. 11 lacks an isolation policy, and an isolation unit needs to be set.

In these examples, combining the characterization power line with the target power state table for chip design correctness checking enables quick checking for problems in chip design.

It should be noted that, as described in the foregoing related content of table 2, the characterization power line corresponding to the design power line may be added at the name of the design power line located at the header position in the power state table, so that the characterization power line is used as the associated index information to find all the power state information associated with the characterization power line, and the combination of the power state information is achieved by differentiating different power modes.

The above process may also be referred to as a "regularization" process, i.e., parsing the header of the power state table, e.g., the design power line, into a particular object, which in this example is the representation power line mapped by the design power line of the header.

In addition, a characterization power line corresponding to a design power line for which power state information needs to be queried may be added at other positions or in other formats, as long as the association index is enabled.

It should be further noted that the logic of merging power state information in this embodiment is consistent with the related art, and the main difference is that the merging is performed by using the characterization power line as the associated index information in the embodiment of the present application.

Further, when the merging is performed by using the characterization power line as the associated index information, two cases may be included, where the power state information related to the design power line mapped by the characterization power line is in the same power state table and the related power state information spans the power domain and is located in different power state tables.

In some examples, for the case that the related power state information is in the same power state table, the characterization power line mapped by the design power line may be used as the first index, and the power state information corresponding to the first index may be combined to obtain the updated power state table.

For example, referring to fig. 13, a process is shown in which the power state information associated with the design power lines "N410" and "N420" mapped by the first index is combined in a single power state table to represent the power line "RN2" as the first index.

In some examples, the power state information corresponding to the second index may be combined between different power state tables to characterize the power line as the second index.

For example, referring to fig. 14, the process shown in the foregoing is to use the power line "RN2" as the second index in the power state tables related to the power domains "V3" and "V4", merge the power state information related to the design power lines "N410/N420" and "N320" mapped by the second index, and finally form the merged power state table v3@v4.

It should be noted that fig. 13 and fig. 14 illustrate, as an alternative example, a process of combining the power state information in the same power state table with a first index to obtain an updated power state table, and then combining the power state information between the latest different power state tables with a second index. In other examples, the process of merging the power state information with the first index and the second index may be performed sequentially, or may be performed in reverse order or performed in random order.

For example, the above-mentioned merging processing of the power state information between the same power state table and the cross-power state table may first perform information merging in the same power state table, then use all updated power state tables and all power state tables that do not need to be merged to perform merging processing with a second index, and finally obtain the target power state table.

For example, there may be only merging processing of power state information within the same power state table, and there may be no merging processing of power state information across power state tables.

For example, there may be only merging processing of power state information across power state tables, and there may not be merging processing of power state information within the same power state table.

In these examples, by using the characterization power line as the first index and the second index, and combining the power state information corresponding to the indexes in a power state table and between different power state tables, the logic of the combining process can be more hierarchical, and the complexity of single information processing can be simplified.

In still other alternative examples, the merging process of the power state information of the cross power state table may be set according to actual needs, for example, please refer to fig. 15, and between different power state tables, the process of merging the power state information corresponding to the second index with the characterization power line as the second index, to obtain the target power state table may include the following steps:

S1510, extracting two power state tables from the different power state tables.

S1520, using the characterization power line as a second index, merging the power state information corresponding to the second index in the extracted two power state tables to obtain an intermediate power state table.

S1530, in a case where there are no remaining power state tables among the different power state tables, the intermediate power state table is the target power state table.

S1540, under the condition that the rest power state tables exist in different power state tables, continuously extracting two power state tables from different power state tables and the middle power state table, continuously executing the step of taking the characterization power line as a second index, and combining the power state information corresponding to the second index in the extracted two power state tables to obtain the middle power state table.

In this example, each time two power state tables are randomly or individually selected and extracted from all the latest power state tables, the merging processing of the power state information of the two power state tables is performed until no other remaining power state tables exist after the merging processing of the different power state tables, that is, the merging processing of the power state information of the power domains crossing the power domain, which is performed by using the characterization power line as the second index, is indicated to be completed, the merging processing is performed on the power state tables corresponding to all the power state tables mapped by the characterization power line, and finally, one intermediate power state table obtained by merging and updating is the target power state table finally containing all the required power state information.

Illustratively, fig. 14 shows a process of merging the power state tables corresponding to the power domains V3 and V4 with "RN2" as the second index to obtain the intermediate power state table v3@v4. On the basis, please refer to fig. 16, after the intermediate power state table v3@v4 is obtained, the remaining power state tables, that is, the power state table corresponding to the power domain V2, still exist in all the power state information tables, the second index may be determined again, the "RN2" is taken as the second index, and the power state information of "N410/N420/N320" in the intermediate power state table v3@v4 and the power state information of "N220" in the power state table corresponding to V2 are combined; taking RN1 as a second index, combining the power state information of N310 in the intermediate power state table V3@V4 with the power state information of N210 in the power state table corresponding to V2; and taking RN3 as a second index, combining the power state information of N430 in the intermediate power state table V3@V4 with the power state information of N230 in the power state table corresponding to V2. Finally, the intermediate power state table v3@v4@v2 is obtained comprehensively, and no other residual power state table exists at the moment, wherein the intermediate power state table v3@v4@v2 is the target power state table which is finally needed.

In these examples, by extracting the two-to-two power state tables, and after each extraction, according to the design power lines with the same power characteristics in the two extracted power state tables, finding out the identical characterization power lines, and using these characterization power lines as the second index, merging the power state information between the two power domains, thereby giving an acquisition scheme of the target power state table, and merging the power state information between the two power domains, so as to simplify the complexity of single information processing, and avoid temporarily using excessive computing resources.

In still other alternative examples, the following steps may be performed after the intermediate power state table is obtained:

and storing the intermediate power state table into a cache.

On this basis, the continuing to extract two power state tables from the power state table and the intermediate power state table may include:

in case the extracted two power state tables comprise the intermediate power state table, the intermediate power state table is read directly from the cache.

After each combination, the intermediate result and the intermediate power state table are cached, in the subsequent combination process, before the next combination, whether the power state table related to the calculation exists or not is firstly queried from the cache, if the power state table related to the combination exists in the cache history, the call is directly made, and therefore the intermediate result of the power state information combination calculation is recorded based on the cache technology, and the subsequent combination processing is convenient.

In still other alternative examples, instead of implementing delta merge to obtain the target power state table, the power state information may be checked during the generation of the target power state table to discover the voltage conflict problem during the chip design process in time.

It should be noted that, the design power line mapped by the characterization power line corresponds to the same physical wiring in the subsequent chip design implementation link, and two conflicting power states should not exist at the same time, so the voltage value information should be consistent. Therefore, whether the voltage value information of each design power line in the power state table corresponding to the characterization power line is consistent or not can be checked in the process of combining the power state information, and if the voltage value information is inconsistent, the error is reported.

For example, in the same power state table, the power state information corresponding to the first index may be checked with the characterization power line as the first index;

in the case where the power state information corresponding to the first index matches, the merging processing may be performed on the power state information corresponding to the first index in the above example, to obtain the updated power state table.

That is, in this example, when condition setting is performed for merging the power state information corresponding to the first index in the same power state information table, the merging process is performed only if the power state information matches; if the power state information is not matched, the condition that voltage conflict exists in the relevant power domain corresponding to the power state table is characterized, and errors can be reported to a user.

For example, referring to fig. 17, it is assumed that there is one power state S44 in the power state table corresponding to the power domain V4, and that the power lines N410 and N420 should have the same power characteristics. However, the power state of the design power line N410 is found to be OFF and the design power line N420 is found to be full_on after inspection, so that there is a conflict between the two power states. At this time, the "RN2" is not used as the first index to perform the merging process in the same power state table, but the error reporting information of the power state is directly fed back to the user S44, so that the error can be reported in advance.

For example, in the case of merging power state information across power state tables, the power state information corresponding to the second index in the extracted two power state tables may be checked with the characterization power line as the second index.

And feeding back error reporting information to the user under the condition that the power state information corresponding to the second index is not matched.

In the case where the power state information corresponding to the second index is matched, the merging processing of the extracted power state information corresponding to the second index in the two power state tables in the above example may be performed, so as to obtain an intermediate power state table.

The example is similar to the merging processing of the power state information between the same power state tables, and before the merging processing of the power state information corresponding to the second index in the extracted two-by-two power state tables, the matching judgment is carried out on the power state information to determine whether the power state information corresponding to the second index between different power state tables has the condition of voltage conflict or not, so that the voltage conflict can be found as early as possible in the merging process of the two-by-two power state tables, and errors can be fed back timely.

Fig. 18 shows a schematic hardware structure of a data processing apparatus according to an embodiment of the present application. In fig. 18, the data processing apparatus may include:

a creation module 1801 for creating a characterization power line;

a selection module 1802 for selecting a target power line from the design power lines;

A traversing module 1803, configured to traverse the design power line;

and a mapping module 1804, configured to map the traversed associated power line corresponding to the target power line to the characterization power line, where the associated power line is the design power line belonging to the same physical wiring as the target power line.

Optionally, the apparatus further includes:

and the adding module is used for adding the characterization power line in the attribute of the associated power line corresponding to the target power line.

Optionally, the apparatus further includes:

and the configuration module is used for configuring the attribute of the design power line corresponding to the mapping through the characterization power line.

Optionally, the associated power line includes:

Optionally, the apparatus further includes:

and the storage module is used for storing the characterization power line and the associated power line mapped by the characterization power line into a cache.

Optionally, the apparatus further includes:

and the assignment module is used for assigning the representation power line to be the associated power line with the highest design level.

Optionally, the traversing module 1803 is further configured to map the target power line as the associated power line into the characterization power line; sequentially searching first power lines in one-by-one layers along the direction close to the top design layer, and mapping the first power lines in one-by-one layers as the associated power lines into the characterization power lines, wherein the first power lines are design power lines connected with the associated power lines in the direction close to the top design layer; and sequentially searching second power lines in one-by-one layers along the direction close to the design bottom layer, and mapping the second power lines in one-by-one layers into the characterization power lines as associated power lines, wherein the second power lines are design power lines connected with the first power lines in the design top layer in the direction close to the design bottom layer.

Optionally, the traversing module 1803 is further configured to determine, through a first port, a first power line in a previous level adjacent to the level where the associated power line is located, where the first port is a port near a top design layer connected to the associated power line, and the first power line is a design power line adjacent to the associated power line and connected to the first port;

Optionally, the traversing module 1803 is further configured to stop searching for the first power line in a hierarchy level by level, and configure the attribute of the found associated power line according to the target representation power line, where the mapped target representation power line exists in the first power line;

in the event that the first power line does not have a mapped target characterization power line, the trigger mapping module 1804 maps the first power line into the characterization power line as a new associated power line.

Optionally, the traversing module 1803 is further configured to determine, through a second port, a second power line in a next level adjacent to the level where the current associated power line is located, where the second port is a port connected to the associated power line and near the bottom layer of the design, and the second power line is a design power line connected to the first power line in the top layer of the design in a direction near the bottom layer of the design, and is further adjacent to the associated power line and connected to the second port;

Optionally, the traversing module 1803 is further configured to stop traversing the design power line if the first power line in the top layer of the design belongs to the characterization power line, and configure the attribute of the found associated power line according to the first power line in the top layer of the design;

In the case where the first power line in the top layer of the design does not belong to the characterization power line, sequentially searching for the second power line in the successive layers along the direction close to the bottom layer of the design, and triggering the mapping module 1804 to map the second power line in the successive layers as an associated power line into the characterization power line.

Optionally, the traversing module 1803 is further configured to store the target power line in an empty stack; executing a spring stack operation to obtain spring stack elements; under the condition that the design power line connected with the spring stack element and not traversed is searched, searching a first power line in a direction which is closer to a top layer of the design than the spring stack element from the design power lines connected with the spring stack element and not traversed;

the mapping module 1804 is further configured to map the first power line as a new associated power line into the characterization power line, trigger the storage module to store the first power line into a stack, and trigger the traversing module 1803 to return to continue to perform the pop operation;

the traversing module 1803 is further configured to return to continue executing the pop operation until the pop element cannot be obtained, if the design power line connected to the pop element and not traversed by the pop element is not found.

Optionally, the traversing module 1803 is further configured to store the target power line in an empty stack; executing a spring stack operation to obtain spring stack elements; under the condition that the layer level of the spring stack element is higher than the value of the representation power line, the representation power line is assigned to be the spring stack element, and search operation is carried out; executing the search operation under the condition that the level of the spring stack element is not higher than the value of the representation power line; under the condition that the design power line which is connected with the spring stack element and is not traversed is searched, the design power line which is connected with the spring stack element and is not traversed is used as an associated power line corresponding to the target power line to be stored in a stack, and the spring stack operation is returned to be continuously executed, so that a new spring stack element is obtained; and returning to continue to execute the spring stack operation under the condition that the design power line connected with the spring stack element and not traversed is not found, so as to obtain a new spring stack element until the spring stack element cannot be obtained.

Optionally, the traversing module 1803 is further configured to store the target power line in an empty stack; executing a spring stack operation to obtain spring stack elements; storing the design power line which is connected with the spring stack element and is not traversed into a stack under the condition of searching the design power line which is connected with the spring stack element and is not traversed, and returning to continue to execute spring stack operation to obtain a new spring stack element; returning to continue to execute the spring stack operation under the condition that the design power line connected with the spring stack element and not traversed is not found, so as to obtain a new spring stack element until the spring stack element cannot be obtained;

The mapping module 1804 is further configured to assign a design power line with a highest level in all stack elements obtained by the stack operation to the representation power line, and map all the stack elements obtained by the stack operation as associated power lines corresponding to the target power line to the representation power line.

Optionally, the apparatus further includes:

the query module is used for responding to a query request of a user, determining a query target corresponding to the query request, wherein the query target comprises at least two design power lines; and triggering the creation module 1801 to create a representation power line under the condition that the representation power line corresponding to the query target is not queried.

Optionally, the query module is further configured to, when the token power line corresponding to the query target is queried, read the token power line corresponding to the query target from a cache.

Optionally, the apparatus further includes:

the acquisition module is used for acquiring power state tables corresponding to the design power lines respectively mapped by the characterization power lines;

and the merging module is used for merging different power supply state information in the power supply state table by taking the characterization power supply line as an index to obtain a target power supply state table.

Optionally, the merging module is further configured to, in the same power state table, use the characterization power line as a first index, and merge the power state information corresponding to the first index to obtain an updated power state table; and combining the power state information corresponding to the second index by taking the characterization power line as the second index among different power state tables to obtain the target power state table.

Optionally, the apparatus further includes:

the detection module is used for checking the power state information corresponding to the first index; feeding back error reporting information to the user under the condition that the power state information corresponding to the first index is not matched; and triggering a merging module to merge the power state information corresponding to the first index under the condition that the power state information corresponding to the first index is matched, so as to obtain the updated power state table.

Optionally, a merging module is configured to extract two power state tables from different power state tables; taking the characterization power line as a second index, and combining the extracted power state information corresponding to the second index in the two power state tables to obtain an intermediate power state table; in the case that no remaining power state tables exist in different power state tables, the intermediate power state table is the target power state table; and under the condition that the rest power state tables exist in different power state tables, continuously extracting two power state tables from the different power state tables and the middle power state table, continuously executing the step of taking the characterization power line as a second index, and combining the power state information corresponding to the second index in the extracted two power state tables to obtain the middle power state table.

Optionally, the checking module is configured to use the characterization power line as a second index, and perform checking processing on the power state information corresponding to the second index in the two extracted power state tables; feeding back error reporting information to the user under the condition that the power state information corresponding to the second index is not matched; and under the condition that the power state information corresponding to the second index is matched, triggering a merging module to merge the extracted power state information corresponding to the second index in the two power state tables to obtain an intermediate power state table.

Optionally, a storage module is configured to store the intermediate power state table into a cache; in case the extracted two power state tables comprise the intermediate power state table, the intermediate power state table is read from the cache.

Optionally, the checking module is configured to check the correctness of the chip design according to the target power state table and the characterization power line, so as to obtain a checking result.

Optionally, the selecting module is further configured to screen out power state information in the target power state table, where the power state information is irrelevant to the query target.

Fig. 19 shows a schematic hardware structure of a data processing apparatus according to an embodiment of the present application. The data processing apparatus includes a processor 1901 and a memory 1902 in which computer program instructions are stored. In particular, the processor 1901 may include a Central Processing Unit (CPU), or an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or may be configured to implement one or more integrated circuits of embodiments of the present application.

Memory 1902 may include mass storage for data or instructions. By way of example, and not limitation, memory 1902 may include a Hard Disk Drive (HDD), floppy Disk Drive, flash memory, optical Disk, magneto-optical Disk, magnetic tape, or universal serial bus (Universal Serial Bus, USB) Drive, or a combination of two or more of the above. The memory 1902 may include removable or non-removable (or fixed) media, where appropriate. Memory 1902 may be internal or external to the data processing device, where appropriate. In a particular embodiment, the memory 1902 is a non-volatile solid state memory.

Memory 1902 may include Read Only Memory (ROM), flash memory devices, random Access Memory (RAM), magnetic disk storage media devices, optical storage media devices, electrical, optical, or other physical/tangible memory storage devices. Thus, in general, memory 1902 includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software that may include computer-executable instructions and that, when executed (e.g., by one or more processors), is operable to perform operations described with reference to methods in accordance with the above aspects of the disclosure.

The processor 1901 implements the data processing method of any of the power state tables of the above embodiments by reading and executing computer program instructions stored in the memory 1902.

In one example, the data processing device may also include a communication interface 1903 and a bus 1910. As shown in fig. 19, the processor 1901, the memory 1902, and the communication interface 1903 are connected to each other via a bus 1910 and communicate with each other.

The communication interface 1903 is mainly used to implement communication between each module, apparatus, unit and/or device in the embodiments of the present application.

Bus 1910 includes hardware, software, or both that couple the components of the data processing apparatus to one another. By way of example, and not limitation, the buses may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an infiniband interconnect, a Low Pin Count (LPC) bus, a memory bus, a micro channel architecture (MCa) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a video electronics standards association local (VLB) bus, or other suitable bus, or a combination of two or more of the above. Bus 1910 may include one or more buses, where appropriate. Although embodiments of the present application describe and illustrate a particular bus, the present application contemplates any suitable bus or interconnect.

The data processing apparatus may be based on the data processing method of the power state table, thereby implementing the data processing method and apparatus of the power state table described in connection with fig. 1 to 18.

In addition, in combination with the data processing method of the power state table in the above embodiment, the embodiment of the application may be implemented by providing a computer storage medium. The computer storage medium has stored thereon computer program instructions; the computer program instructions, when executed by a processor, implement a data processing method for any of the power state tables of the above embodiments.

In addition, the embodiment of the application also provides a computer program product, which comprises a computer program, and the computer program can realize the steps of the embodiment of the method and the corresponding content when being executed by a processor.

In addition, the term "and/or" herein is merely an association relationship describing an association object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

It should be understood that in the embodiments of the present application, "B corresponding to a" means that B is associated with a, from which B may be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may also determine B from a and/or other information.

The foregoing is merely a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any equivalent modifications or substitutions will be apparent to those skilled in the art within the scope of the present application, and these modifications or substitutions should be covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for processing data in a power state table, comprising:

creating a characterization power line and selecting a target power line from the design power lines; the characterization power line is attribute information describing entity wiring to which the design power line belongs;

traversing the design power line, and mapping the traversed associated power line corresponding to the target power line into the representation power line, wherein the associated power line is the design power line belonging to the same entity wiring with the target power line; the associated power lines further comprise first power lines and second power lines which are sequentially searched in a hierarchy-by-hierarchy mode, the first power lines are design power lines connected with the associated power lines in the direction close to the top design layer, and the second power lines are design power lines connected with the first power lines in the top design layer in the direction close to the bottom design layer;

After traversing the design power line, the method further comprises:

2. The method of claim 1, wherein the associated power line is a design power line connected to the same port as the target power line.

3. The method of claim 2, wherein the associated power line comprises:

4. The method for processing data in a power state table according to claim 1, wherein after mapping the traversed associated power line corresponding to the target power line into the characterization power line, the method further comprises:

5. The method for processing data in a power state table according to claim 1, wherein after mapping the traversed associated power line corresponding to the target power line into the characterization power line, the method further comprises:

6. The method for processing data in a power state table according to claim 1, wherein traversing the design power line and mapping the traversed associated power line corresponding to the target power line into the characterization power line comprises:

sequentially searching first power lines in one-by-one layers along the direction close to the top layer of the design, and mapping the first power lines in one-by-one layers into the characterization power lines as the associated power lines;

and sequentially searching second power lines in the successive layers along the direction close to the bottom layer of the design, and mapping the second power lines in the successive layers into the characterization power lines as associated power lines.

7. The method for processing data in a power state table according to claim 6, wherein sequentially searching for a first power line in a hierarchical level by hierarchical level along a direction approaching a top layer of a design, and mapping the first power line in the hierarchical level by hierarchical level as the associated power line into the characterization power line, comprises:

8. The method for processing data in a power state table according to claim 7, wherein after determining, through the first port, the first power line in the previous level adjacent to the level where the associated power line is located, further comprising:

stopping searching the first power lines in the hierarchy-by-hierarchy mode under the condition that the mapped target representation power lines exist in the first power lines, and configuring the searched attribute of the associated power lines according to the target representation power lines; the target representation power line is recorded in an attribute or a cache of the first power line;

9. The method for processing data in a power state table according to claim 7, wherein sequentially searching for second power lines in successive levels along a direction approaching a design bottom layer, and mapping the second power lines in successive levels as associated power lines into the characterization power lines, comprises:

10. The method of claim 7, wherein after mapping the first power line within the hierarchy as the associated power line into the characterization power line, further comprising:

searching whether the characterization power supply line assigned as the first power supply line in the top layer of the design exists or not from all the recorded characterization power supply lines;

if the characterization power line assigned as the first power line in the design top layer is found, the first power line in the design top layer belongs to the characterization power line;

11. The method for processing data in a power state table according to claim 6, wherein sequentially searching for a first power line in a hierarchical level by hierarchical level along a direction approaching a top layer of a design, and mapping the first power line in the hierarchical level by hierarchical level as the associated power line into the characterization power line, comprises:

Storing the target power line into an empty stack;

executing a spring stack operation to obtain spring stack elements;

under the condition that the design power line connected with the spring stack element and not traversed is searched, searching a first power line in a direction which is closer to a top layer of the design than the spring stack element from the design power lines connected with the spring stack element and not traversed;

12. The method for processing data in a power state table according to claim 1, wherein traversing the design power line and mapping the traversed associated power line corresponding to the target power line into the characterization power line comprises:

storing the target power line into an empty stack;

executing a spring stack operation to obtain spring stack elements;

under the condition that the layer level of the spring stack element is higher than the value of the representation power line, the representation power line is assigned to be the spring stack element, and search operation is carried out; when the characterization power line in the initial condition is not assigned, assigning the characterization power line as the target power line;

13. The method for processing data in a power state table according to claim 1, wherein traversing the design power line and mapping the traversed associated power line corresponding to the target power line into the characterization power line comprises:

storing the target power line into an empty stack;

executing a spring stack operation to obtain spring stack elements;

14. The method of claim 1, wherein prior to creating the characterization power line, the method further comprises:

15. The method for processing data in a power state table according to claim 14, wherein after determining a query target corresponding to the query request, the method further comprises:

16. The method of claim 1, further comprising:

17. The method for processing data in a power state table according to claim 16, wherein the merging different power state information in the power state table with the characterization power line as an index to obtain a target power state table includes:

18. The method for processing data in a power state table according to claim 17, wherein after the characterizing power line is used as the first index in the same power state table, the method further comprises:

Checking the power state information corresponding to the first index;

feeding back error reporting information to a user under the condition that the power state information corresponding to the first index is not matched;

19. The method for processing data in a power state table according to claim 17, wherein said merging the power state information corresponding to the second index with the characterization power line as the second index between different power state tables to obtain the target power state table includes:

extracting two power state tables from different power state tables;

20. The method for processing data of a power state table according to claim 19, wherein the step of merging the extracted power state information corresponding to the second index in the two power state tables with the characterization power line as the second index to obtain an intermediate power state table includes:

feeding back error reporting information to a user under the condition that the power state information corresponding to the second index is not matched;

21. The method for processing data in a power state table according to claim 19, further comprising, after said obtaining the intermediate power state table:

storing the intermediate power state table into a cache;

22. The method for processing data in a power state table according to claim 16, wherein after said obtaining a target power state table, the method further comprises:

23. The method for processing data in a power state table according to claim 16, wherein after said obtaining a target power state table, the method further comprises:

24. A data processing apparatus of a power state table, the apparatus comprising:

The creation module is used for creating the characterization power line; the characterization power line is attribute information describing entity wiring to which the design power line belongs;

the traversing module is used for traversing the design power line;

the mapping module is used for mapping the related power line corresponding to the target power line obtained through traversing into the representation power line, wherein the related power line is the design power line belonging to the same entity wiring with the target power line; the associated power lines further comprise first power lines and second power lines which are sequentially searched in a hierarchy-by-hierarchy mode, the first power lines are design power lines connected with the associated power lines in the direction close to the top design layer, and the second power lines are design power lines connected with the first power lines in the top design layer in the direction close to the bottom design layer;

25. A data processing apparatus of a power state table, the apparatus comprising: a processor and a memory storing computer program instructions;

The processor, when executing the computer program instructions, implements the steps of the data processing method of the power state table of any of claims 1-23.

26. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon computer program instructions which, when executed by a processor, implement the steps of the data processing method of the power state table of any of claims 1-23.