CN117436224A - An analog circuit yield optimization method based on preference learning model - Google Patents

Abstract

The invention belongs to the technical field of integrated circuits and relates to an analog circuit yield optimization method based on a preference learning model. This method uses a multi-scale sampling method to gradually increase the standard deviation σ of the process parameter distribution and perform yield analysis. By amplifying the gap between the yields of different design points, it is easier to distinguish the level of the yield of the design points; preference-based learning is used The Gaussian process classification GPC model models the comparison results of multi-scale sampling yields between design points; the preference Bayesian optimization framework is used to optimize the GPC model, and Thompson sampling is used to obtain the utilization and exploration of the function balance optimization process to find the The design point with the highest probability of winning in the yield comparison; the multi-confidence modeling method is used to model the yield under different process parameter standard deviations to further improve the accuracy of the Thompson sampling acquisition function. This method can significantly reduce the number of simulations required for yield optimization of analog circuits.

Description

A method for optimizing analog circuit yield based on preference learning model

Technical Field

The present invention belongs to the technical field of integrated circuits, and relates to analog circuit yield optimization in integrated circuit manufacturability design. Specifically, it relates to an analog circuit yield optimization method based on a preference learning model. The method can significantly reduce the number of simulations required for analog circuit yield optimization.

Background Art

According to existing technical records, as the feature size of semiconductor manufacturing processes shrinks to the nanoscale, process disturbances have a huge impact on the yield of analog circuits. The reliability challenge in analog circuit design is becoming increasingly severe. Recently, the industry has paid more and more attention to the issue of analog circuit yield optimization [1].

Typically, analog circuit yield optimization uses an iterative optimization cycle. In each iterative optimization step, design parameters such as the width and length of the transistor need to be adjusted, and then a very time-consuming yield analysis is performed. Yield analysis generally uses simulations under different process corners or Monte Carlo simulations, and thousands of simulations need to be performed to ensure that the yield analysis results are accurate. Therefore, the time cost of analog circuit yield optimization is extremely high, and reducing the overall simulation time of analog circuit yield optimization has become the most urgent need.

Regarding the problem of analog circuit yield optimization, the current main methods include the following three categories.

Corner-based methods [2]-[4] optimize the “worst” performance of analog circuits under all process corners. This approach avoids the costly yield analysis process, but the optimization results are not very accurate and often lead to over-design. In addition, if the process space is very high, this method is expensive to search for the “worst” performance.

Monte Carlo (MC) based methods are widely used due to their high accuracy and versatility. References [5,6] applied the Optimal Computational Budget Allocation (OCBA) technique to MC acceleration and used evolutionary algorithms to solve optimization problems. Reference [7] used the kernel density estimation method to model yield and proposed a multi-starting point expectation maximization algorithm to solve the problem. Reference [8] proposed an adaptive yield analysis method and used a Bayesian optimization algorithm based on a weighted expected lift function to find the optimal design. Reference [9] further used Gaussian process regression combined with neural network and maximum entropy search method for optimization based on reference [8]. Although the Bayesian optimization method has shown certain advantages, the total number of simulations required is too high. For example, the current most advanced methods [8] and [9] require 6,000 to 20,000 simulations for a yield optimization, which is time-consuming for large-scale analog circuits.

Based on the surrogate model method, the literature [10] attempts to establish a surrogate model of circuit performance to replace expensive circuit simulation, thereby reducing the cost of yield optimization. However, these methods often require a large number of simulation sample points to ensure the accuracy of modeling, and the number of sample points required for modeling increases exponentially with the dimension of the process space [8]. Under the advanced FinFET process, it is extremely difficult to establish a surrogate model.

Research has shown that the scaled-sigma sampling (SSS) [11] method has been successfully applied to yield analysis and optimization of SRAM circuits. Since the failure rate of SRAM circuits is extremely low, the scaled-sigma sampling method artificially increases the standard deviation σ of the Gaussian distribution of process disturbances. For example, the standard deviation provided by the chip foundry is 1, and the SSS method increases it to 3, thereby increasing the failure rate of the design point and reducing the simulation cost of yield analysis. References [7, 8] show that using the SSS method to perform yield analysis will not change the yield relationship between the two design points. In addition, this research team found that the difference between the yields of different design points of the analog circuit can be amplified by changing the process standard deviation σ.

As shown in FIG1 , the horizontal axis represents the standard deviation σ of the Gaussian distribution obeyed by the process parameter perturbation, and the vertical axis represents the yield of the charge pump circuit (see FIG8 ). Curves of different colors correspond to different design points. It can be seen that as the standard deviation σ of the process parameters increases, the amplitude of the process perturbation increases, and the yield of the design point decreases significantly. More importantly, the yield difference between any two design points changes with the change of σ. Generally, the place where the yield difference between design points is the largest is mainly when σ＝[2, 2.5]. For example, the yield difference between design point 1 and design point 3 changes from the original 0.3% (σ＝1) to 6% (σ＝2.5), which means that if σ＝2.5 is used for yield analysis, only 200 simulation samples are needed at most to distinguish them. However, not all the yield differences between any two design points reach the maximum when σ＝2.5. For example, the yield difference between design point 2 and design point 4 in FIG1 decreases from 15% (σ＝1) to 2% (σ＝2.5), so at this time, σ＝1 should be used for yield analysis to improve the efficiency of yield analysis. To this end, different σ values must be dynamically selected during the optimization process to maximize the yield gap, rather than using a preset fixed σ value.

The most advanced analog circuit yield optimization method in the world [8,9] uses the Gaussian process regression (GPR) model, which is a continuity model for yield.

Based on the current status of the prior art, in order to solve the problem of low optimization efficiency in the existing analog circuit yield optimization method, the inventor of this application proposes an analog circuit yield optimization method based on a preference learning model, in which a Gaussian process classification GPC model is used to model the comparison results of multi-scale sampling yields, especially a discrete model based on comparison. By dynamically selecting the σ value at the design point, the yield gap between the design points is maximized, and the design point yield comparison results are obtained at a relatively low simulation cost, thereby reducing the simulation cost.

The prior art related to the present invention includes:

[1]G.Gielen, T.Eeckelaert, E.Martens, and T.McConaghy, "Automatedsynthesis of complex analog circuits," in European Conference on CircuitTheory and Design, 2007.

[2] R.Schwencker, F.Schenkel, M.Pronath, and H.Graeb, "Analog circuitsizing using adaptive worst-case parameter sets," in Proc.DATE, 2002.

[3] M.Barros, J.Guilherme, and N.Horta, "Analog circuits optimization based on evolutionary computation techniques," Integration, the VLSI Journal, 2010.

[4] M. Sengupta, S. Saxena, L. Daldoss, G. Kramer, S. Minehane, and J. Cheng, "Application-specific worst case corners using response surfaces and statistical models," IEEE TCAD, 2005.

[5] B. Liu, F. V. Fernandez, and G. G. Gielen, "Efficient and accurate statistical analog yield optimization and variation-aware circuit sizingbased on computational intelligence techniques," IEEE TCAD, 2011.

[6] I. Guerra-Gomez, E. Tlelo-Cuautle, and L.G. de la Fraga, "Ocba in theyield optimization of analog integrated circuits by evolutionary algorithms," in Proc.ISCAS, 2015.

[7] M.Wang, F.Yang, C.Yan, X.Zeng, and X.Hu, "Efficient Bayesian yieldoptimization approach for analog and sram circuits," in Proc.DAC, 2017.

[8] M.Wang, W.Lv, F.Yang, C.Yan, W.Cai, D.Zhou, and X.Zeng, “Efficient yieldoptimization for analog and sram circuits via Gaussian process regression and adaptive yield estimation,” IEEE TCAD,2018.

[9] S. Zhang, F. Yang, D. Zhou, and X. Zeng, "Bayesian methods for the yieldoptimization of analog and sram circuits," in Proc.ASPDAC, 2020.

[10] S. Basu, B. Kommineni, and R. Vemuri, "Variation-aware macromodeling and synthesis of analog circuits using spline center and range method and dynamically reduced design space," in Proc. VLSI Design, 2009.

[11] S.Sun,

[12]

[13] W. Lyu, P. Xue, F. Yang, C. Yan, Z. Hong, X. Zeng, and D. Zhou, "An efficient bayesian optimization approach for automated optimization of analogcircuits," IEEE TCAS I, 2017.

[14] C.Williams and C.Rasmussen.2006.Gaussian processes for machine learning.Vol.2.MIT press Cambridge,MA.

[15] P. Perdikaris, M. Raissi, A. Damianou, N. Lawrence, and G. Karniadakis, "Nonlinear information fusion algorithms for data-efficient multi-fidelity modeling," Proc.R.Soc.A 473,2198(2017 ),20160751.

[16] D.R.Jones, M.Schonlau, and W.J.Welch, "Efficient global optimization of expensive black-box functions," Journal of Global Optimization, 1998.

[17] O.Chapelle and L.Li, “An empirical evaluation of thompsonsampling,” in Proc.NIPS, 2011.

[18] J. Nocedal and S. Wright, Numerical optimization. Springer Science & Business Media, 2006.

Summary of the invention

The purpose of the present invention is to provide an analog circuit yield optimization method based on the current status of the prior art and to address the problem of low optimization efficiency in existing analog circuit yield optimization methods, specifically relating to an analog circuit yield optimization method based on a preference learning model.

The present invention includes: first, based on the preference learning method, the analog circuit yield optimization problem is converted into a ranking score optimization problem; second, the Gaussian process classification model is used to model the comparison results of the yields of different design points; third, the multi-confidence modeling method is used to model the yields under different process parameter standard deviations, and representative points are selected based on the model to approximately calculate the ranking scores; fourth, the preferred Bayesian optimization is used to solve the problem, in which the Thompson sampling acquisition function balance optimization utilizes and explores the process, and iterates continuously until the yield meets the requirements or reaches the maximum number of iterations.

In the present invention, (1) a multi-scale sampling method is used to gradually increase the standard deviation σ of the process parameter distribution and perform yield analysis. By amplifying the difference between the yields of different design points, it is easier to distinguish the high and low yields of the design points; (2) a Gaussian process classification GPC model based on preference learning is used to model the comparison results of the multi-scale sampling yields between design points; (3) a preference Bayesian optimization framework is used to optimize the GPC model, that is, based on the posterior distribution of the predicted preference, the utilization and exploration in the Thompson sampling acquisition function balance optimization process are used to find the design point with the highest probability of winning in the yield comparison; (4) a multi-confidence modeling method is used to model the yields under different process parameter standard deviations, thereby further improving the accuracy of the Thompson sampling acquisition function.

More specifically, the present invention adopts a varying-sigma sampling method, by gradually increasing the standard deviation of the process parameter distribution and performing yield analysis, the gap between the yields of different design points is enlarged, and it is easier to distinguish the high and low yields of the design points; different from the current mainstream continuous Gaussian process regression (Gaussian process regression, GPR) model, the present method adopts a discrete Gaussian process classification (Gaussian process classification, GPC) model based on preference learning to model the comparison results of multi-scale sampling yields between design points; the GPC model is optimized using a preference Bayesian optimization framework, that is, based on the posterior distribution of the predicted preference, the Thompson sampling (Thompson sampling, TS) is used to obtain the utilization (exploitation) and exploration (exploration) in the process of function balance optimization, and the design point with the highest probability of winning in the yield comparison is found; and the multi-fidelity modeling method is used to model the yields under different process parameter standard deviations, further improving the accuracy of the Thompson sampling acquisition function. The present method can significantly reduce the number of simulations required for analog circuit yield optimization.

The flowchart of the analog circuit yield optimization method of the present invention is shown in FIG2 .

Input parameters:

1. Analog circuit netlist;

2. Probability distribution density function of process parameters;

3. Failure threshold of circuit performance index c _i , i=1, ..., k, where k is the number of circuit performance indexes of interest, and it is assumed that for the i-th performance index y _i of the circuit, if the simulation result y _i ≥ c _i, the circuit is considered successful, otherwise it is considered a failure;

4. The number of points N _init of the initial data set of the Gaussian process classification model; the maximum number of iterations N _pbo of the preferred Bayesian optimization; the number of representative points of the sorting score N _rep ; the maximum number of simulations N _max for variable scale sampling yield analysis; the maximum number of simulations N _pre for calling the analog circuit performance optimization solver; the number of simulation points per batch N _batch for iterative yield analysis.

Output:

Optimal design parameters and yield values obtained by analog circuit yield optimization.

The specific steps include:

Step 1: Based on the preference learning method, the analog circuit yield optimization problem is transformed into a ranking score optimization problem;

Step 2: Data set initialization, i.e., using the TT (Typical-Typical) process corner performance optimization method to obtain N _init prior solutions, and perform low-precision yield analysis as the data set initial point for the preferred Bayesian optimization hot start, and add the current optimal design point to the optimal yield candidate set B (Basket);

Step 3: Use the Gaussian process classification model to model the comparison results of the yield of different design points in the data set;

Step 4: For the yield rate under different process parameter standard deviations, a multi-confidence Gaussian process model is established, and the Markov Chain Monte Carlo (MCMC) method is used to select representative points for calculating the ranking score;

Step 5: Use the preferred Bayesian optimization to solve the sorting score optimization problem, in which the sorting score is used to calculate the Thompson sampling acquisition function; use the multi-scale sampling method to compare the yield of the next candidate point x _next with the current optimal design point x _τ ; update the optimal yield candidate set B according to the comparison result, and select the optimal design point from B, increase N _batch simulations for it, and improve the yield analysis accuracy of this point; continue to iterate until the yield meets the requirements or reaches the maximum number of iterations N _pbo , and finally obtain the optimal design parameters and the corresponding yield results.

In step 1 of the present invention, based on the preference learning method, the analog circuit yield optimization problem is converted into a ranking score optimization problem.

For analog circuits, design parameters refer to variables such as transistor length, width, capacitance, and resistance that can be controlled by circuit designers. Process parameters refer to variables such as threshold voltage provided by chip manufacturers that characterize process disturbances. The yield involved refers to the yield caused by process disturbances.

For an analog circuit, the design parameter x is a d _x- dimensional vector in the design space D, It represents the variables such as the length and width of the transistor that can be controlled by the circuit designer. The process parameter s is a d _s -dimensional vector in the process space V. represents variables such as threshold voltage, and its probability distribution is usually provided by the process manufacturer and satisfies the normal distribution. Without loss of generality, assuming that the process parameters are independent of each other and have nothing to do with the design parameters, the probability density function (PDF) of the process parameter s is

Given design parameters and process parameters (x, s)∈(D, V), x∈D, s∈V, the circuit performance of interest y=[ _y1 , _y2 ,…, _yk ] ^T can be obtained through SPICE simulation. The corresponding threshold condition c=[ _c1 , _c2 ,…, _ck ] ^T is determined by the designer; only when the circuit performance meets all conditions, that is _, yi≥ci _, i=1,…,k, is it considered qualified, otherwise it is considered failed.

Given a design parameter x, the analog circuit yield Y(x) is defined as

Y(x)＝∫ _V I(x,s)p(s)ds (2)

Here, the index function I(x, s)=AND(y _i ≥c _i ), i=1, ..., k, and AND(·) represents the logical function AND.

The analog circuit yield optimization problem is to find the design point x ^* with the maximum yield Y, that is,

In practice, a reasonable analog circuit design should ensure that the circuit meets all performance indicators under the TT process angle. By adding this constraint, the search space of the algorithm can be reduced and the convergence speed can be improved; therefore, the traditional analog circuit yield optimization problem is formally defined as:

Wherein _yi (x, TT) is the i-th performance value of the analog circuit to be optimized when the design parameter is x under the TT process angle.

In order to deal with the constraints in the optimization problem, the present invention converts the constrained optimization problem defined in (4) into an unconstrained form, and the design objective (Figure of Merit, FOM) is described as:

Wherein ω _i , i=1, 2, ..., k is a weight representing the importance of the i-th performance indicator.

Given a design duel [x, x']∈D×D consisting of two design points x and x', the yield comparison result h([x, x'])∈{0,1} can be obtained by calculating t(x) and t(x'). If t(x)≥t(x'), then h＝1, indicating that x is better than x'. Otherwise, h＝0, indicating that x is not better than x'.

Formally, we define π([x, x′]) as a preference function, which represents the probability that t(x) ≥ t(x′). The comparison result of [x, x′] is designed to follow the Bernoulli distribution:

Therefore, the ranking score is defined as:

R(x)＝Vol(D) ^-1 ∫ _D π([x, x′])dx′, (7)

Where Vol(D) represents the volume of the design space, which is a constant and can be ignored during the optimization process. The physical meaning of R(x) is the proportion of all design points in the design space D that are worse than the design point x, that is, the average probability that the yield of x is higher than the yield of other design points.

Intuitively, the globally optimal design point should always win when compared to other design points in the design space. If all design points are sorted by their yield value, then finding the design point with the best yield is equivalent to finding the design point with the highest sorting score.

Figure 3 shows the relationship between the yield curve and the corresponding ranking score curve of a comparator circuit, where the horizontal axis represents the design parameter, i.e., the width of transistor M17 (see Figure 7), the left vertical axis represents the circuit yield, and the right vertical axis represents the ranking score. The black solid line is the circuit yield curve, and the red dotted line is the ranking score curve. Obviously, the highest point of the ranking score curve and the maximum value of the yield curve are at the same design point.

Therefore, the analog circuit yield optimization problem can be transformed into a ranking score optimization problem:

In step 2 of the present invention, the data set is initialized, and the TT process corner performance optimization method proposed in the literature [12] is used to obtain N _init prior solutions, and a low-precision yield analysis is performed as the data set initial point for the preferred Bayesian optimization hot start, and the current optimal design point is added to the optimal yield candidate set B (Basket). It includes the following sub-steps:

Step 2.1: Use the TT process corner performance optimization method proposed in reference [12] to obtain N _init prior solutions.

Reference [12] transforms the construction of the initial solution for analog circuit yield optimization into the performance optimization problem of analog circuit under TT process corner based on the trade-off relationship between analog circuit yield and performance under TT process corner:

The formula means searching for a design point whose performance is slightly greater than the constraint threshold, ω _i is a given weight, representing the importance of the i-th performance indicator. ∈ is a constant coefficient used to measure the distance between the nominal performance y _i (x, TT) and the threshold _ci under the TT process angle. In the present invention, ω _i = 1, i∈1..k and

Then, the weighted expected improvement (WEI) Bayesian optimization algorithm WEIBO[13] is used to solve the performance optimization problem of the analog circuit under the TT process corner defined in (9), and the design points generated in all iterative optimizations are recorded, where the maximum number of simulations calling the solver is set to N _pre . From the design points generated by the iterative optimization, N _init points whose nominal performance under TT meets the failure threshold and has the minimum f(x) value are selected as the initial points for the preferred Bayesian optimization hot start.

Step 2.2: Perform low-precision yield analysis on the obtained N _init initial design points, establish an initial data set, and add the current optimal design point to the optimal yield candidate set B.

In the present invention, for the N _init initial design points obtained in step 2.1, a highly versatile MC method is adopted. Under the process parameter standard deviation σ=1, 2*N _batch sampling points are allocated to perform low-precision yield analysis to obtain the corresponding low-precision yield value, where N _batch is set to 30, which is much lower than the number of simulations required for high-precision yield analysis, for example 1000.

Different design points are combined in pairs to form design pairs to compare the yield rate and establish an initial data set. The MC method is based on the probability density function p(s) of the process parameter s. N sample points s _i , i = 1, ..., N are collected in the process space. The yield rate is calculated by counting the number of qualified samples.

Variance of Yield Estimate The relationship between the estimated value Y _MC (x) and the number of sampling points N is:

The confidence level _kγ is a constant. For example, _kγ = 1.645 corresponds to a confidence level of 90%.

From the above initial data set, select the design point with the highest yield and add it to the optimal yield candidate set B.

In step 3 of the present invention, a Gaussian process classification model is used to model the comparison results of the yields of different design points in the data set.

Since the comparison result of the design pair [x, x′] is binary data, and the regression model is generally applicable to continuous data, it is difficult to model this type of discrete data. The present invention uses the Gaussian process classification [14] method to model the yield comparison result, that is, the preference information. As a probability model, GPC can provide a predicted posterior distribution of the comparison result, which helps the design search strategy to achieve a balance between utilization and exploration.

Usually, in order to deal with classification problems, the Gaussian process classification model uses a nonlinear activation function, such as the Logistic function, to convert the continuous output of the Gaussian process regression model into a binary output. For example, the GPC model defines an implicit function z([x, x′]), and assumes that it obeys the GP prior, and its value covers the entire real number range. Then z([x, x′]) is compressed by the Logistic function to obtain the prior probability distribution of π([x, x′]):

Among them, the preference function π([x, x′]) is the result of GPC modeling, which can be used to predict the high and low relationship between the yields of different design points.

FIG4 shows a comparison between the true preference function π([x, x′]) and the prediction results of the GPC model, where FIG4(a) is the true preference function, the x-axis and the x′-axis both represent design parameters, the color bar corresponds to the preference function value, and reveals the preference information of the design point x relative to the design point x′. The darker the red, the greater the probability that the yield rate Y(x) of the design point x is higher than the yield rate Y(x′) of x′. The black intersection marks the area where the preference function takes the largest value, that is, the design area that needs attention. FIG4(b) is the preference function predicted by the GPC model. Five data points (black dots) on the yield curve (black solid line) in FIG3 are selected, and a classification model training set containing 25 data points is constructed by combining them two by two to form design pairs and comparing them. The GPC model is trained based on this data set. The figure shows that although the preference function predicted by the GPC model is not exactly the same as the true preference function, it accurately captures the high preference area of the true preference function, and the position of the optimal design point in FIG4(b) is close to the optimal position in FIG4(a).

In step 4 of the present invention, for the yield rate under different process parameter standard deviations, a multi-confidence Gaussian process model is established, and a Markov chain Monte Carlo method is used to select representative points for calculating the ranking score. The following sub-steps are included:

Step 4.1: Establish a multi-confidence Gaussian process model for the yield rate under different process parameter standard deviations.

Since the integral in (7) has no analytical solution, this method uses the MC method to approximate it, namely:

in is a set of selected representative points. In the process of comparing the design points, some low-precision yield values with different standard deviations σ are generated. This method uses a multi-confidence model to learn the correlation between yields with different standard deviations σ, and generates the representative points based on this model.

More specifically, the present invention adopts the multi-confidence Gaussian process regression model NARGP method [15], which is expressed as:

Y ^h (x) = g _h (x, Y ^l (x)), (14)

where Y ^l (·) is the output of the low-confidence model, i.e., the yield under low σ, Y ^h (·) is the output of the high-confidence model, i.e., the yield under high σ, and gh(·) represents the Gaussian process regression model based on the design parameters x and the low-σ yield Y ^l (x).

The present invention uses the yields under 1-σ and 2-σ as two low-confidence sources, and selects the yield under 2.5-σ as a high-confidence source. To establish a regression model for the yield under 2.5-σ, the traditional single-confidence GPR method only uses the yield data obtained under 2.5-σ, but the NARGP method can use the yield data under 1-σ and 2-σ, which helps to accurately model the yield under 2.5-σ.

Figure 5 compares the fitting effects of the traditional single-confidence GPR model and the multi-confidence NARGP model, where the horizontal axis represents the design parameters and the vertical axis represents the yield; the black solid line is the actual yield of the circuit at 2.5-σ, the blue dashed line is the yield predicted by the multi-confidence model, and the green dashed line is the yield predicted by the single-confidence model; the training data comes from a comparator circuit (see Figure 7). Specifically, the single-confidence GPR model is trained using only 5 high-confidence data points at 2.5-σ. The multi-confidence model is constructed from the same 5 high-confidence points and an additional 20 low-σ yield points from two low-confidence sources. The figure shows that the multi-confidence NARGP model improves the fitting accuracy compared to the single-confidence GPR model.

Step 4.2: Use the Markov Chain Monte Carlo method to select representative points for calculating the ranking score.

After establishing the NARGP model, the expected improvement (EI) function of yield under i-σ[16] can be calculated by the following formula:

Where I(Y ⁱ (x)) is the improvement of the yield ^Yi (x) predicted by the multi-confidence model, is the mathematical expectation, and max(,) is the maximum value.

In order to obtain the representative points in formula (13), the present invention uses the EI ⁱ function to select representative points for calculating the ranking score. Specifically, the MCMC sampling method is adopted, and sampling is performed in the design space with EI ⁱ as the target distribution. EI ⁱ tends to generate sampling points in the high yield area. In practice, about N _rep /3 points are sampled in each EI ⁱ , and finally N _rep design points are selected from all sampling points as representative points.

In step 5 of the present invention, the preferred Bayesian optimization is used to solve the sorting score optimization problem, wherein the sorting score is used to calculate the Thompson sampling acquisition function; the multi-scale sampling method is used to compare the yield of the next candidate point x _next with the current optimal design point x _τ ; the optimal yield candidate set B is updated according to the comparison result, and the optimal design point is selected from B, and N _{batches of} simulations are added to it to improve the yield analysis accuracy of the point; it is continuously iterated until the yield meets the requirements or reaches the maximum number of iterations N _pbo , and finally the optimal design parameters and the corresponding yield results are obtained. It includes the following sub-steps:

Step 5.1: Use the preferred Bayesian optimization to solve the ranking score optimization problem, where the ranking score is used to calculate the Thompson sampling acquisition function.

In Bayesian optimization, the acquisition function provides a posterior distribution including mean and variance based on the probability model to find the next possible optimal point. The present invention adopts the Thompson sampling function [17] as the acquisition function to guide the exploration and utilization in the optimization process.

The Thompson sampling function first randomly generates a sample from the posterior Gaussian distribution predicted by the GPC model The randomness of sample generation ensures the algorithm's exploration ability and avoids falling into local optimality. The Thompson sampling function selects the design point with the maximum prediction ranking score as the next candidate point. This method selects the optimal scoring design point to ensure the utilization capacity of the algorithm.

Thompson sampling is:

The constant term Vol(D) ^-1 in equation (13) is omitted in (16), which does not affect the optimization result. is the representative point carefully selected in step 4. This method selects a design point with the highest average winning probability compared with the representative point as the next candidate point x _next .

Specifically, the present invention solves the optimization problem defined in (16) based on the multiple starting point Broyden-Fletcher-Goldfarb-Shanno, MSP-BFGS) [18] global optimization algorithm to obtain the next candidate point x _next .

Figure 6 shows the steps of using Thompson sampling to obtain the function to select the next candidate point, where Figure 6(a) shows the sample randomly sampled from the posterior distribution of the preference function. The blue triangle corresponds to the next candidate point that is finally selected, and the preference function sample along the x′ axis By integrating, you can get the corresponding ranking score As shown in Figure 6(b), the design point with the maximum ranking score (the position of the blue dashed line) is selected as x _next . It can be seen that the blue dashed line at x _next in Figure 6(a) passes through the dark red area to the greatest extent, indicating that its yield is most likely to be higher than the yields of other design points.

Step 5.2: Use the multi-scale sampling method to compare the yield of the _next candidate point xnext with the current optimal design point _xτ .

The next design pair to be compared is [x _next , x _τ ], where x _τ represents the current optimal yield design point. Three values are selected for the standard deviation σ of the process parameters in the variable scale sampling method, namely 1-σ, 2-σ and 2.5-σ. The maximum number of simulations N _max is assigned to the yield analysis under each σ, and the present invention takes N _max = 100. The standard deviation σ of the process parameters is increased from 1 to 2.5 in sequence, and the yield analysis is performed on x _next , and the comparison result h _next is obtained as:

The design point _xa is significantly better or significantly worse than the design point _xb, which is defined as:

Where τ ⁱ represents the current maximum yield value under i-σ, and σ _Yi (x) are the yield values and corresponding standard deviations obtained by performing MC analysis on design point x under i-σ, which can be calculated by (10) and (11). The significance indicates whether the yield of x _a obtained based on MC analysis is better or worse than the yield of x _b in a probabilistic sense under 1-σ, 2-σ or 2.5-σ.

Step 5.3: Update the optimal yield candidate set B according to the comparison result of step 5.2, and select the optimal design point from B, increase N _{batches of} simulations for it, and improve the yield analysis accuracy of this point.

If the yield comparison result of the next candidate point x _next and the current optimal design point x _τ is h _next = 1, the optimal yield candidate set B will be cleared and x _next will be added. If there is no significant difference in the yield between x _next and x _τ under the standard deviation σ of the three process parameters, x _next will be added to the optimal yield candidate set B.

In order to obtain the 1-σ high-precision yield of the optimal yield design point x ^* , the present invention adopts the iterative yield analysis method proposed in the literature [12] to gradually improve its yield analysis accuracy. That is, in each iteration, the ranking scores of all design points in the optimal yield candidate set B are calculated, and then the design point with the highest ranking score is selected. N _batches of simulation points are sampled in the process space under the process parameter standard deviation σ=1, and SPICE simulation is performed to gradually improve its 1-σ yield analysis accuracy.

Step 5.4: Add the new data point ([x _next , x _τ ], h _next ) obtained in step 5.2 to the data set.

Step 5.5: If the yield rate does not meet the requirement and the number of iterations is less than the maximum number of iterations N _pbo , jump to step 3 and perform iterative optimization; otherwise, the optimization ends and the optimal design parameters and the corresponding yield rate results are output.

The present invention provides an analog circuit yield optimization method based on a preference learning model, wherein, in order to quickly determine the pros and cons of the yields of different design points, a multi-scale sampling method is adopted to gradually increase the standard deviation σ of the process parameter distribution and perform yield analysis, and the simulation cost of distinguishing the pros and cons of the design points is reduced by amplifying the gap between the yields of different design points; secondly, a discrete Gaussian process classification model based on preference learning is adopted to model the comparison results of the multi-scale sampling yields between the design points; then, the Gaussian process classification model is used to model the comparison results, based on the posterior distribution of the predicted preference, the exploration and utilization in the process of obtaining the function balance optimization by using Thompson sampling, and the design point with the highest probability of winning in the yield comparison is found, and then, in order to utilize the yield numerical information obtained during multi-scale sampling, a multi-confidence modeling method is adopted to learn the correlation of the yields under different process parameter standard deviations, and use it for sorting score approximation, so as to further improve the modeling and optimization efficiency of the algorithm.

The advantages of the present invention are:

1. The present invention proposes a method based on preference learning to transform the analog circuit yield optimization problem into a ranking score optimization problem, thereby avoiding the frequent execution of high-precision yield analysis;

2. The preferred Bayesian optimization method is applied to the yield optimization of analog circuits. The multi-scale sampling method is used to quickly determine the advantages and disadvantages of the yields of different design points. The design space is searched based on the preference information. The advantages of the high sampling efficiency of the Bayesian optimization method and the low cost of multi-scale sampling yield analysis are utilized to improve the efficiency of analog circuit yield optimization.

3. Experimental results show that, compared with the best analog circuit yield optimization method currently available, the simulation time acceleration ratio of the present invention is 5.90 to 12.66 times without reducing the optimization accuracy.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram showing the relationship between the yield rate of an analog circuit and the standard deviation σ of the process parameter distribution.

FIG. 2 is a flow chart of the present invention.

FIG. 3 is a schematic diagram showing the relationship between a yield curve of a comparator circuit and a corresponding ranking score curve.

Figure 4 is a comparison chart of the true preference function and the predicted results of the GPC model.

Figure 5 is a comparison of the fitting effects of the single-confidence GPR model and the multi-confidence NARGP model.

FIG. 6 is a schematic diagram of obtaining the next candidate point using the Thompson sampling acquisition function.

FIG7 is a circuit diagram of a comparator circuit.

FIG8 is a circuit diagram of a charge pump circuit.

DETAILED DESCRIPTION

The method of the present invention is further described below through the implementation process of a specific example.

Implementation Example 1

This example uses the circuit shown in Figure 7. Figure 7 is a circuit diagram of a comparator circuit with a 1.8V supply voltage in a 180nm process.

Among the input parameters, the design parameter is the width of the transistor, which has a total of 12 dimensions; the process parameters include all global and local process perturbation parameters; the failure threshold of the circuit performance is the offset voltage V _off ≤30mV at a sampling frequency of 200MHz at 30°C, the sensitive voltage V _sen ≤2mV, and the maximum operating frequency speed≥1GHz; the number of points in the initial data set of the Gaussian process classification model N _init =30; the maximum number of iterations of the preferred Bayesian optimization N _pbo =800; the number of representative points of the sorting score N _rep =100; the maximum number of simulations for variable scale sampling yield analysis N _max =100; the maximum number of simulations for calling the analog circuit performance optimization solver N _pre =300; the number of simulation points per batch for iterative yield analysis N _batch =30.

The comparison results of the method of the present invention and the algorithms of Ref.[8] and Ref.[9] are shown in Table 1, where PBO represents the yield optimization algorithm proposed by the present invention. In order to reduce the impact of random fluctuations, all algorithms in this example are run 10 times. The number of simulations called by the performance optimization solver under the TT process corner of the analog circuit has been added to the results of PBO.

Table 1 Comparator circuit yield optimization results and speed comparison

Since Ref.[8] is the fastest algorithm in this example, Ref.[8] is used as the speed benchmark. The PBO method has a speedup ratio of 12.66 times that of the Ref.[8] method while ensuring that the yield of the optimization result is higher than 99%. The experimental results verify the effectiveness of this method.

Implementation Example 2

This example uses the circuit shown in Figure 8. Figure 8 is a circuit diagram of a charge pump circuit in a 40nm process.

Among the input parameters, the design parameters are the length and width of the transistor, which has a total of 36 dimensions; the process parameters include all global and local process perturbation parameters; the failure threshold of the circuit performance is diff1≤25μA, diff2≤25μA, diff3≤10μA, diff4≤10μA, deviation≤6μA; other input parameters are the same as those in Example 1.

The comparison results of this method with the algorithms of Ref.[8] and Ref.[9] are shown in Table 2. Since Ref.[9] is the fastest algorithm in this example, Ref.[9] is used as the speed benchmark. The PBO method has a speedup ratio of 6.07 times relative to the Ret.[9] method while ensuring that the yield of the optimization result is higher than 99%. The experimental results verify the effectiveness of this method.

Table 2 Yield optimization results and speed comparison of charge pump circuit

Implementation Example 3

This example uses a power amplifier designed using TSMC 65nm technology, which operates at 2.4GHz. It uses an array-based design that contains 2048 repeating units, each unit contains 4 transistors, and a total of 8192 transistors.

Among the input parameters, the design parameters are the length and width of the transistor, which have a total of 5 dimensions; the process parameters include all global and local process perturbation parameters; the failure threshold of the circuit performance is the output efficiency Eff ≥ 57%, the output power Pout ≥ 22.5dBm and the total harmonic distortion thd ≤ 12.65dB; due to the extremely long simulation time of the power amplifier and the high computing resource usage, the experiment was repeated only 6 times and the results were statistically analyzed, and the maximum number of simulations for each optimization was limited to 30,000 times; the other input parameters are the same as those in Example 1.

The comparison results of this method with the algorithms of Ref.[8] and Ref.[9] are shown in Table 3. Since Ref.[9] is the fastest algorithm in this example, Ref.[9] is used as the speed benchmark. Ref.[8] and Ref.[9] successfully obtained the design point with the target yield greater than 99% in 2 and 4 times in 6 repeated experiments respectively. This method can find the target yield design point in all six repeated experiments, requiring an average of 4017 simulations, and achieved a 5.90 times acceleration ratio compared to Ref.[9]. The experimental results verify the effectiveness of this method.

Table 3 Yield optimization results and speed comparison of power amplifier circuit

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Claims (6)

1. A method for optimizing analog circuit yield based on a preference learning model, characterized in that it includes, first, converting the analog circuit yield optimization problem into a ranking score optimization problem based on a preference learning method; second, using a Gaussian process classification model to model the comparison results of yields at different design points; third, using a multi-confidence modeling method to model the yields under different process parameter standard deviations, and selecting representative points based on the model to approximately calculate the ranking score; fourth, using preference Bayesian optimization for solving, wherein Thompson sampling is used to obtain the function balance optimization and exploration process, and iterates continuously until the yield meets the requirements or reaches the maximum number of iterations; specifically including: Input parameters: 1. Analog circuit netlist; 2. Probability distribution density function of process parameters; 3. Failure threshold of circuit performance index c _i , i=1, ..., k, where k is the number of circuit performance indexes of interest, and it is assumed that for the i-th performance index y _i of the circuit, if the simulation result y _i ≥ c _i, the circuit is considered successful, otherwise it is considered a failure; 4. Number of points N _init of the initial data set of the Gaussian process classification model; Maximum number of iterations N _pbo of the preferred Bayesian optimization; Number of representative points of the ranking score N _rep ; Maximum number of simulations N _max for variable scale sampling yield analysis; Maximum number of simulations N _pre for calling the analog circuit performance optimization solver; Number of simulation points per batch N _batch for iterative yield analysis; Output: Optimal design parameters and yield values obtained by analog circuit yield optimization; Includes steps: Step 1: Based on the preference learning method, the analog circuit yield optimization problem is transformed into a ranking score optimization problem; Step 2: Data set initialization, i.e., using the TT (Typical-Typical) process corner performance optimization method to obtain N _init prior solutions, and perform low-precision yield analysis as the data set initial point for the preferred Bayesian optimization hot start, and add the current optimal design point to the optimal yield candidate set B (Basket); Step 3: Use the Gaussian process classification model to model the comparison results of the yield of different design points in the data set; Step 4: For the yield rate under different process parameter standard deviations, a multi-confidence Gaussian process model is established, and the Markov Chain Monte Carlo (MCMC) method is used to select representative points for calculating the ranking score; Step 5: Use the preferred Bayesian optimization to solve the sorting score optimization problem, in which the sorting score is used to calculate the Thompson sampling acquisition function; use the multi-scale sampling method to compare the yield of the next candidate point x _next with the current optimal design point x _τ ; update the optimal yield candidate set B according to the comparison result, and select the optimal design point from B, increase N _batch simulations for it, and improve the yield analysis accuracy of this point; continue to iterate until the yield meets the requirements or reaches the maximum number of iterations N _pbo , and finally obtain the optimal design parameters and the corresponding yield results. 2. The method according to claim 1, characterized in that, in step 1, based on the preference learning method, the analog circuit yield optimization problem is converted into a ranking score optimization problem; In analog circuits, design parameters refer to the length, width, capacitance, and resistance of transistors, which are variables that can be controlled by circuit designers; process parameters refer to the threshold voltage variables provided by chip manufacturers that characterize process disturbances; the yield mentioned above refers to the yield generated by process disturbances; For an analog circuit, the design parameter x is a d _x- dimensional vector in the design space D, It represents the variables such as the length and width of the transistor that can be controlled by the circuit designer; the process parameter s is a d _s- dimensional vector in the process space V, represents variables such as threshold voltage, whose probability distribution is usually provided by the process manufacturer and satisfies the normal distribution. Without loss of generality, assuming that the process parameters are independent of each other and have nothing to do with the design parameters, the probability density function (PDF) of the process parameter s is: Given design parameters and process parameters (x, s)∈(D, V), x∈D, s∈V, the circuit performance of interest y＝[y ₁ , y ₂ , …, y _k ] ^T can be obtained through SPICE simulation, and the corresponding threshold condition c＝[c ₁ , c ₂ , …, c _k ] ^T is determined by the designer; only when the circuit performance meets all the conditions, that is, y _i ≥ c _i , i＝1, …, k, is it considered qualified, otherwise it is considered failed; Given a design parameter x, the analog circuit yield Y(x) is defined as Y(x)＝∫ _V I(x,s)p(s)ds (2) Wherein, the index function I(x, s) = AND(y _i ≥ c _i ), i = 1, ..., k, and AND(·) represents the logical function AND; The analog circuit yield optimization problem is to obtain the design point x ^* with the maximum yield Y, that is, Reasonable analog circuit design should ensure that the circuit meets all performance indicators under the TT process angle; by adding this constraint, the search space of the algorithm can be reduced and the convergence speed can be improved. Therefore, the traditional analog circuit yield optimization problem is formally defined as: Where _yi (x, TT) is the i-th performance value of the analog circuit to be optimized when the design parameter is x under the TT process angle; In this method, the constrained optimization problem defined in (4) is converted into an unconstrained form to handle the constraints in the optimization problem. The design goal (Figure of Merit, FOM) is described as: Where ω _i , i = 1, 2, …, k is the weight, representing the importance of the i-th performance indicator; Given a design duel [x, x′]∈D×D consisting of two design points x and x′, the yield comparison result h([x, x′])∈{0,1} is obtained by calculating t(x) and t(x′); if t(x)≥t(x′), then h＝1, indicating that x is better than x′; otherwise h＝0, indicating that x is not better than x′; Formally, we define π([x, x′]) as a preference function, which represents the probability that t(x) ≥ t(x′). We design the comparison result of [x, x′] to follow the Bernoulli distribution: Therefore, the ranking score is defined as: R(x)＝Vol(D) ^-1 ∫ _D π([x, x′])dx′, (7) Where Vol(D) represents the volume of the design space, which is a constant and can be ignored during the optimization process; the physical meaning of R(x) is the proportion of all design points in the design space D that are worse than the design point x, that is, the average probability that the yield of x is higher than the yield of other design points; The globally optimal design point should always win; if all design points are sorted by yield value, then finding the design point with the best yield is equivalent to getting the design point with the highest sorting score; Therefore, the analog circuit yield optimization problem can be transformed into a ranking score optimization problem: . 3. The method according to claim 1, characterized in that, in step 2, data set initialization is performed, N _init prior solutions are obtained by using a TT process corner performance optimization method, and low-precision yield analysis is performed as the data set initial point for the preferred Bayesian optimization hot start, and the current optimal design point is added to the optimal yield candidate set B (Basket); comprising the following sub-steps: Step 2.1: Obtain N _init prior solutions using the TT process corner performance optimization method; According to the trade-off relationship between analog circuit yield and performance under TT process corner, the construction of the initial solution for analog circuit yield optimization is transformed into the performance optimization problem under TT process corner of analog circuit: The formula means searching for a design point whose performance is slightly greater than the constraint threshold. _ωi is a given weight, representing the importance of the i-th performance indicator. ∈ is a constant coefficient used to measure the distance between the nominal performance _yi (x, TT) and the threshold _ci under the TT process angle. Set _ωi = 1, i∈1..k and Then, the weighted expected improvement (WEI) Bayesian optimization algorithm WEIBO is used to solve the performance optimization problem of the analog circuit under the TT process corner defined in (9), and the design points generated in all iterative optimizations are recorded, where the maximum number of simulations for calling the solver is set to N _pre ; from the design points generated by the iterative optimization, N _init points whose nominal performance under TT meets the failure threshold and has the minimum f(x) value are selected as the initial points for the preferred Bayesian optimization hot start; Step 2.2: Perform low-precision yield analysis on the obtained N _init initial design points to establish an initial data set, and add the current optimal design point to the optimal yield candidate set B; For the N _init initial design points obtained in step 2.1, the MC method with strong universality is used. Under the process parameter standard deviation σ=1, 2*N _batch sampling points are allocated to perform low-precision yield analysis to obtain the corresponding low-precision yield value, where N _batch is set to 30, which is much lower than the number of simulations required for high-precision yield analysis, such as 1000; Different design points are combined in pairs to form design pairs to compare the yield rate and establish an initial data set. The MC method takes N sample points s _i , i = 1, ..., N in the process space based on the probability density function p(s) of the process parameter s, and calculates the yield rate by counting the number of qualified samples. Variance of Yield Estimate The relationship between the estimated value Y _MC (x) and the number of sampling points N is: Where the confidence level k _γ is a constant; From the above initial data set, select the design point with the highest yield and add it to the optimal yield candidate set B. 4. The method according to claim 1, characterized in that, in step 3, a Gaussian process classification model is used to model the comparison results of the yields of different design points in the data set; The Gaussian process classification method is used to model the yield comparison results, that is, the preference information; the built model is a probabilistic model GPC, which can provide the predicted posterior distribution of the comparison results and help design search strategies to achieve a balance between utilization and exploration; The Gaussian process classification model uses nonlinear activation functions to process classification problems, such as the Logistic function, to convert the continuous output of the Gaussian process regression model into a binary output; the GPC model defines an implicit function z([x, x′]) and assumes that it obeys the GP prior, and its value covers the entire real number range. Then, z([x, x′]) is compressed by the Logistic function to obtain the prior probability distribution of π([x, x′]): Among them, the preference function π([x, x′]) is the result of GPC modeling, which is used to predict the high and low relationship between the yields of different design points. 5. The method according to claim 1, characterized in that, in step 4, for the yield under different process parameter standard deviations, a multi-confidence Gaussian process model is established, and a Markov chain Monte Carlo method is used to select representative points for calculating the ranking score; comprising the following sub-steps: Step 4.1: Establish a multi-confidence Gaussian process model for the yield rate under different process parameter standard deviations; The MC method is used to approximate it, namely: where x ₁ , x ₂ , …, is a set of representative points; in the process of comparing the design points, some low-precision yield values under different standard deviations σ are generated, and the correlation between the yields under different standard deviations σ is learned by using a multi-confidence model, and the representative points are generated based on this model; The multi-confidence Gaussian process regression model NARGP method is used, which is expressed as: Y ^h (x) = g _h (x, Y ^l (x)), (14) Where Y ^l (·) is the output of the low confidence model, i.e., the yield rate under low σ, Y ^h (·) is the output of the high confidence model, i.e., the yield rate under high σ; g _h (·) represents the Gaussian process regression model based on the design parameter x and the low σ yield rate Y ^l (x); The yield rates under 1-σ and 2-σ are taken as two low-confidence sources, and the yield rate under 2.5-σ is selected as a high-confidence source; in order to establish a regression model for the yield rate under 2.5-σ, the NARGP method uses the yield rate data under 1-σ and 2-σ to accurately model the yield rate under 2.5-σ; Step 4.2: Use the Markov Chain Monte Carlo method to select representative points for calculating the ranking score; After the NARGP model is established, the expected improvement (EI) function of the yield under i-σ is calculated by the following formula: Where I(Y ⁱ (x)) is the improvement of the yield ^Yi (x) predicted by the multi-confidence model, is the mathematical expectation, max(,) is the maximum value; In order to obtain the representative points in formula (13), the EI ⁱ function is used to select representative points for calculating the ranking score. The MCMC sampling method is adopted to sample in the design space with EI ⁱ as the target distribution. EI ⁱ tends to generate sampling points in the high yield area. In practice, about N _rep /3 points are sampled in each EI ⁱ . Finally, N _rep design points are selected from all sampling points as representative points. 6. The method according to claim 1, characterized in that, in step 5, the preferred Bayesian optimization is used to solve the sorting score optimization problem, wherein the sorting score is used to calculate the Thompson sampling acquisition function; the yield of the next candidate point x _next is compared with the yield of the current optimal design point x _τ by a multi-scale sampling method; the optimal yield candidate set B is updated according to the comparison result, and the optimal design point is selected from B, and N _{batches of} simulations are added to it to improve the yield analysis accuracy of the point; it is continuously iterated until the yield meets the requirements or reaches the maximum number of iterations N _pbo , and finally the optimal design parameters and the corresponding yield results are obtained; comprising the following sub-steps: Step 5.1: Use the preferred Bayesian optimization to solve the ranking score optimization problem, where the ranking score is used to calculate the Thompson sampling acquisition function; In Bayesian optimization, the acquisition function provides a posterior distribution including mean and variance based on the probability model to find the next possible optimal point; this method uses the Thompson sampling function as the acquisition function, which is explored and utilized in the optimization process; The Thompson sampling function first randomly generates a sample from the posterior Gaussian distribution predicted by the GPC model The randomness of sample generation ensures the algorithm's exploration ability and avoids falling into local optimality. The Thompson sampling function selects the design point with the maximum prediction ranking score as the next candidate point, and the optimal scoring design point is selected to ensure the utilization capacity of the algorithm; Thompson sampling is: The constant term Vol(D) ^-1 in equation (13) is omitted in (16), which does not affect the optimization result; x ₁ , x ₂ , …, is the representative point selected in step 4; select a design point with the highest average winning probability compared with the representative point as the next candidate point x _next ; Solve the optimization problem defined in (16) based on the multiple starting point Broyden-Fletcher-Goldfarb-Shanno (MSP-BFGS) global optimization algorithm to obtain the next candidate point x _next ; Step 5.2: Use the multi-scale sampling method to compare the yield of the next candidate point x _next with the current optimal design point x _τ ; The next design pair to be compared is [x _next , x _τ ], where x _τ represents the current optimal yield design point; select three values for the standard deviation σ of the process parameters in the variable scale sampling method, namely 1-σ, 2-σ and 2.5-σ; assign the maximum number of simulations N _max for the yield analysis under each σ, and take N _max = 100; increase the standard deviation σ of the process parameters from 1 to 2.5 in turn, perform yield analysis on x _next , and obtain the comparison result h _next as: The design point _xa is significantly better or significantly worse than the design point _xb, which is defined as: Where τ ⁱ represents the current maximum yield value under i-σ, and The yield value and the corresponding standard deviation are obtained by performing MC analysis for the design point x under i-σ respectively, and are calculated by (10) and (11); the significance indicates whether the yield of x _a obtained based on MC analysis is better or worse than the yield of x _b in a probabilistic sense under 1-σ, 2-σ or 2.5-σ; Step 5.3: Update the optimal yield candidate set B according to the comparison result of step 5.2, and select the optimal design point from B, increase N _{batches of} simulations for it, and improve the accuracy of yield analysis at this point; If the yield comparison result of the next candidate point x _next and the current optimal design point x _τ is h _next = 1, the optimal yield candidate set B will be cleared and x _next will be added; if under the standard deviation σ of the three process parameters, there is no significant difference between the yields of x _next and x _τ , then x _next will be added to the optimal yield candidate set B; The iterative yield analysis method is used to gradually improve the yield analysis accuracy and obtain the 1-σ high-precision yield of the optimal yield design point x ^* . In each iteration, the ranking scores of all design points in the optimal yield candidate set B are calculated, and then the design point with the highest ranking score is selected. N _batches of simulation points are sampled in the process space under the process parameter standard deviation σ=1, and SPICE simulation is performed to gradually improve the 1-σ yield analysis accuracy. Step 5.4: Add the new data point ([x _next , x _τ ], h _next ) obtained in step 5.2 to the data set; Step 5.5: If the yield rate does not meet the requirement and the number of iterations is less than the maximum number of iterations N _pbo , jump to step 3 and perform iterative optimization; otherwise, the optimization ends and the optimal design parameters and the corresponding yield rate results are output.