CN117436224A - Analog circuit yield optimization method based on preference learning model - Google Patents

Abstract

The invention belongs to the technical field of integrated circuits, and relates to an analog circuit yield optimization method based on a preference learning model. In the method, a multi-scale sampling method is adopted, the standard deviation sigma of the process parameter distribution is gradually improved, the yield analysis is carried out, and the difference between the yields of different design points is amplified, so that the yield of the design points can be more easily distinguished; modeling a comparison result of the multi-scale sampling yield between design points by adopting a Gaussian process classification GPC model based on preference learning; optimizing a GPC model by adopting a preference Bayesian optimization framework, acquiring utilization and exploration in the function balance optimization process by utilizing Thompson sampling, and searching a design point with the maximum winning probability in yield comparison; and modeling the yield under different process parameter standard deviations by adopting a multi-confidence modeling method, and further improving the accuracy of the Thompson sampling acquisition function. The method can greatly reduce the simulation times required by optimizing the yield of the analog circuit.

Description

Analog circuit yield optimization method based on preference learning model

Technical Field

The invention belongs to the technical field of integrated circuits, and relates to simulated circuit yield optimization in integrated circuit manufacturability design. In particular to an analog circuit yield optimization method based on a preference learning model. The method can greatly reduce the simulation times required by optimizing the yield of the analog circuit.

Background

According to the state of the art, as the feature size of the semiconductor manufacturing process is reduced to nanometer scale, process disturbance has a great influence on the yield of analog circuits, reliability challenges in analog circuit design are increasingly serious, and the industry is recently focused on the problem of optimizing the yield of analog circuits [1].

Typically, analog circuit yield optimization employs iterative optimization loops, in each of which design parameters, such as transistor width and length, are adjusted, and then very time-consuming yield analysis is performed. The yield analysis generally adopts simulation or Monte Carlo simulation under different process angles, thousands of simulations are required to be executed to ensure accurate yield analysis results, so that the time cost for optimizing the yield of the analog circuit is extremely high, and the reduction of the overall simulation time for optimizing the yield of the analog circuit becomes the most urgent requirement.

Regarding the analog circuit yield optimization problem, the main methods currently include the following three types.

The process corner-based methods [2] - [4] optimize the "worst" performance of the analog circuit at all process corners. This approach avoids costly yield analysis processes, but the optimization results are not accurate and often result in over-design. Furthermore, this approach is costly to search for "worst" performance if the process space dimensions are high.

The Monte Carlo (MC) based method is widely used due to its high precision and versatility. Literature [5,6] applies optimal computational budget allocation (Optimal Computational Budget Allocation, OCBA) techniques to MC acceleration, using evolutionary algorithms for optimization problem solving. Document [7] uses a kernel density estimation method for yield modeling and proposes a multi-start-point expectation maximization algorithm to solve this problem. Document [8] proposes a self-adaptive yield analysis method and finds the optimal design by using a bayesian optimization algorithm based on a weighted expected lifting function. The literature [9] is further optimized by adopting a Gaussian process regression and maximum entropy searching method combined with a neural network on the basis of the literature [8 ]. Although bayesian optimization methods have shown some advantages, the total number of simulations required is excessive. For example, the current most advanced methods [8] and [9] require 6000 to 20000 simulations for one yield optimization, which is time-unacceptable for large scale analog circuits.

Document [10] attempts to build a proxy model of circuit performance to replace expensive circuit simulations based on proxy model (surrogate model) approach, thereby reducing the cost of yield optimization. However, these methods often require a large number of simulated sample points to ensure modeling accuracy, and the number of sample points required for modeling grows exponentially with process space dimensions [8], with significant difficulty in building proxy models under FinFET advanced processes.

Studies have disclosed that the scaled-sigma sampling (SSS) 11 method has been successfully applied to yield analysis and optimization of SRAM circuits. Because the failure rate of the SRAM circuit is extremely low, the variable-scale sampling method artificially increases the standard deviation sigma value of Gaussian distribution obeyed by process disturbance, for example, the standard deviation provided by a chip foundry is 1, and the SSS method improves the standard deviation to 3, so that the failure rate of a design point is improved, and the simulation cost of yield analysis is reduced. The literature [7,8] shows that performing yield analysis using the SSS method does not change the yield good-bad relationship of the two design points. In addition, the research team discovers that the difference between the yields of different design points of the analog circuit can be amplified by changing the standard deviation sigma value of the process.

As shown in fig. 1, the horizontal axis represents the standard deviation σ of gaussian distribution to which the process parameter perturbation is subjected, and the vertical axis represents the yield of the charge pump circuit (see fig. 8), and curves of different colors correspond to different design points. It can be seen that as the standard deviation σ of the process parameter increases, the process disturbance amplitude increases and the yield of the design point is significantly reduced. More importantly, the yield difference between any two design points changes with sigma, and the place where the yield difference between the design points is the largest is mainly sigma= [2,2.5]. For example, the yield gap between design point 1 and design point 3 changes from 0.3% (σ=1) to 6% (σ=2.5), which means that if σ=2.5 is used for yield analysis, a maximum of 200 simulation samples are needed to distinguish them. However, the difference between yields at any two design points is not maximized at σ=2.5. For example, the yield difference between design point 2 and design point 4 in fig. 1 is reduced from 15% (σ=1) to 2% (σ=2.5), so that the yield analysis should be performed with σ=1 at this time to improve the yield analysis efficiency. For this reason, different σ values must be dynamically selected during the optimization process to maximize the yield gap, without being able to use a preset fixed σ value.

The current internationally advanced analog circuit yield optimization methods [8,9] adopt a Gaussian process regression (Gaussian process regression, GPR) model, which is a continuous model aiming at yield.

Based on the current state of the art, aiming at the problem of low optimization efficiency in the existing analog circuit yield optimization method, the inventor of the application intends to provide an analog circuit yield optimization method based on a preference learning model, wherein a Gaussian process classification GPC model is adopted to model a comparison result of multi-scale sampling yield, and particularly a discrete model based on comparison. And the sigma value at the design points is dynamically selected, so that the yield gap between the design points is maximized, the yield comparison result of the design points is obtained at a small simulation cost, and the simulation cost is reduced.

The prior art related to the present invention is that,

[1]G.Gielen,T.Eeckelaert,E.Martens,and T.McConaghy,“Automated synthesis of complex analog circuits,”in European Conference on Circuit Theory and Design,2007.

[2]R.Schwencker,F.Schenkel,M.Pronath,and H.Graeb,“Analog circuit sizing using adaptive worst-case parameter sets,”in Proc.DATE,2002.

[3]M.Barros,J.Guilherme,and N.Horta,“Analog circuits optimization based on evolutionary computation techniques,”Integration,the VLSI Journal,2010.

[4]M.Sengupta,S.Saxena,L.Daldoss,G.Kramer,S.Minehane,and J.Cheng,“Application-specific worst case corners using response surfaces and statistical models,”IEEE TCAD,2005.

[5]B.Liu,F.V.Fernandez,and G.G.Gielen,“Efficient and accurate statistical analog yield optimization and variation-aware circuit sizing based on computational intelligence techniques,”IEEE TCAD,2011.

[6]I.Guerra-Gomez,E.Tlelo-Cuautle,and L.G.de la Fraga,“Ocba in the yield optimization of analog integrated circuits by evolutionary algorithms,”in Proc.ISCAS,2015.

[7]M.Wang,F.Yang,C.Yan,X.Zeng,and X.Hu,“Efficient Bayesian yield optimization approach for analog and sram circuits,”in Proc.DAC,2017.

[8]M.Wang,W.Lv,F.Yang,C.Yan,W.Cai,D.Zhou,and X.Zeng,“Efficient yield optimization for analog and sram circuits via Gaussian process regression and adaptive yield estimation,”IEEE TCAD,2018.

[9]S.Zhang,F.Yang,D.Zhou,and X.Zeng,“Bayesian methods for the yield optimization of analog and sram circuits,”in Proc.ASPDAC,2020.

[10]S.Basu,B.Kommineni,and R.Vemuri,“Variation-aware macromodeling and synthesis of analog circuits using spline center and range method and dynamically reduced design space,”in Proc.VLSI Design,2009.

[11]S.Sun,X.Li,H.Liu,K.Luo,and B.Gu,“Fast statistical analysis of rare circuit failure events via scaled-sigma sampling for high-dimensional variation space,”IEEE TCAD,2015.

[12]X.Wang,C.Yan,Y.Ma,B.Yu,F.Yang,D.Zhou,and X.Zeng,“Analog Circuit Yield Optimization via Freeze-Thaw Bayesian Optimization Technique,”IEEE TCAD,2022.

[13]W.Lyu,P.Xue,F.Yang,C.Yan,Z.Hong,X.Zeng,and D.Zhou,“An efficient bayesian optimization approach for automated optimization of analog circuits,”IEEE TCAS I,2017.

[14]C.Williams and C.Rasmussen.2006.Gaussian processes for machine learning.Vol.2.MIT press Cambridge,MA.

[15]P.Perdikaris,M.Raissi,A.Damianou,N.Lawrence,and G.Karniadakis,“Nonlinear information fusion algorithms for data-efficient multi-fidelity modelling,”Proc.R.Soc.A 473,2198(2017),20160751.

[16]D.R.Jones,M.Schonlau,and W.J.Welch,“Efficient global optimization of expensive black-box functions,”Journal of Global Optimization,1998.

[17]O.Chapelle and L.Li,“An empirical evaluation of thompson sampling,”in Proc.NIPS,2011.

[18]J.Nocedal and S.Wright,Numerical optimization.Springer Science&Business Media,2006.。

disclosure of Invention

The invention aims to provide an analog circuit yield optimization method based on the current state of the art and aims at solving the problem of low optimization efficiency in the existing analog circuit yield optimization method, and particularly relates to an analog circuit yield optimization method based on a preference learning model.

The invention comprises the following steps: firstly, converting an analog circuit yield optimization problem into a sequencing score optimization problem based on a preference learning method; secondly, modeling comparison results of the yields of different design points by adopting a Gaussian process classification model; thirdly, modeling the yield under different process parameter standard deviations by adopting a multi-confidence modeling method, selecting representative points based on the model, and approximately calculating a sequencing score; fourthly, solving by using preferential Bayesian optimization, wherein the utilization and exploration processes in the balance optimization of the Thompson sampling acquisition function are iterated continuously until the yield meets the requirement or the maximum iteration times are reached.

In the invention, (1) a multi-scale sampling method is adopted, the standard deviation sigma of the process parameter distribution is gradually improved, the yield analysis is executed, and the difference between the yields of different design points is amplified, so that the yield of the design points can be more easily distinguished; (2) Modeling a comparison result of the multi-scale sampling yield between design points by adopting a Gaussian process classification GPC model based on preference learning; (3) Optimizing the GPC model by adopting a preference Bayesian optimization framework, namely acquiring utilization and exploration in the function balance optimization process by utilizing Thompson sampling based on posterior distribution of prediction preference, and searching a design point with the maximum winning probability in yield comparison; (4) And modeling the yield under different process parameter standard deviations by adopting a multi-confidence modeling method, and further improving the accuracy of the Thompson sampling acquisition function.

More specifically, the invention adopts a multi-scale sampling (varying-sigma sampling) method, and by gradually improving the standard deviation of the process parameter distribution and executing the yield analysis, the difference between the yields of different design points is amplified, so that the yield of the design points can be more easily distinguished; unlike the continuous gaussian process regression (Gaussian process regression, GPR) model of the current mainstream, the method models the comparison result of multi-scale sampling yield among design points by adopting a discrete gaussian process classification (Gaussian process classification, GPC) model based on preference learning; optimizing a GPC model by adopting a preference Bayesian optimization framework, namely acquiring utilization (explloition) and exploration (expllocation) in the function balance optimization process by utilizing Thompson sampling (Thompson sampling, TS) based on posterior distribution of prediction preference, and searching a design point with the maximum winning probability in yield comparison; and modeling the yield under different process parameter standard deviations by adopting a multi-confidence modeling method, so as to further improve the accuracy of the Thompson sampling acquisition function. The method can greatly reduce the simulation times required by optimizing the yield of the analog circuit.

A flow chart of the analog circuit yield optimization method of the invention is shown in FIG. 2.

Inputting parameters:

1. simulating a circuit netlist;

2. probability distribution density functions of process parameters;

3. failure threshold c of circuit performance index _i I=1,..k, where k is the number of circuit performance indicators of interest and assumes the circuit's thi performance index y _i If the simulation result y _i ≥c _i The circuit is considered to be successful, otherwise, the circuit is considered to be failed;

4. point N of Gaussian process classification model initial dataset _init The method comprises the steps of carrying out a first treatment on the surface of the Maximum number of iterations N of preference Bayesian optimization _pbo The method comprises the steps of carrying out a first treatment on the surface of the Ranking score represents points N _rep The method comprises the steps of carrying out a first treatment on the surface of the Maximum simulation times N of variable-scale sampling yield analysis _max The method comprises the steps of carrying out a first treatment on the surface of the Calling maximum simulation times N of analog circuit performance optimization resolver _pre The method comprises the steps of carrying out a first treatment on the surface of the Iterative yield analysis of the number N of simulation points per batch _batch 。

Outputting a result:

and simulating optimal design parameters and yield values obtained by optimizing the yield of the circuit.

The method comprises the following specific steps:

step 1: converting the analog circuit yield optimization problem into a sequencing score optimization problem based on a preference learning method;

step 2: initializing data sets, namely acquiring N by adopting TT (biological-biological) process corner performance optimization method _init Performing prior solution, performing low-precision yield analysis, taking the solution as a data set initial point for preference Bayesian optimization hot start, and adding the current optimal design point into an optimal yield candidate set B (Basset);

Step 3: modeling comparison results of yield of different design points in the data set by adopting a Gaussian process classification model;

step 4: for the yield under different technological parameter standard deviations, a multi-confidence Gaussian process model is established, and a Markov chain Monte Carlo (Markov Chain Monte Carlo, MCMC) method is utilized to select representative points for calculating a sorting score;

step 5: solving a sorting score optimization problem by adopting preferential Bayesian optimization, wherein a Thompson sampling acquisition function is calculated by using a sorting score; comparing the next candidate point x by adopting a multi-scale sampling method _next With the current optimal design point x _τ Is a yield of (3); updating the optimal yield candidate set B according to the comparison result, selecting an optimal design point from the B, and adding N to the optimal design point _batch Sub-simulation, promote this pointYield analysis accuracy; iteration is continued until the yield meets the requirement or the maximum iteration number N is reached _pbo And finally, obtaining the optimal design parameters and corresponding yield results.

In the step 1, the method based on preference learning converts the analog circuit yield optimization problem into a sequencing score optimization problem.

For analog circuits, design parameters refer to variables such as the length, width, capacitance, resistance of the transistor that can be controlled by the circuit designer. Process parameters refer to variables characterizing process disturbances, such as threshold voltages provided by a chip manufacturer. The yield referred to refers to the yield resulting from process upsets.

For an analog circuit, the design parameter x is D in design space D _x The vector of dimensions is used to determine,representing the variable of the transistor length, width, etc., that can be controlled by the circuit designer. The process parameter s is d in the process space V _s Vector of dimensions>The probability distribution representing the threshold voltage, etc., is typically provided by the process manufacturer and satisfies the normal distribution. Without loss of generality, assuming that the process parameters are independent of each other and of the design parameters, the probability density function (probability density function, PDF) of the process parameters s is

Given design parameters and process parameters (x, s) e (D, V), x e D, s e V, the concerned circuit performance y= [ y ] can be obtained through SPICE simulation ₁ ，y ₂ ，…，y _k ] ^T Corresponding threshold condition c= [ c ₁ ，c ₂ ，…，c _k ] ^T Determined by the designer; only when the circuit performance meets all conditions, i.e. y _i ≥c _i I=1, …, kIt is considered to be acceptable, otherwise it is considered to be ineffective.

Given a design parameter x, the analog circuit yield Y (x) is defined as

Y(x)＝∫ _V I(x，s)p(s)ds (2)

Wherein the index function I (x, s) =and (y _i ≥c _i ) I=1, …, k, AND (·) represents a logical function AND.

The problem of optimizing the yield of the analog circuit is to find the design point x with the maximum yield Y ^* I.e.

In practice, a reasonable analog circuit design should ensure that the circuit meets all performance metrics at the TT process corner. By adding the constraint, the search space of the algorithm can be reduced, and the convergence speed is improved; thus, the conventional analog circuit yield optimization problem is formally defined as:

Wherein y is _i And (x, TT) is an ith performance value when the design parameter of the analog circuit to be optimized is x under the TT process angle.

In order to deal with constraints in the optimization problem, the present invention converts the constrained optimization problem defined in (4) into an unconstrained form, and the design objective (FOM) is described as:

wherein omega _i I=1, 2, …, k is a weight representing the importance of the ith performance indicator.

Given a design pair (design product) [ x, x '] e D x D composed of two design points x and x', the yield comparison result h ([ x, x ']) e {0,1} can be obtained by calculating t (x) and t (x'). If t (x) > t (x '), h=1, indicating that x is better than x'. Otherwise h=0, meaning that x is not better than x'.

Formally, pi ([ x, x ']) is defined as a preference function (preference function), representing the probability of t (x) > t (x'). The comparison of the design versus [ x, x' ] follows the bernoulli distribution (Bernoulli distribution):

thus, a ranking score (rankingscore) is defined as:

R(x)＝Vol(D) ^-1 ∫ _D π([x，x′])dx′， (7)

where Vol (D) represents the design space volume, is a constant and can be ignored during the optimization process. The physical meaning of R (x) is to count the proportion of all design points that are worse than the design point x in the design space D, i.e. the yield of x is higher than the average probability of the yields of other design points.

Intuitively, a globally optimal design point should always win compared to other design points in the design space. If all the design points are ranked according to the value of the yield, finding the design point with the optimal yield is equivalent to finding the design point with the highest ranking score.

Fig. 3 shows the relationship between the yield curve of a comparator circuit and the corresponding rank score curve, wherein the horizontal axis represents the design parameter, i.e., the width of transistor M17 (see fig. 7), the left vertical axis represents the circuit yield, and the right vertical axis represents the rank score. The black solid line is the circuit yield curve, while the red dashed line is the rank score curve. Obviously, the highest point of the ranking score curve is located at the same design point as the maximum value of the yield curve.

Thus, the analog circuit yield optimization problem may be translated into a rank score optimization problem:

in step 2 of the present invention, data set initialization is performed using literature [12 ]]The TT process corner performance optimization method is used for obtaining N _init And a priori solving and performing low-precision yield analysis as a data set initial point for preference Bayesian optimization hot start, and adding the current optimal design point into an optimal yield candidate set B (Basset). Comprises the following substeps:

Step 2.1: using literature [12]]The TT process corner performance optimization method is used for obtaining N _init And a priori solution.

Document [12] converts the construction of the initial solution for optimizing the yield of the analog circuit into the problem of optimizing the performance of the analog circuit under the TT process angle according to the compromise relation between the yield of the analog circuit and the performance under the TT process angle:

wherein the formula means that the search performance is slightly larger than the design point, omega of the constraint threshold _i Is given weight representing the importance of the ith performance indicator. E is a constant coefficient used to measure the nominal performance y at the TT process corner _i (x, TT) and threshold c _i Distance between them. Omega is set in the invention _i =1, i e 1..k and

a weighted expectation promotion (weighted Expected Improvement, wEI) Bayesian optimization algorithm WEIBO [13 ] is then employed]Solving the performance optimization problem under the process angle TT of the analog circuit defined in the step (9), and recording design points generated in all iterative optimization, wherein the maximum simulation times of calling the resolver is set as N _pre . From design points resulting from iterative optimization, N is selected for TT sub-nominal performance meeting failure threshold and having a minimum f (x) value _init And (3) taking the point as an initial point of optimizing the hot start by preference Bayes.

Step 2.2: n to be obtained _init Performing low-precision yield analysis at each initial design point, establishing an initial data set, andand adding the current optimal design point into the optimal yield candidate set B.

In the invention, aiming at N obtained in the step 2.1 _init The initial design points are distributed 2*N by adopting a MC method with strong universality under the condition that the standard deviation sigma=1 of the technological parameter _batch Sampling points, performing low-precision yield analysis to obtain corresponding low-precision yield values, wherein N is _batch Set to 30, which is well below the number of simulations required for high precision yield analysis, e.g., 1000.

And combining different design points two by two to form a design comparison yield, and establishing an initial data set. The MC method adopts N sample points s in a process space based on a probability density function p(s) of a process parameter s _i I=1, …, N, and the yield is calculated by counting the number of qualified samples therein as

Variance of yield estimatesAnd the estimated value Y _MC (x) The relation with the sampling point number N is as follows:

where confidence level k _γ Is constant. For example, k _γ =1.645 corresponds to a confidence of 90%.

And selecting a design point with the highest yield from the initial data set, and adding the design point into the optimal yield candidate set B.

In the step 3, a Gaussian process classification model is adopted to model comparison results of yield of different design points in a data set.

Since the comparison of the design pair [ x, x' ] is binary data, while the regression model is generally applicable to continuous data, it is difficult to model such discrete data. The invention uses Gaussian process classification [14] method to model the yield comparison result, namely preference information, and as a probability model, GPC can provide the prediction posterior distribution of the comparison result, thereby being beneficial to design of search strategy to realize the balance of utilization and exploration.

Typically, to address classification problems, gaussian process classification models use a nonlinear activation function, such as a Logistic function, to convert the continuous output of the gaussian process regression model to a binary output. For example, the GPC model defines a hidden function z ([ x, x ' ]) and assumes that it obeys GP priors, its values contain the entire real range, and then compresses z ([ x, x ' ]) by a Logistic function to obtain a priori probability distribution of pi ([ x, x ' ]):

the preference function pi ([ x, x' ]) is a modeling result of the GPC model, and can be used for predicting the high-low relationship between the yields of different design points.

FIG. 4 shows a comparison of the true preference function pi ([ x, x ' ]) and the GPC model prediction result, wherein FIG. 4 (a) is a true preference function, the x-axis and the x ' -axis both represent design parameters, the color bars correspond to preference function values, revealing preference information of the design point x relative to the design point x ', the darker the red, the greater the probability that the yield Y (x) of the design point x is higher than the yield Y (x ') of x '; the black intersection points mark the area with the maximum value of the preference function, namely the design area needing to be concerned; FIG. 4 (b) is a graph showing a preference function predicted by GPC models, selecting 5 data points (black dots) on the yield curve (black solid line) in FIG. 3, constructing a training set of classification models comprising 25 data points by combining two by two to form a design pair and comparing, and training GPC models based on the data sets; it is shown that although the preference function predicted by the GPC model is not exactly the same as the real preference function, it accurately captures the high preference region of the real preference function, and the position of the optimum design point in fig. 4 (b) is close to the optimum position in fig. 4 (a).

In step 4 of the invention, a multi-confidence Gaussian process model is established for the yield under different process parameter standard deviations, and a Markov chain Monte Carlo method is used for selecting representative points for calculating the sorting score. Comprises the following substeps:

step 4.1: and establishing a multi-confidence Gaussian process model for the yield under different process parameter standard deviations.

Since the integral in (7) has no analytical solution, the method adopts the MC method to perform approximate calculation, namely:

wherein the method comprises the steps ofIs a set of selected representative points. In the process of comparing design points, low-precision yield values under different standard deviations sigma are generated, a multi-confidence model is adopted to learn the correlation among the yields under different standard deviations sigma, and the representative points are generated based on the model.

More specifically, the invention adopts a multi-confidence Gaussian process regression model NARGP method [15], which is expressed as follows:

Y ^h (x)＝g _h (x，Y ^l (x))， (14)

wherein Y is ^l (. Cndot.) is the output of the low confidence model, i.e., yield at low σ, Y ^h (. Cndot.) is the output of the high confidence model, i.e., yield at high σ, and gh (. Cndot.) represents yield Y as established by design parameter x and low σ ^l (x) Above a gaussian process regression model.

The invention takes the yields at 1-sigma and 2-sigma as two low confidence sources, and selects the yield at 2.5-sigma as a high confidence source. In order to build a regression model of yield at 2.5-sigma, the traditional single confidence GPR method only uses yield data obtained at 2.5-sigma, but the NARGP method can utilize the yield data at 1-sigma and 2-sigma to help accurately model the yield at 2.5-sigma.

FIG. 5 compares the effect of fitting a conventional single confidence GPR model and a multiple confidence NARGP model, with the horizontal axis representing design parameters and the vertical axis representing yield; the black solid line is the actual yield of the circuit at 2.5-sigma, the blue dotted line is the multi-confidence model predicted yield, and the green dotted line is the single-confidence model predicted yield; the training data is from a comparator circuit (see fig. 7). Specifically, the single confidence GPR model is trained using only 5 high confidence data points at 2.5- σ. The multi-confidence model is built from the same 5 high confidence points and an additional 20 low σ yield points from two low confidence sources. The figure shows that the multiple confidence NARGP model improves fitting accuracy over the single confidence GPR model.

Step 4.2: representative points are selected using the Markov chain Monte Carlo method for calculating the ranking score.

After the NARGP model is built, the desired improvement in yield (EI) function at i- σ [16] can be calculated by the following formula:

wherein I (Y) ⁱ (x) Predicting yield Y for a multi-confidence model ⁱ (x) Is used for the lifting amount of the car,for mathematical expectations, max (,) is the maximum value.

In order to obtain the representative point in the formula (13), the present invention uses EI ⁱ The function selects representative points for use in calculating the ranking score. Specifically adopts MCMC sampling method and EI ⁱ Sampling in design space as target distribution, EI ⁱ Tends to generate sampling points in high yield regions, in practice at each EI ⁱ Mid-sampling about N _rep 3 points, finally selecting N from all sampling points _rep The design points are taken as representative points.

In the step 5, the optimization problem of the ordering score is solved by adopting the optimization of the preference Bayesian, wherein the ordering score is used for calculating a Thompson sampling acquisition function; under the comparison of adopting a multi-scale sampling methodCandidate point x _next With the current optimal design point x _τ Is a yield of (3); updating the optimal yield candidate set B according to the comparison result, selecting an optimal design point from the B, and adding N to the optimal design point _batch Sub-simulation, namely improving the analysis precision of the yield of the point; iteration is continued until the yield meets the requirement or the maximum iteration number N is reached _pbo And finally, obtaining the optimal design parameters and corresponding yield results. Comprises the following substeps:

step 5.1: and solving a sorting score optimization problem by adopting preferential Bayesian optimization, wherein a Thompson sampling acquisition function is calculated by using the sorting score.

In bayesian optimization, the acquisition function provides posterior distribution including mean and variance based on the probability model, finding the next possible optimal point. The invention adopts the Toepson sampling function [17] as the acquisition function to guide the exploration and utilization in the optimization process.

The thompson sampling acquisition function first randomly generates a sample from a posterior gaussian distribution predicted by the GPC modelThe randomness of the sample generation ensures the exploratory capacity of the algorithm and avoids sinking into local optimum. Then based on this random +.>The Topson sampling function selects the design point with the largest predicted ranking score as the next candidate point, and the method selects the optimal score design point to ensure the utilization capacity of the algorithm.

The thompson sampling is as follows:

wherein the constant term Vol (D) in the formula (13) is omitted in (16) ^-1 Which does not affect the result of the optimization,is the representative point selected in the step 4, and the method selects a design point with highest average winning probability as the next candidate point x compared with the representative point _next 。

Specifically, the present invention is based on a multi-starting point BFGS (multiple startingpointBroyden-Fletcher-Goldfarb-Shanno, MSP-BFGS) [18]The global optimization algorithm solves the optimization problem defined in the step (16) to obtain the next candidate point x _next 。

FIG. 6 shows the step of selecting the next candidate point using a Thompson sample acquisition function, where FIG. 6 (a) shows samples randomly sampled from a preference function posterior distributionWherein the blue triangle corresponds to the next candidate point of final choice, the preference function sample is +. >Integrating to obtain corresponding sorting score +.>As shown in fig. 6 (b), the design point with the largest ranking score (where the blue dotted line is located) is selected as x _next . It can be seen that x in FIG. 6 (a) _next The blue dashed line at this point passes through the dark red region to the greatest extent, indicating that the probability of a higher yield than other design points is greatest.

Step 5.2: comparing the next candidate point x by adopting a multi-scale sampling method _next With the current optimal design point x _τ Is a high yield of the product.

The next design pair to be compared is [ x ] _next ，x _τ ]Wherein x is _τ Representing the current optimum yield design point. Three values, i.e., 1-sigma, 2-sigma, and 2.5-sigma, are selected for the standard deviation sigma of the process parameter in the variable-scale sampling method. Assigning a maximum number of simulations N to yield analysis at each σ _max The invention takes N _max =100. Sequentially taking the standard deviation sigma value of the process parameters from1 to 2.5 for x _next Yield analysis is carried out to obtain a comparison result h _next The method comprises the following steps:

wherein the design point x _a Significantly (domino) is better or significantly worse than the design point x _b The definition is as follows:

wherein τ ⁱ Representing the current maximum yield value at i-sigma,sum sigma _Y And (3) performing MC analysis on the design point x under the condition of i-sigma to obtain a yield value and a corresponding standard deviation, wherein i (x) is the design point x, and the yield value and the corresponding standard deviation can be obtained through calculation of (10) and (11). Significance is expressed as x based on MC analysis at 1-sigma or 2-sigma or 2.5-sigma _a Whether or not the yield probability of (2) is better or worse than x _b Is a high yield of the product.

Step 5.3: updating the optimal yield candidate set B according to the comparison result of the step 5.2, selecting an optimal design point from the B, and adding N to the optimal design point _batch And (5) sub-simulation, and improving the yield analysis precision of the point.

If the next candidate point x _next With the current optimal design point x _τ Yield comparison result h of (2) _next =1, the optimal yield candidate set B will be emptied and added to x _next . If x is the standard deviation sigma of these 3 process parameters _next And x _τ Always no significant difference in yield of (2), x will be _next And adding the optimal yield candidate set B.

Design point x for optimal yield ^* 1-sigma high precision yield of (2), the invention adopts document [12 ]]The iterative yield analysis method gradually improves the yield analysis precision. That is, in each iteration, the optimal yield is calculatedRanking scores of all design points in the candidate set B, then selecting the design point with the highest ranking score, and sampling N in the process space under the condition that the standard deviation sigma=1 of the process parameters _batch And (3) simulating points, and performing SPICE simulation to gradually improve the 1-sigma yield analysis precision.

Step 5.4: the data point newly obtained in step 5.2 ([ x) _next ，x _τ ]，h _next ) Added to the dataset.

Step 5.5: if the yield does not meet the requirement and the iteration number is smaller than the maximum iteration number N _pbo Step 3, jumping to the step, and performing iterative optimization; otherwise, the optimization is finished, and the optimal design parameters and the corresponding yield result are output.

The invention provides a simulation circuit yield optimization method based on a preference learning model, wherein in order to quickly determine the advantages and disadvantages of the yields of different design points, a multi-scale sampling method is adopted, the standard deviation sigma of process parameter distribution is gradually improved, yield analysis is executed, and the simulation cost for distinguishing the advantages and disadvantages of the design points is reduced by amplifying the differences between the yields of the different design points; secondly, modeling a comparison result of multi-scale sampling yield among design points by adopting a discrete Gaussian process classification model based on preference learning; then modeling a comparison result by using a Gaussian process classification model, acquiring search and utilization in a function balance optimization process by using Thompson sampling based on posterior distribution of prediction preference, searching a design point with the maximum winning probability in yield comparison, and then learning correlation of yield under different process parameter standard deviations by using a multi-confidence modeling method for yield numerical information obtained by using multi-scale sampling, wherein the correlation is used for sequencing score approximation, so that modeling and optimization efficiency of an algorithm is further improved.

The invention has the advantages that:

1. the invention provides a preference learning-based method for converting the optimization problem of the yield of the analog circuit into the optimization problem of the sequencing score, thereby avoiding frequent execution of high-precision yield analysis;

2. the method is applied to the rate of finished products optimization of the analog circuit, the advantages of high sampling efficiency and low analysis cost of the multi-scale sampling rate of the Bayesian optimization method are utilized, the multi-scale sampling method is adopted to rapidly determine the advantages and disadvantages of the rates of finished products of different design points, design space searching is carried out according to preference information, and the rate of finished products optimization of the analog circuit is improved;

3. experimental results show that compared with the current optimal simulation circuit yield optimization method, the simulation time acceleration ratio is 5.90-12.66 times under the condition of not reducing the optimization precision.

Drawings

FIG. 1 is a schematic diagram of the relationship between the yield of an analog circuit and the standard deviation sigma of the process parameter distribution.

Fig. 2 is a flow chart of the present invention.

FIG. 3 is a schematic diagram showing the relationship between the yield curve and the corresponding ranking score curve of the comparator circuit.

Fig. 4 is a graph comparing the actual preference function and the GPC model prediction results.

Fig. 5 is a graph comparing the effect of fitting a single confidence GPR model and a multiple confidence NARGP model.

Fig. 6 is a schematic diagram of the acquisition of the next candidate point using a thompson sampling acquisition function.

Fig. 7 is a circuit diagram of a comparator circuit.

Fig. 8 is a circuit diagram of a charge pump circuit.

Detailed Description

The process of the invention is further described below by way of specific example implementations.

Example 1

The present example employs a circuit as shown in fig. 7. Fig. 7 is a circuit diagram of a comparator circuit with a supply voltage of 1.8V at 180nm process.

Among the input parameters, the design parameters are the width of the transistor, and the total is 12 dimensions; the process parameters include all global and local process disturbance parameters; offset voltage V when failure threshold of circuit performance is 200MHz sampling frequency at 30 DEG C _off Sensitivity voltage V less than or equal to 30mV _sen Less than or equal to 2mV, and the maximum working frequency speed is more than or equal to 1GHz; point N of initial dataset of Gaussian process classification model _init =30; maximum number of iterations N of preference Bayesian optimization _pbo =800; ranking score represents the number of points N _rep =100; maximum simulation times N of variable-scale sampling yield analysis _max =100; calling maximum simulation times N of analog circuit performance optimization resolver _pre =300; iterative yield analysis of the number N of simulation points per batch _batch ＝30。

The comparison results of the method of the present invention with Ref 8 and Ref 9 algorithms are shown in Table 1, wherein PBO represents the yield optimization algorithm proposed by the present invention. To reduce the effect of random fluctuations, all algorithms of this example were run 10 times. The simulation times of the performance optimization solver call under the TT process angle of the simulation circuit are added to the result of the PBO.

Table 1 yield optimization results and speed comparison of comparator circuits

Since Ref 8 is the fastest algorithm in this example, ref 8 is used as a speed reference. On the premise of ensuring that the yield of the optimized result is higher than 99%, the speed ratio of the PBO method is 12.66 times compared with that of the Ref 8 method. The experimental result verifies the effectiveness of the method.

Example 2

The present example employs a circuit as shown in fig. 8. Fig. 8 is a circuit diagram of a charge pump circuit under a 40nm process.

Among the input parameters, the design parameters are the length and width of the transistor, and 36 dimensions are used in total; the process parameters include all global and local process disturbance parameters; the failure threshold value of the circuit performance is diff1 less than or equal to 25 mu A, diff2 less than or equal to 25 mu A, diff3 less than or equal to 10 mu A, diff4 less than or equal to 10 mu A, and the displacement is less than or equal to 6 mu A; other input parameters are the same as in example 1.

The results of the comparison of this method with the Ref 8 and Ref 9 algorithms are shown in Table 2. Since Ref 9 is the fastest algorithm in this example, ref 9 is used as a speed reference. On the premise of ensuring that the yield of the optimized result is higher than 99%, the speed ratio is 6.07 times compared with the Ret 9 method. The experimental result verifies the effectiveness of the method.

TABLE 2 yield optimization results and speed comparison for charge pump circuits

Example 3

The working frequency of the power amplifier designed by adopting the TSMC 65nm technology in the calculation example is 2.4GHz. It employs an array-based design, comprising 2048 repeating units, each unit comprising 4 transistors, for a total of 8192 transistors.

Among the input parameters, the design parameters are the length and width of the transistor, and the total is 5 dimensions; the process parameters include all global and local process disturbance parameters; the failure threshold of the circuit performance is that the output efficiency Eff is more than or equal to 57%, the output power Pout is more than or equal to 22.5dBm and the total harmonic distortion thd is less than or equal to 12.65dB; because the simulation time of the power amplifier is extremely long, the occupation of calculation resources is high, the experiment is repeated for 6 times only, the result is counted, and the maximum simulation times of each optimization are limited to 30000 times; other input parameters are the same as in example 1.

The results of the comparison of this method with the Ref 8 and Ref 9 algorithms are shown in Table 3. Since Ref 9 is the fastest algorithm in this example, ref 9 is used as a speed reference. Ref 8 and Ref 9 have been successful in achieving design points with target yields of greater than 99% in 2 and 4, respectively, of 6 replicates. The method can find out the design point of the target yield in all six repeated experiments, and the simulation is needed for 4017 times on average, and compared with Ref 9, the method obtains the acceleration ratio of 5.90 times. The experimental result verifies the effectiveness of the method.

TABLE 3 yield optimization results and speed comparison for Power Amplifier circuits

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Claims (6)

1. The method is characterized by comprising the steps of firstly, converting an analog circuit yield optimization problem into a sequencing score optimization problem based on a preference learning method; secondly, modeling comparison results of the yields of different design points by adopting a Gaussian process classification model; thirdly, modeling the yield under different process parameter standard deviations by adopting a multi-confidence modeling method, selecting representative points based on the model, and approximately calculating a sequencing score; fourthly, solving by using preferential Bayesian optimization, wherein the thompson sampling is used for acquiring the utilization and exploration process in the function balance optimization, and iterating continuously until the yield meets the requirement or reaches the maximum iteration times; the method specifically comprises the following steps:

inputting parameters:

1. simulating a circuit netlist;

2. probability distribution density functions of process parameters;

3. failure threshold c of circuit performance index _i I=1,..k, where k is the number of circuit performance indicators of interest and assumes the ith performance indicator y for the circuit _i If the simulation result y _i ≥c _i The circuit is considered to be successful, otherwise, the circuit is considered to be failed;

4. Point N of Gaussian process classification model initial dataset _init The method comprises the steps of carrying out a first treatment on the surface of the Maximum number of iterations N of preference Bayesian optimization _pbo The method comprises the steps of carrying out a first treatment on the surface of the Ranking score represents points N _rep The method comprises the steps of carrying out a first treatment on the surface of the Maximum simulation times N of variable-scale sampling yield analysis _max The method comprises the steps of carrying out a first treatment on the surface of the Calling maximum simulation times N of analog circuit performance optimization resolver _pre The method comprises the steps of carrying out a first treatment on the surface of the Iterative yield analysis of the number N of simulation points per batch _batch ；

Outputting a result:

simulating optimal design parameters and yield values obtained by optimizing the yield of the circuit;

the method comprises the following steps:

step 1: converting the analog circuit yield optimization problem into a sequencing score optimization problem based on a preference learning method;

step 2: initializing data sets, namely acquiring N by adopting TT (biological-biological) process corner performance optimization method _init A priori solution and performing a low-precision yield analysis as a preference Bayesian optimization heatStarting a data set initial point, and adding the current optimal design point into an optimal yield candidate set B (Basset);

step 3: modeling comparison results of yield of different design points in the data set by adopting a Gaussian process classification model;

step 4: for the yield under different technological parameter standard deviations, a multi-confidence Gaussian process model is established, and a Markov chain Monte Carlo (Markov Chain Monte Carlo, MCMC) method is utilized to select representative points for calculating a sorting score;

Step 5: solving a sorting score optimization problem by adopting preferential Bayesian optimization, wherein a Thompson sampling acquisition function is calculated by using a sorting score; comparing the next candidate point x by adopting a multi-scale sampling method _next With the current optimal design point x _τ Is a yield of (3); updating the optimal yield candidate set B according to the comparison result, selecting an optimal design point from the B, and adding N to the optimal design point _batch Sub-simulation, namely improving the analysis precision of the yield of the point; iteration is continued until the yield meets the requirement or the maximum iteration number N is reached _pbo And finally, obtaining the optimal design parameters and corresponding yield results.

2. The method as set forth in claim 1, wherein in said step 1, the analog circuit yield optimization problem is converted into a rank score optimization problem based on a preference learning method;

in an analog circuit, design parameters refer to variables of the length, width, capacitance and resistance of a transistor, which can be controlled by a circuit designer; process parameters refer to variables that characterize process disturbances by threshold voltages provided by the chip manufacturer; the yield refers to the yield generated by process disturbance;

for an analog circuit, the design parameter x is D in design space D _x The vector of dimensions is used to determine, A variable representing the length, width, etc. of the transistor that can be controlled by a circuit designer; the process parameter s is d in the process space V _s The vector of dimensions is used to determine,a variable representing a threshold voltage, etc., the probability distribution of which is typically provided by a process manufacturer and satisfies a normal distribution; without loss of generality, assuming that the process parameters are independent of each other and of the design parameters, the probability density function (probability density function, PDF) of the process parameters s is

Given design parameters and process parameters (x, s) e (D, V), x e D, s e V, the circuit performance of interest y= [ y ] can be obtained through SPICE simulation ₁ ，y ₂ ，…，y _k ] ^T Corresponding threshold condition c= [ c ₁ ，c ₂ ，…，c _k ] ^T Determined by the designer; only when the circuit performance meets all conditions, i.e. y _i ≥c _i I=1, …, k, then it is considered to be acceptable, otherwise it is considered to be failed;

given a design parameter x, the analog circuit yield Y (x) is defined as

Y(x)＝∫ _V I(x，s)p(s)ds (2)

Wherein the index function I (x, s) =and (y _i ≥c _i ) I=1, …, k, AND (·) represents a logical function AND;

the problem of optimizing the yield of the analog circuit is to obtain the design point x with the maximum yield Y ^* I.e.

Based on reasonable analog circuit design, the circuit can meet all performance indexes under TT process angle; by adding the constraint, the search space of the algorithm can be reduced, and the convergence speed is improved, so that the traditional analog circuit yield optimization problem is formally defined as:

Wherein y is _i (x, TT) is an ith performance value when the design parameter of the analog circuit to be optimized is x under the TT process angle;

converting the constrained optimization problem defined in (4) into an unconstrained form to handle constraints in the optimization problem, the design objective (FOM) being described as:

wherein omega _i I=1, 2, …, k is a weight representing the importance of the ith performance indicator;

giving a design pair (design product) formed by two design points x and x ', wherein the yield comparison result h ([ x, x' ]) epsilon {0,1} of the design pair (x, x '] epsilon D x D is obtained by calculating t (x) and t (x'); if t (x) > t (x '), h=1, indicating that x is better than x'; otherwise h=0, meaning that x is not better than x';

formally, pi ([ x, x ']) is defined as a preference function (preference function), representing the probability of t (x) > t (x'); the comparison of the design versus [ x, x' ] follows the bernoulli distribution (Bernoulli distribution):

thus, a ranking score (ranking score) is defined as:

R(x)＝Vol(D) ^-1 ∫ _D π([x，x′])dx′， (7)

where Vol (D) represents the design space volume, is a constant and can be ignored during the optimization process; the physical meaning of R (x) is to count the proportion of all design points worse than the design point x in the design space D, i.e. the average probability that the yield of x is higher than that of other design points;

The global optimum design point should always win based; if all the design points are ranked according to the value of the yield, searching the design point with the optimal yield is equivalent to obtaining the design point with the highest ranking score;

thus, the analog circuit yield optimization problem may be translated into a rank score optimization problem:

。

3. the method of claim 1, wherein in step 2, data set initialization is performed, and N is obtained by using a TT-based process corner performance optimization method _init Performing prior solution, performing low-precision yield analysis, taking the solution as a data set initial point for preference Bayesian optimization hot start, and adding the current optimal design point into an optimal yield candidate set B (Basset); comprises the following substeps:

step 2.1: n is obtained by adopting TT-based process corner performance optimization method _init A priori solution;

according to the compromise relation between the yield of the analog circuit and the performance under the TT process angle, the structure of the initial solution for optimizing the yield of the analog circuit is converted into the problem of optimizing the performance under the TT process angle of the analog circuit:

wherein the formula means that the searching performance is slightly larger than the design point, omega of the constraint threshold _i Is given weight, and represents the importance of the ith performance index; e is a constant coefficient used to measure the nominal performance y at the TT process corner _i (x, TT) and threshold c _i A distance therebetween; setting omega _i =1, i e 1..k and

then adopting a weighted expected lifting (weighted Expected Improvement, wEI) Bayesian optimization algorithm WEIBO to solve (9) the defined performance optimization problem under the TT process angle of the analog circuit, recording design points generated in all iterative optimization, wherein the maximum simulation times for calling the solver is set as N _pre The method comprises the steps of carrying out a first treatment on the surface of the From design points resulting from iterative optimization, N is selected for TT sub-nominal performance meeting failure threshold and having a minimum f (x) value _init A plurality of points, which are used as initial points for optimizing the hot start by preference Bayes;

step 2.2: n to be obtained _init Performing low-precision yield analysis on the initial design points, establishing an initial data set, and adding the current optimal design points into an optimal yield candidate set B;

for N obtained in step 2.1 _init The initial design points are distributed 2*N by adopting a MC method with strong universality under the condition that the standard deviation sigma=1 of the technological parameter _batch Sampling points, performing low-precision yield analysis to obtain corresponding low-precision yield values, wherein N is _batch Set to 30, which is much lower than the number of simulations required for high precision yield analysis, e.g., 1000;

combining different design points two by two to form a design comparison yield, and establishing an initial data set; the MC method adopts N sample points s in a process space based on a probability density function p(s) of a process parameter s _i I=1, …, N, and the yield is calculated by counting the number of qualified samples therein as

Variance of yield estimatesAnd the estimated value Y _MC (x) The relation with the sampling point number N is as follows:

where confidence level k _γ Is a constant;

and selecting a design point with the highest yield from the initial data set, and adding the design point into the optimal yield candidate set B.

4. The method of claim 1, wherein in the step 3, a gaussian process classification model is used to model the comparison results of the yields of different design points in the dataset;

modeling the yield comparison result, namely preference information, by using a Gaussian process classification method; the built model is used as a probability model GPC, can provide prediction posterior distribution of comparison results, and is helpful for designing a search strategy to realize balance of utilization and exploration;

the Gaussian process classification model uses a nonlinear activation function to process classification problems, such as a Logistic function, and converts continuous output of the Gaussian process regression model into binary output; the GPC model defines a hidden function z ([ x, x ' ]) and assumes that it obeys GP priors, its values contain the entire real range, then z ([ x, x ' ]) is compressed by a Logistic function, resulting in a prior probability distribution of pi ([ x, x ' ]):

The preference function pi ([ x, x' ]) is the modeling result of the GPC model, and is used for predicting the high-low relationship between the yields of different design points.

5. The method according to claim 1, wherein in the step 4, for the yield under different process parameter standard deviations, a multi-confidence gaussian process model is established, and a markov chain monte carlo method is used for selecting representative points for calculating the ranking score; comprises the following substeps:

step 4.1: establishing a multi-confidence Gaussian process model for the yield under different process parameter standard deviations;

the MC method is adopted to perform approximate calculation, namely:

wherein x is ₁ ，x ₂ ，…，Is a set of representative points; in the process of comparing design points, low-precision yield values under different standard deviations sigma are generated, a multi-confidence model is adopted to learn the correlation between the yields under different standard deviations sigma, and the representative points are generated based on the model;

the NARGP method adopting the multi-confidence Gaussian process regression model is expressed as follows:

Y ^h (x)＝g _h (x，Y ^l (x))， (14)

wherein Y is ^l (. Cndot.) is the output of the low confidence model, i.e., yield at low σ, Y ^h (. Cndot.) is the output of the high confidence model, i.e., yield at high σ; g _h (. Cndot.) is expressed as a function of design parameter x and low σ yield Y ^l (x) A gaussian process regression model above;

taking the yields at 1-sigma and 2-sigma as two low confidence sources, and selecting the yield at 2.5-sigma as a high confidence source; in order to establish a regression model of the yield under 2.5-sigma, the NARGP method accurately models the yield under 2.5-sigma by using the yield data under 1-sigma and 2-sigma;

step 4.2: selecting representative points by using a Markov chain Monte Carlo method for calculating a ranking score;

after the NARGP model is built, the Expected Improvement (EI) function for yield at i- σ is calculated by the following formula:

wherein I (Y) ⁱ (x) Predictive for multiple confidence modelsYield Y ⁱ (x) Is used for the lifting amount of the car,for mathematical expectations, max (,) is the maximum value;

to obtain the representative point in formula (13), EI is used ⁱ Selecting representative points by the function, and calculating a sorting score; by MCMC sampling method, EI ⁱ Sampling as target distribution in design space, EI ⁱ Tends to generate sampling points in high yield regions, in practice at each EI ⁱ Mid-sampling about N _rep 3 points, finally selecting N from all sampling points _rep The design points are taken as representative points.

6. The method of claim 1, wherein in step 5, a preference bayesian optimization is used to solve a rank score optimization problem, wherein a thompson sampling acquisition function is calculated using rank scores; comparing the next candidate point x by adopting a multi-scale sampling method _next With the current optimal design point x _τ Is a yield of (3); updating the optimal yield candidate set B according to the comparison result, selecting an optimal design point from the B, and adding N to the optimal design point _batch Sub-simulation, namely improving the analysis precision of the yield of the point; iteration is continued until the yield meets the requirement or the maximum iteration number N is reached _pbo Finally, the optimal design parameters and the corresponding yield result are obtained; comprises the following substeps:

step 5.1: solving a sorting score optimization problem by adopting preferential Bayesian optimization, wherein a Thompson sampling acquisition function is calculated by using a sorting score;

in bayesian optimization, the acquisition function provides posterior distribution including mean and variance based on a probability model, and the next possible optimal point is found; the method adopts a Thompson sampling function as an acquisition function, and the exploration and the utilization in the optimization process are carried out;

the thompson sampling acquisition function first randomly generates a sample from a posterior gaussian distribution predicted by the GPC modelThe randomness of the sample generation ensures the exploration capability of the algorithm and avoids sinking into local optimum; then based on this random +.>The Topson sampling function selects a design point with the maximum prediction ordering score as a next candidate point, and selects an optimal score design point to ensure the utilization capacity of an algorithm;

The thompson sampling is as follows:

wherein the constant term Vol (D) in the formula (13) is omitted in (16) ^-1 It does not affect the optimization result; x is x ₁ ，x ₂ ，…，The representative points selected in the step 4; selecting a design point with highest average winning probability as the next candidate point x _next ；

Solving the optimization problem defined in (16) based on a multi-starting-point BFGS (multiple starting point Broyden-Fletcher-Goldfarb-Shanno, MSP-BFGS) global optimization algorithm to obtain the next candidate point x _next ；

Step 5.2: comparing the next candidate point x by adopting a multi-scale sampling method _next With the current optimal design point x _τ Is a yield of (3);

the next design pair to be compared is [ x ] _next ，x _τ ]Wherein x is _τ Representing a current optimal yield design point; three values, namely 1-sigma, 2-sigma and 2.5-sigma, are selected for the standard deviation sigma of the technological parameter in the variable-scale sampling method; assigning a maximum number of simulations N to yield analysis at each σ _max Taking N _max =100; sequentially increasing the standard deviation sigma value of the process parameters from 1 to 2.5 for x _next Yield analysis is carried out to obtain a comparison result h _next The method comprises the following steps:

wherein the design point x _a Significantly (domino) is better or significantly worse than the design point x _b The definition is as follows:

wherein τ ⁱ Representing the current maximum yield value at i-sigma, And->MC analysis is carried out on the design point x under i-sigma, and the obtained yield value and the corresponding standard deviation are obtained through calculation of (10) and (11); significance is expressed as x based on MC analysis at 1-sigma or 2-sigma or 2.5-sigma _a Whether or not the yield probability of (2) is better or worse than x _b Is a yield of (3);

step 5.3: updating the optimal yield candidate set B according to the comparison result of the step 5.2, selecting an optimal design point from the B, and adding N to the optimal design point _batch Sub-simulation, namely improving the analysis precision of the yield of the point;

if the next candidate point x _next With the current optimal design point x _τ Yield comparison result h of (2) _next =1, the optimal yield candidate set B will be emptied and added to x _next The method comprises the steps of carrying out a first treatment on the surface of the If x is the standard deviation sigma of the 3 process parameters _next And x _τ Always no significant difference in yield of (2), x will be _next Adding the optimal yield candidate set B;

gradually improving the yield analysis precision by adopting an iterative yield analysis method to obtain the optimal yieldYield design point x ^* 1-sigma high precision yield of (2); in each iteration, the ranking scores of all design points in the optimal yield candidate set B are calculated, then the design point with the highest ranking score is selected, and the process space is sampled N under the condition that the standard deviation sigma=1 of the process parameters _batch Simulation points are selected, SPICE simulation is carried out, and the 1-sigma yield analysis precision of the simulation points is gradually improved;

step 5.4: the data point newly obtained in step 5.2 ([ x) _next ，x _τ ]，h _next ) Adding into the data set;

step 5.5: if the yield does not meet the requirement and the iteration number is smaller than the maximum iteration number N _pbo Step 3, jumping to the step, and performing iterative optimization; otherwise, the optimization is finished, and the optimal design parameters and the corresponding yield result are output.