CN117435533A - Chip and multi-chip system - Google Patents

Chip and multi-chip system Download PDF

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Publication number
CN117435533A
CN117435533A CN202310880455.6A CN202310880455A CN117435533A CN 117435533 A CN117435533 A CN 117435533A CN 202310880455 A CN202310880455 A CN 202310880455A CN 117435533 A CN117435533 A CN 117435533A
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China
Prior art keywords
chip
data
uart
uart interface
application circuits
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CN202310880455.6A
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Chinese (zh)
Inventor
徐嘉宏
姚正浩
王俊吉
蔡侑霖
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MediaTek Inc
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MediaTek Inc
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Publication date
Priority claimed from US18/221,402 external-priority patent/US20240031438A1/en
Application filed by MediaTek Inc filed Critical MediaTek Inc
Publication of CN117435533A publication Critical patent/CN117435533A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • Communication Control (AREA)

Abstract

The invention provides a chip, which comprises a plurality of application circuits and UART interfaces. The application circuits are respectively used for generating a plurality of data, wherein the data respectively generated by the application circuits are transmitted to another chip through the same UART interface.

Description

Chip and multi-chip system
Technical Field
Embodiments of the present invention relate generally to an interface communication technology and, more particularly, to a chip and multi-chip system.
Background
In a multi-chip design, when the chip has multiple applications (applications), two or more data interfaces are required for communication between the two chips. For example, if a chip has three applications, the chip will have three universal asynchronous receiver transmitter (universal asynchronous receiver/transmitter, UART) interfaces, one for each application. However, since the chip requires at least three UART interfaces and other interface(s) (e.g., sideband interfaces, etc.), the chip needs to be designed with many pins to communicate, which results in increased manufacturing costs.
Disclosure of Invention
The following summary is illustrative only and is not intended to be in any way limiting. That is, the following summary is provided to introduce a selection of concepts, emphasis, benefits, and advantages of the novel and non-obvious techniques described herein. Selected embodiments are further described in the detailed description below. Accordingly, the following summary is not intended to identify essential features of the claimed subject matter, nor is it intended to be used to determine the scope of the claimed subject matter.
It is therefore an object of the present invention to provide a chip with a UART hub (hub) capable of transmitting data of a plurality of applications to another chip using one UART interface to solve the above-mentioned problems.
In a first aspect, the present invention provides a chip comprising: a plurality of application circuits configured to generate a plurality of data, respectively; and a universal asynchronous receiver transmitter (universal asynchronous receiver/transmitter, UART) interface; the plurality of data respectively generated by the plurality of application circuits are sent to another chip through the same UART interface.
In some embodiments, the chip includes a UART hub including control circuitry and the UART interface; and the control circuit schedules the plurality of data respectively generated by the plurality of application circuits and sends the plurality of data to the other chip through the UART interface.
In some embodiments, the control circuit encapsulates each of the plurality of data to generate a packet and sends the packet to the other chip via the UART interface, wherein the data of different application circuits are individually encapsulated into different packets.
In some embodiments, the packet includes a header including first information indicating a length of the packet and second information identifying which application circuit the packet belongs to, a payload and a cyclic redundancy check (cyclic redundancy check, CRC), wherein the payload is data from one of the plurality of application circuits.
In some embodiments, the UART interface includes only one transmit pin and only one receive pin, the chip transmits the plurality of data to the other chip via only the transmit pin, and the chip receives data from the other chip via only the receive pin.
In some embodiments, the plurality of application circuits are core circuits having different functions.
In some embodiments, the plurality of application circuits includes at least two of Wi-Fi circuits, bluetooth circuits, and audio circuits.
In some embodiments, the plurality of application circuits includes a first application circuit, and the first application circuit receives data of other application circuits, schedules the plurality of data respectively generated by the plurality of application circuits, and transmits the plurality of data to the other chip via the UART interface.
In some embodiments, the chip sends a sideband signal to the other chip via the UART interface.
In a second aspect, the present invention provides a multi-chip system comprising a first chip and a second chip, wherein the first chip comprises: a plurality of first application circuits configured to generate a plurality of first data, respectively; a first universal asynchronous receiver transmitter (universal asynchronous receiver/transmitter, UART) interface; the second chip includes: a plurality of second application circuits configured to generate a plurality of second data, respectively; a second UART interface; the first data generated by the first application circuits are sent to the second chip through the same first UART interface, and the second data generated by the second application circuits are sent to the first chip through the same second UART interface.
In some embodiments, the first chip includes a first UART hub including a first control circuit and the first UART interface; and the first control circuit schedules the first data respectively generated by the first application circuits and sends the first data to the second chip through the first UART interface.
In some embodiments, the second chip includes a second UART hub including a second control circuit and the second UART interface; and the second control circuit schedules the second data respectively generated by the second application circuits and sends the second data to the first chip through the second UART interface.
In some embodiments, the first control circuit encapsulates each of the plurality of first data to generate a packet and transmits the packet to the second chip via the first UART interface, wherein the data of different application circuits are individually encapsulated into different packets.
In some embodiments, the packet includes a header including first information indicating a length of the packet and second information identifying which first application circuit the packet belongs to, a payload, and a cyclic redundancy check (cyclic redundancy check, CRC), wherein the payload is data from one of the plurality of first application circuits.
In some embodiments, the first UART interface includes only one transmit pin and only one receive pin, the first chip transmits the plurality of first data to the second chip via only the transmit pin, and the first chip receives the plurality of second data from the second chip via only the receive pin.
In some embodiments, the second UART interface includes only one transmit pin and only one receive pin, the second chip transmits the plurality of second data to the first chip only via the transmit pin of the second UART interface, and the second chip receives the plurality of first data from the first chip only via the receive pin of the second UART interface.
In some embodiments, the plurality of first application circuits are core circuits having different functions.
In some embodiments, the plurality of first application circuits includes at least two of Wi-Fi circuitry, bluetooth circuitry, and audio circuitry.
These and other objects of the present invention will be readily understood by those skilled in the art after reading the following detailed description of the preferred embodiments as illustrated in the accompanying drawings. The detailed description will be given in the following embodiments with reference to the accompanying drawings.
Drawings
The accompanying drawings, in which like numerals indicate like components, illustrate embodiments of the invention. The accompanying drawings are included to provide a further understanding of embodiments of the disclosure, and are incorporated in and constitute a part of the embodiments of the disclosure. The drawings illustrate implementations of embodiments of the present disclosure and, together with the description, serve to explain principles of embodiments of the present disclosure. It is to be understood that the drawings are not necessarily to scale, because some components may be shown out of scale from actual implementation to clearly illustrate the concepts of the embodiments of the disclosure.
Fig. 1 is a schematic diagram of a multichip system according to one embodiment of the invention.
FIG. 2 is a diagram of a packet generated by a control circuit of a UART hub according to an embodiment of the present invention.
Fig. 3 is a diagram illustrating shortening of packet sizes according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a multi-chip system according to an embodiment of the invention.
Fig. 5 is a schematic diagram of a multi-chip system according to an embodiment of the invention.
In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the invention. It will be apparent, however, that one or more embodiments may be practiced without these specific details, and that different embodiments may be combined as desired and should not be limited to the embodiments set forth in the drawings.
Detailed Description
The following description is of preferred embodiments of the invention, which are intended to illustrate the technical features of the invention, but not to limit the scope of the invention. Certain terms are used throughout the description and claims to refer to particular elements, and it will be understood by those skilled in the art that manufacturers may refer to a like element by different names. Therefore, the present specification and claims do not take the difference in names as a way of distinguishing elements, but rather take the difference in functions of elements as a basis for distinction. The terms "element," "system," and "apparatus" as used in the present invention may be a computer-related entity, either hardware, software, or a combination of hardware and software. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to …". Furthermore, the term "coupled" means an indirect or direct electrical connection. Thus, if one device is coupled to another device, that device can be directly electrically connected to the other device or indirectly electrically connected to the other device through other devices or connection means.
Wherein corresponding numerals and symbols in the various drawings generally refer to corresponding parts, unless otherwise indicated. The drawings are clearly illustrative of relevant portions of the embodiments and are not necessarily drawn to scale.
The term "substantially" or "approximately" as used herein means that within an acceptable range, a person skilled in the art can solve the technical problem to be solved, substantially to achieve the technical effect to be achieved. For example, "substantially equal" refers to a manner in which a technician can accept a certain error from "exactly equal" without affecting the accuracy of the result.
Fig. 1 is a schematic diagram of a multi-chip system (multi-chip system) according to an embodiment of the invention. As shown in fig. 1, the multi-chip system includes a first chip 110 and a second chip 120, for example, the first chip 110 and the second chip 120 are mounted on a printed circuit board (printed circuit board, PCB), and the first chip 110 and the second chip 120 can communicate with each other by using UART interfaces (interfaces). The first chip 110 includes a plurality of application circuits (application circuit) 112_1-112_N and a UART hub 114, wherein the UART hub 114 includes a control circuit 118 and a UART interface 119. The second chip 120 includes application circuitry 122 and UART interfaces 124. In one embodiment, the multi-chip system may be applied to wireless communications, for example, the first chip 110 is an application processor (application processor, AP) and the second chip 120 is a wireless communication chip capable of wirelessly transmitting data provided by the first chip 110. In addition, the application circuits 112_1 to 112_n may be core circuits (also referred to as "function circuits") having different functions, for example, the application circuit 112_1 may be a Wi-Fi circuit capable of generating Wi-Fi payloads (payload), the application circuit 112_2 may be a bluetooth circuit capable of generating bluetooth data, and the application circuit 112_n may be an audio processing circuit capable of generating audio data.
In the embodiment shown in FIG. 1, the data generated by the application circuits 112_1-112_N is transferred to the second chip 120 using the UART hub 114. For example, the control circuit 118 may employ a round-robin scheduling algorithm (also referred to as "round-robin scheduling") to process the data of the application circuits 112_1-112_n, i.e., a plurality of time slots (time slots) are allocated to each of the application circuits 112_1-112_n in a round-robin order (in circular order), and the data of the application circuits 112_1-112_n are executed in a round-robin execution. For example, in the present embodiment, the UART interface 119 has a plurality of pins, and two pins are only required for bi-directional communication with the second chip 120, but the present invention is not limited thereto. For example, UART interface 119 may have only one transmit pin (TX pin) and only one receive pin (RX pin), where first chip 110 only transmits data to second chip 120 over the TX pin and first chip 110 only receives data from second chip 120 over the RX pin. Therefore, since the first chip 110 uses only one (only one) UART interface 119 to transmit/transmit data of the plurality of application circuits 112_1-112_n to the second chip 120, the number of pins (pins, also referred to as "pins") of the first chip 110 can be reduced, thereby reducing the manufacturing cost.
In one embodiment, the control circuit 118 encapsulates (pack) each of the data provided by the application circuits 112_1-112_N to enable the second chip 120 to identify which application circuit the received data was generated from. Taking fig. 2 as an example, the control circuit 118, upon receiving data from one of the application circuits 112_1-112_n, encapsulates the data to generate a packet (packet) 200 having a Header (shown as "Header") that includes first information indicating the length of the packet 200 and second information that can/can be used to identify to which application circuit the packet 200 belongs, a Payload (shown as "Payload" in the figure) that is received from one of the application circuits 112_1-112_n, and a cyclic redundancy check (cyclic redundancy check, CRC) that is an error-detection code for detecting whether the packet 200 is erroneous. Then, the control circuit 118 sends the packet to the second chip 120 through the UART interface 119.
In one embodiment, the first chip 110 and the second chip 120 may use a packet retransmission protocol (packet retransmission protocol). For example, when the application circuit 112_1 transmits data to the second chip 120 via the UART hub 114, the application circuit 112_1 can only confirm (confirm) that the data has been correctly received by the chip 120 when receiving an acknowledgement (acknowledgement) from the chip 120. If the acknowledgement of the second chip 120 is not received after a period of time, the retransmission mechanism is triggered, so that the application circuit 112_1 retransmits the data to the second chip 120.
In addition, since only one UART interface 119 is used to transmit/send data for the application circuits 112_1-112_n, each application circuit can only be allocated a portion of the data transmission time (data transmission time), which can result in additional delays to the data transmission. To address this problem, the baud rate (baud rate) of the UART interface 119 may be increased to shorten the data transmission time and/or reduce the packet size of each packet, thereby reducing the delay time of each application circuit 112_1-112_n. For example, using fig. 3 as an example, the control circuitry 118 may split the original payload into three parts, and each part forms a packet for transmission. That is, the first packet includes a first Header (shown as "header_1" in the drawing, including the above-described information of the first packet, i.e., the first Header includes first information indicating the length of the first packet and second information for identifying to which application circuit the first packet belongs), a first Payload (i.e., a first portion of the original Payload, shown as "payload_1" in the drawing), and a first CRC (shown as "CRC 1" in the drawing). The second packet includes a second header (including the above information of the packet, i.e., the second header includes first information indicating a length of the second packet and second information for identifying to which application circuit the second packet belongs), a second payload (i.e., a second portion of the original payload), and a second CRC; the third packet comprises a third header (comprising the above information of the packet, i.e. the third header comprises first information indicating the length of the third packet and second information identifying to which application circuit the third packet belongs), a third payload (i.e. a third part of the original payload) and a third CRC. Then, the first packet, the second packet and the third packet are sequentially transmitted to the second chip 120.
In an embodiment, one or more sideband signals may be transmitted between the first chip 110 and the second chip 120, and these sideband signals may be transmitted through the use of the UART hub 114, wherein the sideband signals may be wake-up signals that are used to wake the device from sleep mode. In particular, the first chip 110 may send a wake-up signal to wake up the second chip 120 via the UART hub 114, and since the wake-up signal is typically a signal with a specific pattern (specific pattern), the control circuit 118 may send the wake-up signal directly to the second chip 120 via the UART interface 119 without first encapsulating the wake-up signal. Therefore, since the first chip 110 does not need to design an additional pin to transmit the sideband signal, the number of pins of the first chip 110 can be further reduced.
Fig. 4 is a schematic diagram of a multi-chip system according to an embodiment of the invention. As shown in fig. 4, the multichip system shown in fig. 4 includes a first chip 410 and a second chip 420, for example, the first chip 410 and the second chip 420 are mounted on a printed circuit board, and the first chip 410 and the second chip 420 can communicate with each other by using UART interfaces. The first chip 410 includes a plurality of application circuits 412_1-412_N and a UART hub 414, wherein the UART hub 414 includes a control circuit 418 and a UART interface 419. The second chip 420 includes a plurality of application circuits 422_1-422_M and a UART hub 414, wherein the UART hub 424 includes control circuits 428 and UART interfaces 429. In one embodiment, the multi-chip system may be used for wireless communication, for example, the first chip 410 is an application processor and the second chip 420 is a wireless communication chip capable of wirelessly transmitting data provided by the first chip 410. Further, the application circuits 412_1 to 412_n in the first chip 410 may be core circuits having different functions, for example, the application circuit 412_1 may be a Wi-Fi circuit capable of generating Wi-Fi payloads, the application circuit 412_2 may be a bluetooth circuit capable of generating bluetooth data, and the application circuit 412_n may be an audio processing circuit capable of generating audio data. In addition, the application circuits 422_1 to 422_m in the second chip 420 may be core circuits having different functions.
In the embodiment shown in fig. 4, the data generated by the application circuits 412_1-412_n is transmitted to the second chip 420 through the UART hub 414. For example, the control circuit 418 may process the data of the application circuits 412_1 to 412_n using a round robin schedule, i.e., a plurality of time slices are allocated to each of the application circuits 412_1 to 412_n in a round robin sequential manner, and the data of the application circuits 412_1 to 412_n is executed in a round robin execution. For example, in the present embodiment, but not limiting to the invention, the UART interface 419 has multiple pins, and only two pins are required for bi-directional communication with the second chip 420. For example, UART interface 419 has only one TX pin and only one RX pin, where first chip 410 sends data to second chip 420 only through the TX pin and first chip 410 receives data from second chip 420 only through the RX pin. Therefore, since the first chip 410 uses only one UART interface 419 to transmit data of the plurality of application circuits 412_1 to 412_n to the second chip 420, the number of pins of the first chip 410 may be reduced, thereby reducing manufacturing costs.
Similarly, by using the UART hub 424, data generated by the application circuits 422_1 to 422_m is transferred to the first chip 410. For example, the control circuit 428 may employ round robin scheduling to process the data of the application circuits 422_1-422_m. In this embodiment, without limiting the invention, UART interface 429 has a plurality of pins, and only two pins are needed for bi-directional communication with first chip 410. For example, UART interface 429 has only one TX pin and only one RX pin, wherein second chip 420 only transmits data to first chip 410 through the TX pin and second chip 420 only receives data from first chip 410 through the RX pin. Therefore, since the second chip 420 uses only one UART interface 429 to transmit data of the plurality of application circuits 422_1 to 422_m to the first chip 410, the number of pins of the second chip 420 can be reduced, thereby reducing manufacturing costs.
In one embodiment, the control circuit 418 encapsulates each piece of data provided by the application circuits 412_1-412_N such that the second chip 420 can identify which application circuit the received data was generated. In detail, after receiving the data from one of the application circuits 412_1 to 412_n, the control circuit 418 encapsulates the data to generate a packet with a header, a payload and a CRC as shown in fig. 2, and then the control circuit 418 transmits the packet to the second chip 420 through the UART interface 419. Similarly, for the second chip 420, the control circuit 428 encapsulates each of the pieces of data provided by the application circuits 422_1-422_M so that the first chip 410 can identify which application circuit generated the received data. In detail, after receiving the data from one of the application circuits 422_1 to 422_m, the control circuit 428 encapsulates the data to generate a packet having a header, a payload and a CRC as shown in fig. 2, and then the control circuit 428 transmits the packet to the first chip 410 through the UART interface 429.
In an embodiment, one or more sideband signals may be transferred between the first chip 410 and the second chip 420 and may be transmitted through the use of the UART hub 414, where the sideband signals may be wake-up signals for waking up the device from sleep mode. In particular, when the first chip 410 needs to send a wake-up signal to wake up the second chip 420, the control circuit 418 may send the wake-up signal directly to the second chip 420 via the UART interface 419 without first encapsulating the wake-up signal. Accordingly, since the first chip 410 and the second chip 420 do not need to design additional pins to transmit the sideband signals, the number of pins of the first chip 410 and the second chip 420 can be further reduced.
Fig. 5 is a schematic diagram of a multi-chip system according to an embodiment of the invention. As shown in fig. 5, the multi-chip system includes a first chip 510 and a second chip 520, wherein the first chip 510 and the second chip 520 are mounted on a printed circuit board, and the first chip 510 and the second chip 520 can communicate with each other by using UART interfaces 514, 524. The first chip 510 includes a plurality of application circuits 512_1-512_N and UART interfaces 514. The second chip 520 includes application circuitry 522 and UART interfaces 524. In one embodiment, the multi-chip system may be used in wireless communications. For example, the first chip 510 is an application processor, and the second chip 520 is a wireless communication chip capable of wirelessly transmitting data provided by the first chip 510. In addition, the application circuits 512_1 to 512_n may be core circuits having different functions.
In the embodiment shown in FIG. 5, the data generated by the application circuits 512_1-512_N are transferred to the second chip 120 by using the UART interface 514. For example, the application circuit 512_1 may receive data from the application circuits 512_2-512_n, and the application circuit 512_1 may schedule the data of the application circuits 512_1-512_n (e.g., process the data with round robin scheduling) to transfer the data of the application circuits 512_1-512_n to the second chip 510. For example, in this embodiment, UART interface 514 has multiple pins, and only two pins are required for bi-directional communication with second chip 520. For example, UART interface 514 has only one TX pin and only one RX pin, where first chip 510 sends data to second chip 520 only through the TX pin and first chip 510 receives data from second chip 520 only through the RX pin. Therefore, since the first chip 510 uses only one UART interface 514 to transmit data of the plurality of application circuits 512_1 to 512_n to the second chip 520, the number of pins of the first chip 510 can be reduced, thereby reducing manufacturing costs.
In an embodiment, one or more sideband signals may be transferred between the first chip 510 and the second chip 520 and may be transmitted using the UART interface 514, where the sideband signals may be wake-up signals that are used to wake the device from sleep mode. Accordingly, since the first chip 510 does not need to design additional pins to transmit the sideband signal, the number of pins of the first chip 510 can be further reduced.
In the claims, ordinal terms such as "first," "second," "third," etc., are used to modify a claim element, and do not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a same name from another element having a same name using the ordinal term.
While the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as will be apparent to those skilled in the art), e.g., combinations or alternatives of the different features in the different embodiments. The scope of the following claims is, therefore, to be accorded the broadest interpretation so as to encompass all such modifications and similar structures.

Claims (18)

1. A chip, comprising:
a plurality of application circuits configured to generate a plurality of data, respectively; and
UART interface of universal asynchronous receiver transmitter;
the plurality of data respectively generated by the plurality of application circuits are sent to another chip through the same UART interface.
2. The chip of claim 1, wherein the chip comprises a UART hub, the UART hub comprising control circuitry and the UART interface; and the control circuit schedules the plurality of data respectively generated by the plurality of application circuits and sends the plurality of data to the other chip through the UART interface.
3. The chip of claim 2, wherein the control circuit encapsulates each of the plurality of data to generate a packet and sends the packet to the other chip via the UART interface, wherein the data of different application circuits are individually encapsulated into different packets.
4. The chip of claim 3, wherein the packet includes a header, a payload, and a cyclic redundancy check, CRC, the header including first information indicating a length of the packet and second information identifying which application circuit the packet belongs to, wherein the payload is data from one of the plurality of application circuits.
5. The chip of claim 1, wherein the UART interface includes only one transmit pin and only one receive pin, the chip transmits the plurality of data to the other chip via only the transmit pin, and the chip receives data from the other chip via only the receive pin.
6. The chip of claim 1, wherein the plurality of application circuits are core circuits having different functions.
7. The chip of claim 6, wherein the plurality of application circuits includes at least two of Wi-Fi circuitry, bluetooth circuitry, and audio circuitry.
8. The chip of claim 1, wherein the plurality of application circuits includes a first application circuit, and wherein the first application circuit receives data of other application circuits, schedules the plurality of data generated by the plurality of application circuits, respectively, and transmits the plurality of data to the other chip via the UART interface.
9. The chip of claim 1, wherein the chip sends a sideband signal to the other chip via the UART interface.
10. A multi-chip system comprising a first chip and a second chip, wherein the first chip comprises:
a plurality of first application circuits configured to generate a plurality of first data, respectively; and
a first universal asynchronous receiver transmitter, UART, interface;
the second chip includes:
a plurality of second application circuits configured to generate a plurality of second data, respectively; and
a second UART interface;
the first data generated by the first application circuits are sent to the second chip through the same first UART interface, and the second data generated by the second application circuits are sent to the first chip through the same second UART interface.
11. The multi-chip system of claim 10, wherein the first chip includes a first UART hub, the first UART hub including a first control circuit and the first UART interface; and the first control circuit schedules the first data respectively generated by the first application circuits and sends the first data to the second chip through the first UART interface.
12. The multi-chip system of claim 11, wherein the second chip includes a second UART hub, the second UART hub including a second control circuit and the second UART interface; and the second control circuit schedules the second data respectively generated by the second application circuits and sends the second data to the first chip through the second UART interface.
13. The multi-chip system of claim 11, wherein the first control circuit encapsulates each of the plurality of first data to generate a packet and sends the packet to the second chip via the first UART interface, wherein data of different application circuits are individually encapsulated into different packets.
14. The multi-chip system of claim 13, wherein the packet includes a header, a payload, and a cyclic redundancy check, CRC, the header including first information indicating a length of the packet and second information identifying to which first application circuit the packet belongs, wherein the payload is data from one of the plurality of first application circuits.
15. The multi-chip system of claim 10, wherein the first UART interface includes only one transmit pin and only one receive pin, the first chip transmits the plurality of first data to the second chip via only the transmit pin, and the first chip receives the plurality of second data from the second chip via only the receive pin.
16. The multi-chip system of claim 15, wherein the second UART interface includes only one transmit pin and only one receive pin, the second chip transmits the plurality of second data to the first chip via only the transmit pin of the second UART interface, and the second chip receives the plurality of first data from the first chip via only the receive pin of the second UART interface.
17. The multi-chip system of claim 10, wherein the plurality of first application circuits are core circuits having different functions.
18. The multi-chip system of claim 17, wherein the plurality of first application circuits includes at least two of Wi-Fi circuitry, bluetooth circuitry, and audio circuitry.
CN202310880455.6A 2022-07-20 2023-07-18 Chip and multi-chip system Pending CN117435533A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US63/368,898 2022-07-20
US63/439,161 2023-01-16
US18/221,402 2023-07-13
US18/221,402 US20240031438A1 (en) 2022-07-20 2023-07-13 Uart-hub design for multiple data transmission

Publications (1)

Publication Number Publication Date
CN117435533A true CN117435533A (en) 2024-01-23

Family

ID=89548675

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310880455.6A Pending CN117435533A (en) 2022-07-20 2023-07-18 Chip and multi-chip system

Country Status (1)

Country Link
CN (1) CN117435533A (en)

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