CN117435347A

CN117435347A - Scheduling method and system of processor core, equipment and storage medium

Info

Publication number: CN117435347A
Application number: CN202311560885.6A
Authority: CN
Inventors: 谭文文; 陶伟; 孟磊
Original assignee: ARCHERMIND TECHNOLOGY (NANJING) CO LTD
Current assignee: ARCHERMIND TECHNOLOGY (NANJING) CO LTD
Priority date: 2023-11-22
Filing date: 2023-11-22
Publication date: 2024-01-23

Abstract

The application discloses a scheduling method, a scheduling system, scheduling equipment and scheduling storage media of a processor core, wherein the scheduling method comprises the following steps: according to the configuration priority, a first scheduling coefficient and a second scheduling coefficient of a target thread are obtained; traversing all the alternative cores of the target thread, and selecting a target scheduling coefficient from the first scheduling coefficient and the second scheduling coefficient according to the processing capacity of the alternative cores relative to the processing capacity of the previous core for processing the target thread if the processing capacity of the alternative cores is smaller than the upper limit processing capacity of the system; judging whether the alternative core meets the processing requirement of the target thread or not according to the target scheduling coefficient and the load parameter of the target thread; and selecting an alternative core meeting the processing requirement as a next core for processing the target thread. The method and the device can realize the processor core scheduling of the thread level in the kernel space of the operating system, and balance the system performance and the power consumption to a certain extent.

Description

Scheduling method and system of processor core, equipment and storage medium

Technical Field

The present disclosure relates to the field of processor technologies, and in particular, to a method, a system, an apparatus, and a storage medium for scheduling a processor core.

Background

Most of the current intelligent terminal devices adopt multi-core processors, and the energy efficiency ratios of different cores are different, for example, the small cores have low power consumption and general performance, and are suitable for running low-load tasks or background tasks; the large core has high power consumption and good performance, and is suitable for high-load tasks.

However, in some situations, some low-load tasks also need to run in the middle-large core to improve performance to meet user experience requirements, such as scenes of camera preview, photographing, video call, and the like, and the task load in these scenes is not heavy, so the tasks generally run in the small core, but when the performance requirements of users are improved, the small core running causes poor user experience.

In the prior art, a thread binding core technology is generally adopted to bind related threads of a certain scene and processor threads, for example, threads in a camera preview scene are all bound to a big core. However, this approach can cause excessive processor load and may not balance system power consumption and performance.

Disclosure of Invention

In order to solve the technical problems, the application provides a scheduling method, a scheduling system, scheduling equipment and a scheduling storage medium of a processor core.

Specifically, the technical scheme of the application is as follows:

In a first aspect, a method for scheduling a processor core, applied to a kernel space of an operating system, includes:

according to the configuration priority, a first scheduling coefficient and a second scheduling coefficient of a target thread are obtained;

traversing all the alternative cores of the target thread, and selecting a target scheduling coefficient from the first scheduling coefficient and the second scheduling coefficient according to the processing capacity of the alternative cores relative to the processing capacity of the previous core for processing the target thread if the processing capacity of the alternative cores is smaller than the upper limit processing capacity of the system;

judging whether the alternative core meets the processing requirement of the target thread or not according to the target scheduling coefficient and the load parameter of the target thread;

and selecting an alternative core meeting the processing requirement as a next core for processing the target thread.

In some embodiments, the acquiring the first scheduling coefficient and the second scheduling coefficient according to the configuration priority includes:

if the target thread is configured with an upward scheduling value and/or a downward scheduling value, acquiring the upward scheduling value and/or the downward scheduling value of the target thread as the first scheduling coefficient and/or the second scheduling coefficient;

And if the target thread is not configured with the upward scheduling value and/or the downward scheduling value, acquiring the upward scheduling value and/or the downward scheduling value of the packet to which the target thread belongs as the first scheduling coefficient and/or the second scheduling coefficient.

In some embodiments, further comprising: and if the target thread is not configured with an upward scheduling value and/or a downward scheduling value and the group to which the target thread belongs is not configured with the upward scheduling value and/or the downward scheduling value, taking the upward scheduling value and/or the downward scheduling value of the system as the first scheduling coefficient and/or the second scheduling coefficient.

In some embodiments, the selecting the target scheduling coefficient from the first scheduling coefficient and the second scheduling coefficient according to the processing capability of the candidate core relative to the previous core processing the target thread includes:

if the processing capacity of the previous core is smaller than or equal to that of the alternative core, selecting the first scheduling coefficient as the target scheduling coefficient;

and if the processing capacity of the previous core is larger than that of the alternative core, selecting the second scheduling coefficient as the target scheduling coefficient.

In some embodiments, the determining, according to the target scheduling coefficient and the load parameter of the target thread, whether the candidate core meets the processing requirement of the target thread includes:

converting the target scheduling coefficient according to the conversion ratio of the kernel space to the user space to obtain a third scheduling coefficient;

and if the third scheduling coefficient and the load parameter of the target thread meet the following formulas, the alternative core is considered to meet the processing requirement of the target thread:

capacity(cpu)*capacity(max)＞uclamp(p)*margin；

wherein capability (cpu) is a processing capability of the candidate core, capability (max) is the system upper limit processing capability, uclamp (p) is a load parameter of the target thread, and margin is the third scheduling coefficient.

In some embodiments, after determining whether the candidate core meets the processing requirement of the target thread according to the target scheduling coefficient and the load parameter of the target thread, the method includes:

if all the alternative cores do not meet the processing requirements of the target thread, judging whether the previous core is positioned in the alternative cores or not;

if yes, taking the previous core as the next core;

If not, judging whether the core of the awakening target thread is in the alternative core;

if yes, taking the core which wakes up the target thread as the next core;

and if not, taking the first core in the scheduling domain as the next core.

In a second aspect, the present application provides a scheduling system for a processor core, for use in kernel space of an operating system, comprising:

the acquisition module is used for acquiring a first scheduling coefficient and a second scheduling coefficient of the target thread according to the configuration priority;

the first selecting module is used for traversing all the alternative cores of the target thread, and selecting a target scheduling coefficient from the first scheduling coefficient and the second scheduling coefficient according to the processing capacity of the alternative cores relative to the processing capacity of the previous core for processing the target thread if the processing capacity of the alternative cores is smaller than the upper limit processing capacity of the system;

the judging module is used for judging whether the alternative core meets the processing requirement of the target thread according to the target scheduling coefficient and the load parameter of the target thread;

and the second selecting module selects the alternative core meeting the processing requirement as the next core for processing the target thread.

In some embodiments, the obtaining module is configured to obtain, as the first scheduling coefficient and/or the second scheduling coefficient, an upward scheduling value and/or a downward scheduling value of the target thread if the target thread has configured the upward scheduling value and/or the downward scheduling value;

the obtaining module is further configured to obtain, if the target thread is not configured with an upward scheduling value and/or a downward scheduling value, the upward scheduling value and/or the downward scheduling value of the packet to which the target thread belongs as the first scheduling coefficient and/or the second scheduling coefficient. Specifically, two layers of priorities are set, the first layer of priority is a thread level, the second layer of priority is a grouping level, and the refinement degree of the processor during scheduling is improved.

In some embodiments, the obtaining module is further configured to use a system upward scheduling value and/or downward scheduling value as the first scheduling coefficient and/or the second scheduling coefficient if the target thread is not configured with an upward scheduling value and/or a downward scheduling value, and the packet to which the target thread belongs is also not configured with an upward scheduling value and/or a downward scheduling value. In addition to the two-layer priority, the system control value is used as the spam base, in

In some embodiments, further comprising:

the packet scheduling module is positioned in the controller and provides a packet configuration interface for a user space so that the user space can set up scheduling values and/or down scheduling values of all packets through the packet configuration interface;

and the thread scheduling module is used for providing a thread configuration interface for the user space so that the user space can set an upward scheduling value and/or a downward scheduling value of each thread through the thread configuration interface.

In a third aspect, the present application provides an apparatus comprising a scheduling system for a processor core as described in any one of the above.

In some embodiments, further comprising: and the adjusting system is used for adjusting the processor scheduling mode of the equipment to a mode corresponding to the adjusting instruction according to the adjusting instruction input by the user.

In a fourth aspect, the present application provides a storage medium having stored therein at least one instruction that is loaded and executed by a processor to implement operations performed by a scheduling method for a processor core as described in any of the above.

Compared with the prior art, the application has at least one of the following beneficial effects:

(1) According to the method and the device, the processor core can be dynamically scheduled according to the requirements of different user scenes, and compared with a static core binding technology, the scheduling mode is more flexible, so that the situation that the processor is overloaded is avoided.

(2) According to the method and the device, the processor core scheduling is performed based on the scheduling coefficient, the thread-level scheduling coefficient configuration is realized, and finer scheduling can be provided according to the requirements of a user scene.

(3) According to the method and the device, the scheduling coefficient is superimposed on the basis of the load parameter, and the scheduling coefficient is used as a core selection basis, so that compared with a mode of directly adjusting the load parameter, the method and the device are beneficial to reducing the system power consumption.

(4) The method expands the functions of the cpu subsystem in the process group controller (cpu) in the kernel space, and increases the scheduling coefficient configuration function, so that parameter configuration can be carried out on the process group, and processor core scheduling at the process group level is realized.

Drawings

The drawings that accompany the description can be briefly described as follows:

FIG. 1 is a flow chart of a method of scheduling a processor core provided in an embodiment of the present application;

FIG. 2 is a flowchart of acquiring a first target scheduling coefficient and a second target scheduling coefficient in an embodiment of the present application;

FIG. 3 is a flow chart of another method of scheduling processor cores provided in an embodiment of the present application;

FIG. 4 is a block diagram of a scheduling system for a processor core provided in an embodiment of the present application;

fig. 5 is a block diagram of another processor core scheduling system provided in an embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following description will explain specific embodiments of the present application with reference to the accompanying drawings. It is obvious that the drawings in the following description are only examples of the present application, and that other drawings and other embodiments may be obtained from these drawings by those skilled in the art without undue effort.

For simplicity of the drawing, only the parts relevant to the application are schematically shown in each drawing, and they do not represent the actual structure thereof as a product. Additionally, in order to simplify the drawing for ease of understanding, components having the same structure or function in some of the drawings are shown schematically with only one of them, or only one of them is labeled. Herein, "a" means not only "only this one" but also "more than one" case.

It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

In addition, in the description of the present application, the terms "first," "second," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.

Currently, many smart terminal devices, such as mobile phones and tablet computers, use a multi-Core processor, where one processor has multiple cores (cores), for example, a four-Core processor and an eight-Core processor. The multi-core processor adopts a large-small core design, and the processor topological structure is, for example, 4 small cores+4 large cores or 4 small cores+3 medium cores+1 large cores. The large core and the small core use different processor microarchitecture, and the different processor microarchitecture has different energy efficiency ratios, such as small core power consumption but general performance, and is suitable for running low-load tasks or background tasks; large cores consume large amounts of power but perform well, and are suitable for running high-load tasks or tasks that are more perceptible to the user (e.g., user interface related tasks). Reference to a "task" in embodiments of the present application refers to one or more threads, or one or more processes, or a combination of threads and processes.

In some scenarios, however, flexible scheduling of processor cores is required according to the requirements of the user experience. In an Android system, a camera provider service processes algorithms related to coding and decoding and camera effects, and multiple threads are started to process the algorithms in parallel, so that the load of each thread is not heavy, and most of the threads of the camera provider service run on a small core. However, as the expected value of the camera performance requirements of users increases, the camera provider service thread needs to run as much as possible on the middle and large cores. To solve this problem, the conventional approach is to use thread binding techniques to bind the relevant thread to several of the processor cores, e.g., to bind the camera provider service thread to the middle-large core execution. However, the bound cores are overloaded and are easy to be in a busy state, and there is no way to respond to the related threads in time.

Based on this, the embodiment of the application provides a scheduling method of a processor core, which can flexibly schedule the processor core according to the requirements of different user scenes, and can balance the system performance and the power consumption to a certain extent.

Referring to the drawings, as shown in fig. 1, a method for scheduling a processor core according to an embodiment of the present application is applied to a kernel space of an operating system, and includes the steps of:

s100, acquiring a first scheduling coefficient and a second scheduling coefficient of the target thread according to the configuration priority.

Specifically, the process is the minimum unit of resource allocation by the operating system, each process corresponds to a program, and the process is one execution process of the program. A process may have multiple sub-tasks, i.e., threads, such as sending messages, receiving messages, etc., through a chat tool.

The target thread is a thread which needs to be transferred from the small core operation to the large core operation, is set according to the hardware capability of the processor chip and the requirement under the user scene, and can be selected according to user experience feedback and laboratory test data. For example, the user has higher performance requirements in the camera scene and is not satisfied with the image effect, the video call quality and the like in the current camera scene, and then the target thread can be set as a thread related to the camera; for another example, the laboratory test data indicates that the user interface thread and rendering thread of the foreground application need to run in the big core in some scenarios, and then the thread may be set as the target thread.

Threads are the basic unit of scheduling and allocation of processor cores, which are scheduled in the kernel space of the operating system, and a scheduler in the kernel space performs kernel selection according to the load condition of the threads, and places the threads on the proper processor cores to run. For example, for a highly loaded thread, the small core may not have sufficient processing power and the scheduler may select the large core to run the thread. However, this kernel selection method is very single and cannot provide finer scheduling according to the needs of the user scene. Thus, the present application introduces the concept of scheduling coefficients and based thereon processor core scheduling is performed.

The scheduling coefficients include an up-schedule value (upscales) and a down-schedule value (downscales), the smaller the upscales of the processor cores, the easier it is to transfer the threads it handles to the large cores (which can be understood as up-scaling), and the larger the downscales, the easier it is to transfer to the small cores (which can be understood as down-scaling).

In the prior art, the scheduler has an up-scale interface and a down-scale interface, and the user space can configure the two thresholds through the two interfaces, but the two interfaces are specific to the system, the specific parameter value configured by the user space affects all threads in the system, and no method is provided for configuring a certain thread. In the kernel space, each thread is allocated a task_struct structure to manage information of each thread, which includes various information about the thread, such as an identifier, a state, a priority, memory information, file information, and the like of the thread. Based on the above, in the embodiment of the present application, the function of the task_struct structure is extended, and the scheduling coefficient configuration function is added, so that the scheduling coefficient can be configured for a specific thread.

The first scheduling coefficient and the second scheduling coefficient mentioned in the embodiment of the present application refer to an uplink and a downlink determined according to the configuration priority. Under some user scenarios, there may be more than one thread, if each thread is configured with a scheduling coefficient separately, the efficiency is too low, so in this embodiment, the configuration priority is set, the target thread is the highest priority configured, if the target thread is configured with a scheduling coefficient, the up and down of the target thread are directly used as the first scheduling coefficient and the second scheduling coefficient, and if the target thread is not configured with a scheduling coefficient, the configuration may be uniformly performed by adopting the manner of the scheduler. In this embodiment, only two levels of priority are taken as an example, and the priority may be set to multiple levels in implementation, and the priority of the thread may not be the highest level.

S200, judging whether the processing capacity of the alternative core is smaller than the upper limit processing capacity of the system, if so, executing step S300; otherwise, step S500 is performed.

Specifically, according to the foregoing, the target thread is a thread that needs to be transferred from the small core running to the large core running, that is, the core currently running the target thread cannot meet the performance requirement of the target thread, so that the target thread needs to be transferred to the large core with higher processing capability. In this embodiment, all the candidate cores are traversed, and if the processing capability of the candidate core is already greater than or equal to the upper limit processing capability of the system, the candidate core may be directly used as the next core of the processing target thread. The candidate cores include all processor cores, or may be initially screened, where cores obtained after the initial screening are used as candidate cores.

S300, selecting a target scheduling coefficient from the first scheduling coefficient and the second scheduling coefficient according to the processing capacity of the alternative core relative to the previous core of the processing target thread.

S400, judging whether the alternative core meets the processing requirement of the target thread according to the target scheduling coefficient and the load parameter of the target thread.

Specifically, the load parameter (Utilization Clamping, uclamp) refers to a threshold value of the target thread utilization, which is used to indicate the usage of the CPU by a thread, and indicates whether the thread is high or low. Therefore, increasing the load parameter of the thread is equivalent to increasing the load of the thread (higher than the actual load of the thread), so that the thread has higher probability of running on the middle-large core. But increasing the load parameters, while causing an increase in the frequency of the processor, affects power consumption. Therefore, in this embodiment, the load parameter and the scheduling coefficient are combined, the load parameter is not directly adjusted, and the scheduling coefficient is superimposed on the basis of the load parameter, so that the target thread can be selected, and unnecessary power consumption is not increased.

S500, selecting an alternative core meeting the processing requirement as the next core of the processing target thread.

According to the embodiment, the processor core scheduling can be dynamically performed by combining the load parameters with the scheduling coefficients according to the requirements of different user scenes, and compared with a static core binding technology, the processor core scheduling method is beneficial to avoiding the condition that the processor is overloaded.

In addition, if multiple alternative cores meeting the processing requirement are generated at the same time, other core selection modes can be adopted until one processor core which can meet the target thread best is screened out. For example, the target threads are respectively put into the alternative cores meeting the processing requirements to run, and the cores with the minimum capability consumption are selected by comparing the capability consumption of the alternative cores.

Further, based on the above embodiment, as shown in fig. 2, step S100 specifically includes:

s110, judging whether the target thread is configured with an upward scheduling value and/or a downward scheduling value, if so, executing step S120; otherwise, step S130 is performed.

S120, the upward scheduling value and/or the downward scheduling value of the target thread are/is obtained as a first scheduling coefficient and/or a second scheduling coefficient.

S130, judging whether the grouping to which the target thread belongs is configured with an upward scheduling value and/or a downward scheduling value, if yes, executing step S140; otherwise, step S150 is performed.

S140, the upward scheduling value and/or the downward scheduling value of the packet to which the target thread belongs are obtained as the first scheduling coefficient and/or the second scheduling coefficient.

S150 uses the system upward scheduling value and/or the downward scheduling value as the first scheduling coefficient and/or the second scheduling coefficient.

Specifically, the configuration priority is divided into three levels according to the level height: threads, groups to which threads belong, and systems.

The grouping refers to dividing processes belonging to the same type into one group according to the type of the process. Because a process includes several threads, the packets to which the process belongs can be directly used as the packets of the threads. It should be noted that a thread can only belong to one of the packets, and if a thread is set to packet B before packet a, then it is removed from packet a.

Taking an android system as an example, the android system supports simultaneous existence and operation of a plurality of processes or threads, including an application process and a system process, and at the moment, some processes interact with a user at a user interface, for example, the user is using video software; some processes are used by the user before, the processes are switched to the background and are invisible and imperceptible to the user, and the android system caches the processes in the memory as much as possible, so that the processes can be started quickly when the user starts the applications next time without time-consuming starting processes such as initialization and the like; some processes, although the user has switched to the background, are still perceivable by the user, such as music-like applications, and the switch to music may be played later. It should be noted that, the grouping method in this embodiment is not only applicable to the android system, but also applicable to other operating systems, such as a Linux system.

And so on, for such scenarios, the system resources are limited and more system resources need to be provided to the process interacting with the user, the user perceivable process, or the process affecting the user experience for the user experience. If separate system resource control is performed for each process, it is too cumbersome, so the android system groups processes that have the same characteristic performance for the user experience, and then performs system resource provisioning configuration for each group. For example, the grouping may be performed in the following manner:

(1) Top-layer packet (top-app): applications that interact directly with users.

(2) Foreground packet (forecourt): a process that is visible to the user but does not interact directly with the user.

(3) Background packet (background): a process that runs in the background and is imperceptible to the user.

(4) Key-background grouping (key-background): a process that runs in the background and is user-perceivable.

(5) System group (system): and (5) a system process.

(6) System critical grouping (key-system): and (5) a key process of the system.

(7) Some processes of the camera are divided into camera groups; similar audio playback related processes are classified into audio group graphics image related processes, graphic groups, and the like.

In addition, the method can be expanded on the basis of the grouping, such as a new key-forward grouping (key-forward) for finer resource control of a forward process, a new game grouping for control of a game process, and the like.

The cpu system (cpu) is a subsystem of a process group controller (cpu) for limiting and controlling the resource usage of a process group (packet). Specifically, for example, the load parameter (uclamp) of the packet is configured, and the size of the uclamp affects the CPU frequency of the thread in the packet during running; the cpu.shares value configuration of a packet affects the usage time obtained by the packet, and threads of multiple packets may need to run on one core, requiring that the packets be allocated usable time by cpu.shares. cgroup provides an interface implementation that sets a process to a packet to which all threads of a process are set when the process is set to the packet.

In this embodiment, the function of cpu is extended, so that it can configure the scheduling coefficient of the process group, and then a configuration interface of the scheduling coefficient is provided to the user space through the cgroup. The user space sets up-scheduling values and/or down-scheduling values of the thread groups through the configuration interface, and all threads under the configured process groups have the same up-scheduling values and/or down-scheduling values.

In one embodiment of the present application, a scheduling method of a processor, as shown in fig. 3, includes the steps of:

S210, traversing all the alternative cores of the target thread, if the processing capacity of the alternative cores is smaller than the upper limit processing capacity of the system, judging whether the processing capacity of the previous core is larger than the processing capacity of the alternative cores, and if not, executing the step S220; otherwise, step S230 is performed.

S220 selects the first scheduling coefficient as the target scheduling coefficient, and step S240 is executed.

S230, selecting the second scheduling coefficient as a target scheduling coefficient, and executing step S240.

S240, converting the target scheduling coefficient according to the conversion ratio of the kernel space to the user space to obtain a third scheduling coefficient;

s250, judging whether the third scheduling coefficient and the load parameter of the target thread meet the following conditions:

capacity(cpu)*capacity(max)＞uclamp(p)*margin；

if yes, the alternative core is considered to meet the processing requirement of the target thread; otherwise, the core selection is considered to be failed.

Specifically, if the processing capability (capability) of the candidate core is the upper limit processing capability of the system, that is, the capability of the corresponding large core at the highest frequency, the thread requirement can be satisfied. Processing power refers to the number of instructions per second that a core can process, where the capability of a large core processor running at the highest frequency in the system is defined as 1024, and the maximum capability of other frequencies or other processors scales with 1024 as a base.

If the candidate core is limited or not large at this time, which means that the processing capacity of the candidate core is smaller than the upper limit processing capacity of the system, it is determined whether the processing capacity of the previous core is larger than the capacity of the candidate core.

If the processing capacity of the previous core is larger than that of the alternative core, the previous core is a large core relative to the alternative core, and the purpose of the alternative core is to adjust the target thread from small core processing to large core processing, so that the previous core becomes a new alternative core instead of the alternative core. For a large core, it is necessary to keep its downward scheduling threshold (the second scheduling coefficient) as small as possible, avoiding its fallback to the small core.

If the processing capability of the previous core is less than or equal to the candidate core, the candidate core is a big core, and the objective of the selection core is to adjust the target thread from the small core processing to the big core processing, then for the candidate core at this time, it needs to be kept as large as possible, so it needs to keep its upward scheduling threshold (first scheduling coefficient) as small as possible, so that it is easier to rise to the big core.

In the foregoing embodiment, it is mentioned that the up and down metrics of the target thread are both input to the kernel space by the user space, so after entering the kernel space, the target thread needs to be converted to be used by the user space, and the conversion formula is as follows:

Third scheduling coefficient = sched_fix_ratio_scale 100/target scheduling coefficient;

where sched_fix_scale is a constant that specifies the time granularity, by using sched_fix_scale, the scheduler may convert the time requirements of the task (e.g., the time range of task execution) into a fixed point representation for task scheduling and prioritization. The conversion can enable the scheduling algorithm to be more accurate and flexible, meanwhile, the dependence on actual time is reduced, and the expandability and portability of the scheduling algorithm are improved. The specific sched_fix_command value varies depending on the implementation of the operating system and scheduling algorithm, for example being set to 1024, or shifting 1024 left by 10 bits through a shift operation, etc. "100" means that the array of user space is 0-100, and the above formula is to normalize the data of user space to the data representation of kernel space.

After the third scheduling coefficient is obtained, whether the candidate core can meet the requirement of the target thread is judged according to the following formula:

capacity(cpu)*capacity(max)＞uclamp(p)*margin；

wherein capability (cpu) is the processing capability of the candidate core, capability (max) is the upper limit processing capability of the system, uclamp (p) is the load parameter of the target thread, and margin is the third scheduling coefficient (inversely proportional to the upscales or downscales).

If the third scheduling coefficient and the load parameter of the target thread can meet the above formula, the alternative core is considered to meet the processing requirement of the target thread; otherwise, the core selection is considered to be failed. While adjusting uclamp (p) can naturally perform core scheduling as described above, the essence of this approach is that the load of the thread is artificially increased (higher than the actual load of the thread), which tends to increase the frequency of the processor and affect the power consumption. Therefore, in this embodiment, the uclamp and the margin are combined, and the target thread can be transferred to the large core to run without adjusting the uclamp, so that the power consumption is reduced.

Further, after the core selection failure, the core selection is performed for the target thread through the following steps:

step 1, judging whether the alternative core comprises a previous core of the processing target thread, and if so, taking the previous core as a next core of the processing target thread; otherwise, step 2 is performed.

Step 2, judging whether the core of the awakening target thread is in the alternative core, if so, taking the core of the awakening target thread as the next core; otherwise, the first core in the scheduling domain is taken as the next core.

And providing a standby scheme for the core selection failure through the steps.

The embodiment of the application further provides a storage medium, wherein at least one instruction is stored in the storage medium, and the instruction is loaded and executed by a processor to realize the operation performed in the scheduling method embodiment of any processor core. For example, the storage medium may be read-only memory (ROM), random-access memory (RAM), compact disk read-only (CD-ROM), magnetic tape, floppy disk, optical data storage device, etc. They may be implemented in program code that is executable by a computing device such that they may be stored in a memory device for execution by the computing device, or they may be separately fabricated into individual integrated circuit modules, or a plurality of modules or steps in them may be fabricated into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.

Based on the same technical concept, the embodiment of the present application provides a scheduling system 100 of a processor core, as shown in fig. 4, applied to a kernel space of an operating system, including an obtaining module 110, a first selecting module 120, a judging module 130, and a second selecting module 140, where:

the obtaining module 110 is configured to obtain, according to the configuration priority, the first scheduling coefficient and the second scheduling coefficient of the target thread.

The first selection module 120 is configured to traverse all the candidate cores of the target thread, and if the processing capacity of the candidate cores is smaller than the upper limit processing capacity of the system, select the target scheduling coefficient from the first scheduling coefficient and the second scheduling coefficient according to the processing capacity of the candidate cores relative to the previous core for processing the target thread.

The judging module 130 is configured to judge whether the candidate core meets the processing requirement of the target thread according to the target scheduling coefficient and the load parameter of the target thread.

The second selecting module 140 is configured to select an alternative core that meets the processing requirement as a next core of the processing target thread.

In one embodiment, the obtaining module 110 is configured to obtain, as the first scheduling coefficient and/or the second scheduling coefficient, the upward scheduling value and/or the downward scheduling value of the target thread if the target thread has configured the upward scheduling value and/or the downward scheduling value; the obtaining module 110 is further configured to obtain, if the target thread is not configured with the upward scheduling value and/or the downward scheduling value, the upward scheduling value and/or the downward scheduling value of the packet to which the target thread belongs as the first scheduling coefficient and/or the second scheduling coefficient.

In one embodiment, the obtaining module 110 is further configured to use the system up-scheduling value and/or down-scheduling value as the first scheduling coefficient and/or the second scheduling coefficient if the target thread is not configured with the up-scheduling value and/or down-scheduling value and the packet to which the target thread belongs is also not configured with the up-scheduling value and/or down-scheduling value.

In one implementation, an embodiment of the present application provides a scheduling system for a processor core, as shown in fig. 5, further including, on the basis of the foregoing embodiment:

the packet scheduling module 151 is located in the controller 150, and the packet scheduling module 151 provides a packet configuration interface to the user space, so that the user space sets up scheduling values and/or down scheduling values of the respective packets through the packet configuration interface.

The controller 150 is, for example, a control group (cgroup) for controlling, limiting, separating process group resources (such as CPU, memory, disk input/output, etc.) in the kernel space of the operating system, and the packet scheduling module 151 is, for example, a CPU system (CPU), which is a subsystem of the cgroup for limiting, controlling the resource usage of a process group (packet), which provides control over specific actions of the CPU, such as CPU frequency adjustment, CPU power management, etc. Through the CPU subsystem, CPU related parameters in the system, such as setting CPU usage limits, priority adjustment, etc., can be managed.

In the general kernel, the cpu subsystem does not have a function of configuring a scheduling coefficient, and in this embodiment, the cpu subsystem expands the function of the cpu to enable the cpu to configure the scheduling coefficient of the process group, and then provides a configuration interface of the scheduling coefficient for the user space through the cpu group. The user space sets up-scheduling values and/or down-scheduling values of the thread groups through the configuration interface, and all threads under the configured process groups have the same up-scheduling values and/or down-scheduling values.

The thread scheduling module 160, the thread scheduling module 160 provides a thread configuration interface to the user space, so that the user space sets up scheduling values and/or down scheduling values of the respective threads through the thread configuration interface. Specifically, in the kernel space, each thread is allocated a task_struct structure that manages information of each thread, and it contains various information about the thread, such as an identifier, a state, a priority, memory information, file information, and the like of the thread. The functions of the structure body are expanded, so that the structure body can configure the scheduling coefficients of the threads, then a configuration interface is provided for a user space through a scheduler, and the user space can configure the scheduling parameters of each thread through the interface.

In kernel space, a scheduling coefficient (uplink/downlink) configuration is a function of the scheduler, and in this embodiment, the function is respectively expanded to a cpu subsystem and a task_struct structure, so that processor core scheduling at a thread level and a process group level is realized, and scheduling flexibility and refinement degree are improved.

It should be noted that, the embodiments of the processor core scheduling system provided in the present application and the embodiments of the processor core scheduling method provided in the foregoing embodiments are both based on the same inventive concept, and can achieve the same technical effects. Thus, for further details of embodiments of a scheduling system for a processor core, reference may be made to the description of embodiments of a scheduling method for a processor core described above.

In addition, the embodiment of the application also provides equipment, such as a computer, a mobile phone and other terminal equipment, including the processor core scheduling system in any embodiment. The device provided by the embodiment of the application comprises a processor core scheduling system and an adjusting system.

The processor core scheduling system can traverse the alternative cores and screen out the cores meeting the requirements of the target threads. And the adjusting system is used for adjusting the processor scheduling mode of the equipment to a mode corresponding to the adjusting instruction according to the adjusting instruction input by the user.

Specifically, the processor scheduling modes include, for example, an automatic scheduling mode and a scene scheduling mode. In the automatic adjustment mode, the processor core scheduling system automatically selects the processor core matched with the requirement of the current user scene. The scene scheduling mode is used for presetting corresponding fixed parameters (parameters which are tested and verified) for different user scenes, for example, setting two sets of parameters of high performance and low performance in a camera scene, and when the user switches to the scene scheduling mode, the user can select to configure the high performance parameters or the low performance parameters by himself.

Further, the device further comprises a data acquisition system, when a user uses the device, operation data of different cores of the processor in processing tasks are recorded, the acquired data are sent to the server, and the server analyzes the received data, so that parameters are adjusted according to analysis results. Of course, parameters may also be adjusted by opinion fed back by the user or laboratory test data; the processor core scheduling system selects cores according to the adjusted parameters. In the embodiment, the acquisition module can analyze the habit of the user, provide a personalized processor core scheduling scheme and improve the user experience.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment. It should be noted that the above embodiments can be freely combined as needed. The foregoing is merely a preferred embodiment of the present application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present application and are intended to be comprehended within the scope of the present application.

Claims

1. A method of scheduling a processor core, applied to a kernel space of an operating system, comprising:

2. The method for scheduling a processor core according to claim 1, wherein said obtaining the first scheduling coefficient and the second scheduling coefficient according to the configuration priority comprises:

3. The method of scheduling a processor core of claim 2, further comprising:

and if the target thread is not configured with an upward scheduling value and/or a downward scheduling value and the group to which the target thread belongs is not configured with the upward scheduling value and/or the downward scheduling value, taking the upward scheduling value and/or the downward scheduling value of the system as the first scheduling coefficient and/or the second scheduling coefficient.

4. The method of scheduling a processor core according to claim 1, wherein selecting the target scheduling coefficient from the first scheduling coefficient and the second scheduling coefficient according to a processing capability of the candidate core with respect to a previous core processing the target thread comprises:

5. The method for scheduling a processor according to claim 1, wherein the determining whether the candidate core meets the processing requirement of the target thread according to the target scheduling coefficient and the load parameter of the target thread comprises:

capacity(cpu)*capacity(max)＞uclamp(p)*margin；

6. The method for scheduling a processor core according to claim 1, wherein after determining whether the candidate core meets the processing requirement of the target thread according to the target scheduling coefficient and the load parameter of the target thread, the method comprises:

If yes, taking the previous core as the next core;

if yes, taking the core which wakes up the target thread as the next core;

and if not, taking the first core in the scheduling domain as the next core.

7. A scheduling system for a processor core, for use in a kernel space of an operating system, comprising:

8. The scheduling system of a processor core of claim 7,

the obtaining module is configured to obtain, if the target thread has configured an upward scheduling value and/or a downward scheduling value, the upward scheduling value and/or the downward scheduling value of the target thread as the first scheduling coefficient and/or the second scheduling coefficient;

the obtaining module is further configured to obtain, if the target thread is not configured with an upward scheduling value and/or a downward scheduling value, the upward scheduling value and/or the downward scheduling value of the packet to which the target thread belongs as the first scheduling coefficient and/or the second scheduling coefficient.

9. The scheduling system of a processor core of claim 8,

and the acquisition module is further configured to use the system upward scheduling value and/or downward scheduling value as the first scheduling coefficient and/or the second scheduling coefficient if the target thread is not configured with the upward scheduling value and/or the downward scheduling value and the packet to which the target thread belongs is also not configured with the upward scheduling value and/or the downward scheduling value.

10. The scheduling system of a processor core of claim 7, further comprising:

11. An apparatus comprising a scheduling system of a processor core according to any one of claims 7-10.

12. The apparatus as recited in claim 11, further comprising:

and the adjusting system is used for adjusting the processor scheduling mode of the equipment to a mode corresponding to the adjusting instruction according to the adjusting instruction input by the user.

13. A storage medium having stored therein at least one instruction that is loaded and executed by a processor to implement operations performed by a scheduling method of a processor core according to any one of claims 1 to 6.