CN1174314C - 用于64位寻址的调用选通扩充 - Google Patents

用于64位寻址的调用选通扩充 Download PDF

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Publication number
CN1174314C
CN1174314C CNB008183430A CN00818343A CN1174314C CN 1174314 C CN1174314 C CN 1174314C CN B008183430 A CNB008183430 A CN B008183430A CN 00818343 A CN00818343 A CN 00818343A CN 1174314 C CN1174314 C CN 1174314C
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China
Prior art keywords
descriptor
segment
entry
bit
processor
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Expired - Lifetime
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CNB008183430A
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English (en)
Chinese (zh)
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CN1423774A (zh
Inventor
���ġ�J����˸���˹
凯文·J·马克格瑞斯
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication of CN1423774A publication Critical patent/CN1423774A/zh
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Publication of CN1174314C publication Critical patent/CN1174314C/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/342—Extension of operand address space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CNB008183430A 2000-01-14 2000-07-19 用于64位寻址的调用选通扩充 Expired - Lifetime CN1174314C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/483,078 US6715063B1 (en) 2000-01-14 2000-01-14 Call gate expansion for 64 bit addressing
US09/483,078 2000-01-14

Publications (2)

Publication Number Publication Date
CN1423774A CN1423774A (zh) 2003-06-11
CN1174314C true CN1174314C (zh) 2004-11-03

Family

ID=23918555

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB008183430A Expired - Lifetime CN1174314C (zh) 2000-01-14 2000-07-19 用于64位寻址的调用选通扩充

Country Status (8)

Country Link
US (1) US6715063B1 (https=)
EP (1) EP1247172B1 (https=)
JP (1) JP4615810B2 (https=)
KR (1) KR100643874B1 (https=)
CN (1) CN1174314C (https=)
DE (1) DE60014438T2 (https=)
TW (1) TWI222016B (https=)
WO (1) WO2001052059A1 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6807622B1 (en) * 2000-08-09 2004-10-19 Advanced Micro Devices, Inc. Processor which overrides default operand size for implicit stack pointer references and near branches
US7100028B2 (en) * 2000-08-09 2006-08-29 Advanced Micro Devices, Inc. Multiple entry points for system call instructions
CN1902600A (zh) * 2003-06-17 2007-01-24 皇家飞利浦电子股份有限公司 微控制器和寻址方法
US8843727B2 (en) * 2004-09-30 2014-09-23 Intel Corporation Performance enhancement of address translation using translation tables covering large address spaces
US7962725B2 (en) * 2006-05-04 2011-06-14 Qualcomm Incorporated Pre-decoding variable length instructions
US8504807B2 (en) 2009-12-26 2013-08-06 Intel Corporation Rotate instructions that complete execution without reading carry flag
US8528083B2 (en) * 2011-03-10 2013-09-03 Adobe Systems Incorporated Using a call gate to prevent secure sandbox leakage
EP2701077A1 (en) * 2012-08-24 2014-02-26 Software AG Method and system for storing tabular data in a memory-efficient manner
US10120663B2 (en) 2014-03-28 2018-11-06 Intel Corporation Inter-architecture compatability module to allow code module of one architecture to use library module of another architecture
CN105094870A (zh) * 2014-05-13 2015-11-25 中标软件有限公司 64位Linux操作系统兼容32位应用软件的方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4620274A (en) 1983-04-01 1986-10-28 Honeywell Information Systems Inc. Data available indicator for an exhausted operand string
US4701946A (en) 1984-10-23 1987-10-20 Oliva Raymond A Device for controlling the application of power to a computer
US5381537A (en) 1991-12-06 1995-01-10 International Business Machines Corporation Large logical addressing method and means
US5617554A (en) 1992-02-10 1997-04-01 Intel Corporation Physical address size selection and page size selection in an address translator
US5692167A (en) 1992-07-31 1997-11-25 Intel Corporation Method for verifying the correct processing of pipelined instructions including branch instructions and self-modifying code in a microprocessor
US5371867A (en) * 1992-11-10 1994-12-06 International Business Machines Corporation Method of using small addresses to access any guest zone in a large memory
US5517651A (en) * 1993-12-29 1996-05-14 Intel Corporation Method and apparatus for loading a segment register in a microprocessor capable of operating in multiple modes
US5481684A (en) * 1994-01-11 1996-01-02 Exponential Technology, Inc. Emulating operating system calls in an alternate instruction set using a modified code segment descriptor
US5758116A (en) 1994-09-30 1998-05-26 Intel Corporation Instruction length decoder for generating output length indicia to identity boundaries between variable length instructions
US5644755A (en) 1995-02-24 1997-07-01 Compaq Computer Corporation Processor with virtual system mode
US5774686A (en) 1995-06-07 1998-06-30 Intel Corporation Method and apparatus for providing two system architectures in a processor
US5784638A (en) 1996-02-22 1998-07-21 International Business Machines Corporation Computer system supporting control transfers between two architectures
US5826074A (en) 1996-11-22 1998-10-20 S3 Incorporated Extenstion of 32-bit architecture for 64-bit addressing with shared super-page register
US6086623A (en) * 1997-06-30 2000-07-11 Sun Microsystems, Inc. Method and implementation for intercepting and processing system calls in programmed digital computer to emulate retrograde operating system

Also Published As

Publication number Publication date
EP1247172B1 (en) 2004-09-29
DE60014438T2 (de) 2005-10-06
TWI222016B (en) 2004-10-11
WO2001052059A1 (en) 2001-07-19
DE60014438D1 (de) 2004-11-04
CN1423774A (zh) 2003-06-11
JP2003519869A (ja) 2003-06-24
KR100643874B1 (ko) 2006-11-10
KR20020091067A (ko) 2002-12-05
US6715063B1 (en) 2004-03-30
EP1247172A1 (en) 2002-10-09
JP4615810B2 (ja) 2011-01-19

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Granted publication date: 20041103