CN117425340A

CN117425340A - Semiconductor device, manufacturing method thereof and electronic equipment

Info

Publication number: CN117425340A
Application number: CN202310097723.7A
Authority: CN
Inventors: 贾礼宾; 平延磊; 田超
Original assignee: Beijing Superstring Academy of Memory Technology
Current assignee: Beijing Superstring Academy of Memory Technology
Priority date: 2023-01-19
Filing date: 2023-01-19
Publication date: 2024-01-19

Abstract

A semiconductor device, a method of manufacturing the same, and an electronic apparatus, the semiconductor device including: at least one transistor, bit line disposed on the substrate; the transistor includes: the semiconductor column extends along the direction perpendicular to the substrate, the semiconductor column comprises a channel region, a first region and a second region, the first region and the second region are respectively arranged on two sides of the channel region, the second region is arranged on one side, facing the substrate, of the channel region, the bit line is in contact with the second region, the first region comprises two end portions and a middle portion located between the two end portions, and orthographic projections of the two end portions are located in orthographic projections of the middle portion. According to the scheme provided by the embodiment, the first area is arranged as the orthographic projection of the end part and is positioned in the orthographic projection of the middle part, the first area is not formed in a conventional mode of etching on the substrate, but is additionally formed in an epitaxial growth mode, the depth-to-width ratio of the isolation groove can be reduced, the process difficulty is reduced, and the possibility of leaving slits and cavities when filling is reduced.

Description

Semiconductor device, manufacturing method thereof and electronic equipment

Technical Field

Embodiments of the present disclosure relate to, but not limited to, semiconductor technology, and more particularly, to a semiconductor device, a method of manufacturing the same, and an electronic apparatus.

Background

A memory cell of a dynamic random access memory (Dynamic Random Access Memory, DRAM) includes a transistor and a capacitor, the gate of the transistor being connected to a word line, the drain being connected to a bit line, and the source being connected to the capacitor.

In order to improve the integration of DRAM memory, the size of transistors is becoming smaller. With the shrinking size, the coupling between word lines is serious, and a large parasitic capacitance exists, which affects the operation performance of the memory.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the disclosure provides a semiconductor device, a manufacturing method thereof and electronic equipment, which reduce the process difficulty and improve the device performance.

The disclosed embodiment provides a semiconductor device, comprising: at least one transistor, bit line disposed on the substrate; the transistor includes: the semiconductor column comprises a channel region, a first region and a second region, wherein the first region and the second region are respectively arranged on two sides of the channel region, the second region is arranged on one side of the channel region, which faces the substrate, the bit line is in contact with the second region, the first region comprises two end parts and a middle part, the middle part is arranged between the two end parts, along the direction perpendicular to the substrate, and on a plane parallel to the substrate, the orthographic projection of the two end parts is positioned in the orthographic projection of the middle part.

In some embodiments, the orthographic projection of the channel region is located within the orthographic projection of the first region on a plane parallel to the substrate.

In some embodiments, the cross-section of the first region comprises a hexagon along a direction perpendicular to the substrate.

In some embodiments, the transistor further comprises a gate electrode surrounding a sidewall of the channel region;

the semiconductor device comprises a plurality of transistors distributed in an array along a first direction and a second direction, a plurality of bit lines extending along the second direction, and a plurality of word lines extending along the first direction, wherein second areas of transistors of the same column distributed along the second direction are connected with the same bit line, gate electrodes of transistors of the same row distributed along the first direction are connected to form one word line, and the first direction and the second direction are intersected.

In some embodiments, the semiconductor device further includes bit line isolation trenches disposed between adjacent bit lines extending in a second direction, a ratio of a depth of the bit line isolation trenches along a direction perpendicular to a substrate to a width of the bit line isolation trenches along a direction parallel to the substrate and perpendicular to the second direction being 4:1 to 6:1.

In some embodiments, the semiconductor device further includes word line isolation trenches disposed between adjacent word lines extending in a first direction, a ratio of a depth of the word line isolation trenches along a direction perpendicular to the substrate to a width of the word line isolation trenches along a direction parallel to the substrate and perpendicular to the first direction being 2:1 to 4:1.

In some embodiments, the semiconductor device further comprises a third insulating layer disposed on a side of the gate electrode remote from the substrate, filling between adjacent first regions, the third insulating layer being provided with a gas gap.

In some embodiments, the third insulating layer includes a first surface proximate to the substrate and a second surface distal from the substrate, the distance between the gas gap and the first surface being less than the distance between the gas gap and the second surface in a direction perpendicular to the substrate.

In some embodiments, the material of the third insulating layer comprises phosphosilicate glass.

In some embodiments, the semiconductor device further comprises: and a third isolation layer disposed between the third insulation layer and the first region, and between the third insulation layer and the gate electrode.

An embodiment of the present disclosure provides an electronic device including the semiconductor device described in any one of the embodiments above.

Embodiments of the present disclosure provide a method of manufacturing a semiconductor device including at least one transistor including a semiconductor pillar extending in a direction perpendicular to a substrate, the method of manufacturing including:

providing a substrate, and forming a semiconductor column of the at least one transistor, wherein the semiconductor column extends along the direction perpendicular to the substrate and comprises a channel region and a second region arranged on one side of the channel region facing the substrate;

forming a bit line in contact with the second region;

sequentially forming a gate insulating layer surrounding a sidewall of the channel region and a gate electrode surrounding the sidewall of the gate insulating layer;

performing epitaxial growth on the surface of one side of the semiconductor column away from the substrate to form a first region; the first region includes two end portions and an intermediate portion located between the two end portions in a direction perpendicular to the substrate, and orthographic projections of the two end portions are located within orthographic projections of the intermediate portion on a plane parallel to the substrate.

In some embodiments, after the first region is formed by epitaxial growth on the surface of the semiconductor pillar on the side away from the substrate, the method further includes:

An insulating layer is formed on the side of the gate electrode away from the substrate, wherein the insulating layer is filled between adjacent first areas and is provided with an air gap.

In some embodiments, the forming the semiconductor pillar of the at least one transistor extending in a direction perpendicular to the substrate includes:

etching the substrate to form a plurality of bit line isolation grooves extending along a second direction and a plurality of word line isolation grooves extending along a first direction so as to form semiconductor columns of the at least one transistor, wherein the depth of the bit line isolation grooves along the direction perpendicular to the substrate is larger than the depth of the word line isolation grooves along the direction perpendicular to the substrate, the first direction and the second direction are intersected, the ratio of the depth of the bit line isolation grooves along the direction perpendicular to the substrate to the width of the bit line isolation grooves along the direction parallel to the substrate and perpendicular to the second direction is 4:1 to 6:1, and the ratio of the depth of the word line isolation grooves along the direction perpendicular to the substrate to the width of the word line isolation grooves along the direction parallel to the substrate and perpendicular to the first direction is 2:1 to 4:1.

Embodiments of the present disclosure include a semiconductor device, a method of manufacturing the same, and an electronic apparatus, the semiconductor device including: at least one transistor, bit line disposed on the substrate; the transistor includes: the semiconductor column comprises a channel region, a first region and a second region, wherein the first region and the second region are respectively arranged on two sides of the channel region, the second region is arranged on one side of the channel region, which faces the substrate, the bit line is in contact with the second region, the first region comprises two end parts and a middle part, the middle part is arranged between the two end parts, along the direction perpendicular to the substrate, and on a plane parallel to the substrate, the orthographic projection of the two end parts is positioned in the orthographic projection of the middle part. According to the scheme provided by the embodiment, the first area is arranged as the orthographic projection of the end part and is positioned in the orthographic projection of the middle part, and is generated in an epitaxial growth mode instead of a conventional mode of etching on the substrate, so that the first area is not needed to be considered when the isolation groove is etched in the process of forming the semiconductor column, the depth-to-width ratio of the isolation groove can be reduced, the process difficulty is reduced, the possibility of leaving slits and holes in filling is reduced, and the device performance is improved.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities particularly pointed out in the specification and the appended drawings.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the technical aspects of the present disclosure, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present disclosure and together with the embodiments of the disclosure, and not constitute a limitation of the technical aspects.

Fig. 1 is a schematic plan view of a semiconductor device according to an embodiment;

FIG. 2 is a cross-sectional view of the semiconductor device of FIG. 1 taken along the aa' direction;

fig. 3 is a cross-sectional view of the semiconductor device of fig. 1 along the cc' direction;

FIG. 4A is a cross-sectional view of an embodiment of the aa' direction after forming semiconductor pillars and bit lines;

FIG. 4B is a cross-sectional view of the bb' direction after formation of semiconductor pillars and bit lines, according to one embodiment;

FIG. 4C is a cross-sectional view of the cc' direction after formation of semiconductor pillars and bit lines, according to one embodiment;

FIG. 4D is a cross-sectional view of an embodiment after formation of semiconductor pillars and bit lines in the dd' direction;

FIG. 5A is a cross-sectional view of an embodiment of a second insulating layer formed in the aa' direction;

FIG. 5B is a cross-sectional view of the bb' direction after forming a second insulating layer according to one embodiment;

FIG. 5C is a cross-sectional view in the cc' direction after formation of a second insulating layer according to one embodiment;

FIG. 5D is a cross-sectional view taken along dd' after formation of a second insulating layer according to one embodiment;

FIG. 6A is a cross-sectional view in the aa' direction after exposing the channel region, according to one embodiment;

FIG. 6B is a cross-sectional view in the bb' direction after exposing the channel region, as provided by one embodiment;

FIG. 6C is a cross-sectional view in the cc' direction after exposing the channel region, as provided by one embodiment;

FIG. 6D is a cross-sectional view in the dd' direction after exposing the channel region, as provided by one embodiment;

FIG. 7A is a cross-sectional view of an embodiment of a sacrificial layer formed in the aa' direction;

FIG. 7B is a cross-sectional view of the bb' direction after formation of the sacrificial layer according to one embodiment;

FIG. 7C is a cross-sectional view of the cc' direction after formation of the sacrificial layer, according to one embodiment;

FIG. 7D is a cross-sectional view taken along the dd' direction after formation of the sacrificial layer, according to one embodiment;

FIG. 8A is a cross-sectional view in the aa' direction after forming a second spacer according to one embodiment;

FIG. 8B is a cross-sectional view of the bb' direction after forming a second spacer according to one embodiment;

FIG. 8C is a cross-sectional view in the cc' direction after formation of a second separator layer according to one embodiment;

FIG. 8D is a cross-sectional view taken in the dd' direction after formation of a second isolation layer according to one embodiment;

FIG. 9A is a cross-sectional view of an embodiment of the second spacer layer after etching in the aa' direction;

FIG. 9B is a cross-sectional view of the bb' direction after etching the second spacer layer according to one embodiment;

FIG. 9C is a cross-sectional view of the cc' direction after etching the second spacer layer according to one embodiment;

FIG. 9D is a cross-sectional view of the dd' direction after etching the second isolation layer according to one embodiment;

FIG. 10A is a cross-sectional view in the aa' direction after exposing the channel region, according to one embodiment;

FIG. 10B is a cross-sectional view in the bb' direction after exposing the channel region, as provided by one embodiment;

FIG. 10C is a cross-sectional view in the cc' direction after exposing the channel region, as provided by one embodiment;

FIG. 10D is a cross-sectional view in the dd' direction after exposing the channel region, as provided by one embodiment;

FIG. 11A is a cross-sectional view of an embodiment of a gate insulating layer formed in the aa' direction;

FIG. 11B is a cross-sectional view of the bb' direction after forming a gate insulation layer according to one embodiment;

FIG. 11C is a cross-sectional view of the cc' direction after forming a gate insulation layer according to one embodiment;

FIG. 11D is a cross-sectional view of the gate insulating layer formed in the dd' direction according to one embodiment;

FIG. 12A is a cross-sectional view in the aa' direction after forming a gate electrode according to one embodiment;

FIG. 12B is a cross-sectional view of the bb' direction after forming a gate electrode according to one embodiment;

FIG. 12C is a cross-sectional view in the cc' direction after formation of a gate electrode according to one embodiment;

FIG. 12D is a cross-sectional view taken in the dd' direction after formation of the gate electrode according to one embodiment;

FIG. 13A is a cross-sectional view in the aa' direction after forming the first region according to one embodiment;

FIG. 13B is a cross-sectional view of the bb' direction after forming the first region according to one embodiment;

FIG. 13C is a cross-sectional view of the cc' direction after formation of the first region according to one embodiment;

FIG. 13D is a cross-sectional view taken in the dd' direction after formation of the first region, as provided in one embodiment;

FIG. 14A is a cross-sectional view in the aa' direction after forming a third spacer according to one embodiment;

FIG. 14B is a cross-sectional view of the bb' direction after formation of a third spacer layer according to one embodiment;

FIG. 14C is a cross-sectional view of the cc' direction after formation of a third separator layer according to one embodiment;

FIG. 14D is a cross-sectional view taken in the dd' direction after formation of a third spacer layer according to one embodiment;

FIG. 15A is a cross-sectional view of an embodiment of a third insulating layer formed in the aa' direction;

FIG. 15B is a cross-sectional view of the bb' direction after forming a third insulating layer according to one embodiment;

FIG. 15C is a cross-sectional view of the cc' direction after formation of a third insulating layer according to one embodiment;

fig. 15D is a cross-sectional view of the dd' direction after forming the third insulating layer according to one embodiment;

FIG. 16A is a cross-sectional view of an embodiment of the third spacer layer after etching in the aa' direction;

FIG. 16B is a cross-sectional view of the bb' direction after etching the third spacer according to one embodiment;

FIG. 16C is a cross-sectional view of the cc' direction after etching the third spacer layer according to one embodiment;

FIG. 16D is a cross-sectional view of an embodiment of a dd' direction after etching the third spacer;

fig. 17 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The embodiments of the present disclosure and features in the embodiments may be arbitrarily combined with each other without collision.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs.

Embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, the shapes and sizes of the various components in the drawings do not reflect true proportions. Furthermore, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or the numerical values shown in the drawings.

The ordinal numbers of "first", "second", "third", etc. in the present disclosure are provided to avoid intermixing of constituent elements, and do not denote any order, quantity, or importance.

In the present disclosure, for convenience, terms such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe positional relationships of the constituent elements with reference to the drawings, only for convenience in describing the present specification and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the respective constituent elements are described. Therefore, the present invention is not limited to the words described in the disclosure, and may be replaced as appropriate.

In this disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly, unless otherwise specifically indicated and defined. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.

In this disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region through which current mainly flows.

In the present disclosure, "parallel" refers to a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, for example, and thus, a state in which the angle is-5 ° or more and 5 ° or less is also included. The term "vertical" refers to a state in which an angle formed by two straight lines is 80 ° or more and 100 ° or less, for example, and thus includes a state in which an angle is 85 ° or more and 95 ° or less.

The term "the front projection of B is within the range of the front projection of a" in this disclosure means that the boundary of the front projection of B falls within the boundary range of the front projection of a.

In the present disclosure, the substrate 1 has two main surfaces, which are an upper surface and a lower surface disposed opposite to each other, respectively, and the upper surface, i.e., the surface provided with the transistor, is parallel to the lower surface of the substrate 1, and the perpendicular to the substrate 1 is perpendicular to the lower surface of the substrate 1. Before the formation of the semiconductor pillars 10, the substrate 1 refers to the entire substrate (including the semiconductor region for manufacturing the semiconductor pillars 10), and after the formation of the semiconductor layer 10, the substrate 1 refers to the region below the transistor in the entire substrate.

In a conventional vertical channel transistor, the total length of a source electrode, a drain electrode and a channel needs to be considered, the depth-width ratio of an isolation trench is large, the subsequent dielectric filling is difficult, the filling process is difficult, and slits are easy to exist, for example, slit residues are easy to exist when filling a bit line isolation trench.

In the embodiment of the disclosure, only one of the source electrode or the drain electrode and the channel length are considered, so that the depth-to-width ratio of the isolation trench can be reduced, the process difficulty is reduced, and the possibility of slit leaving during filling is reduced.

Fig. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present disclosure. Fig. 2 is a sectional view of the semiconductor device shown in fig. 1 along aa 'direction, and fig. 3 is a sectional view of the semiconductor device shown in fig. 1 along cc' direction. As shown in fig. 1, 2 and 3, the semiconductor device provided in this embodiment may include: a plurality of array distributed vertical channel transistors, bit lines 30, disposed on substrate 1, may include: the semiconductor pillar 10 extending in a direction perpendicular to the substrate 1, the semiconductor pillar 10 having a main surface which is a side surface or a side wall, and an end portion which is a tip of the semiconductor pillar 10. The semiconductor column 10 is formed by etching a trench in a silicon substrate to form a part and forming the other part by epitaxy, so that the other end of the semiconductor column 10 is connected with the substrate 1 as a unitary structure.

The semiconductor pillar 10 may include a channel region 11 and a first region 12 and a second region 13 disposed on both sides of the channel region 11, respectively, the second region 13 disposing the channel region 11 toward the substrate 1 side; the first region 12, the channel region 11, and the second region 13 are sequentially arranged along the extension direction of the semiconductor pillar 10. It can be understood that the regions near both ends of the semiconductor pillar 10 are a first region 12 and a second region 13, the region between the first region 12 and the second region 13 is a channel region 11, and the channel region 11 can be substantially distinguished from the first region 12 and the second region 13 by the position of the gate electrode, or can be substantially distinguished from the channel region 11 by the degree of conduction of the first region 12 and the second region 13 being different from that of the channel region 11.

The second region 13 is located at the bottom end of the semiconductor pillar 10, and the first region 12 is located at the top end of the semiconductor pillar 10. The bit line 30 is buried between the substrate 1 and the transistor and is in contact with the second region 13; in a direction perpendicular to the substrate 1, the first region 12 comprises two end portions and a middle portion between the two end portions, the orthographic projection of the two end portions being located within the orthographic projection of the middle portion on a plane parallel to the substrate 1.

According to the scheme provided by the embodiment, the front projection of the first area is arranged as the end part and is positioned in the front projection of the middle part, the first area is not formed by a conventional method of forming the semiconductor column by etching on the substrate, but is formed by epitaxial growth on the top end of the semiconductor column, so that the first area is not needed to be considered when the isolation groove is etched in the process of forming the semiconductor column, namely, the height of the first area is not needed to be calculated in the height range of the semiconductor column, therefore, the depth-to-width ratio of the isolation groove can be reduced, the process difficulty is further reduced, the possibility of leaving slits and holes in filling is reduced, and the device performance is improved.

The first region 12 and the second region 13 may be regions in which the semiconductor pillar 10 is doped with impurities, and in an embodiment, the conductivity type of the first region 12 and the second region 13 may be n-type or p-type. The first region 12 may be a source region, the second region 13 may be a drain region, or the first region 12 may be a drain region, and the second region 13 may be a source region.

In an exemplary embodiment, the semiconductor pillars 10 extending in a direction perpendicular to the substrate 1 may be understood as extending only in a direction perpendicular to the substrate 1 as a whole, and the morphology of the sidewalls of the semiconductor pillars 10 is not limited.

In an exemplary embodiment, the bulk material of the semiconductor pillars 10 may be consistent with the bulk material of the substrate 1, such as silicon material.

In an exemplary embodiment, the channel region 11 may have substantially the same size and shape at different locations in cross-section in a direction parallel to the substrate 1. It will be appreciated that the sidewall of the channel region 11 is a curved surface with a continuous smooth surface, and the cross-sections at different locations of the curved surface are similar in shape, but may vary in size, for example, in some embodiments, the cross-sectional area of the channel region 11 near the top end is smaller than the cross-sectional area away from the top end.

In an exemplary embodiment, the dimensions and shape of the second region 13 at different locations in a cross section parallel to the direction of the substrate 1 may be substantially the same.

In an exemplary embodiment, the orthographic projection of the channel region 11 may be located within the orthographic projection of the first region 12 in a plane parallel to the substrate 1. In this embodiment, the first region 12 may be formed by epitaxial growth on top of the channel region 11, such that the orthographic projection of the channel region 11 is located within the orthographic projection of the first region 12.

In an exemplary embodiment, the cross section of the first region 12 may include a hexagon in a direction perpendicular to the substrate 1. That is, the cross-section of the epitaxially grown first region 12 may exhibit a hexagonal shape. The first region 12 may be a hexahedron.

In an exemplary embodiment, the transistor may further include a gate electrode 21, and the gate electrode 21 may surround the channel region 11 of the sidewall of the semiconductor pillar 10.

In an exemplary embodiment, the transistor may further include a gate insulating layer 14 surrounding sidewalls of the semiconductor pillar 10, the gate insulating layer 14 being located between the gate electrode 21 and the semiconductor pillar 10 to insulate the gate electrode 21 from the semiconductor pillar 10.

In an exemplary embodiment, the semiconductor device may be a memory array, and the memory array may include a plurality of transistors respectively distributed along a first direction X and a second direction Y, a plurality of word lines 20 extending along the first direction X, and a plurality of bit lines 30 extending along the second direction Y, gate electrodes 21 of transistors of the same row distributed along the first direction X are connected to form one word line 20, and second regions 13 of transistors of the same column distributed along the second direction Y are connected to the same bit line 30. The first direction X and the second direction Y may intersect. In an exemplary embodiment, the first direction X and the second direction Y may be perpendicular.

In an exemplary embodiment, the first direction X may be parallel to the substrate 1, and the second direction Y may be parallel to the substrate 1.

In an exemplary embodiment, the plurality of word lines 20 may be spaced apart along the second direction Y, and the plurality of bit lines 30 may be spaced apart along the first direction X.

In an exemplary embodiment, the semiconductor device may further include bit line isolation trenches T1 extending in the second direction Y disposed between adjacent bit lines 30, the bit line isolation trenches T1 having a depth D in a direction perpendicular to the substrate 1 _BL The ratio of the width W1 of the bit line isolation trench T1 parallel to the substrate 1 and perpendicular to the second direction Y may be 4:1 to 6:1. In the technical scheme of forming the first region 12, the channel region 11 and the second region 13 by etching, the aspect ratio of the bit line isolation trench T1 is 6:1 to 10:1, compared with the scheme, the aspect ratio of the bit line isolation groove T1 in the embodiment is greatly reduced, the etching process difficulty is reduced, the subsequent filling process difficulty is also reduced, and slits and the like are not easy to form. Wherein, the depth D of the bit line isolation trench T1 _BL The etching depth of the bit line isolation groove T1 is along the direction vertical to the substrate 1; the width W1 of the bit line isolation trench T1 is a width of the bit line isolation trench T1 along a direction parallel to the substrate 1 and perpendicular to the extending direction of the bit line isolation trench T1 (in this embodiment, the extending direction of the bit line isolation trench T1 is the second direction Y), and the width W1 may be a maximum width or an average width of the bit line isolation trench T1 along a direction parallel to the substrate 1 and perpendicular to the extending direction of the bit line isolation trench T1, and the like.

In an exemplary embodiment, the semiconductor device may further include word line isolation trenches T2 extending in the first direction X disposed between adjacent word lines 20, the word line isolation trenches T2 having a depth D in a direction perpendicular to the substrate 1 _WL The ratio of the width W2 of the word line isolation groove T2 along the direction parallel to the substrate 1 and perpendicular to the first direction X (the first direction X is the extending direction of the word line isolation groove T2) may be 2:1 to 4:1. By engravingIn the technical scheme of etching the first region 12, the channel region 11 and the second region 13, the aspect ratio of the word line isolation trench is 4:1 to 6:1, compared with the scheme, the aspect ratio of the word line isolation groove T2 in the embodiment is greatly reduced, the etching process difficulty is reduced, the subsequent filling process difficulty is also reduced, and slits and the like are not easy to form. Wherein, the depth D of the word line isolation groove T2 _WL The etching depth of the word line isolation groove T2 is along the direction vertical to the substrate 1; the width W2 of the word line isolation trench T2 is a width of the bit line isolation trench T1 along an extending direction parallel to the substrate 1 and perpendicular to the word line isolation trench T2, and the width W2 may be a maximum width or an average width of the word line isolation trench T2 along an extending direction parallel to the substrate 1 and perpendicular to the word line isolation trench T2, or the like.

In an exemplary embodiment, the semiconductor device may further include: a third insulating layer 5 is arranged on the side of the gate electrode 21 remote from the substrate 1, filling between adjacent first regions 12, said third insulating layer 5 may be provided with a gas gap 50. According to the scheme provided by the embodiment, the gas gap is arranged, and the dielectric constant and the capacitance of the gas gap are small, so that the resistance-capacitance retardation of the transistor can be reduced.

In an exemplary embodiment, the third insulating layer 5 may be formed by filling with a material having poor fluidity, such as phosphosilicate glass, etc., so as to realize the gas gap 50. However, the embodiment of the present disclosure is not limited thereto, and the gas gap 50 may not be provided, that is, the third insulating layer 5 may be formed by filling with a material having better fluidity, so that the formation of the gas gap is avoided.

In an exemplary embodiment, the gas gap 50 between adjacent first regions 12 may be one.

In an exemplary embodiment, the gas in the gas gap 50 may be air.

In an exemplary embodiment, the third insulating layer 5 may include a first surface close to the substrate 1 and a second surface far from the substrate 1, and a distance between the gas gap 50 and the first surface may be smaller than a distance between the gas gap 50 and the second surface in a direction perpendicular to the substrate 1. That is, the gas gap 50 is provided on the side of the third insulating layer 5 close to the substrate 1. In the direction perpendicular to the substrate 1, since the first regions 12 form structures with small intermediate ends, structures with large intermediate ends are formed between adjacent first regions 12, and when the third insulating layer 5 is formed to fill the region between adjacent first regions 12, a gas gap is easily formed on the side close to the substrate 1.

In an exemplary embodiment, the semiconductor device may further include: a third isolation layer 53, the third isolation layer 53 being disposed between the third insulation layer 5 and the first region 12, and between the third insulation layer 5 and the gate electrode 21. The third isolation layer 53 covers the gate electrode 21 and the first region 12, and protects the gate electrode 21 and the first region 12. The third isolation layer 53 may be formed to cover the continuous surfaces of the adjacent first region 12 and gate electrode 21, i.e., after forming the gate electrode 21 and the first region 12, a third isolation layer film is deposited to form the third isolation layer 53, thereby realizing protection of the first region 12 and the gate electrode 21.

The transistor may be filled with an insulating material or the like, such as a first isolation layer 51 disposed in the word line isolation trench T2 to cover the second region 13 and the bit line 30, a first insulation layer 2 filled in the bit line isolation trench T1, a second insulation layer 3 filled in the word line isolation trench T2, and the like.

The technical scheme of this embodiment will be further described below through the manufacturing process of the semiconductor device of this embodiment. In this embodiment, the deposition may be performed by known processes such as sputtering, evaporation, chemical vapor deposition, etc., the coating may be performed by known coating processes, and the etching may be performed by known methods, which are not particularly limited herein. In the description of the present embodiment, it is to be understood that "thin film" refers to a thin film made by depositing or coating a certain material on a substrate.

1) Forming a semiconductor pillar 10 and a bit line 30;

the forming of the semiconductor pillar 10 and the bit line 30 may include:

a plurality of bit lines extending in a second direction Y are formed on the substrate 1Isolation trench T1, bit line isolation trench T1 having depth D _BL The method comprises the steps of carrying out a first treatment on the surface of the The plurality of bit line isolation grooves T1 are distributed at intervals along the first direction X;

depositing a first insulating film on the substrate 1 to form a first insulating layer 2, wherein the first insulating layer 2 fills the bit line isolation groove T1;

a plurality of word line isolation trenches T2 extending in the first direction X are formed, and the plurality of word line isolation trenches T2 may be spaced apart in the second direction Y. At this time, a plurality of semiconductor pillars 10 are formed on the substrate 1 through the bit line isolation trench T1 and the word line isolation trench T2, and the plurality of semiconductor pillars 10 may form channel regions 11 and second regions 13 of a plurality of transistors, respectively; according to the scheme provided by the embodiment, the semiconductor column 10 only needs to form the channel region 11 and the second region 13, and the first region 12 is not needed to be formed, so that the depth of the semiconductor column 10 along the direction vertical to the substrate can be reduced, the depth-to-width ratio of the bit line isolation groove T1 and the word line isolation groove T2 is reduced, the process difficulty of etching and filling holes and the like is reduced, and the possibility of leaving slits in filling is reduced.

Etching the substrate 1 to form a bit line groove T3, wherein the bit line groove T3 extends along a second direction Y, and the bit line groove T3 exposes a second region 13 of the semiconductor column;

a connection layer film and a conductive film are sequentially deposited on the substrate 1 forming the above structure, and the connection layer film and the conductive film outside the bit line groove T3 are etched to form the bit line 30.

A first isolation layer film is deposited on the substrate 1 having the above-described structure to form a first isolation layer 51, as shown in fig. 4A, 4B, 4C and 4D, wherein fig. 4A is a sectional view in the aa 'direction, fig. 4B is a sectional view in the bb' direction, fig. 4C is a sectional view in the cc 'direction, and fig. 4D is a sectional view in the dd' direction.

In an exemplary embodiment, the connection layer film may be, for example, titanium (Ti), cobalt (Co), nickel (Ni), or nickel platinum (NiPt), etc., and the subsequent connection layer film may be silicided by a silicide (metal silicide) process, such as forming titanium disilicide (TiSi) ₂ ) Cobalt disilicide (CoSi) ₂ ) And nickel platinum silicide (NiPtSi) or the like, thereby reducing contact electricity between the bit line 30 and the second region 13Resistance.

In an exemplary embodiment, the conductive film may include an adhesion sub-layer including but not limited to TiN and a conductive sub-layer including but not limited to W, i.e., tiN may be deposited first to form the adhesion sub-layer and then W may be deposited to form the conductive sub-layer, which may enhance adhesion of W to other film layers. The conductive sub-layer fills the bit line groove T3.

In an exemplary embodiment, the tie layer film and the adhesion sub-layer may be deposited by atomic layer deposition (Atomic Layer Deposition, ALD).

In an exemplary embodiment, the conductive sub-layer may be deposited using physical vapor deposition (Physical Vapor Deposition, PVD).

In an exemplary embodiment, etching away the connection layer film and the conductive film outside the bit line groove T3 to form the bit line 30 may include: etching the connecting layer film and the conductive film back by adopting dry etching to remove the connecting layer film and the conductive film between the semiconductor columns 10 and keep the connecting layer film and the conductive film in the bit line groove T3; and removing the residual connecting layer film and conductive film outside the bit line groove T3 by wet etching, byproducts of dry etching and the like.

In an exemplary embodiment, the substrate 1 may be a semiconductor substrate; such as at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

In an exemplary embodiment, the first insulating film includes, but is not limited to, silicon oxide (SiOx).

In an exemplary embodiment, the first isolation layer film may be a nitride of silicon, such as silicon nitride (SiN), or the like.

2) Forming a second insulating layer 3;

the forming of the second insulating layer 3 may include: and performing SOD coating after depositing a third insulating film by ALD, performing planarization after annealing, and forming a second insulating layer 3, wherein the second insulating layer 3 is flush with the first insulating layer 51, and the second insulating layer 3 fills the word line isolation groove T2, as shown in fig. 5A, 5B, 5C and 5D, wherein fig. 5A is an aa 'direction cross-sectional view, fig. 5B is a bb' direction cross-sectional view, fig. 5C is a cc 'direction cross-sectional view, and fig. 5D is a dd' direction cross-sectional view.

In an exemplary embodiment, the third insulating film may be an oxide of silicon, such as silicon dioxide (SiO ₂ )。

3) Exposing the channel region 11 by etching;

the exposing of the channel region 11 by etching may include: the second insulating layer 3 is etched back to a predetermined height, and the first insulating layer 51 not covered by the second insulating layer 3 is wet etched to remove the first insulating layer, as shown in fig. 6A, 6B, 6C and 6D, wherein fig. 6A is a sectional view in aa 'direction, fig. 6B is a sectional view in bb' direction, fig. 6C is a sectional view in cc 'direction, and fig. 6D is a sectional view in dd' direction.

In the related technical scheme, two steps of wet etching are used, the length of a source electrode is defined by the first step of wet etching, siN is filled and the cc' direction is opened, the length of a channel is defined by the second step of wet etching, the precision of the two steps of wet etching and the previous process is required to be strictly controlled, and otherwise, the ratio of the length of the source electrode to the drain electrode to the channel is influenced; in addition, the profile of SiN after etching needs to be strictly considered in the first wet etching, once the shape of the large top and the small bottom (big end) is formed, slits or even holes are generated in the subsequent SiN deposition, the slits or even holes are exposed and enlarged in the second wet etching, and gate electrode materials are filled in the slits or even short circuits of the device. In the embodiment of the disclosure, the channel length can be defined through one-step wet etching, the source and drain electrodes and the channel length are easy to control, the electric leakage and even short circuit caused by the slit or the cavity are avoided, and the yield and the performance of the device can be improved.

4) Forming a sacrificial layer 4

The forming of the sacrificial layer 4 may include: a sacrificial layer film is deposited on the substrate 1 on which the foregoing structure is formed, and the sacrificial layer 4 is formed as shown in fig. 7A, 7B, 7C, and 7D, wherein fig. 7A is a sectional view in the aa 'direction, fig. 7B is a sectional view in the bb' direction, fig. 7C is a sectional view in the cc 'direction, and fig. 7D is a sectional view in the dd' direction. A sacrificial layer 4 may be formed on each exposed surface.

In an exemplary embodiment, the sacrificial layer film may be an oxide of silicon, such as SiO ₂ 。

5) Forming a second isolation layer 52;

the forming of the second isolation layer 52 may include: a second spacer film is deposited on the substrate 1 having the above-described structure to form a second spacer 52, as shown in fig. 8A, 8B, 8C and 8D, wherein fig. 8A is a sectional view in the aa 'direction, 8B is a sectional view in the bb' direction, 8C is a sectional view in the cc 'direction, and 8D is a sectional view in the dd' direction. The second isolation layer 52 covers the first isolation layer 51 and fills the word line isolation trench T2.

In an exemplary embodiment, the second isolation layer film may be a nitride of silicon, such as silicon nitride (SiN), or the like.

6) The second isolation layer 52 is etched such that the surface of the second isolation layer 52 away from the substrate 1 is flush with the surface of the sacrificial layer 4 away from the substrate 1, as shown in fig. 9A, 9B, 9C and 9D, wherein fig. 9A is an aa 'direction cross-sectional view, fig. 9B is a bb' direction cross-sectional view, fig. 9C is a cc 'direction cross-sectional view, and fig. 9D is a dd' direction cross-sectional view.

7) The first insulating layer 2 and the sacrificial layer 4 are etched to expose the channel region 11, as shown in fig. 10A, 10B, 10C, and 10D, wherein fig. 10A is an aa 'direction cross-sectional view, 10B is a bb' direction cross-sectional view, 10C is a cc 'direction cross-sectional view, and 10D is a dd' direction cross-sectional view.

The etching selectivity of the first insulating layer 2, the sacrificial layer 4 and the second insulating layer 52 is controlled such that the second insulating layer 52 is flush with the top of the semiconductor pillars 10 or the second insulating layer 52 is slightly higher than the top of the semiconductor pillars 10 when the first insulating layer 2, the sacrificial layer 4 are etched in place.

8) Forming a gate insulating layer 14;

the forming of the gate insulating layer 14 may include: a gate insulating film may be deposited first and then grown by an In-situ vapor generation (In-Situ Steam Generation, ISSG) method to form the gate insulating layer 14, as shown In fig. 11A, 11B, 11C and 11D, wherein fig. 11A is an aa 'direction cross-sectional view, fig. 11B is a bb' direction cross-sectional view, fig. 11C is a cc 'direction cross-sectional view, and fig. 11D is a dd' direction cross-sectional view. The substrate can be consumed less by depositing a layer of gate insulating film, and the compactness can be improved and the impurities can be reduced by the gate insulating film generated in an in-situ water vapor generation mode.

The gate insulating layer 14 surrounds the semiconductor pillar 10, and may insulate a gate electrode 21 formed later from the semiconductor pillar 10.

In an exemplary embodiment, the gate insulating film may be a High-K dielectric material, such as SiO ₂ Etc.

9) Forming a gate electrode 21

The forming of the gate electrode 21 may include: a gate electrode film is deposited and planarized on the substrate 1 having the above-described structure to form a gate electrode 21, as shown in fig. 12A, 12B, 12C, and 12D, wherein fig. 12A is a sectional view in the aa 'direction, fig. 12B is a sectional view in the bb' direction, fig. 12C is a sectional view in the cc 'direction, and fig. 12D is a sectional view in the dd' direction.

In an exemplary embodiment, the gate electrode film may include an adhesion sub-layer such as TiN and a conductive sub-layer such as W.

In an exemplary embodiment, the method may further include: the exposed surface of the gate electrode 21 is nitrided by a remote plasma nitridation (Remote Plasma Nitridation, RPN) process.

10 Forming the first region 12

The forming of the first region 12 may include: epitaxial growth is performed on top of the semiconductor pillar 10 to form a first region 12 on the side of the top of the semiconductor pillar 10 away from the substrate 1, as shown in fig. 13A, 13B, 13C and 13D, wherein fig. 13A is an aa 'direction cross-sectional view, fig. 13B is a bb' direction cross-sectional view, fig. 13C is a cc 'direction cross-sectional view, and fig. 13D is a dd' direction cross-sectional view. The epitaxial growth is only carried out at the exposed place of the silicon, and the method has the characteristics of selectivity and self-alignment.

In an exemplary embodiment, before the epitaxial growth, the method further includes: removing surface contaminants on top of semiconductor column 10 and naturally oxidized SiO on top of semiconductor column 10 ₂ Etc.

In an exemplary embodiment, the first region 12 may include two end portions and a middle portion located therebetween in a direction perpendicular to the substrate 1, and orthographic projections of the two end portions are located within orthographic projections of the middle portion on a plane parallel to the substrate 1. The different crystal phases of the monocrystalline silicon substrate have different growth rates during epitaxy, the shape of the first region 12 being determined thereby.

In an exemplary embodiment, the cross section of the first region 12 may include a hexagon in a direction perpendicular to the substrate 1.

According to the scheme provided by the embodiment, the first region 12 is formed in an epitaxial growth mode, so that the length of the first region 12 (the etched semiconductor column does not comprise the first region 12) is not needed to be considered when the bit line isolation groove T1 and the word line isolation groove T2 are etched, the depth of the bit line isolation groove T1 and the word line isolation groove T2 can be reduced, the depth-to-width ratio can be reduced under the condition that the widths of the bit line isolation groove T1 and the word line isolation groove T2 are unchanged, the etching process difficulty and the subsequent filling process difficulty are reduced, the possibility of slit leaving is reduced, and the device performance is improved.

11 Forming a third isolation layer 53

The forming of the third isolation layer 53 may include: a third separator film is deposited on the substrate 1 having the above-described structure to form a third separator 53, as shown in fig. 14A, 14B, 14C, and 14D, wherein fig. 14A is a sectional view in the aa 'direction, fig. 14B is a sectional view in the bb' direction, fig. 14C is a sectional view in the cc 'direction, and fig. 14D is a sectional view in the dd' direction. The third isolation layer 53 may cover exposed areas of the gate electrode 21 and the first area 12, protect the gate electrode 21 and the first area 12, and isolate electrical properties.

In an exemplary embodiment, the third isolation layer film may be a nitride of silicon, such as silicon nitride (SiN), or the like.

12 Forming a third insulating layer 5

The forming of the third insulating layer 5 may include: a third insulating layer 5 is formed by depositing and planarizing a third insulating layer film on the substrate 1 having the above-described structure, as shown in fig. 15A, 15B, 15C, and 15D, wherein fig. 15A is a sectional view in aa 'direction, 15B is a sectional view in bb' direction, 15C is a sectional view in cc 'direction, and 15D is a sectional view in dd' direction.

In an exemplary embodiment, the third insulating layer 5 is provided with at least one gas gap 50. The dielectric constant of the gas gap is small, the capacitance is small, and the resistance-capacitance retardation of the transistor can be reduced. The embodiments of the present disclosure are not limited thereto and the third insulating layer 5 may not be provided with the gas gap 50. That is, a material having a good fluidity can be used as the third insulating film, so that formation of a gas gap can be avoided.

In an exemplary embodiment, the gas gap 50 is disposed between adjacent second regions 12. The region between the adjacent second regions 12 has a shape with both ends wide and a narrow middle in a direction perpendicular to the substrate 1, and is liable to form an air gap on a side close to the substrate 1. The gas gap 50 may be naturally formed at the time of depositing the third insulating film.

In an exemplary embodiment, the third insulating film is, for example, phosphosilicate glass (Phospho Silicate Glass, PSG), but the practice of the present disclosure is not limited thereto, and other materials may be used, with PSG being advantageous for forming the gas gap 50.

13 The third isolation layer 53 is etched to expose the surface of the side of the first region 12 away from the substrate 1 for subsequent manufacturing processes, as shown in fig. 16A, 16B, 16C and 16D, wherein fig. 16A is an aa 'direction cross-sectional view, fig. 16B is a bb' direction cross-sectional view, fig. 16C is a cc 'direction cross-sectional view, and fig. 16D is a dd' direction cross-sectional view.

The embodiment of the disclosure also provides electronic equipment, which comprises the semiconductor device of any one of the previous embodiments. The electronic device may be: storage, smart phones, computers, tablet computers, artificial intelligence devices, wearable devices or mobile power sources, etc. The storage device may include, without limitation, memory in a computer, and the like.

Fig. 17 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. As shown in fig. 17, the present embodiment provides a manufacturing method of a semiconductor device including at least one transistor including a semiconductor pillar extending in a direction perpendicular to a substrate, the manufacturing method including:

step 1701, providing a substrate, forming a semiconductor column of the at least one transistor extending along a direction perpendicular to the substrate, wherein the semiconductor column comprises a channel region and a second region arranged on one side of the channel region facing the substrate;

step 1702, forming a bit line in contact with the second region;

a step 1703 of sequentially forming a gate insulating layer surrounding a sidewall of the channel region and a gate electrode surrounding a sidewall of the gate insulating layer;

step 1704, performing epitaxial growth on the surface of the semiconductor column, which is far away from the substrate side, to form a first region; the orthographic projection of the channel region is located within the orthographic projection of the first region on a plane parallel to the substrate, the first region including two end portions and an intermediate portion located between the two end portions in a direction perpendicular to the substrate, the orthographic projections of the two end portions being located within the orthographic projection of the intermediate portion on a plane parallel to the substrate.

According to the manufacturing method of the semiconductor device, the first region is formed through epitaxial growth, the advantages of selectivity and self alignment are achieved, in addition, the depth-to-width ratio of an etched isolation groove in the process of forming a semiconductor column can be reduced, the process difficulty is reduced, the possibility of slit leaving is reduced, the channel length is not required to be defined through two-step wet etching, the problem of electric leakage or short circuit of the device caused by hollow slits and the like caused by two-step wet etching is avoided, the channel length can be defined through one-step wet etching, and compared with a two-step wet etching implementation mode, the channel length, the source region and the drain region are easy to control.

In an exemplary embodiment, after the surface of the semiconductor pillar on the side away from the substrate is epitaxially grown to form the first region, the method further includes:

an insulating layer is formed on the side of the gate electrode away from the substrate, wherein the insulating layer is filled between adjacent first areas and is provided with an air gap. According to the scheme provided by the embodiment, the resistance-capacitance retardation of the transistor can be reduced by forming the gas gap.

In an exemplary embodiment, the forming the semiconductor pillar of the at least one transistor extending in a direction perpendicular to the substrate includes:

Etching the substrate to form a plurality of bit line isolation grooves extending along a second direction and a plurality of word line isolation grooves extending along a first direction so as to form semiconductor columns of the at least one transistor, wherein the depth of the bit line isolation grooves along the direction perpendicular to the substrate is larger than the depth of the word line isolation grooves along the direction perpendicular to the substrate, the first direction and the second direction are intersected, the ratio of the depth of the bit line isolation grooves along the direction perpendicular to the substrate to the width of the bit line isolation grooves along the direction parallel to the substrate and perpendicular to the second direction is 4:1 to 6:1, and the ratio of the depth of the word line isolation grooves along the direction perpendicular to the substrate to the width of the word line isolation grooves along the direction parallel to the substrate and perpendicular to the first direction is 2:1 to 4:1. The scheme provided by the embodiment can realize the low depth-to-width ratio of the word line isolation groove and the bit line isolation groove and reduce the process difficulty.

Although the embodiments of the present invention are described above, the embodiments are only used for facilitating understanding of the present invention, and are not intended to limit the present invention. Any person skilled in the art can make any modification and variation in form and detail without departing from the spirit and scope of the present disclosure, but the scope of the present disclosure is to be determined by the appended claims.

Claims

1. A semiconductor device, comprising: at least one transistor, bit line disposed on the substrate; the transistor includes: the semiconductor column comprises a channel region, a first region and a second region, wherein the first region and the second region are respectively arranged on two sides of the channel region, the second region is arranged on one side of the channel region, which faces the substrate, the bit line is in contact with the second region, the first region comprises two end parts and a middle part, the middle part is arranged between the two end parts, along the direction perpendicular to the substrate, and on a plane parallel to the substrate, the orthographic projection of the two end parts is positioned in the orthographic projection of the middle part.

2. The semiconductor device of claim 1, wherein an orthographic projection of the channel region is located within an orthographic projection of the first region in a plane parallel to the substrate.

3. The semiconductor device of claim 1, wherein a cross-section of the first region comprises a hexagon in a direction perpendicular to the substrate.

4. The semiconductor device of claim 1, wherein the transistor further comprises a gate electrode surrounding a sidewall of the channel region;

5. The semiconductor device according to claim 4, further comprising bit line isolation trenches arranged between adjacent bit lines and extending in a second direction, wherein a ratio of a depth of the bit line isolation trenches in a direction perpendicular to a substrate to a width of the bit line isolation trenches in a direction parallel to the substrate and perpendicular to the second direction is 4:1 to 6:1.

6. The semiconductor device of claim 4, further comprising word line isolation trenches disposed between adjacent word lines extending in a first direction, wherein a ratio of a depth of the word line isolation trenches in a direction perpendicular to the substrate to a width of the word line isolation trenches in a direction parallel to the substrate and perpendicular to the first direction is 2:1 to 4:1.

7. The semiconductor device according to claim 4, further comprising a third insulating layer provided on a side of the gate electrode remote from the substrate, the third insulating layer being filled between adjacent first regions, the third insulating layer being provided with an air gap.

8. The semiconductor device according to claim 7, wherein the third insulating layer includes a first surface close to the substrate and a second surface remote from the substrate, and wherein a distance between the gas gap and the first surface is smaller than a distance between the gas gap and the second surface in a direction perpendicular to the substrate.

9. The semiconductor device according to claim 7, wherein a material of the third insulating layer comprises phosphosilicate glass.

10. The semiconductor device according to claim 7, wherein the semiconductor device further comprises: and a third isolation layer disposed between the third insulation layer and the first region, and between the third insulation layer and the gate electrode.

11. An electronic device comprising the semiconductor device according to any one of claims 1 to 10.

12. A method of manufacturing a semiconductor device, the semiconductor device comprising at least one transistor including a semiconductor pillar extending in a direction perpendicular to a substrate, the method comprising:

forming a bit line in contact with the second region;

13. The method for manufacturing a semiconductor device according to claim 12, wherein after the surface of the semiconductor pillar on a side away from the substrate is epitaxially grown to form the first region, further comprising:

14. The method for manufacturing the semiconductor device according to claim 12 or 13, wherein the forming the semiconductor pillar of the at least one transistor extending in a direction perpendicular to the substrate comprises: