CN117423716A - Back-illuminated semiconductor structure etching method and etching device - Google Patents
Back-illuminated semiconductor structure etching method and etching device Download PDFInfo
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- 238000005530 etching Methods 0.000 title claims abstract description 296
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
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- 239000012528 membrane Substances 0.000 claims description 20
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- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 36
- 125000001424 substituent group Chemical group 0.000 abstract description 28
- 239000010410 layer Substances 0.000 description 34
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- 229910052710 silicon Inorganic materials 0.000 description 10
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 9
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
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- 150000004706 metal oxides Chemical class 0.000 description 3
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- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
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- 238000001179 sorption measurement Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- MGWGWNFMUOTEHG-UHFFFAOYSA-N 4-(3,5-dimethylphenyl)-1,3-thiazol-2-amine Chemical compound CC1=CC(C)=CC(C=2N=C(N)SC=2)=C1 MGWGWNFMUOTEHG-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
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- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 description 1
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- 229910017604 nitric acid Inorganic materials 0.000 description 1
- JCXJVPUVTGWSNB-UHFFFAOYSA-N nitrogen dioxide Inorganic materials O=[N]=O JCXJVPUVTGWSNB-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14698—Post-treatment for the devices, e.g. annealing, impurity-gettering, shor-circuit elimination, recrystallisation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67075—Apparatus for fluid treatment for etching for wet etching
- H01L21/67086—Apparatus for fluid treatment for etching for wet etching with the semiconductor substrates being dipped in baths or vessels
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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Abstract
The invention relates to a back-illuminated semiconductor structure etching method and an etching device, wherein the back-illuminated semiconductor structure is fixed in an etching cavity, so that the bottom surface of a device wafer in the back-illuminated semiconductor structure is contacted with an anode disc in the etching cavity, an etching solution is contacted with a cathode electrode, and voltage is applied to the anode disc and the cathode electrode, so that the bottom surface of the device wafer is activated, nucleophilic substituent groups are generated in the etching solution to react with the bottom surface of the device wafer, and the bottom surface of the device wafer is etched. Meanwhile, the voltage value applied between the anode disk and the cathode electrode and the current value flowing through different areas on the anode disk are controlled to adjust the etching rates of different areas on the bottom surface of the device wafer, and different etching time and etching rates are selected according to the difference value between the thickness values of different areas and the corresponding target values, so that the thickness of all areas reaches the corresponding target values, the accuracy of etching control is improved, and the stability of substrate thinning treatment is ensured.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and in particular, to a backside illuminated semiconductor structure etching method and etching apparatus.
Background
Complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image sensors can be classified into front-illuminated (Front Side Illumination, FSI) and back-illuminated (Back Side Illumination, BSI) complementary metal oxide semiconductor image sensors.
In order to avoid light attenuation by the metal wiring layer, the BSI CMOS image sensor needs to bond the device wafer and the carrier wafer after completing the fabrication of the device wafer, and thin the substrate of the device wafer to reduce the scattering of light by the substrate. In the prior art, a high-selectivity solution is generally adopted to thin the substrate, but the high-selectivity solution is expensive in cost and insufficient in stability, so that how to improve the stability of substrate thinning becomes one of the technical problems to be solved urgently at present.
Disclosure of Invention
Based on this, it is necessary to provide a backside-illuminated semiconductor structure etching method and etching apparatus for solving the problem of weak etching stability in the prior art of thinning a substrate.
In order to achieve the above objective, in one aspect, the present invention provides a back-illuminated semiconductor structure etching method for etching a back-illuminated semiconductor structure fixed in an etching chamber, where the back-illuminated semiconductor structure includes a carrier wafer and a device wafer located on a top surface of the carrier wafer; the top surface of the device wafer is bonded with the top surface of the bearing wafer, the bottom surface of the device wafer is contacted with the anode disc in the etching cavity, and the etching cavity also comprises a cathode electrode positioned right below the anode disc; the etching method comprises the following steps: controlling the voltage value applied between the anode disk and the cathode electrode and the current value flowing through different areas on the anode disk, so that the bottom surface of the device wafer is activated and reacts with nucleophilic substituents generated in etching solution in the etching cavity to adjust the etching rate of the different areas of the bottom surface of the device wafer; and adjusting etching time and/or etching rate of different areas according to the difference value between the thickness values of the different areas of the bottom surface of the device wafer and the corresponding target values.
In one embodiment, the different regions include a center region, a middle region, and an edge region, the middle region surrounding the center region and located between the center region and the edge region; the etching rate of the central area is positively correlated with the value of the flowing current; the etching rate of the middle area is positively correlated with the value of the flowing current; the etching rate of the edge area is positively correlated with the value of the flowing current; adjusting the etching time and/or etching rate of different areas comprises: and changing the current value flowing through the central area, the current value flowing through the middle area and the current value flowing through the edge area, and the etching time of the central area, the etching time of the middle area and the etching time of the edge area.
In one embodiment, the central region, the middle region, and the edge regions are concentric; the central area is circular, and the middle area is annular; the edge region surrounds the middle region and is annular.
In one embodiment, the etching chamber further includes a semi-permeable membrane positioned between the anode disk and the cathode electrode.
In one embodiment, the nucleophilic substituent comprises at least one of hydroxide ion, fluoride ion.
In one embodiment, adjusting the etching time and/or etching rate of the different regions further includes: and continuously measuring thickness values of different areas during etching, and adjusting etching time and/or etching rate according to the thickness values in a feedback manner.
In a second aspect, the present application further provides an etching apparatus for etching a back-illuminated semiconductor structure fixed in an etching cavity, where the back-illuminated semiconductor structure includes a carrier wafer and a device wafer located on a top surface of the carrier wafer; the top surface of the device wafer is bonded with the top surface of the bearing wafer; the etching device comprises: an anode disk, a cathode electrode, and a controller; the anode disc is positioned in the etching cavity, and the bottom surface of the device wafer is contacted with the anode disc; the cathode electrode is positioned in the etching cavity and is positioned right below the anode disc; the controller is electrically connected with the anode disk and the cathode electrode and is configured to: controlling the voltage value applied between the anode disk and the cathode electrode and the current value flowing through different areas on the anode disk, so that the bottom surface of the device wafer is activated and reacts with nucleophilic substituents generated in etching solution in the etching cavity to adjust the etching rate of the different areas of the bottom surface of the device wafer; and adjusting etching time and/or etching rate of different areas according to the difference value between the thickness values of the different areas of the bottom surface of the device wafer and the corresponding target values.
In one embodiment, the etching apparatus further includes: and the bearing device is arranged on the etching cavity and used for fixing the back-illuminated semiconductor structure.
In one embodiment, the etching apparatus further includes: and the thickness sensor is electrically connected with the controller and is used for measuring thickness values of different areas.
In one embodiment, the etching apparatus further includes: a semipermeable membrane positioned in the etching cavity and between the anode disk and the cathode electrode for permeation of nucleophilic substituents; the circulating solution inlet is positioned on the side wall of the etching cavity and is used for inputting etching solution into the etching cavity; the circulating solution outlet is positioned on the side wall of the etching cavity and is used for outputting etching solution in the etching cavity; the circulating solution inlet and the circulating solution outlet are respectively positioned on the same side of the semipermeable membrane, which is away from the anode disc, or the circulating solution inlet is positioned on the side of the semipermeable membrane, which is away from the anode disc, and the circulating solution outlet is positioned on the side of the semipermeable membrane, which is close to the anode disc.
The back-illuminated semiconductor structure etching method and the etching device have the following unexpected beneficial effects:
in the back-illuminated semiconductor structure etching method, the back-illuminated semiconductor structure is fixed in the etching cavity, so that the bottom surface of a device wafer in the back-illuminated semiconductor structure is contacted with the anode disc in the etching cavity, the etching solution is contacted with the cathode electrode, and voltage is applied to the anode disc and the cathode electrode, so that the bottom surface of the device wafer is activated, nucleophilic substituent is generated in the etching solution, the nucleophilic substituent reacts with the bottom surface of the device wafer, and covalent bonds between silicon are replaced by the nucleophilic substituent, so that the bottom surface of the device wafer is etched. Meanwhile, the resistance values of different areas of the anode disk are controlled, so that the current values flowing through the different areas on the anode disk are controlled, the etching time and the etching rate of the different areas of the bottom surface of the device wafer are adjusted, different etching time and etching rate are selected according to the difference value between the thickness values of the different areas and the corresponding target values, so that the reaction degrees of the different areas are different, the thickness values after etching of all the areas reach the corresponding target values, the accuracy of etching control is improved, the stability of thinning treatment of the substrate is ensured, and the uniformity of the thickness of the etched film surface is further ensured.
In the etching device disclosed by the disclosure, the bottom surface of the device wafer is contacted with the anode disk, the cathode electrode is contacted with the etching solution, the voltage value applied between the anode disk and the cathode electrode and the current value flowing through different areas on the anode disk are controlled by the controller, so that the bottom surface of the device wafer is activated, nucleophilic substituent groups are generated by the etching solution, the nucleophilic substituent groups react with silicon on the bottom surface of the device wafer and replace covalent bonds among the silicon, thereby realizing the etching of the bottom surface of the device wafer, and the etching time and the etching rate of different areas are controlled by the controller, thereby realizing the control of the reaction degree of different areas, further enabling the thickness value after etching of all areas to reach the corresponding target value, ensuring the flatness of the etched film surface, and controlling the etching time and the etching rate by the controller, thereby improving the accuracy of etching control.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a backside illuminated semiconductor structure etching method according to one embodiment;
FIG. 2 is a cross-sectional view of a back-illuminated semiconductor structure in step S102 of a back-illuminated semiconductor structure etching method according to one embodiment;
FIG. 3 is a flow chart of a method for etching a backside illuminated semiconductor structure according to another embodiment;
FIG. 4 is a cross-sectional view of a back-illuminated semiconductor structure provided in another embodiment;
FIG. 5 is a schematic diagram of an etching process in a backside illuminated semiconductor structure etching method in one embodiment;
FIG. 6 is a schematic view of different areas of an anode disk in one embodiment;
FIG. 7 is a block diagram of an etching apparatus in one embodiment;
FIG. 8a is a schematic diagram of an etching apparatus according to an embodiment;
FIG. 8b is a schematic diagram of an etching apparatus according to another embodiment;
FIG. 9 is a flow chart of the operation of the thickness sensor in one embodiment.
Reference numerals illustrate:
202. carrying a wafer; 204. a device layer; 206. an epitaxial layer; 208. a substrate; 210. a device wafer; 402. a device substrate; 602. a central region; 604. a middle region; 606. an edge region; 700. etching device; 701. an anode disk; 702. a cathode electrode; 703. a controller; 801. etching the cavity; 802. a carrying device; 803. a back-illuminated semiconductor structure; 805. a brush; 806. a semipermeable membrane; 807. a circulating solution outlet; 809. and a circulating solution inlet.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
Referring to fig. 1 and 2, typically, an HNA solution formed by mixing acetic acid, hydrofluoric acid, and nitric acid is selected to thin the bottom surface of the device wafer 210, and an epitaxial layer 206 is required to serve as an etching stop layer to avoid damaging the device layer 204. The etching process comprises the following steps:
step S101: providing a carrier wafer 202 and a device wafer 210, the device wafer 210 comprising a substrate 208 and an epitaxial layer 206 and a device layer 204 on the front side of the substrate 208;
step S102: bonding the top surface of the device layer 204 to the top surface of the carrier wafer 202;
step S103: removing a main body portion of the substrate 208 along a direction perpendicular to the substrate 208 by Back Grinding (BG) to obtain a residual substrate; the thickness of the body portion is 50% -90% of the thickness of the substrate 208;
step S104: the residual substrate is etched using HNA solution with epitaxial layer 206 as a stop layer.
Wherein, to ensure high selectivity of HNA solution, the epitaxial layer 206 is lightly doped and the substrate 208 is heavily doped. In forming the device layer 204, since the dopant ions between the epitaxial layer 206 and the substrate 208 are affected by thermal diffusion, a transition layer (not shown) having a different doping concentration is formed between the epitaxial layer 206 and the substrate 208, and the etching rate of the HNA solution is associated with the doping concentration, so that uncontrollability of etching of the transition layer due to thermal diffusion increases. In addition, since the concentration of nitrogen dioxide in the HNA solution fluctuates with the time of the reaction, the stability of the HNA solution is insufficient. The present application thus proposes a backside illuminated semiconductor structure etching method.
Referring to fig. 3, the present invention provides a method for etching a back-illuminated semiconductor structure, which comprises fixing the back-illuminated semiconductor structure in an etching chamber, wherein the back-illuminated semiconductor structure comprises a carrier wafer and a device wafer located on the top surface of the carrier wafer, and the top surface of the device wafer is bonded with the top surface of the carrier wafer; the bottom surface of the device wafer is contacted with an anode disc in an etching cavity, and the etching cavity also comprises a cathode electrode positioned right below the anode disc; the method comprises the following steps:
step S302: controlling the voltage value applied between the anode disk and the cathode electrode and the current value flowing through different areas on the anode disk, so that the bottom surface of the device wafer is activated and easily reacts with nucleophilic substituents in etching solution in the etching cavity to adjust the etching rate of different areas of the bottom surface of the device wafer;
step S304: and adjusting etching time and/or etching rate of different areas according to the difference value between the thickness values of the different areas of the bottom surface of the device wafer and the corresponding target values.
Referring to fig. 4, the back-illuminated semiconductor structure includes a carrier wafer 202, a device layer 204, and a device substrate 402. The device substrate 402 may be formed of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The device substrate 402 may have a single-layer structure or a multi-layer structure. For example, it may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Alternatively, and also for example, device substrate 402 may be a layered substrate comprising a material such as Si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. The type of device substrate 402 should not limit the scope of the present disclosure. Furthermore, the device substrate 402 need not be heavily doped.
In addition, the anode disk is a device for partitioning, which is connected with the positive electrode of the power supply through the electric brush, can be in a hollowed-out shape and is used for connecting different areas of the bottom surface of the device wafer with different currents. For example, the bottom surface of the device wafer can be divided into a plurality of sector areas by the anode disk, all sector areas share vertexes, the vertexes of the sector areas are the circle centers of the bottom surface of the device wafer, and different sector areas can be connected with different currents by adopting the anode disk, so that the etching rate of different sector areas in the bottom surface of the device wafer is controlled. The shape of the anode disk and the shapes of different areas are not particularly limited, so long as the flatness requirement of the etched film surface can be met.
As shown in fig. 5, as an example, by controlling the voltage value applied between the anode disk and the cathode electrode, the bottom surface of the device wafer is activated, so that the bottom surface of the device wafer is easy to react with nucleophilic substituents in the etching solution in the etching cavity, silicon in the bottom surface of the device wafer loses electrons to become silicon ions, and is combined with the nucleophilic substituents, covalent bonds between the silicon are broken, and the broken reactant is separated from the device wafer, thereby realizing the etching of the bottom surface of the device wafer. In the etching process, according to the difference value between the thickness values of different areas and the corresponding target values, the resistance values of different areas in the anode disk can be controlled, so that the current flowing through the different areas can be controlled, and for areas with larger difference values, the etching rate can be increased. Further, the corresponding target values for all regions may be the same value. In other embodiments, when different patterns are required to be fabricated on the bottom surface of the device wafer, the corresponding target values may not be the same, and may be set according to the actual requirements.
In the above embodiment, the bottom surface of the device wafer in the back-illuminated semiconductor structure is fixed in the etching cavity, so that the bottom surface of the device wafer in the back-illuminated semiconductor structure is contacted with the anode disk in the etching cavity, the resistance values of different areas in the anode disk are controlled, the current values of different areas are further controlled, the etching solution is contacted with the cathode electrode, the voltage is applied to the anode disk and the cathode electrode, nucleophilic substituents are generated in the etching solution, and the nucleophilic substituents replace covalent bonds between silicon, so that the bottom surface of the device wafer is etched, the current values flowing through different areas on the anode disk are controlled, the etching time and the etching rate of different areas of the bottom surface of the device wafer are adjusted, the partition etching of different areas is realized, and the thickness of all areas reaches the same corresponding target value, and the uniformity of the thickness of the etched film surface is ensured. In addition, the etching solution does not react with the bottom surface of the device wafer when not electrified, so that a stopping point of the etching process can be accurately controlled, thereby avoiding the reaction between the device layer and the etching solution, avoiding the damage to the device layer in the etching process, and the etching solution does not have etching selectivity, so that the device substrate is not required to be heavily doped, the manufacturing process of the device wafer is simplified, and certain economic benefit is achieved.
In one embodiment, the different regions include a center region, a middle region, and an edge region, the middle region surrounding the center region and located between the center region and the edge region.
The etching rate of the central area is positively correlated with the value of the flowing current; the etching rate of the middle area is positively correlated with the value of the flowing current; the etching rate of the edge area is positively correlated with the value of the flowing current; adjusting the etching time and/or etching rate of different areas comprises: and changing the current value flowing through the central area, the current value flowing through the middle area and the current value flowing through the edge area, and the etching time of the central area, the etching time of the middle area and the etching time of the edge area.
As an example, the central region may be square, the central region may be a square annular structure of fixed width, and the edge regions may be the remaining irregular structure. Because the etching solution reacts with the bottom surface of the device wafer, the edge of the device wafer is heated faster, the temperature of the edge of the device wafer is increased along with the progress of the etching process, the temperature is gradually increased from the circle center of the device wafer to the edge, and the etching rate is associated with the temperature, therefore, by dividing different areas into a central area, a middle area and an edge area according to the distance from the circle center of the device wafer, the area with similar temperature influence can be divided into the same area, and the control accuracy is ensured.
As an example, in the case of dividing the bottom surface of the device wafer into a center region, a middle region, and an edge region, the etching time and etching rate of the different regions may be adjusted according to the difference between the thickness values of the different regions and the corresponding target values, for example: the thickness value of the central area before the reaction can be K1, the thickness value of the middle area can be K2, and the thickness value of the edge area can be K3, wherein K1 is smaller than K2, and K2 is smaller than K3; because the corresponding target values can be the same value, the difference value X1 of the central area is smaller than the difference value X2 of the middle area, the difference value X2 of the middle area is smaller than the difference value X3 of the edge area, etching time of all areas can be set to be the same, the flowing current value of the central area is smaller than the flowing current value of the middle area, and the flowing current value of the middle area is smaller than the flowing current value of the edge area, so that the thickness of the etched film surface is consistent, and the flatness of the film surface is ensured.
In one embodiment, referring to FIG. 6, the center region 602, the middle region 604, and the edge region 606 are concentric; the central region 602 is circular and the middle region 604 is annular; the edge region 606 surrounds the middle region 604 and is annular. In addition, in other embodiments, the middle region 604 and the edge region 606 may include a plurality of ring structures, and the number of ring structures is not particularly limited herein, and the greater the number of ring structures, the higher the accuracy of the control of the etching process.
In the above embodiment, as the temperature of the edge of the device wafer increases along with the progress of the etching process, the temperature gradually increases from the center to the edge, so that the use of a circle as the center area and a ring as the middle area and the edge area can improve the probability of dividing the area with the same temperature influence into the same area, and further can ensure that the influence degree of other factors on the etching rate tends to be consistent in the same area, thereby improving the control accuracy of the etching process.
In one embodiment, the etching chamber further comprises a semi-permeable membrane positioned between the anode disk and the cathode electrode.
As an example, the etching solution may adopt a circulating flow mode, and a semipermeable membrane is used to isolate a circulating inlet of the etching solution from a circulating outlet of the etching solution, so as to control the etching solution at the circulating outlet to react with the bottom surface of the device wafer; wherein the semipermeable membrane may be an anion exchange membrane having uniform pores to allow anions (nucleophilic substituents) dissociated in the etching solution to migrate sufficiently to the anode disk side.
In one embodiment, the nucleophilic substituent comprises at least one of hydroxide, fluoride, organofluoride, or organoamine.
In the above embodiment, the solution containing nucleophilic substituents such as hydroxide ions and fluoride ions is adopted to react with the bottom surface of the device wafer, and the concentration of the nucleophilic substituents is associated with the voltage value and the current value, so that the stability of the concentration of the nucleophilic substituents is ensured, and the stability of the etching reaction is ensured.
In one embodiment, adjusting the etching time and/or etching rate of the different regions further comprises: and continuously measuring thickness values of different areas during etching, and adjusting etching time and/or etching rate according to the thickness values in a feedback manner. For example, when it is detected that the thickness value of a certain area reaches a corresponding target value, the application of current to this area may be stopped.
In the above embodiment, the etching time and the etching rate may be adjusted by measuring the thickness value in the reaction process, and the influence of other factors on the etching rate may be comprehensively considered by monitoring the thickness value, so as to adjust the current values flowing through different regions in real time, thereby ensuring the accuracy of etching control, for example, avoiding that when the temperature influence causes the temperature of the edge region to be too high, the etching rate is faster than the etching rate caused by the current value, and the thickness value after etching the edge region is smaller than the corresponding target value.
It should be understood that, although the steps in the flowcharts of the embodiments are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the flowcharts may include a plurality of steps or stages that are not necessarily performed at the same time, but may be performed at different times, and the order of execution of the steps or stages is not necessarily sequential, but may be performed in rotation or alternately with at least a portion of the steps or stages in other steps or other steps.
Based on the same inventive concept, the embodiment of the application also provides an etching device for implementing the above related back-illuminated semiconductor structure etching method. The implementation of the solution provided by the apparatus is similar to that described in the above method, so the specific limitation of one or more embodiments of the etching apparatus provided below may be referred to above for limitation of the etching method of the back-illuminated semiconductor structure, and will not be repeated here.
The application also provides an etching device for etching the back-illuminated semiconductor structure fixed in the etching cavity, wherein the back-illuminated semiconductor structure comprises a bearing wafer and a device wafer positioned on the top surface of the bearing wafer; the top surface of the device wafer is bonded to the top surface of the carrier wafer.
Referring to fig. 7, the etching apparatus 700 includes: an anode disk 701, a cathode electrode 702, and a controller 703; the anode disk 701 is positioned in the etching cavity, and the bottom surface of the device wafer is contacted with the anode disk 701; the cathode electrode 702 is located within the etch chamber and directly below the anode disk 701.
The controller 703 is electrically connected to both the anode disk 701 and the cathode electrode 702, and is configured to: controlling the resistance values of different areas of the anode disk 701 to control the current values flowing through the different areas on the anode disk 701, so that the bottom surface of the device wafer is activated and reacts with nucleophilic substituents generated in etching solution in the etching cavity to adjust the etching rate of the different areas of the bottom surface of the device wafer; and adjusting etching time and/or etching rate of different areas according to the difference value between the thickness values of the different areas of the bottom surface of the device wafer and the corresponding target values.
In the above embodiment, the anode disc is contacted with the bottom surface of the device wafer, the cathode electrode is located in the etching cavity and contacted with the solution, the controller is electrically connected with the anode disc and the cathode electrode, the voltage value applied between the anode disc and the cathode electrode is controlled by the controller, so that the bottom surface of the device wafer is activated, nucleophilic substituent is generated by the solution, the nucleophilic substituent reacts with the bottom surface of the device wafer, and meanwhile, the current values of different areas on the anode disc are controlled to adjust the etching rates of the different areas, so that the etching rates are controllable, the reaction stopping point is controllable, the stability of the etching process is improved, and meanwhile, the etching time and the etching rate of the different areas are adjusted according to the difference value between the thickness values of the different areas of the bottom surface of the device wafer and the corresponding target values, so as to improve the flatness of the etched film surface.
In one embodiment, the etching apparatus further comprises: and the bearing device is arranged on the etching cavity and used for fixing the back-illuminated semiconductor structure. The bearing device can fix the back-illuminated semiconductor structure in an adsorption mode.
As an example, please refer to fig. 8a, a rectangular container may be used as the etching cavity 801, the top surface of the etching cavity 801 is provided with the carrying device 802, the carrying device 802 contacts with the bottom surface of the carrying wafer in the back-illuminated semiconductor structure 803, the bottom surface of the device wafer contacts with the anode disc 701, the anode disc 701 is connected with the positive electrode of the power supply through the brush 805, the anode disc 701 may be a hollow device, the bottom surface of the device wafer contacts with the etching solution, the cathode electrode 702 is connected with the negative electrode of the power supply, and the device wafer is disposed on the bottom surface of the etching cavity 801 and contacts with the solution.
In the above embodiment, the carrying device is used to fix the back-illuminated semiconductor structure on the top surface of the etching cavity, so that only the bottom surface of the device wafer is in contact with the etching solution, the whole back-illuminated semiconductor structure is prevented from being placed in the etching solution to damage the device layer, and meanwhile, the back-illuminated semiconductor structure can be fixed in a vacuum adsorption mode or the like, and breakage caused by uneven stress of the back-illuminated semiconductor structure in a single-point fixing mode is prevented.
In one embodiment, the etching apparatus further comprises: and the thickness sensor is electrically connected with the controller and is used for measuring thickness values of different areas.
As an example, please refer to fig. 9, the workflow of the thickness sensor includes:
step S902: measuring a thickness value K1 of a central area before unreacted and a thickness value K2 of a middle area before unreacted by using a plurality of thickness sensors, and a thickness value K3 of an edge area before unreacted; the current thickness value comprises a thickness value K1, a thickness value K2 and a thickness value K3, and the corresponding target value is K0.
Step S904: the etching time and the etching rate of the central area, the middle area and the edge area are controlled by controlling the value of the flowing current.
Step S906: and adjusting the etching time and the etching rate according to the difference value between the current thickness value and the corresponding target value.
As an example, for any one region, the ratio between the difference of the current thickness value and the corresponding target value and the etching time is equal to the etching rate, and since the etching rate is positively correlated with the current value, the etching time and etching rate of the center region, the middle region, and the edge region can be controlled by controlling the current value flowing therethrough. In the etching process, the difference value between the current thickness value and the corresponding target value is continuously monitored, and the current value is adjusted to enable the thickness values of different areas to trend to the corresponding target value, so that the stability of etching is improved, and the flatness of the etched film surface is ensured.
In the embodiment, the etching process is monitored in real time by using the thickness sensor, and the etching rate and the etching time are adjusted according to the monitored real-time thickness values of different areas, so that the accuracy of the control of the etching process is ensured.
In one embodiment, referring to fig. 8a, the etching apparatus further comprises:
a semipermeable membrane 806 positioned within the etching chamber and between the anode disk 701 and the cathode electrode 702 for permeation of nucleophilic substituents;
a circulating solution inlet 809, which is positioned on the side wall of the etching cavity 801 and is used for inputting etching solution into the etching cavity 801;
a circulating solution outlet 807 located on a side wall of the etching chamber 801 for outputting the etching solution in the etching chamber 801;
wherein the circulating solution inlet 809 is located at a side of the semipermeable membrane 806 facing away from the anode disk 701 and the circulating solution outlet 807 is located at a side of the semipermeable membrane 806 facing towards the anode disk 701.
In one embodiment, referring to fig. 8b, the etching apparatus further comprises:
a semipermeable membrane 806 positioned within the etching chamber and between the anode disk 701 and the cathode electrode 702 for permeation of nucleophilic substituents;
a circulating solution inlet 809, which is positioned on the side wall of the etching cavity 801 and is used for inputting etching solution into the etching cavity 801;
a circulating solution outlet 807 located on a side wall of the etching chamber 801 for outputting the etching solution in the etching chamber 801;
wherein the circulating solution inlet 809 and the circulating solution outlet 807 are located on the same side of the semipermeable membrane 806 facing away from the anode disk 701, respectively. By way of example, the etching solution may be circulated through the circulation solution inlet 809 and the circulation solution outlet 807.
The back-illuminated semiconductor structure etching method and the etching device have the following unexpected effects: the bottom surface of the device wafer is activated by contacting the anode disk with the bottom surface of the device wafer, contacting the cathode electrode with the etching solution, controlling the resistance values of different areas of the anode disk, further controlling the current values flowing through the different areas of the anode disk, enabling the etching solution to generate nucleophilic substituents, enabling the nucleophilic substituents to react with silicon on the bottom surface of the device wafer and replace covalent bonds between the silicon, thereby realizing etching of the bottom surface of the device wafer, controlling the etching time and the etching rate of the different areas by the controller, realizing the control of the reaction degree of the different areas, further enabling the thickness values after etching of all the areas to reach corresponding target values, ensuring the flatness of the film surface after etching, controlling the etching time and the etching rate by the controller, and improving the accuracy of etching control. Meanwhile, the application can also adopt a semipermeable membrane allowing nucleophilic substituent groups to permeate, and the etching solution is recycled through a circulating solution inlet and a circulating solution outlet, so that the process cost is saved.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application.
Claims (10)
1. The back-illuminated semiconductor structure etching method is characterized by being used for etching the back-illuminated semiconductor structure fixed in an etching cavity, wherein the back-illuminated semiconductor structure comprises a bearing wafer and a device wafer positioned on the top surface of the bearing wafer; the top surface of the device wafer is bonded with the top surface of the bearing wafer, the bottom surface of the device wafer is in contact with the anode disc in the etching cavity, and the etching cavity further comprises a cathode electrode positioned right below the anode disc; the etching method comprises the following steps:
controlling voltage values applied between the anode disk and the cathode electrode and current values flowing through different areas on the anode disk, so that the bottom surface of the device wafer is activated and reacts with nucleophilic substituents generated in etching solution in the etching cavity to adjust etching rates of different areas of the bottom surface of the device wafer;
and adjusting etching time and/or etching rate of different areas according to the difference value between the thickness value of the different areas of the bottom surface of the device wafer and the corresponding target value.
2. The etching method of claim 1, wherein the different regions include a center region, a middle region, and an edge region, the middle region surrounding the center region and being located between the center region and the edge region;
the etching rate of the central area is positively correlated with the value of the flowing current;
the etching rate of the middle area is positively correlated with the value of the flowing current;
the etching rate of the edge area is positively correlated with the value of the flowing current;
adjusting the etching time and/or etching rate of the different regions comprises:
and changing the current value flowing through the central area, the current value flowing through the middle area and the current value flowing through the edge area, and the etching time of the central area, the etching time of the middle area and the etching time of the edge area.
3. The etching method according to claim 2, wherein the center region, the middle region, and the edge region are concentric;
the central area is circular, and the middle area is annular;
the edge region surrounds the middle region and is annular.
4. An etching method according to any one of claims 1-3, wherein the etching chamber further comprises a semi-permeable membrane located between the anode disk and the cathode electrode.
5. An etching method according to any one of claims 1-3, wherein said nucleophilic substituent comprises at least one of hydroxide ion, fluoride ion.
6. An etching method according to any of claims 1-3, wherein adjusting the etching time and/or etching rate of the different regions further comprises:
and continuously measuring thickness values of the different areas during etching, and adjusting the etching time and/or the etching rate according to the thickness values in a feedback manner.
7. The etching device is characterized by being used for etching a back-illuminated semiconductor structure fixed in an etching cavity, wherein the back-illuminated semiconductor structure comprises a bearing wafer and a device wafer positioned on the top surface of the bearing wafer; the top surface of the device wafer is bonded with the top surface of the bearing wafer; the etching device comprises:
the anode disc is positioned in the etching cavity, and the bottom surface of the device wafer is contacted with the anode disc;
the cathode electrode is positioned in the etching cavity and is positioned right below the anode disc; and
and a controller electrically connected to both the anode disk and the cathode electrode, configured to:
controlling voltage values applied between the anode disk and the cathode electrode and current values flowing through different areas on the anode disk, so that the bottom surface of the device wafer is activated and reacts with nucleophilic substituents generated in etching solution in the etching cavity to adjust etching rates of different areas of the bottom surface of the device wafer;
and adjusting etching time and/or etching rate of different areas according to the difference value between the thickness value of the different areas of the bottom surface of the device wafer and the corresponding target value.
8. The etching apparatus according to claim 7, further comprising:
and the bearing device is arranged on the etching cavity and used for fixing the back-illuminated semiconductor structure.
9. The etching apparatus according to claim 7, further comprising:
and the thickness sensor is electrically connected with the controller and is used for measuring thickness values of the different areas.
10. An etching apparatus according to any one of claims 7 to 9, further comprising:
a semipermeable membrane positioned in the etching cavity and between the anode disk and the cathode electrode for permeation of the nucleophilic substituent;
the circulating solution inlet is positioned on the side wall of the etching cavity and is used for inputting the etching solution into the etching cavity;
the circulating solution outlet is positioned on the side wall of the etching cavity and is used for outputting the etching solution in the etching cavity;
wherein the circulating solution inlet and the circulating solution outlet are respectively positioned on the same side of the semipermeable membrane away from the anode disk, or
The circulating solution inlet is positioned at one side of the semipermeable membrane, which is away from the anode disc, and the circulating solution outlet is positioned at one side of the semipermeable membrane, which is close to the anode disc.
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Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040219797A1 (en) * | 2001-12-05 | 2004-11-04 | Masanobu Honda | Plasma etching method and plasma etching unit |
| KR20060044089A (en) * | 2004-11-11 | 2006-05-16 | 삼성전자주식회사 | Plasma etch apparatus having height-adjustable and segmented anode electrodes and etching method using the apparatus |
| KR20080003157U (en) * | 2007-02-01 | 2008-08-06 | 어플라이드 머티어리얼스, 인코포레이티드 | Mask etch plasma reactor with cathode lift pin assembly |
| CN102751299A (en) * | 2012-05-04 | 2012-10-24 | 香港应用科技研究院有限公司 | Low-cost high-integration BSI image sensor packaging |
| TW201405788A (en) * | 2012-07-17 | 2014-02-01 | Taiwan Semiconductor Mfg | Methods of minimizing edge peeling in the manufacturing of backside illumination image sensor chips |
| JP2015220352A (en) * | 2014-05-19 | 2015-12-07 | 東京エレクトロン株式会社 | Plasma processing apparatus |
| CN109449172A (en) * | 2018-10-16 | 2019-03-08 | 德淮半导体有限公司 | Wafer bonding method |
| CN110364427A (en) * | 2019-07-17 | 2019-10-22 | 德淮半导体有限公司 | Wafer bonding method |
| CN112582387A (en) * | 2019-08-01 | 2021-03-30 | 文和文森斯设备公司 | Microstructure enhanced absorption photosensitive device |
| CN112863991A (en) * | 2021-01-04 | 2021-05-28 | 长江存储科技有限责任公司 | Etching chamber and method for designing and manufacturing upper electrode of etching chamber |
| US20220013458A1 (en) * | 2020-07-07 | 2022-01-13 | Nanya Technology Corporation | Vertical electrical fuse device and method for forming the same |
| US20220148883A1 (en) * | 2019-04-26 | 2022-05-12 | Sciocs Compny Limited | Structure manufacturing method and intermediate structure |
| CN116110840A (en) * | 2021-11-09 | 2023-05-12 | 中微半导体设备(上海)股份有限公司 | Electrostatic chuck and plasma reaction device for improving etching uniformity |
| CN116581135A (en) * | 2023-05-12 | 2023-08-11 | 中国科学院长春光学精密机械与物理研究所 | Back etching device and method for bonding wafers with different sizes based on BSI (base station interface) process |
| US20230268368A1 (en) * | 2020-09-10 | 2023-08-24 | Sony Semiconductor Solutions Corporation | Solid-state imaging device, method of producing the same, and electronic apparatus |
-
2023
- 2023-12-19 CN CN202311749109.0A patent/CN117423716B/en active Active
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040219797A1 (en) * | 2001-12-05 | 2004-11-04 | Masanobu Honda | Plasma etching method and plasma etching unit |
| KR20060044089A (en) * | 2004-11-11 | 2006-05-16 | 삼성전자주식회사 | Plasma etch apparatus having height-adjustable and segmented anode electrodes and etching method using the apparatus |
| KR20080003157U (en) * | 2007-02-01 | 2008-08-06 | 어플라이드 머티어리얼스, 인코포레이티드 | Mask etch plasma reactor with cathode lift pin assembly |
| CN102751299A (en) * | 2012-05-04 | 2012-10-24 | 香港应用科技研究院有限公司 | Low-cost high-integration BSI image sensor packaging |
| TW201405788A (en) * | 2012-07-17 | 2014-02-01 | Taiwan Semiconductor Mfg | Methods of minimizing edge peeling in the manufacturing of backside illumination image sensor chips |
| JP2015220352A (en) * | 2014-05-19 | 2015-12-07 | 東京エレクトロン株式会社 | Plasma processing apparatus |
| CN109449172A (en) * | 2018-10-16 | 2019-03-08 | 德淮半导体有限公司 | Wafer bonding method |
| US20220148883A1 (en) * | 2019-04-26 | 2022-05-12 | Sciocs Compny Limited | Structure manufacturing method and intermediate structure |
| CN110364427A (en) * | 2019-07-17 | 2019-10-22 | 德淮半导体有限公司 | Wafer bonding method |
| CN112582387A (en) * | 2019-08-01 | 2021-03-30 | 文和文森斯设备公司 | Microstructure enhanced absorption photosensitive device |
| US20220013458A1 (en) * | 2020-07-07 | 2022-01-13 | Nanya Technology Corporation | Vertical electrical fuse device and method for forming the same |
| US20230268368A1 (en) * | 2020-09-10 | 2023-08-24 | Sony Semiconductor Solutions Corporation | Solid-state imaging device, method of producing the same, and electronic apparatus |
| CN112863991A (en) * | 2021-01-04 | 2021-05-28 | 长江存储科技有限责任公司 | Etching chamber and method for designing and manufacturing upper electrode of etching chamber |
| CN116110840A (en) * | 2021-11-09 | 2023-05-12 | 中微半导体设备(上海)股份有限公司 | Electrostatic chuck and plasma reaction device for improving etching uniformity |
| CN116581135A (en) * | 2023-05-12 | 2023-08-11 | 中国科学院长春光学精密机械与物理研究所 | Back etching device and method for bonding wafers with different sizes based on BSI (base station interface) process |
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| Publication number | Publication date |
|---|---|
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