CN117423702A - Integrated circuit device and method of manufacturing the same - Google Patents

Integrated circuit device and method of manufacturing the same Download PDF

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Publication number
CN117423702A
CN117423702A CN202311103855.2A CN202311103855A CN117423702A CN 117423702 A CN117423702 A CN 117423702A CN 202311103855 A CN202311103855 A CN 202311103855A CN 117423702 A CN117423702 A CN 117423702A
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China
Prior art keywords
electrical connection
nmos
body contact
diode
pmos
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CN202311103855.2A
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Chinese (zh)
Inventor
许嘉麟
苏郁迪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US18/309,172 external-priority patent/US20240113099A1/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN117423702A publication Critical patent/CN117423702A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Embodiments of the present application provide an integrated circuit device and a method of manufacturing the same. The integrated circuit device includes first and second CMOS structures positioned in the n-doped region of the substrate, the first CMOS structure including a common gate terminal, first NMOS body and source contacts, and first PMOS body and source contacts, the second CMOS structure including a common drain terminal, second NMOS body and source contacts, and second PMOS body and source contacts. The IC device includes: a first electrical connection from the common drain terminal to the common gate terminal; a clamp device including a diode; a second electrical connection from the cathode of the diode to the first PMOS body contact and the source contact; and a third electrical connection from the anode of the diode to the first NMOS body contact and the source contact, and the entirety of each of the second and third electrical connections is positioned between the substrate and the third metal layer of the IC device.

Description

Integrated circuit device and method of manufacturing the same
Technical Field
Embodiments of the present application relate to integrated circuit devices and methods of manufacturing the same.
Background
The trend toward miniaturized Integrated Circuits (ICs) has been to make increasingly smaller devices consume less power and provide more functionality at higher speeds than earlier technologies. Such miniaturization has been achieved through design and manufacturing innovations associated with increasingly stringent specifications. Various Electronic Design Automation (EDA) tools are used to generate, modify, and verify the design of a semiconductor device while ensuring that the IC structural design and manufacturing specifications are met.
Disclosure of Invention
According to an aspect of an embodiment of the present application, there is provided an integrated circuit device including: a first CMOS structure positioned in the first n-doped region of the substrate, the first CMOS structure including a common gate terminal, a first NMOS body contact, a first NMOS source contact, a first PMOS body contact, and a first PMOS source contact; a second CMOS structure positioned in the second n-doped region of the substrate, the second CMOS structure including a common drain terminal, a second NMOS body contact, a second NMOS source contact, a second PMOS body contact, and a second PMOS source contact; a first electrical connection from the common drain terminal to the common gate terminal; a first clamping device including a first diode; a second electrical connection from the cathode of the first diode to each of the first PMOS body contact and the first PMOS source contact; and a third electrical connection from the anode of the first diode to each of the first NMOS body contact and the first NMOS source contact, wherein an entirety of each of the second electrical connection and the third electrical connection is positioned between the substrate and the third metal layer of the integrated circuit device.
According to another aspect of embodiments of the present application, there is provided an integrated circuit device comprising: a first CMOS structure positioned in the first n-doped region of the substrate, the first CMOS structure including a common gate terminal, a first NMOS body contact, a first NMOS source contact, a first PMOS body contact, and a first PMOS source contact; a second CMOS structure positioned in the second n-doped region of the substrate, the second CMOS structure including a common drain terminal, a second NMOS body contact, a second NMOS source contact, a second PMOS body contact, and a second PMOS source contact; a first electrical connection from the common drain terminal to the common gate terminal; and a first clamping device including a first diode, wherein a length of the first electrical connection is greater than a length of the first current path, the first current path comprising: a second electrical connection from each of the first PMOS body contact and the source contact to the cathode of the first diode; a first diode; and a third electrical connection from the anode of the first diode to each of the first NMOS body contact and the source contact.
According to yet another aspect of embodiments of the present application, there is provided a method of manufacturing an integrated circuit device, the method comprising: constructing a first CMOS structure in a first n-type doped region of the substrate, the constructing the first CMOS structure including forming a first NMOS body contact region, a first NMOS source region, a first PMOS body contact region, and a first PMOS source region; constructing a second CMOS structure in the second n-type doped region of the substrate, the constructing the second CMOS structure including forming a second NMOS body contact region, a second NMOS source region, a second PMOS body contact region, and a second PMOS source region; constructing a first clamping device in a third n-type region of the substrate, the constructing the first clamping device including forming a first diode including a first cathode and a first anode; constructing a second clamping device in a fourth n-type region of the substrate, the constructing the second clamping device including forming a second diode, the second diode including a second cathode and a second anode; and forming a first plurality of metal segments located on the substrate from a surface of the substrate through the second metal layer of the integrated circuit device, wherein forming the first plurality of metal segments comprises: forming a first electrical connection from the first cathode to each of the first PMOS body contact region and the first PMOS source region; forming a second electrical connection from the first anode to each of the first NMOS body contact region and the first NMOS source region; forming a third electrical connection from the second cathode to each of the second PMOS body contact region and the second PMOS source region; and forming a fourth electrical connection from the second anode to each of the second NMOS body contact region and the second NMOS source region.
Drawings
The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. Indeed, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 is a diagram of an IC device according to some embodiments.
Fig. 2 is a diagram of a portion of an IC device, according to some embodiments.
Fig. 3 is a diagram of a portion of an IC device, according to some embodiments.
Fig. 4A and 4B are schematic diagrams of a portion of an IC device according to some embodiments.
Fig. 5 is a diagram of a portion of an IC device, according to some embodiments.
Fig. 6 is a flow chart of a method of manufacturing an IC device according to some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, steps, operations, materials, arrangements, etc. are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are in direct contact, as well as embodiments in which additional components are formed between the first component and the second component such that the first component and the second component are not in direct contact. Moreover, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, for ease of description, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly.
In various embodiments, an Integrated Circuit (IC) device includes first and second Complementary Metal Oxide Semiconductor (CMOS) structures positioned in first and second n-doped regions of a substrate, a first electrical connection between a common gate terminal of the first CMOS structure and a common drain terminal of the second CMOS structure, a clamp device including a diode positioned in a third n-doped region, a second electrical connection from a cathode of the diode to PMOS body and source contact points of the first CMOS structure, and a third electrical connection from an anode of the diode to NMOS body and source contact points of the second CMOS structure. By positioning the entirety of each of the second and third electrical connections between the substrate and the third or underlying metal layer of the IC device, a diode leakage path is established, thereby reducing the risk of potentially damaging charge accumulation during fabrication operations for forming the metal layers over the second and third electrical connections, thereby reducing the risk of Process Induced Damage (PID) on the CMOS structure, particularly the gate dielectric of the first CMOS device.
As described below, fig. 1 is a schematic diagram of an IC device, each of fig. 2-5 is a schematic diagram of a portion of an IC device, and fig. 6 is a flowchart of a method of manufacturing an IC device, according to various embodiments.
Each of the figures herein (e.g., fig. 1-5) is simplified for illustrative purposes. These figures are views of IC structures and devices, including and excluding various features, to facilitate the discussion below. In various embodiments, the IC structures and/or devices include one or more features corresponding to power distribution structures, metal interconnects, contacts, vias, gate structures, source/drain (S/D) structures, block connections or other transistor elements, isolation structures, etc., in addition to the features described in fig. 1-5.
Fig. 1 is a schematic diagram of an IC device 100 according to some embodiments. In addition to IC device 100 (also referred to as circuit 100 in some embodiments), fig. 1 depicts X and Z directions corresponding to cross-sectional views of Complementary Metal Oxide Semiconductor (CMOS) structural elements of IC device 100 discussed below.
The IC device 100 includes a substrate 100B in which n-type regions NR1 and NR2 are located. As described below, the n-type region NR1 includes the p-well PW1 and the n-well NW1 and corresponds to the CMOS structure 100C1, and the n-type region NR2 includes the p-well PW2 and the n-well NW2 and corresponds to the CMOS structure 100C2. The IC device 100 further includes metal interconnect elements (not separately labeled for clarity) arranged such that the CMOS structure 100C1 is electrically connected to a clamp circuit CL1 coupled to the trigger circuit TR1, and/or the CMOS structure 100C2 is electrically connected to a clamp circuit CL2 coupled to the trigger circuit TR2, as described below.
In the embodiment depicted in fig. 1, n-type regions NR1 and NR2 are positioned in substrate 100B adjacent to each other. In some embodiments, one or more features, such as one or more additional n-type regions, are positioned in the substrate 100B between the n-type regions NR1 and NR 2.
The substrate 100B includes a p-type semiconductor material, such as silicon, including one or more p-type dopants, such as boron, configured to support the construction of various IC features, for example, as described below. In some embodiments, the substrate 100B is part of a silicon-on-oxide (SOI) configuration of a semiconductor wafer.
An n-type region, such as n-type region NR1 or NR2, is a volume within the substrate 100B that includes one or more n-type dopants, such as phosphorus or arsenic, at a doping concentration large enough to form a p-n junction with a surrounding portion of the substrate 100B. In some embodiments, the n-type region is referred to as an n+ buried layer or deep n-well.
A p-well, such as p-well PW1 or PW2, is a volume within an n-type region that includes one or more p-type dopants in a concentration large enough to form a p-n junction with the surrounding portion of the n-type region and small enough to include a channel region having conductivity controllable by an applied electric field.
An n-well, such as n-well NW1 or NW2, is a volume within an n-type region that includes one or more n-type dopants at a doping concentration that is small enough to include a channel region having conductivity that can be controlled by an applied electric field.
Each of the P-wells PW1 and PW2 and the N-wells NW1 and NW2 includes one or more P-type regions p+ and one or more N-type regions n+, which are configured as described below. The region p+ or n+ is a volume within the respective P-well or N-well that is doped at a significantly higher concentration than the respective P-well or N-well. The region p+ located in the P-well or the region n+ located in the N-well is thus configured as a body contact region, and the region n+ located in the P-well or the region p+ located in the N-well is thus configured as a source region or a drain region.
Each of the P-wells PW1 and PW2 includes a body contact region p+ and a source region n+ positioned on a first side of the upper gate structure G and a drain region n+ positioned on a second side of the upper gate structure G and is thus configured as an N-type MOS (NMOS) transistor of the respective CMOS structure 100C1 or 100C 2.
Each of the N-wells NW1 and NW2 includes a body contact region n+ and a source region p+ positioned on a first side of the upper gate structure G and a drain region p+ positioned on a second side of the upper gate structure G and is thereby configured as a P-type MOS (PMOS) transistor of the respective CMOS structure 100C1 or 100C 2.
In the embodiment depicted in fig. 1, regions p+ and n+ are located in P-wells PW1 and PW2 and N-wells NW1 and NW2 as planar transistors corresponding to upper surface 100S of substrate 100B. In some embodiments, regions p+ and n+ are otherwise located in P-wells PW1 and PW2 and N-wells NW1 and NW2, e.g., as fin field effect transistors (finfets), corresponding to upper surface 100S.
An example of a gate structure, such as gate structure G, is a volume that is located on or partially or fully over upper surface 100S and includes one or more conductive segments, such as a gate electrode, including one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials, substantially surrounded by one or more insulating materials, the one or more conductive segments thereby being configured to control a voltage provided to an adjacent gate dielectric layer.
The dielectric layer, e.g., gate dielectric layer, is a volume comprising one or more insulating materials, e.g., silicon dioxide, silicon nitride (Si 3 N 4 ) And/or one or more other suitable materials, such as a low-K material having a K value less than 3.8 or a high-K material having a K value greater than 3.8 or 7.0, such as alumina (Al) 2 O 3 ) Hafnium oxide (HfO) 2 ) Tantalum pentoxide (Ta) 2 O 5 ) Or titanium oxide (TiO) 2 ) It is suitable to provide a high resistance between the IC structural elements, i.e. a resistance level above a predetermined threshold corresponding to one or more tolerance levels based on the influence of the resistance on the circuit performance.
The example of regions p+ and n+ and the gate electrodes of gate structures G of CMOS structures 100C1 and 100C2 are electrically connected to each other and to other IC device elements by upper layer metal interconnect elements of IC device 100 as described in fig. 1.
The metal interconnect element includes metal segments positioned in the Z-direction in metal layers M0 through MN, and via structures positioned in adjacent underlying via layers V0 through VN.
A metal segment is a volume comprising one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials, that are located in a particular metal layer used in the fabrication process that constructs the IC device 100. In some embodiments, the metal segments positioned in metal layer M0 correspond to a first metal layer, also referred to as a metal zero layer in some embodiments, the metal segments positioned in metal layer M1 correspond to a second metal layer, also referred to as a metal one layer in some embodiments, and the metal segments positioned in metal layer M2 correspond to a third metal layer, also referred to as a metal two layer in some embodiments. A given one of the metal layers M0-MN is referred to in some embodiments as metal layer MN.
The total number N of metal layers M0-MN is a function of the manufacturing process. As the total number N increases, the number of plasma-based fabrication processes used to form the IC device 100 increases and the risk of plasma-induced charge damage to the dielectric layer of an example of the gate structure G increases. In some embodiments, the total number N varies from seven to ten. In some embodiments, the total number N has a value greater than ten, e.g., from eleven to fifteen.
In some embodiments, a given metal layer, such as metal layer MN, corresponds to a power distribution layer of IC device 100, and metal segments positioned in the given metal layer correspond to an interconnect structure, e.g., including one or more power rails, configured to distribute power and reference voltage levels. In some embodiments, interconnect structure VDDN, also referred to as supply node VDDN, is configured to distribute a supply voltage level VDD and interconnect structure VSSN, also referred to as reference node VSSN, is configured to distribute a reference voltage level VSS.
A via structure, also referred to in some embodiments as a via, is a volume comprising one or more conductive materials configured to provide an electrical connection between an upper conductive structure (e.g., a metal segment of a given metal layer Mn) and a lower conductive structure (e.g., a metal segment of a lower metal layer Mn-1, a gate electrode of a gate structure G, or region p+ or n+).
In some embodiments, the via structure is configured to provide an electrical connection with the underlying region p+ or n+ by direct contact with the region p+ or n+. In some embodiments, the IC device 100 includes one or more metal-like defining (MD) segments located on and in contact with a given region p+ or n+ and the upper via structure is configured to provide electrical connection to the underlying region p+ or n+ by directly contacting the corresponding MD segment.
The MD segments are portions of conductive lines or traces (including one or more conductive materials) and/or semiconductor substrates and/or epitaxial layers in and/or on the substrate 100B that have a doping level, e.g., based on an implantation process, sufficient to cause the MD segments to have a resistance level below a specified level.
In some embodiments, the via structure that covers and is electrically connected to the gate electrode, region p+ or n+ or MD segment of the gate structure G is referred to as a contact, contact structure or terminal.
In the embodiment depicted in fig. 1, the gate structures G of the NMOS and PMOS transistors of CMOS structure 100C1 are electrically connected to each other at metal layer M1 as a common gate terminal GT, and the drain regions n+ and p+ of the respective NMOS and PMOS transistors of CMOS structure 100C2 are electrically connected to each other at metal layer M1 as a common drain terminal DT. In some embodiments, the common gate terminal GT and/or the common drain terminal DT include electrical connections at layers other than the metal layer M1 (e.g., metal layer M2).
The IC device 100 includes one or more metal interconnect elements electrically connected to the common gate terminal GT as an electrical connection C1, one or more metal interconnect elements electrically connected to the common drain terminal DT as an electrical connection C2, and one or more metal interconnect elements (not shown for clarity) electrically connected to each of the electrical connections C1 and C2, such that the IC device 100 is configured to include an electrical connection C1/C2 from the common drain terminal DT to the common gate terminal GT. In some embodiments, the electrical connection C1/C2 corresponds to a signal path from the common drain terminal DT to the common gate terminal GT.
In the embodiment depicted in FIG. 1, electrical connection C1/C2 includes metal interconnect elements positioned in metal and via layers from upper surface 100S to and including metal layer M3. In some embodiments, electrical connection C1/C2 includes metal interconnect elements positioned in metal and via layers from upper surface 100S to and including metal layers other than metal layer M3 (e.g., metal layer M4 or metal layer MN).
In the embodiment depicted in fig. 1, the NMOS transistor of CMOS structure 100C1 includes a body contact region p+ and a source region n+ electrically connected to each other through a segment of metal layer M1, the PMOS transistor of CMOS structure 100C1 includes a body contact region n+ and a source region p+ electrically connected to each other through a segment of metal layer M1, the NMOS transistor of CMOS structure 100C2 includes a body contact region p+ and a source region n+ electrically connected to each other through a segment of metal layer M1, and the PMOS transistor of CMOS structure 100C2 includes a body contact region n+ and a source region p+ electrically connected to each other through a segment of metal layer M0. In some embodiments, one or both of CMOS structures 100C1 or 100C2 include one or more electrical connections between the corresponding body contact region and the source region at one or more metal layers other than those depicted in fig. 1, e.g., the entire electrical connection between the corresponding body contact region and the source region at metal layer M0.
The IC device 100 includes one or more metal interconnect elements that are electrically connected to the common connection of the NMOS body contact region and the source region of the CMOS structure 100C1 as an electrical connection C3, one or more metal interconnect elements that are electrically connected to the common connection of the PMOS body contact region and the source region of the CMOS structure 100C1 as an electrical connection C4, one or more metal interconnect elements that are electrically connected to the common connection of the NMOS body contact region and the source region of the CMOS structure 100C2 as an electrical connection C5, and one or more metal interconnect elements that are electrically connected to the common connection of the PMOS body contact region and the source region of the CMOS structure 100C2 as an electrical connection C6.
Each of the electrical connectors C3 and C4 is electrically connected to the input terminal of the clamp circuit CL1, and each of the electrical connectors C5 and C6 is electrically connected to the input terminal of the clamp circuit CL 2.
In the embodiment depicted in fig. 1, the entirety of each of electrical connections C3-C6 includes metal interconnect elements positioned in the metal and via layers from upper surface 100S to and including metal layer M1. In some embodiments, the entirety of one or more of electrical connectors C3-C6 includes metal interconnect elements positioned in metal and via layers from upper surface 100S to and including metal layers other than metal layer M1 (e.g., metal layer M0 or M2).
Each of the electrical connections C3 and C5 is further electrically connected to one or more upper metal interconnect structures configured to distribute a reference voltage level, e.g., a reference voltage node VSSN configured to distribute a reference voltage level VSS, and each of the electrical connections C4 and C6 is further electrically connected to one or more upper metal interconnect structures configured to distribute a supply voltage level, e.g., a supply voltage node VDDN configured to distribute a supply voltage level VDD.
The clamp circuit CL1 is an electronic circuit that includes one or more switching devices (not shown in fig. 1) configured to selectively provide a low resistance current path from the supply voltage node VDDN and electrical connection C4 to the reference voltage node VSSN and electrical connection C3 in response to a signal TS1 received from the trigger circuit TR1 on the signal path TSN 1.
Clamp circuit CL2 is an electronic circuit that includes one or more switching devices (not shown in fig. 1) configured to selectively provide a low resistance current path from supply voltage node VDDN and electrical connection C6 to reference voltage node VSSN and electrical connection C5 in response to signal TS2 received from trigger circuit TR2 on signal path TSN 2.
Each of the flip-flop circuits TR1 and TR2 is an electronic circuit configured to detect an overvoltage event, for example, an Electrical Overstress (EOS) or an electrostatic discharge (ESD) event on one or both of the supply voltage node VDDN or the reference voltage node VSSN, and to generate a corresponding signal TS1 or TS2 on the signal path TSN1 or TSN2 in response to detecting the overvoltage event.
The trigger circuit TR1 and the clamp circuit CL1 are thereby configured to cause the switching devices of the clamp circuit CL1 to be turned on in response to detecting an overvoltage event, otherwise turned off, and the trigger circuit TR2 and the clamp circuit CL2 are thereby configured to cause the switching devices of the clamp circuit CL2 to be turned on in response to detecting an overvoltage event, otherwise turned off.
As depicted in fig. 1, the switching device of clamp CL1 includes a p-n junction labeled diode D1, and the switching device of clamp CL2 includes a p-n junction labeled diode D2. The anode of diode D1 is coupled to electrical connection C3, the cathode of diode D1 is coupled to electrical connection C4, the anode of diode D2 is coupled to electrical connection C5, and the cathode of diode D2 is coupled to electrical connection C6.
In various embodiments, the anode or cathode is coupled to the respective electrical connection by a direct electrical connection or by an additional feature of the respective clamping circuit, e.g., another switching device and/or another p-n junction of the respective switching device.
The switching device of each of the clamp circuits CL1 and CL2 is positioned at an n-type region (not shown in fig. 1) of the substrate 100B separate from the n-type regions NR1 and NR 2. In various embodiments, the n-type region is positioned adjacent to one of the n-type regions NR1 or NR2, or one or more IC features are positioned between the n-type region and one or both of the n-type regions NR1 or NR 2.
In some embodiments, the switching device of clamp CL1 or CL2 includes NMOS transistor N1 discussed below with respect to fig. 2, PMOS transistor P1 discussed below with respect to fig. 3, bipolar Junction Transistor (BJT) PNP1 discussed below with respect to fig. 4A, or BJT NPN1 discussed below with respect to fig. 4B.
In the embodiment depicted in fig. 1, IC device 100 includes a single instance of clamp circuit CL1 electrically connected to electrical connections C3 and C4 and a single instance of clamp circuit CL2 electrically connected to electrical connections C5 and C6. In some embodiments, IC device 100 does not include one of clamp circuits CL1 or CL2, includes one or more additional instances of clamp circuit CL1 electrically connected to electrical connections C3 and C4, and/or includes one or more additional instances of clamp circuit CL2 electrically connected to electrical connections C5 and C6.
The IC device 100 is thus configured to include an example of at least one clamp switching device, including a diode D1 or D2 having an anode electrically connected to an electrical connection C3 or C5 and a cathode electrically connected to an electrical connection C4 or C6. Accordingly, the respective CMOS structure 100C1 or 100C2 includes a leakage path from the PMOS body contact region n+ to the NMOS body contact region p+ through the respective electrical connection C4 or C6, the respective diode D1 or D2, and the respective electrical connection C3 or C5.
Because all of the electrical connections C3-C6 are positioned between the upper surface 100S of the substrate 100B and the metal layer M3 (or metal layer M2 in some embodiments), a leakage path is constructed prior to performing a plasma-based fabrication process for forming an upper metal layer (e.g., metal layer M3-MN or metal layer M2-MN). In some embodiments, the performance of the plasma-based fabrication process for forming the upper metal layer corresponds to the formation of the metal segments included in the electrical connections C1/C2 (e.g., in the metal layer M3).
In some embodiments, the total length of the leakage path is thus less than the length of the electrical connection C1/C2.
By including at least one diode leakage path built prior to formation of metal segments at or above metal layers M1, M2, or M3 (e.g., including those in electrical connections C1/C2), IC device 100 is able to provide a discharge path between respective PMOS and NMOS body contact regions, thereby reducing potentially damaging charge accumulation during fabrication operations for forming the upper metal layers, thereby reducing PID risks on CMOS structures (particularly dielectrics of instances of gate structure G in CMOS device 100C 1).
Each of fig. 2-4B is a diagram of a portion of IC device 100 according to some embodiments. Each of fig. 2-4B depicts a collective representation of flip-flop circuits TR1 and TR2, signal paths TSN1 and TSN2, clamp circuits CL1 and CL2 including diodes D1 and D2, electrical connections C3 and C5, and electrical connections C4 and C6, each discussed above with respect to fig. 1. Fig. 2 further depicts a cross-sectional view of the NMOS transistor N1 and X and Z directions, and fig. 3 further depicts a cross-sectional view of the PMOS transistor P1 and X and Z directions.
As described below, each of the NMOS transistor N1 depicted in fig. 2, the PMOS transistor P1 depicted in fig. 3, the BJT PNP1 depicted in fig. 4A, and the BJT NPN1 depicted in fig. 4B may be used as a switching device for one or both of the clamp circuits CL1 or CL 2.
As depicted in fig. 2, NMOS transistor N1 includes an N-type region NR3 positioned in substrate 100B and a p-well PW3 positioned in N-type region NR 3. The body contact region p+ and the source region n+ are positioned in the P-well PW3 at the first side of the gate structure G, electrically connected to each other, and electrically connected to a respective one of the electrical connections C3 or C5. The drain region n+ is positioned in the p-well PW3 on the second side of the gate structure G and is electrically connected to a respective one of the electrical connections C4 or C6. The gate electrode of the gate structure G is electrically connected to the signal path TSN1 or TSN2 and thus configured to receive the respective signal TS1 or TS2.
The body contact region p+ of the NMOS transistor N1 thus corresponds to the anode of the respective diode D1 or D2, and the drain region n+ of the NMOS transistor N1 thus corresponds to the cathode of the respective diode D1 or D2.
As depicted in fig. 3, PMOS transistor P1 includes an n-type region NR4 positioned in substrate 100B and an n-well NW3 positioned in n-type region NR 4. The body contact region n+ and the source region p+ are positioned in the N-well NW3 at the first side of the instance of the gate structure G, electrically connected to each other, and electrically connected to a respective one of the electrical connections C4 or C6. The drain region p+ is positioned in the NW3 hole on the second side of the example gate structure G and is electrically connected to a corresponding one of the electrical connections C3 or C5. The gate electrode of an example of gate structure G is electrically connected to signal path TSN1 or TSN2 and is thereby configured to receive a respective signal TS1 or TS2.
The drain region p+ of the PMOS transistor P1 thus corresponds to the anode of the respective diode D1 or D2, and the body contact region n+ of the PMOS transistor P1 thus corresponds to the cathode of the respective diode D1 or D2.
As depicted in fig. 4A, BJT PNP1 includes an emitter electrically connected to a respective one of electrical connections C4 or C6, a collector electrically connected to a respective one of electrical connections C3 or C5, and a base electrically connected to signal path TSN1 or TSN2 and thereby configured to receive a respective signal TS1 or TS2. The emitter of the BJT PNP1 thus corresponds to the anode of the respective diode D1 or D2, and the base of the BJT PNP1 thus corresponds to the cathode of the respective diode D1 or D2.
As depicted in fig. 4B, BJT NPN1 includes a collector electrically connected to a respective one of electrical connections C4 or C6, an emitter electrically connected to a respective one of electrical connections C3 or C5, and a base electrically connected to signal path TSN1 or TSN2 and configured to receive a respective signal TS1 or TS2 therefrom. The base of the BJT NPN1 thus corresponds to the anode of the respective diode D1 or D2, and the collector of the BJT NPN1 thus corresponds to the cathode of the respective diode D1 or D2.
Each of the NMOS transistor N1 depicted in fig. 2, the PMOS transistor P1 depicted in fig. 3, the BJT PNP1 depicted in fig. 4A, and the BJT NPN1 depicted in fig. 4B is configured to be usable as a switching device of the clamp circuit CL1 or CL2, and the IC device 100 including one or more of the NMOS transistor N1, the PMOS transistor P1, and the BJT PNP1 is thereby capable of achieving the advantages described above.
Fig. 5 is a schematic diagram of a portion of IC device 100 according to some embodiments. Fig. 5 depicts an X-direction, a Y-direction, and a corresponding plan view of a metal interconnect structure corresponding to power supply node VDDN and reference node VSSN, each of which was discussed with respect to fig. 1.
Each of the power supply node VDDN and the reference node VSSN includes an instance (not labeled) of a metal segment MSn extending in the Y-direction in the metal layer Mn, an instance (not labeled) of a metal segment msn+1 extending in the X-direction in the upper metal layer mn+1, and an instance of a via vn+1 configured to electrically connect the metal segment MSn to the corresponding metal segment msn+1.
The metal segment MSn corresponds to the metal layer Mn, which is one of the metal layers M0-M2, the first instance of the metal segment MSn corresponds to one of the electrical connectors C3 or C5, and the second instance of the metal segment MSn corresponds to one of the electrical connectors C4 or C6.
In some embodiments, metal segment msn+1, via vn+1, and additional upper metal segments and vias are configured to electrically connect one of electrical connections C3 or C5 to reference node VSSN configured to distribute reference voltage level VSS, and one of electrical connections C4 or C6 to supply voltage node VDDN configured to distribute supply voltage level VDD.
The metal segments MSn and msn+1 and the via vn+1 are thus configured to include some or all of the electrical connectors C3-C6, and further electrically connect the electrical connectors C3 and C5 to the reference node VSSN and the electrical connectors C4 and C6 to the power supply node VDDN, so that the IC device 100 including the metal segments MSn and msn+1 and the via vn+1 can thereby achieve the benefits described above.
Fig. 6 is a flow chart of a method 600 of manufacturing an IC device according to some embodiments. The method 600 is operable to form the IC device 100 discussed above with respect to fig. 1-5.
In some embodiments, the operations of method 600 are performed in the order depicted in fig. 6. In some embodiments, the operations of method 600 are performed in an order different from the order depicted in fig. 6. In some embodiments, one or more additional operations are performed before, during, and/or after the operations of method 600.
In operation 610, in some embodiments, first and second CMOS structures of an IC device are built in corresponding first and second n-doped regions of a substrate. In some embodiments, building the first and second CMOS structures includes forming CMOS structures 100C1 and 100C2, for example, including examples of gate structures G, as discussed above with reference to fig. 1-5.
In various embodiments, forming the first and second CMOS structures includes performing a plurality of fabrication operations, for example, one or more of photolithography, diffusion, deposition, etching, planarization, or other operations suitable for forming n-type and p-type regions and gate structures, as discussed above with reference to fig. 1-5.
In operation 620, first and/or second clamping devices, each comprising a diode, are built in corresponding third and fourth n-doped regions of the substrate. Constructing the clamp device includes forming a diode including an anode and a cathode.
In some embodiments, constructing the first and/or second clamp devices includes constructing clamp devices CL1 and/or CL2, including forming corresponding diodes D1 and/or D2 discussed above with reference to fig. 1-5. In some embodiments, constructing the first and/or second clamp devices includes constructing the corresponding flip-flop circuits TR1 and/or TR2 discussed above with reference to fig. 1-5.
In some embodiments, constructing the first and/or second clamp devices includes constructing one or more instances of NMOS transistor N1 discussed above with reference to fig. 2, one or more instances of PMOS transistor P1 discussed above with reference to fig. 3, one or more instances of BJT PNP1 discussed above with reference to fig. 4A, and/or one or more instances of BJT NPN1 discussed above with reference to fig. 4B.
In various embodiments, forming the first and/or second clamp devices includes performing a plurality of fabrication operations, e.g., one or more of photolithography, diffusion, deposition, etching, planarization, or other operations suitable for forming n-type and p-type regions and gate structures, as discussed above with reference to fig. 1-5.
At operation 630, a first plurality of metal segments including electrical connections between the CMOS structure and corresponding diodes of the clamp device are formed on the substrate from the surface of the substrate through the second metal layer of the IC device.
Forming the first plurality of metal segments includes forming a first electrical connection from the cathode of the first diode to each of the first PMOS body contact region and the first PMOS source region of the first CMOS structure, and a second electrical connection from the anode of the first diode to each of the first NMOS body contact region and the first NMOS source region of the first CMOS structure, and/or forming a third electrical connection from the cathode of the second diode to each of the second PMOS body contact region and the second PMOS source region of the second CMOS structure, and a fourth electrical connection from the anode of the second diode to each of the second NMOS body contact region and the second NMOS source region of the second CMOS structure.
In some embodiments, forming the first plurality of metal segments includes forming metal interconnect elements as discussed above with reference to fig. 1-5.
In various embodiments, forming the first plurality of metal segments includes performing a plurality of fabrication operations, e.g., one or more of photolithography, diffusion, deposition, etching, planarization, or other operations suitable for building metal segments and vias according to the configurations discussed above with reference to fig. 1-5.
In operation 640, in some embodiments, a second plurality of metal segments is formed on the first plurality of metal segments, the second plurality of metal segments including electrical connections to metal interconnect structures configured to distribute the power supply voltage level and the reference voltage level. In some embodiments, forming the second plurality of metal segments includes forming metal interconnect elements as discussed above with reference to fig. 1-5.
In some embodiments, forming the second plurality of metal segments includes forming an electrical connection from each of the first and third electrical connections to a first metal interconnect structure configured to distribute a supply voltage level (e.g., supply voltage VDD), and forming an electrical connection from each of the second and fourth electrical connections to a second metal interconnect structure configured to distribute a reference voltage level (e.g., reference voltage level VSS), as discussed above with reference to fig. 1-5.
In some embodiments, forming the second plurality of metal segments includes forming a portion of an electrical connection from the common drain terminal of the second CMOS structure to the common gate terminal of the first CMOS structure, e.g., electrical connection C1/C2 discussed above with reference to fig. 1-5.
In various embodiments, forming the second plurality of metal segments includes performing a plurality of fabrication operations, such as one or more of photolithography, diffusion, deposition, etching, planarization, or other operations suitable for building metal segments and vias according to the configurations discussed above with reference to fig. 1-5.
By performing some or all of the operations of method 600, an IC device is formed that includes the features discussed above with reference to IC device 100, and thus the benefits discussed above with reference to IC device 100 can be realized.
In some embodiments, an IC device includes: a first CMOS structure positioned in the first n-doped region of the substrate, the first CMOS structure including a common gate terminal, a first NMOS body contact, a first NMOS source contact, a first PMOS body contact, and a first PMOS source contact; a second CMOS structure positioned in the second n-doped region of the substrate, the second CMOS structure including a common drain terminal, a second NMOS body contact, a second NMOS source contact, a second PMOS body contact, and a second PMOS source contact; a first electrical connection from the common drain terminal to the common gate terminal; a first clamping device including a first diode; a second electrical connection from the cathode of the first diode to each of the first PMOS body contact and the first PMOS source contact; and a third electrical connection from the anode of the first diode to each of the first NMOS body contact and the first NMOS source contact, wherein an entirety of each of the second and third electrical connections is positioned between the substrate of the IC device and the third metal layer. In some embodiments, an IC device includes: a second clamping device including a second diode; a fourth electrical connection from the cathode of the second diode to each of the second PMOS body contact and the second PMOS source contact; and a fifth electrical connection from the anode of the second diode to each of the second NMOS body contact and the second NMOS source contact, and the entirety of each of the fourth and fifth electrical connections is positioned between the substrate of the IC device and the third metal layer. In some embodiments, the second electrical connection is further connected to an upper level metal interconnect structure configured to distribute a supply voltage level. In some embodiments, the third electrical connection is further connected to an upper metal interconnect structure configured to distribute the reference voltage level. In some embodiments, the first clamp circuit comprises an NMOS transistor, the anode of the first diode comprises a body contact of the NMOS transistor, and the cathode of the first diode comprises a drain contact of the NMOS transistor. In some embodiments, the first clamp circuit comprises a PMOS transistor, the anode of the first diode comprises a drain contact of the PMOS transistor, and the cathode of the first diode comprises a bulk contact of the PMOS transistor. In some embodiments, the first clamp circuit includes a bipolar transistor, and the first diode corresponds to a P-N junction of the bipolar transistor. In some embodiments, the IC device includes a trigger circuit coupled to the clamp circuit and configured to output a signal in response to an ESD event, the clamp circuit being configured to electrically couple the second and third electrical connections to each other in response to the signal. In some embodiments, the length of the first electrical connection is greater than the sum of the length of the second electrical connection, the length of the third electrical connection, and the distance between the cathode and anode of the first diode. In some embodiments, an entirety of each of the second and third electrical connections is positioned between the substrate of the IC device and the second metal layer.
In some embodiments, an IC device includes: a first CMOS structure positioned in the first n-doped region of the substrate, the first CMOS structure including a common gate terminal, a first NMOS body contact, a first NMOS source contact, a first PMOS body contact, and a first PMOS source contact; a second CMOS structure positioned in the second n-doped region of the substrate, the second CMOS structure including a common drain terminal, a second NMOS body contact, a second NMOS source contact, a second PMOS body contact, and a second PMOS source contact; a first electrical connection from the common drain terminal to the common gate terminal; a first clamping device comprising a first diode, wherein a length of the first electrical connection is greater than a length of the first current path, the first current path comprising a second electrical connection from each of the first PMOS body contact and the source contact to a cathode of the first diode, and a third electrical connection from an anode of the first diode to each of the first NMOS body contact and the source contact. In some embodiments, the entirety of the first current path is positioned in the substrate and between the substrate and the second metal layer of the IC device. In some embodiments, the IC device includes a second clamp device including a second diode, wherein a length of the first electrical connection is greater than a length of a second current path including a fourth electrical connection from each of the second PMOS body contact and the source contact to a cathode of the second diode, and a fifth electrical connection from an anode of the second diode to each of the second NMOS body contact and the source contact. In some embodiments, the first and second clamp circuits include respective first and second NMOS transistors positioned in corresponding n-doped regions of the substrate, an anode of the first diode including a body contact of the first NMOS transistor, a cathode of the first diode including a drain contact of the first NMOS transistor, an anode of the second diode including a body contact of the second NMOS transistor, and a cathode of the second diode including a drain contact of the second NMOS transistor. In some embodiments, the first and second clamp circuits include respective first and second PMOS transistors positioned in corresponding n-type doped regions of the substrate, an anode of the first diode including a drain contact of the first PMOS transistor, a cathode of the first diode including a body contact of the first PMOS transistor, an anode of the second diode including a drain contact of the second PMOS transistor, and a cathode of the second diode including a body contact of the second PMOS transistor. In some embodiments, the second electrical connector is configured to electrically connect the first PMOS body contact and the source contact to a first metal interconnect structure configured to distribute a supply voltage level, the third electrical connector is configured to electrically connect the first NMOS body contact and the source contact to a second metal interconnect structure configured to distribute a reference voltage level, and the first clamping circuit is configured to couple the first and second metal interconnect structures to one another in response to a signal received from the trigger circuit.
In some embodiments, a method of manufacturing an IC device includes: constructing a first CMOS structure in a first n-type doped region of the substrate, the constructing the first CMOS structure including forming a first NMOS body contact region, a first NMOS source region, a first PMOS body contact region, and a first PMOS source region; constructing a second CMOS structure in the second n-type doped region of the substrate, the constructing the second CMOS structure including forming a second NMOS body contact region, a second NMOS source region, a second PMOS body contact region, and a second PMOS source region; constructing a first clamping device in a third n-type region of the substrate, the constructing the first clamping device including forming a first diode including a first cathode and a first anode; constructing a second clamping device in a fourth n-type region of the substrate, the constructing the second clamping device including forming a second diode including a second cathode and a second anode; and forming a first plurality of metal segments located on the substrate from the surface of the substrate through the second metal layer of the IC device, wherein forming the first plurality of metal segments includes forming a first electrical connection from the first cathode to each of the first PMOS body contact region and the first PMOS source region, forming a second electrical connection from the first anode to each of the first NMOS body contact region and the first NMOS source region, forming a third electrical connection from the second cathode to each of the second PMOS body contact region and the second PMOS source region, and forming a fourth electrical connection from the second anode to each of the second NMOS body contact region and the second NMOS source region. In some embodiments, constructing each of the first and second clamp devices includes forming an NMOS transistor, and forming each of the first and second diodes includes: forming a corresponding first or second cathode comprising a drain region of the NMOS transistor; and forming a corresponding first or second anode comprising a body contact region of the NMOS transistor. In some embodiments, constructing each of the first and second clamp devices includes forming a PMOS transistor, and forming each of the first and second diodes includes: forming a corresponding first or second cathode comprising a body contact region of the PMOS transistor; and forming a corresponding first or second anode comprising a drain region of the PMOS transistor. In some embodiments, the method includes forming a second plurality of metal segments over the first plurality of metal segments, wherein forming the second plurality of metal segments includes: forming a fifth electrical connection from each of the first and third electrical connections to the first metal interconnect structure configured to distribute a power supply voltage level; forming a sixth electrical connection from each of the second and fourth electrical connections to a second metal interconnect structure configured to distribute a reference voltage level; and forming a portion of a seventh electrical connection from the common drain terminal of the second CMOS structure to the common gate terminal of the first CMOS structure.
It will be apparent to one of ordinary skill in the art that the disclosed one or more embodiments achieve one or more of the advantages set forth above. Numerous variations, equivalents, and numerous other embodiments as broadly disclosed herein will occur to those of ordinary skill in the art upon reading the foregoing description. Accordingly, it is intended that the protection granted hereon be limited only by the definition contained in the appended claims and equivalents thereof.

Claims (10)

1. An integrated circuit device, comprising:
a first CMOS structure positioned in the first n-doped region of the substrate, the first CMOS structure including a common gate terminal, a first NMOS body contact, a first NMOS source contact, a first PMOS body contact, and a first PMOS source contact;
a second CMOS structure positioned in a second n-doped region of the substrate, the second CMOS structure including a common drain terminal, a second NMOS body contact, a second NMOS source contact, a second PMOS body contact, and a second PMOS source contact;
a first electrical connection from the common drain terminal to the common gate terminal;
a first clamping device including a first diode;
A second electrical connection from the cathode of the first diode to each of the first PMOS body contact and the first PMOS source contact; and
a third electrical connection from the anode of the first diode to each of the first NMOS body contact and the first NMOS source contact,
wherein the entirety of each of the second electrical connector and the third electrical connector is positioned between the substrate and a third metal layer of the integrated circuit device.
2. The integrated circuit device of claim 1, further comprising:
a second clamping device including a second diode;
a fourth electrical connection from the cathode of the second diode to each of the second PMOS body contact and the second PMOS source contact; and
a fifth electrical connection from the anode of the second diode to each of the second NMOS body contact and the second NMOS source contact,
wherein the entirety of each of the fourth electrical connector and the fifth electrical connector is positioned between the substrate and a third metal layer of the integrated circuit device.
3. The integrated circuit device of claim 1, wherein the second electrical connection is further connected to an upper metal interconnect structure configured to distribute a supply voltage level.
4. The integrated circuit device of claim 1, wherein the third electrical connection is further connected to an upper metal interconnect structure configured to distribute a reference voltage level.
5. The integrated circuit device of claim 1, further comprising:
a trigger circuit coupled to the first clamp device and configured to output a signal in response to an electrostatic discharge event,
wherein the first clamping device is configured to electrically couple the second electrical connector and the third electrical connector to each other in response to the signal.
6. An integrated circuit device, comprising:
a first CMOS structure positioned in the first n-doped region of the substrate, the first CMOS structure including a common gate terminal, a first NMOS body contact, a first NMOS source contact, a first PMOS body contact, and a first PMOS source contact;
a second CMOS structure positioned in a second n-doped region of the substrate, the second CMOS structure including a common drain terminal, a second NMOS body contact, a second NMOS source contact, a second PMOS body contact, and a second PMOS source contact;
a first electrical connection from the common drain terminal to the common gate terminal; and
A first clamping device comprising a first diode,
wherein the length of the first electrical connection is greater than the length of a first current path comprising:
a second electrical connection from each of the first PMOS body contact and source contact to the cathode of the first diode;
the first diode; and
a third electrical connection from the anode of the first diode to each of the first NMOS body contact and source contact.
7. The integrated circuit device of claim 6, further comprising:
a second clamping device comprising a second diode,
wherein the length of the first electrical connection is greater than the length of a second current path comprising:
a fourth electrical connection from each of the second PMOS body contact and source contact to the cathode of the second diode;
the second diode; and
a fifth electrical connection from the anode of the second diode to each of the second NMOS body contact and the source contact.
8. The integrated circuit device of claim 7, wherein
The first and second clamping devices include respective first and second NMOS transistors positioned in corresponding n-type doped regions of the substrate,
The anode of the first diode includes a body contact of the first NMOS transistor,
the cathode of the first diode includes the drain contact of the first NMOS transistor,
the anode of the second diode includes the body contact of the second NMOS transistor, and
the cathode of the second diode includes a drain contact of the second NMOS transistor.
9. A method of manufacturing an integrated circuit device, the method comprising:
constructing a first CMOS structure in a first n-type doped region of a substrate, wherein constructing the first CMOS structure comprises forming a first NMOS body contact region, a first NMOS source region, a first PMOS body contact region and a first PMOS source region;
constructing a second CMOS structure in a second n-type doped region of the substrate, the constructing the second CMOS structure including forming a second NMOS body contact region, a second NMOS source region, a second PMOS body contact region, and a second PMOS source region;
constructing a first clamping device in a third n-type region of the substrate, the constructing the first clamping device including forming a first diode including a first cathode and a first anode;
constructing a second clamping device in a fourth n-type region of the substrate, the constructing the second clamping device including forming a second diode including a second cathode and a second anode; and
Forming a first plurality of metal segments located on the substrate from a surface of the substrate through a second metal layer of the integrated circuit device, wherein forming the first plurality of metal segments comprises:
forming a first electrical connection from the first cathode to each of the first PMOS body contact region and the first PMOS source region;
forming a second electrical connection from the first anode to each of the first NMOS body contact region and the first NMOS source region;
forming a third electrical connection from the second cathode to each of the second PMOS body contact region and the second PMOS source region; and
a fourth electrical connection is formed from the second anode to each of the second NMOS body contact region and the second NMOS source region.
10. The method of claim 9, further comprising:
forming a second plurality of metal segments over the first plurality of metal segments, wherein forming the second plurality of metal segments comprises:
forming a fifth electrical connection from each of the first electrical connection and the third electrical connection to a first metal interconnect structure configured to distribute a power supply voltage level;
Forming a sixth electrical connection from each of the second electrical connection and the fourth electrical connection to a second metal interconnect structure configured to distribute a reference voltage level; and
a portion of a seventh electrical connection is formed from a common drain terminal of the second CMOS structure to a common gate terminal of the first CMOS structure.
CN202311103855.2A 2022-09-30 2023-08-30 Integrated circuit device and method of manufacturing the same Pending CN117423702A (en)

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US63/387,477 2022-12-14
US18/309,172 2023-04-28
US18/309,172 US20240113099A1 (en) 2022-09-30 2023-04-28 Integrated circuit protection device and method

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