CN117423626A - Wafer processing method and wafer - Google Patents
Wafer processing method and wafer Download PDFInfo
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- CN117423626A CN117423626A CN202311302533.0A CN202311302533A CN117423626A CN 117423626 A CN117423626 A CN 117423626A CN 202311302533 A CN202311302533 A CN 202311302533A CN 117423626 A CN117423626 A CN 117423626A
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- 238000003672 processing method Methods 0.000 title claims abstract description 25
- 229940095676 wafer product Drugs 0.000 claims abstract description 166
- 239000000758 substrate Substances 0.000 claims abstract description 103
- 238000002955 isolation Methods 0.000 claims abstract description 92
- 238000000034 method Methods 0.000 claims abstract description 81
- 230000008569 process Effects 0.000 claims abstract description 64
- 238000012545 processing Methods 0.000 claims abstract description 63
- 239000010410 layer Substances 0.000 claims description 154
- 238000005516 engineering process Methods 0.000 claims description 30
- 230000008021 deposition Effects 0.000 claims description 26
- 238000004140 cleaning Methods 0.000 claims description 12
- 238000001039 wet etching Methods 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 239000011241 protective layer Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 239000010408 film Substances 0.000 description 40
- 238000005530 etching Methods 0.000 description 33
- 238000000151 deposition Methods 0.000 description 26
- 239000000463 material Substances 0.000 description 14
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 238000005468 ion implantation Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 239000010409 thin film Substances 0.000 description 8
- 238000004590 computer program Methods 0.000 description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910010271 silicon carbide Inorganic materials 0.000 description 6
- 239000007789 gas Substances 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- 239000002994 raw material Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 238000010884 ion-beam technique Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 239000007787 solid Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 239000012808 vapor phase Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010891 electric arc Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000010574 gas phase reaction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000006552 photochemical reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000011343 solid material Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Physical Vapour Deposition (AREA)
Abstract
The embodiment of the invention provides a wafer processing method and a wafer, wherein the wafer processing method comprises the steps of arranging an isolation protection layer on a wafer substrate, wherein the isolation protection layer is used for protecting the wafer substrate; setting a stress adjustment layer on the side surface of the isolation protection layer, which is far away from the wafer substrate, to obtain a first wafer product, wherein the stress adjustment layer is used for adjusting the stress of the wafer substrate during processing; carrying out a wafer processing process on the first wafer product to obtain a second wafer product; removing the substrate film of the second wafer product, and removing the isolation protection layer and the stress adjustment layer; carrying out a wafer back process on the second wafer product to obtain a target wafer product; the embodiment of the invention can increase the anti-warping strength of the wafer during forced working by adding the isolation protection layer and the stress adjustment layer of the wafer substrate, optimize the wafer warping, have no influence on the original wafer and ensure the production quality of the wafer.
Description
Technical Field
The present invention relates to the field of semiconductor device manufacturing technology, and in particular, to a wafer processing method and a wafer.
Background
Silicon carbide (SiC) is one of the third-generation semiconductor materials, has the advantages of high breakdown electric field, high thermal conductivity, high saturated electron mobility and the like, and has good development prospect in the field of power devices. With the improvement of the power density of the silicon carbide device, the feature size of the device is reduced, the wafer substrate is developed to the thin-sheet technology, and the size is developed to the large-size high-integration direction, however, due to the specificity of the silicon carbide material and the processing technology, the silicon carbide device is easy to warp during the processing, which severely limits the improvement of the process capability.
In the prior art, the wafer warpage is avoided by performing a related process on the back of the SiC wafer, but the substrate ion type and concentration are affected by directly performing the related process on the back of the wafer, and additional back ion implantation is required to be introduced for balancing; etching on the back of the wafer can affect the substrate thickness distribution, resulting in a damaged wafer quality.
Disclosure of Invention
In view of the foregoing, embodiments of the present invention have been developed to provide a wafer processing method and a wafer that overcome, or at least partially solve, the foregoing problems.
In order to solve the above problems, in a first aspect of the present invention, an embodiment of the present invention discloses a wafer processing method, including:
setting an isolation protection layer on a wafer substrate, wherein the isolation protection layer is used for protecting the wafer substrate;
setting a stress adjustment layer on the side surface of the isolation protection layer, which is far away from the wafer substrate, to obtain a first wafer product, wherein the stress adjustment layer is used for adjusting the stress of the wafer substrate during processing;
carrying out a wafer processing process on the first wafer product to obtain a second wafer product;
removing the substrate film of the second wafer product, and removing the isolation protection layer and the stress adjustment layer;
and carrying out a wafer back process on the second wafer product to obtain a target wafer product.
Optionally, the disposing an isolation protection layer on the wafer substrate includes:
and generating the isolation protection layer on the wafer substrate through deposition growth.
Optionally, the disposing a stress adjustment layer on a side of the isolation protection layer away from the wafer substrate includes:
and generating the stress adjustment layer on the side surface of the isolation protection layer, which is far away from the wafer substrate, through deposition and growth.
Optionally, the step of removing the substrate from the second wafer product includes:
removing the film from the stress adjustment layer on the second wafer product;
and removing the film of the isolation protection layer on the second wafer product.
Optionally, the removing the stress adjustment layer on the second wafer product includes:
and performing dry etching on the second wafer product, and removing the film of the stress adjustment layer.
Optionally, the removing the isolation protection layer on the second wafer product includes:
and carrying out wet etching on the second wafer product, and removing the film of the isolation protection layer.
Optionally, the performing a wafer processing process on the first wafer product to obtain a second wafer product includes:
performing a first front side processing process on the first wafer product to generate a first front side structure of the wafer;
performing a back stress adjustment process on the first wafer product to offset stress generated by the first front processing process;
and performing a second front processing technology on the first wafer product to generate a second front structure of the wafer, and obtaining the second wafer product.
Optionally, the performing a wafer back process on the second wafer product to obtain a target wafer product includes:
and carrying out deposition growth on the back surface of the second wafer product to generate a metal electrode, thereby obtaining the target wafer product.
Optionally, after the removing the substrate film from the second wafer product and removing the isolation protection layer and the stress adjustment layer, the wafer processing method further includes:
and cleaning the back surface of the second wafer product.
In a second aspect of the present invention, an embodiment of the present invention discloses a wafer, which is prepared by the wafer processing method as described above.
The embodiment of the invention has the following advantages:
according to the embodiment of the invention, the isolation protection layer is arranged on the wafer substrate and is used for protecting the wafer substrate; setting a stress adjustment layer on the side surface of the isolation protection layer, which is far away from the wafer substrate, to obtain a first wafer product, wherein the stress adjustment layer is used for adjusting the stress of the wafer substrate during processing; carrying out a wafer processing process on the first wafer product to obtain a second wafer product; removing the substrate film of the second wafer product, and removing the isolation protection layer and the stress adjustment layer; carrying out a wafer back process on the second wafer product to obtain a target wafer product; the stress can be adjusted by the stress adjusting layer on the back of the wafer when the wafer processing technology is carried out so as to offset the stress generated by the wafer processing technology, so that the warp resistance strength of the wafer is enhanced, the risk of wafer warp during the wafer front technology is reduced, and meanwhile, the isolation protection layer is arranged to protect the wafer substrate, so that the influence on the structure and components of the back of the wafer is avoided, and the production quality of the wafer is ensured.
Drawings
FIG. 1 is a flow chart of steps of an embodiment of a wafer processing method of the present invention;
FIG. 2 is a flow chart of steps of another embodiment of a wafer processing method of the present invention;
FIG. 3 is a wafer state diagram illustrating another embodiment of a wafer processing method according to the present invention;
FIG. 4 is a second wafer state diagram illustrating another embodiment of a wafer processing method according to the present invention;
fig. 5 is a schematic diagram of a wafer state according to another embodiment of the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Referring to fig. 1, a flowchart illustrating steps of an embodiment of a wafer processing method according to the present invention may specifically include the following steps:
step 101, setting an isolation protection layer on a wafer substrate, wherein the isolation protection layer is used for protecting the wafer substrate;
an isolation protective layer can be arranged on the back surface of the wafer, namely the wafer substrate, and covers the whole wafer substrate to protect the wafer substrate and prevent structures and components on the wafer substrate from being damaged by other foreign matters.
102, arranging a stress adjustment layer on the side surface of the isolation protection layer away from the wafer substrate to obtain a first wafer product, wherein the stress adjustment layer is used for adjusting the stress of the wafer substrate during processing;
after the isolation protection layer is arranged, a stress adjustment layer is arranged on the isolation protection layer, namely, on the side surface, far away from the wafer substrate, of the isolation protection layer, and the original wafer is prepared into a first wafer product. Wherein the stress adjustment layer completely covers the entire isolation protection layer, i.e., the stress adjustment layer completely covers the entire wafer substrate.
Step 103, performing a wafer processing process on the first wafer product to obtain a second wafer product;
and then carrying out a required processing technology, namely a wafer processing technology, on the first wafer product to generate a required front structure on the front surface of the first wafer product so as to obtain a second wafer product.
104, removing the substrate film of the second wafer product, and removing the isolation protection layer and the stress adjustment layer;
and removing the substrate film from the second wafer product, and removing the isolation protection layer and the stress adjustment layer so as to facilitate subsequent process processing on the back surface of the second wafer product.
And 105, performing a wafer back surface process on the second wafer product to obtain a target wafer product.
And after removing the film from the substrate of the second wafer product, performing a wafer back process on the second wafer product, and processing a required back structure on the back of the second wafer product to obtain the target wafer product.
According to the embodiment of the invention, the isolation protection layer is arranged on the wafer substrate and is used for protecting the wafer substrate; setting a stress adjustment layer on the side surface of the isolation protection layer, which is far away from the wafer substrate, to obtain a first wafer product, wherein the stress adjustment layer is used for adjusting the stress of the wafer substrate during processing; carrying out a wafer processing process on the first wafer product to obtain a second wafer product; removing the substrate film of the second wafer product, and removing the isolation protection layer and the stress adjustment layer; carrying out a wafer back process on the second wafer product to obtain a target wafer product; the stress can be adjusted by the stress adjusting layer on the back of the wafer when the wafer processing technology is carried out so as to offset the stress generated by the wafer processing technology, so that the warp resistance strength of the wafer is enhanced, the risk of wafer warp during the wafer front technology is reduced, and meanwhile, the isolation protection layer is arranged to protect the wafer substrate, so that the influence on the structure and components of the back of the wafer is avoided, and the production quality of the wafer is ensured.
Referring to fig. 2, a flowchart illustrating steps of another embodiment of a wafer processing method of the present invention may specifically include the steps of:
step 201, setting an isolation protection layer on a wafer substrate, wherein the isolation protection layer is used for protecting the wafer substrate;
in the embodiment of the invention, before the wafer processing, the back surface of the wafer, namely the wafer substrate, can be cleaned first and then the subsequent process is carried out, so that the product quality is ensured. The wafer in the embodiment of the invention may be a silicon carbide wafer.
After cleaning, an isolation protective layer may be provided on the wafer substrate, the lattice force protective layer being used to protect the wafer substrate from damage by foreign substances resulting in wafer concentration components and structures.
Specifically, the disposing an isolation protection layer on a wafer substrate includes: and generating the isolation protection layer on the wafer substrate through deposition growth.
In practice, the isolation protective layer may be grown on the wafer substrate by deposition growth. The isolation protection layer should be selected from materials that are lattice matched to the wafer and have a coefficient of thermal expansion close to that of the wafer, while being easily deposited and selectively removed, such as SiO2 (silicon dioxide)/SiNx (silicon nitride)/TaC (tantalum carbide)/AlN (aluminum nitride), etc. The isolation protection layer completely covers the wafer substrate.
The isolation protection layer may be formed by Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD), which is not limited in this embodiment of the present invention. Chemical vapor deposition techniques are those in which a solid thin film is formed and deposited on a substrate surface by chemically reacting preselected reactive species in a vapor phase. The chemical vapor deposition technique may include the steps of: preparing a substrate: a suitable substrate material is selected and cleaned and treated to provide a clean, planar surface. And (3) preparing a reaction gas: appropriate reactant materials and carrier gases are selected and fed into the reaction chamber under specific temperature and pressure conditions. The reactive species may be a gas, liquid or solid, while the carrier gas is primarily used to dilute and transport the reactive species. Gas phase reaction: in the reaction chamber, the reactive species react chemically to form the desired species, such as film components or precursors. Film deposition: the resulting species diffuses and deposits along the substrate surface to form a thin film. The deposition process may be a thermochemical reaction, photochemical reaction, or plasma reaction. Control parameters: parameters such as temperature, pressure, reaction time and reaction gas flow rate of the reaction chamber are controlled to adjust the growth rate, composition and properties of the thin film. Cooling and treating: after the film deposition is completed, the substrate is cooled and the film is subjected to subsequent treatments such as annealing, oxidation, or coating.
Physical vapor deposition techniques form thin films by physically converting a solid material into a vapor phase under vacuum or atmosphere control and depositing the material onto a substrate surface. The physical vapor deposition technique may include the steps of: and (3) evaporation: the raw material (which may be solid, powder or wire block) is heated to an elevated temperature to convert it to a gas phase. The raw materials can be heated by means of electron beam evaporation, magnetron sputtering, anode arc discharge and the like. Sputtering: the surface of the raw material is bombarded with ions of an inert gas (e.g., argon) in a vacuum or atmosphere, such that the raw material is directly transformed from a solid state to a gas phase and forms a thin film via diffusion and deposition. This process is called physical sputtering. Evaporation/sputtering atmosphere control: by adjusting the degree of vacuum and the atmosphere composition, the impurity content, the film composition, the structure, and the like in the atmosphere can be controlled. And (3) deposition: the generated vapor phase species diffuses and deposits along the substrate surface to form a thin film. During deposition, the thin film forms a crystalline or amorphous structure on the substrate surface, depending on the material and deposition conditions. Control parameters: parameters such as the temperature of raw materials, sputtering energy, vacuum degree, atmosphere pressure and the like are controlled to adjust the growth rate, composition and properties of the film. Microstructure regulation: by adjusting the evaporation/sputtering process parameters and the substrate surface characteristics, microstructure characteristics such as grain boundaries, nanoparticle size, orientation, stress and the like of the thin film can be controlled.
By way of one example, the deposited growth of the isolation protection layer is illustrated: taking silicon dioxide as an example, a chemical vapor deposition mode is adopted, a film layer with stress of-50 to-400 MPa (megapascal) can be obtained by adjusting the process, and the thickness can be adjusted from hundreds of angstroms to thousands of angstroms.
Step 202, setting a stress adjustment layer on the side surface of the isolation protection layer away from the wafer substrate to obtain a first wafer product, wherein the stress adjustment layer is used for adjusting the stress of the wafer substrate during processing;
after the isolation protection layer is generated, a stress adjustment layer can be arranged on the side surface, far away from the wafer substrate, of the isolation protection layer, so that a first wafer product is obtained. Referring to fig. 3, a wafer substrate, an isolation protection layer, and a stress adjustment layer are sequentially stacked, and are layered. The stress adjustment layer can be made of material with correlation coefficient between the material of the wafer substrate and the film layer grown in the front side process, and the stress adjustment processes such as ion implantation and etching, such as Si (silicon)/TiN (titanium nitride)/metal, are easy to perform. The correlation coefficient may employ a pearson correlation coefficient (Pearson correlation coefficient).
Specifically, the disposing a stress adjustment layer on a side of the isolation protection layer away from the wafer substrate includes: and generating the stress adjustment layer on the side surface of the isolation protection layer, which is far away from the wafer substrate, through deposition and growth.
In practical applications, the stress adjustment layer may be deposited on the side of the isolation protection layer away from the wafer substrate by deposition growth. The stress adjustment layer may be deposited by chemical vapor deposition, physical vapor deposition, or the like, which is not limited in the embodiment of the present invention. In addition, the isolation protection layer and the stress adjustment layer can be deposited in the same deposition mode, or can be deposited in different deposition modes. The embodiment of the present invention is not limited thereto. For example, the stress adjustment layer is deposited by physical vapor deposition technology, and the isolation protection layer is formed by chemical vapor deposition technology.
In one example of the present invention, tiN may be used as a material and sputtered by physical vapor deposition techniques to provide a stress accommodating layer having a thickness of several hundred angstroms to tens of thousands of angstroms.
Step 203, performing a wafer processing process on the first wafer product to obtain a second wafer product;
after the first wafer product is obtained, a wafer processing technology can be performed on the first wafer product, and the structure required by the front surface of the wafer is processed to obtain a second wafer product.
Specifically, the wafer processing process is performed on the first wafer product to obtain a second wafer product, which includes:
sub-step S2031, performing a first front side processing process on the first wafer product to generate a first front side structure of the wafer;
the first front side processing process may be performed on a wafer product, where the first front side processing process includes, but is not limited to, any one of cleaning, deposition, photolithography, etching, ion implantation, etc. to form a front side structure required for forming a semiconductor device on the front side of the first wafer product, that is, to generate the first front side structure of the wafer.
Sub-step S2032, performing a back side stress adjustment process on the first wafer product to offset stress generated by the first front side processing process;
after the first front side processing technology is performed, a back side stress adjustment technology can be performed on the back side of the first wafer product, and an ion implantation or etching technology is performed on the back side of the first wafer product so as to form a plurality of ion implantation areas or etching grooves on the back side of the first wafer product, so that the stress generated by the back side and the front side ion implantation or etching technology is mutually counteracted. Referring to fig. 4, the back side of the first wafer product is ion implanted to counteract the stress of the front side ion implantation. Referring also to fig. 5, etching trenches into the back side of the first wafer product removes the front side trench stress.
And step S2033, performing a second front side processing process on the first wafer product to generate a second front side structure of the wafer, and obtaining the second wafer product.
And (3) performing a second front side processing process on the first wafer product subjected to the back side stress adjustment process, wherein the second front side processing process comprises any one of cleaning, depositing, photoetching, etching, ion implantation and the like, and finishing all front side processes of the wafer to generate a second front side structure of the wafer, so as to obtain all required front side structures and obtain the second wafer product.
The wafer processing process is illustrated below with examples to yield a second wafer product:
1. taking a MOS (Metal-Oxide-Semiconductor) gate structure as an example:
1. first, the first front side processing technology is carried out to etch the groove (needing cleaning, photoetching and etching),
2. correspondingly etching grooves on the back stress adjustment layer;
3. continuing the second front processing technology (deposition, etching and photoetching) to finish filling the groove and obtain the MOS gate;
2. taking a MOS source drain structure as an example:
1. firstly, performing a first front processing technology, namely depositing, cleaning, photoetching and etching to obtain an ion implantation window, and performing ion implantation;
2. performing a corresponding window process and ion implantation on the back stress adjustment layer;
3. and performing a second front processing technology (deposition, cleaning, photoetching and etching are needed) to obtain a source electrode and a drain electrode, and then performing high-temperature annealing to repair the ion implantation defect.
Step 204, removing the substrate film of the second wafer product, and removing the isolation protection layer and the stress adjustment layer;
and after the second wafer product is obtained, removing the substrate film from the second wafer product, and removing the isolation protection layer and the stress adjustment layer so that the subsequent process can be performed on the back surface of the second wafer product. The isolation protection layer and the stress adjustment layer can be removed by wet etching or dry etching, and the isolation protection layer and the stress adjustment layer can be removed in the same way or in different ways. The embodiment of the present invention is not limited thereto. Among them, wet etching may use chemical reaction to dissolve atoms on the surface of a semiconductor material, and then discharge the dissolved portion thereof into a solution. The dry etching may be physical vapor etching (Physical Vapor Etching, PVE) or chemical vapor etching (Chemical Vapor Etching, CVE). For physical vapor etching may include: electron beam etching (Electron Beam Etching): the surface of the sample is irradiated with an electron beam, and the etching effect is achieved by electron energy transfer. Ion Beam Etching (Ion Beam Etching): the sample surface is bombarded with a high-speed ion beam, and the momentum transfer by the ions causes etching of the surface material. Reactive ion etching (Reactive Ion Etching, RIE): and introducing a reactive ion beam generated by gas discharge into the etching chamber, and etching the material through the reaction of the reactive ions and the surface of the sample. The chemical vapor etching may include: selective etching (Selective Etching) in chemical vapor deposition (Chemical Vapor Deposition, CVD): the film layer obtained by chemical vapor deposition has selectivity and can selectively etch specific materials. Selective etching (Selective Etching) in plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD): the etching is performed by initiating a chemical reaction on the surface by activating the gas with the plasma.
Specifically, the step of removing the film from the substrate from the second wafer product includes: removing the film from the stress adjustment layer on the second wafer product; and removing the film of the isolation protection layer on the second wafer product.
When the substrate is subjected to film removal, the stress adjustment layer can be removed first in the second wafer product to expose the isolation protection layer, and then the isolation protection layer is removed on the second wafer product to complete the integral film removal.
Further, the removing the stress adjustment layer on the second wafer product includes: and performing dry etching on the second wafer product, and removing the film of the stress adjustment layer.
In practical application, the stress adjustment layer can be subjected to film removal by dry etching, isotropy and etching rate are high, and film removal speed is improved.
Further, the removing the isolation protection layer on the second wafer product includes: and carrying out wet etching on the second wafer product, and removing the film of the isolation protection layer.
In practical application, the isolation protection layer can be subjected to film removal by wet etching, the wet etching has strong selectivity, the isolation protection layer can be directionally removed, the damage to the wafer substrate is avoided, and the quality of the wafer is ensured.
Step 205, cleaning the back surface of the second wafer product;
after the film removal is completed, the back surface of the second wafer product can be cleaned, and dirt and residues on the back surface of the second wafer product can be removed.
And step 207, performing a wafer back surface process on the second wafer product to obtain a target wafer product.
After cleaning, the back surface of the second wafer product can be processed, and the wafer back surface process is performed on the second wafer product to generate a back surface structure. Obtaining the target wafer product.
Specifically, the performing a wafer back process on the second wafer product to obtain a target wafer product includes: and carrying out deposition growth on the back surface of the second wafer product to generate a metal electrode, thereby obtaining the target wafer product.
In the embodiment of the invention, the back surface of the second wafer product can be subjected to deposition growth by adopting a chemical vapor deposition technology or a physical vapor deposition technology to generate the metal electrode, so that the target wafer product is obtained.
According to the embodiment of the invention, the isolation protection layer is arranged on the wafer substrate and is used for protecting the wafer substrate; setting a stress adjustment layer on the side surface of the isolation protection layer, which is far away from the wafer substrate, to obtain a first wafer product, wherein the stress adjustment layer is used for adjusting the stress of the wafer substrate during processing; carrying out a wafer processing process on the first wafer product to obtain a second wafer product; removing the substrate film of the second wafer product, and removing the isolation protection layer and the stress adjustment layer; cleaning the back surface of the second wafer product; carrying out a wafer back process on the second wafer product to obtain a target wafer product; the stress can be adjusted by the stress adjusting layer on the back of the wafer when the wafer processing technology is carried out so as to offset the stress generated by the wafer processing technology, so that the warp resistance strength of the wafer is enhanced, the risk of wafer warp during the wafer front technology is reduced, and meanwhile, the isolation protection layer is arranged to protect the wafer substrate, so that the influence on the structure and components of the back of the wafer is avoided, and the production quality of the wafer is ensured.
It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.
The embodiment of the invention also discloses a wafer, which is prepared by the wafer processing method.
In one example of the invention, the wafer may be a silicon carbide wafer.
Specifically, the wafer processing method comprises the following steps:
setting an isolation protection layer on a wafer substrate, wherein the isolation protection layer is used for protecting the wafer substrate;
setting a stress adjustment layer on the side surface of the isolation protection layer, which is far away from the wafer substrate, to obtain a first wafer product, wherein the stress adjustment layer is used for adjusting the stress of the wafer substrate during processing;
carrying out a wafer processing process on the first wafer product to obtain a second wafer product;
removing the substrate film of the second wafer product, and removing the isolation protection layer and the stress adjustment layer;
and carrying out a wafer back process on the second wafer product to obtain a target wafer product.
Optionally, the disposing an isolation protection layer on the wafer substrate includes:
and generating the isolation protection layer on the wafer substrate through deposition growth.
Optionally, the disposing a stress adjustment layer on a side of the isolation protection layer away from the wafer substrate includes:
and generating the stress adjustment layer on the side surface of the isolation protection layer, which is far away from the wafer substrate, through deposition and growth.
Optionally, the step of removing the substrate from the second wafer product includes:
removing the film from the stress adjustment layer on the second wafer product;
and removing the film of the isolation protection layer on the second wafer product.
Optionally, the removing the stress adjustment layer on the second wafer product includes:
and performing dry etching on the second wafer product, and removing the film of the stress adjustment layer.
Optionally, the removing the isolation protection layer on the second wafer product includes:
and carrying out wet etching on the second wafer product, and removing the film of the isolation protection layer.
Optionally, the performing a wafer processing process on the first wafer product to obtain a second wafer product includes:
performing a first front side processing process on the first wafer product to generate a first front side structure of the wafer;
performing a back stress adjustment process on the first wafer product to offset stress generated by the first front processing process;
and performing a second front processing technology on the first wafer product to generate a second front structure of the wafer, and obtaining the second wafer product.
Optionally, the performing a wafer back process on the second wafer product to obtain a target wafer product includes:
and carrying out deposition growth on the back surface of the second wafer product to generate a metal electrode, thereby obtaining the target wafer product.
Optionally, after the removing the substrate film from the second wafer product and removing the isolation protection layer and the stress adjustment layer, the wafer processing method further includes:
and cleaning the back surface of the second wafer product.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The foregoing has outlined a detailed description of a wafer processing method and a wafer in accordance with the present invention, wherein specific examples are provided herein to illustrate the principles and embodiments of the present invention, and the above examples are provided to assist in understanding the method and core concepts of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (10)
1. A method of processing a wafer, comprising:
setting an isolation protection layer on a wafer substrate, wherein the isolation protection layer is used for protecting the wafer substrate;
setting a stress adjustment layer on the side surface of the isolation protection layer, which is far away from the wafer substrate, to obtain a first wafer product, wherein the stress adjustment layer is used for adjusting the stress of the wafer substrate during processing;
carrying out a wafer processing process on the first wafer product to obtain a second wafer product;
removing the substrate film of the second wafer product, and removing the isolation protection layer and the stress adjustment layer;
and carrying out a wafer back process on the second wafer product to obtain a target wafer product.
2. The method of claim 1, wherein disposing an isolation protective layer on the wafer substrate comprises:
and generating the isolation protection layer on the wafer substrate through deposition growth.
3. The method of claim 1, wherein disposing a stress adjustment layer on a side of the isolation protection layer away from the wafer substrate comprises:
and generating the stress adjustment layer on the side surface of the isolation protection layer, which is far away from the wafer substrate, through deposition and growth.
4. The wafer processing method of claim 1, wherein said step of de-filming said second wafer product comprises:
removing the film from the stress adjustment layer on the second wafer product;
and removing the film of the isolation protection layer on the second wafer product.
5. The method of claim 4, wherein the removing the stress adjustment layer from the second wafer product comprises:
and performing dry etching on the second wafer product, and removing the film of the stress adjustment layer.
6. The method of claim 4, wherein the removing the isolation protection layer from the second wafer product comprises:
and carrying out wet etching on the second wafer product, and removing the film of the isolation protection layer.
7. The wafer processing method according to claim 1, wherein the performing a wafer processing process on the first wafer product to obtain a second wafer product comprises:
performing a first front side processing process on the first wafer product to generate a first front side structure of the wafer;
performing a back stress adjustment process on the first wafer product to offset stress generated by the first front processing process;
and performing a second front processing technology on the first wafer product to generate a second front structure of the wafer, and obtaining the second wafer product.
8. The wafer processing method according to claim 1, wherein the performing a wafer backside process on the second wafer product to obtain a target wafer product comprises:
and carrying out deposition growth on the back surface of the second wafer product to generate a metal electrode, thereby obtaining the target wafer product.
9. The wafer processing method according to claim 1, wherein after the removing of the substrate film from the second wafer product, the wafer processing method further comprises:
and cleaning the back surface of the second wafer product.
10. A wafer prepared by the wafer processing method of any one of claims 1-9.
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