CN117423371A - All-optical memory array and method - Google Patents
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Abstract
The invention belongs to the field of all-optical information calculation, and provides an all-optical memory array and a method, wherein the all-optical memory array comprises a plurality of memory units, one end of each memory unit is connected with an input signal, a write control signal, a clear signal and a clock signal, the other end of each memory unit is connected with an output signal bus, and the plurality of memory units are connected in series to form the all-optical memory array; the memory unit comprises an input signal line, a write control signal line, a clearing signal line, a clock signal line and an address signal line; the plurality of storage units are connected in series to form the all-optical memory array, so that the accuracy and the range of data storage are improved, the same amount of information is stored, the number of data bus bars and N times of address bus are saved, and the multiplexing efficiency of the data bus is improved; the data line can be flexibly controlled by combining reading, writing and clearing with an address bus according to the requirement.
Description
Technical Field
The invention belongs to the field of all-optical information calculation, and particularly relates to an all-optical memory array and a method.
Background
All-optical computing and all-optical communication are next generation information technologies replacing electronic computing in the future, are main development directions of the future information technologies, and are key technologies for breaking technical blockages and technical barriers. Due to physical properties such as parallelism and high speed of light, it is possible to develop a high-performance information processing system that is far more than electronic technology. Light computing has therefore become an attractive area of research. The optical signal has very strong anti-interference and confidentiality; the resistance and capacitance resistance are not blocked, and devices such as a resistor and a capacitor are not needed to be added in the optical path for circuit matching, so that the optical path design is simpler than the circuit design. Thus, all-optical computing will become a support technology for all-optical information networks in the future, and all-optical networks and all-optical computers using all-optical signal processing technology will be the mainstream trend of the development of information technology in the future. The all-optical memory is a key function of all-optical calculation, is the core technology for forming all-optical calculation time sequence logic data calculation and storage, and is the core technology point that all-optical calculation and all-optical information exchange are not bypassed as the position of the memory in the electronic field is the same as that of the memory in the electronic field. And the development and layout of the all-optical memory are carried out early, so that the strategic layout in the all-optical technical direction in the future is facilitated, and the competitiveness in the all-optical information technology in the future is improved. It can be used to realize storage, calculation, exchange, data coding, parity check, forwarding, etc. of all-optical signals. All-optical memory arrays are key devices for information storage and calculation combined on the basis of basic all-optical logic gates, and the existing memory arrays are mainly in the field of electronic semiconductors, and a small part of the technology is optical disk type memories based on photoelectric conversion.
Most of the existing memory arrays are in the field of electronic semiconductors, and cannot realize storage, calculation, exchange, data encoding, parity check, forwarding and the like of optical signals; the small part of optical disk type optical memory is based on photoelectric and electro-optical conversion, and the processes of information storage, calculation, exchange, data coding, parity check, forwarding and the like need to be firstly subjected to photoelectric conversion, and then subjected to electro-optical conversion after the processing of an electric domain; high density, large scale integration in the optical domain is inconvenient due to the existence of photoelectric and electro-optical conversion.
Disclosure of Invention
In order to solve at least one technical problem in the background art, the invention provides an all-optical memory array and a method, which adopt a plurality of memory units to form the all-optical memory array in series, thereby improving the accuracy and the range of data storage, storing the same amount of information, saving the number of data bus bars and N times of address bus, and improving the multiplexing efficiency of the data bus; the use flexibility of the data line is improved; the data line can be flexibly controlled by combining reading, writing and clearing with an address bus according to the requirement.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
in a first aspect, the present invention provides an all-optical memory array, including a plurality of memory cells, one end of each memory cell is connected to an input signal, a write control signal, a clear signal and a clock signal, the other end is connected to an output signal bus, and the plurality of memory cells are connected in series to form the all-optical memory array; the memory unit comprises an input signal line, a write control signal line, a clearing signal line, a clock signal line and an address signal line;
the input signal line comprises an optical splitter eight, an optical AND gate first, an optical memory second, an optical AND gate third and a wave combiner fifth which are sequentially connected in series;
the write control signal line comprises a beam splitter nine, an optical AND gate I, an optical memory II, an optical AND gate III and a wave combiner five which are sequentially connected in series;
the clear signal line comprises an eleventh optical splitter, an optical AND gate IV, an optical memory II and a fifth optical combiner which are sequentially connected in series;
the read control signal line comprises a beam splitter ten, an optical AND gate three and a combiner five which are sequentially connected in series;
the clock signal line comprises a light splitter twelve, a light splitter seven, an optical AND gate first and an optical AND gate third which are sequentially connected in series, the light splitter seven is provided with two output ends, the first output end is connected with the optical AND gate first, and the second output end is connected with the optical AND gate third;
the address signal line comprises a beam splitter six, an optical AND gate one, an optical AND gate three and an optical AND gate four which are sequentially connected in series; the optical splitter six is provided with three output ends, the first output end is connected with the optical AND gate four, the second output end is connected with the optical AND gate one, and the third output end is connected with the optical AND gate three.
Further, the first optical and gate is provided with four input ports, the first input port is connected with the optical splitter eight, the second input port is connected with the optical splitter nine, the third input port is connected with the optical splitter six, and the fourth input port is connected with the optical splitter seven.
Further, the optical and gate four is provided with two input ports, the first input port is connected with the optical splitter eleven, and the second input port is connected with the optical splitter six.
Furthermore, the second optical memory is provided with two input ports, the first input port is connected with the fourth optical AND gate, and the second input port is connected with the first optical AND gate.
Further, the optical and gate three has four input ports, the first input port is connected with the optical memory two, the second input port is connected with the optical splitter ten, the third input port is connected with the optical splitter six, and the fourth input port is connected with the optical splitter seven.
In a second aspect, the present invention provides a method for operating an all-optical memory array, including:
when the write control signal, the clock signal and the address signal are simultaneously 1, the first output signal of the optical AND gate is identical to the input signal of the data bus, so that signal gating input is realized;
when any one signal of a write control signal, a clock signal and an address signal is 0, the output of the first optical AND gate is zero, and the input of a signal is forbidden; the output signal of the first optical AND gate is output to the second optical memory, and the second optical memory is output to the third optical AND gate;
when the read control signal, the clock signal and the address signal are 1 at the same time, the output of the optical AND gate III is the same as the output signal of the optical memory II, so that the signal is output to the combiner in a gating way, and the output of the combiner V is used as an output signal;
when any one of the read control signal, the clock signal and the address signal is 0, the output signal of the optical AND gate three is zero, and no signal is output, so that the multiplexer five is not output. The whole memory unit realizes the selective input and output of address signals, clock signals and read-write control signals.
The beneficial effects of the invention are as follows:
1. the invention adopts a plurality of storage units to form an all-optical memory array in series, improves the accuracy and the range of data storage, takes an integer as an example, stores 1-bit data in a numerical range of 0-1 (2^1), stores 2-bit data in a range of 0-3 (2^2), and stores N bits in a range of 0-2-N-1;
2. the invention stores the same amount of information, saves the number of data bus bars and N times of address bus (N is the number of data bits), and improves the multiplexing efficiency of the data bus: only the total storage bit number/N is needed for the data bus and the address bus;
3. the invention controls the bus to read, write and clear only by three, saves 3 times of total storage digits, does not use a storage array, and each storage unit needs one read, write and clear control line.
4. The invention improves the flexibility of the data line. The data line can be flexibly controlled by combining reading, writing and clearing with an address bus according to the requirement.
Additional aspects of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention.
FIG. 1 is a schematic diagram of an all-optical memory array according to the present invention;
1. an optical AND gate I; 2. an optical storage II; 3. An optical AND gate III; 4. an optical AND gate IV; 5. a wave combiner; 6. a beam splitter six; 7. a beam splitter seven; 8. a beam splitter eight; 9. A beam splitter nine; 10. a beam splitter; 11. an eleventh beam splitter; 12. and a beam splitter twelve.
Detailed Description
The invention will be further described with reference to the drawings and examples.
It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the invention. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present invention. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
In the present invention, terms such as "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "side", "bottom", etc. refer to an orientation or a positional relationship based on that shown in the drawings, and are merely relational terms, which are used for convenience in describing structural relationships of various components or elements of the present invention, and do not denote any one of the components or elements of the present invention, and are not to be construed as limiting the present invention.
In the present invention, terms such as "fixedly attached," "connected," "coupled," and the like are to be construed broadly and refer to either a fixed connection or an integral or removable connection; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the terms in the present invention can be determined according to circumstances by a person skilled in the relevant art or the art, and is not to be construed as limiting the present invention.
Term interpretation: memories are a collective term for products such as electronics, magnetism, lasers, chemistry, etc. for temporarily storing or long-term storing data.
And operation (≡): the two data to be operated on are AND operated on by binary bits.
Rules: 0&0 =0, 0& 1=0, 1& 0=0, 1& 1=1;
namely: the two bits are simultaneously '1', and the result is '1', otherwise, the two bits are 0
Or operation (|): the two data to be operated on are OR operated on by binary bit.
Operation rule: 0|0 =0; 0|1 =1; 1|0 =1; 1|1 =1; namely: only one of the two objects participating in the calculation is 1, and the value thereof is 1.
Non-operation: the method comprises the following steps: 1 is 0,0 is 1 to 1=0, 0 to 1 is 1 to (10001) =01110
Exclusive-or operation (): the two data participating in the operation are exclusive-ored according to binary bits.
Operation rule: 0^0 =0; 0^1 =1; 1^0 =1; 1^1 =0; namely: two objects participating in the operation result in a bit of 1 if the two corresponding bits are "exclusive" (different values), and in 0 otherwise.
Example 1
As shown in fig. 1, this embodiment provides an all-optical memory array, taking a 2×2-bit memory cell array (2-bit data) as an example, including a plurality of memory cells, where one end of each memory cell is connected to an input signal, a write control signal, a clear signal and a clock signal, and the other end is connected to an output signal bus, and the plurality of memory cells are connected in series to form the all-optical memory array; the memory unit comprises an input signal line, a write control signal line, a clear signal line, a clock signal line, a read control signal line and an address signal line;
the input signal line comprises an optical splitter eight, an optical AND gate first, an optical memory second, an optical AND gate third and a wave combiner fifth which are sequentially connected in series;
the write control signal line comprises a beam splitter nine, an optical AND gate I, an optical memory II, an optical AND gate III and a wave combiner five which are sequentially connected in series;
the clear signal line comprises an eleventh optical splitter, an optical AND gate IV, an optical memory II and a fifth optical combiner which are sequentially connected in series;
the read control signal line comprises a beam splitter ten, an optical AND gate three and a combiner five which are sequentially connected in series;
the clock signal line comprises a light splitter twelve, a light splitter seven, an optical AND gate first and an optical AND gate third which are sequentially connected in series, the light splitter seven is provided with two output ends, the first output end is connected with the optical AND gate first, and the second output end is connected with the optical AND gate third;
the address signal line comprises a beam splitter six, an optical AND gate one, an optical AND gate three and an optical AND gate four which are sequentially connected in series; the optical splitter six is provided with three output ends, the first output end is connected with the optical AND gate four, the second output end is connected with the optical AND gate one, and the third output end is connected with the optical AND gate three.
Further, the first optical and gate is provided with four input ports, the first input port is connected with the optical splitter eight, the second input port is connected with the optical splitter nine, the third input port is connected with the optical splitter six, and the fourth input port is connected with the optical splitter seven.
Further, the optical and gate four is provided with two input ports, the first input port is connected with the optical splitter eleven, and the second input port is connected with the optical splitter six.
Furthermore, the second optical memory is provided with two input ports, the first input port is connected with the fourth optical AND gate, and the second input port is connected with the first optical AND gate.
Further, the optical AND gate III is provided with four input ports, the first input port is connected with the optical memory II, the second input port is connected with the optical splitter III, the third input port is connected with the optical splitter six, and the fourth input port is connected with the optical splitter seven;
specifically, the second optical storage (2) is a basic storage unit; the first optical AND gate (1) and the third optical AND gate (3) form a basic input port and an output port; the optical splitter eight (8) and the combiner five (5) form an input data bus and an output data bus to be connected with each other by an up-down signal; the beam splitter nine (9) and the optical AND gate one (1) form a control signal bus for outputting; the beam splitter six (6) outputs the address signal in a branching way; the twelve (12) optical splitters and the seven (7) optical splitters output the clock signals in a branching way.
The optical splitter eight is connected with the optical AND gate I, the optical splitter nine is connected with the optical AND gate I, the optical splitter ten is connected with the optical AND gate III, the optical splitter eleven is connected with the optical AND gate IV, the optical splitter six is connected with the optical AND gate I, the optical AND gate III and the optical AND gate IV, the optical splitter twelve is connected with the optical splitter seven, the optical splitter seven is connected with the optical AND gate I, the optical AND gate III and the optical AND gate IV is connected with the memory II; the first optical AND gate is connected with the fourth optical OR gate; the second memory is connected with the third optical AND gate; the optical AND gate III is connected with the wave combiner V.
The linking and function of each storage end member is the same as that of the storage unit and will not be repeated. In the case of a multi-bit data bus, multi-bit memory bits can be expanded, a larger array of memory cells can be formed.
As an embodiment, the optical or gate may employ a passive all-optical logic or gate device (optical or gate patent number: 202020187533.6) comprising a waveguide cavity; the middle part of the front side of the waveguide cavity is provided with a reflector, the front end of the rear side of the waveguide cavity is provided with an input light path, the rear end of the rear side of the waveguide cavity is provided with an output light path, the reflector is connected with a data input light path, and the whole and operation are carried out in an optical state without photoelectric conversion.
As an implementation manner, the optical and gate may adopt a passive all-optical logic and gate (optical and gate patent No. zl202020187543. X), and is provided with a waveguide cavity; four reflectors are respectively arranged on the front side and the rear side of the waveguide cavity, the reflectors are respectively connected with a data input optical path, the left end of the waveguide cavity is connected with an input optical path, and the right end of the waveguide cavity is connected with an output optical path.
As an embodiment, the beam splitter consists of an entrance and an exit slit, a mirror and a dispersive element, which function to separate the desired resonance absorption line.
As an implementation manner, the optical not gate may adopt an all-optical logic not gate device (optical not gate patent number: ZL 202020187470.4), where the all-optical logic not gate device is provided with a waveguide cavity; the middle part of the front side of the waveguide cavity is provided with a reflector, the front end of the rear side of the waveguide cavity is provided with an input light path, the rear end of the rear side of the waveguide cavity is provided with an output light path, and the reflector is connected with a data input light path.
As an implementation manner, the optical memory may be an all-optical memory (optical non-gate patent number: CN 216353343U), which includes a combiner, an optical and gate, and an optical splitter, where the combiner is connected to the optical and gate, the optical and gate is connected to the optical splitter, the combiner, the optical and gate, and the optical splitter can form a closed loop, and the combiner, the optical and gate, and the optical splitter form a closed loop, so that an optical signal is transmitted in the closed loop in a circulating manner, and is regenerated by the optical and gate.
Example two
The embodiment provides a working method of an all-optical memory array, which comprises the following steps:
the principle is as follows: taking the storage unit 1 as an example;
because the optical splitter only changes the number of output ports, the nature of the output signal is not changed, and the logic operation process is not described.
When the write control signal, the clock signal and the address signal are simultaneously 1, the first output signal of the optical AND gate is identical to the input signal of the data bus, so that signal gating input is realized; when any one signal of a write control signal, a clock signal and an address signal is 0, the output of the first optical AND gate is zero, and the input of a signal is forbidden; the output signal of the first optical AND gate is output to the second optical memory, the second optical memory is output to the third optical AND gate, when the read control signal, the clock signal and the address signal are 1 at the same time, the output of the third optical AND gate is the same as the output signal of the second optical memory, the signal gating output to the combiner is realized, and the output of the fifth combiner is used as the output signal; when any one of the read control signal, the clock signal and the address signal is 0, the output signal of the optical AND gate three is zero, and no signal is output, so that the multiplexer five is not output. The whole memory unit realizes the selective input and output of address signals, clock signals and read-write control signals.
When the clearing signal and the address signal are both '1', the output of the optical AND gate IV is '1', the output is output to a zero clearing end of the optical memory II, and the output of the optical memory II is '0', so that signal clearing is realized.
Therefore, the whole memory cell realizes the gating input of the write-in data bus signal, the gating readout of the readout data bus signal and the clearing of the memory signal.
The input end of the memory unit 2 is connected with the bit line of the other writing data bus and the reading data bus, and the memory functions are the same, but the writing, reading and storing of data with different digits are realized.
Different memory cells access bit lines of different write data buses and bit lines of different read buses (e.g., memory cell 1 and memory cell 3, and memory cell 2 and memory cell 4 in this example), memory arrays of different numbers of bits and sizes can be implemented.
Therefore, the whole all-optical memory array can realize storage, reading, writing and clearing of different address signals according to the needs, and can realize expansion of any bit number according to the needs. The greatest benefit is that:
1. the precision and the range of the stored data are improved, taking an integer as an example, a 1-bit data storage numerical value range is 0-1 (2^1), 2-bit data storage is 0-3 (2^2), and N-bit data storage range is 0-2-N-1;
2. the same amount of information is stored, the number of data bus bars and N times of address buses (N is the number of data bits) are saved, and the multiplexing efficiency of the data buses is improved: only the total storage bit number/N is needed for the data bus and the address bus;
3. the read, write and clear control lines of each memory unit are needed to be read, written and cleared.
4. The flexibility of the data line is improved. The data line can be flexibly controlled by combining reading, writing and clearing with an address bus according to the requirement.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. The all-optical memory array is characterized by comprising a plurality of memory units, wherein one end of each memory unit is connected with an input signal, a write control signal, a clear signal and a clock signal, the other end of each memory unit is connected with an output signal bus, and the memory units are connected in series to form the all-optical memory array; the memory unit comprises an input signal line, a write control signal line, a clear signal line, a clock signal line, a read control signal line and an address signal line;
the input signal line comprises an optical splitter eight, an optical AND gate first, an optical memory second, an optical AND gate third and a wave combiner fifth which are sequentially connected in series;
the write control signal line comprises a beam splitter nine, an optical AND gate I, an optical memory II, an optical AND gate III and a wave combiner five which are sequentially connected in series;
the clear signal line comprises an eleventh optical splitter, an optical AND gate IV, an optical memory II and a fifth optical combiner which are sequentially connected in series;
the read control signal line comprises a beam splitter ten, an optical AND gate three and a combiner five which are sequentially connected in series;
the clock signal line comprises a light splitter twelve, a light splitter seven, an optical AND gate first and an optical AND gate third which are sequentially connected in series, the light splitter seven is provided with two output ends, the first output end is connected with the optical AND gate first, and the second output end is connected with the optical AND gate third;
the address signal line comprises a beam splitter six, an optical AND gate one, an optical AND gate three and an optical AND gate four which are sequentially connected in series; the optical splitter six is provided with three output ends, the first output end is connected with the optical AND gate four, the second output end is connected with the optical AND gate one, and the third output end is connected with the optical AND gate three.
2. The all-optical memory array of claim 1 wherein the first optical and gate has four input ports, a first input port connected to the optical splitter eight, a second input port connected to the optical splitter nine, a third input port connected to the optical splitter six, and a fourth input port connected to the optical splitter seven.
3. The all-optical memory array of claim 1 wherein the optical and gate four has two input ports, a first input port connected to the optical splitter eleven and a second input port connected to the optical splitter six.
4. The all-optical memory array of claim 1 wherein the second optical memory has two input ports, a first input port connected to the optical and gate four and a second input port connected to the optical and gate one.
5. The all-optical memory array of claim 1 wherein the optical and gate three has four input ports, a first input port connected to the optical memory two, a second input port connected to the optical splitter ten, a third input port connected to the optical splitter six, and a fourth input port connected to the optical splitter seven.
6. A method of operating an all-optical memory array, comprising:
when the write control signal, the clock signal and the address signal are simultaneously 1, the first output signal of the optical AND gate is identical to the input signal of the data bus, so that signal gating input is realized;
when any one signal of a write control signal, a clock signal and an address signal is 0, the output of the first optical AND gate is zero, and the input of a signal is forbidden; the output signal of the first optical AND gate is output to the second optical memory, and the second optical memory is output to the third optical AND gate;
when the read control signal, the clock signal and the address signal are 1 at the same time, the output of the optical AND gate III is the same as the output signal of the optical memory II, so that the signal is output to the combiner in a gating way, and the output of the combiner V is used as an output signal;
when any one of the read control signal, the clock signal and the address signal is 0, the output signal of the optical AND gate three is zero, and no signal is output, so that the multiplexer five does not output; the whole memory unit realizes the selective input and output of address signals, clock signals and read-write control signals.
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