CN117421176A - Intelligent control method and device for DDR power consumption optimization - Google Patents
Intelligent control method and device for DDR power consumption optimization Download PDFInfo
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Abstract
The invention discloses an intelligent control method and device for DDR power consumption optimization, wherein the method comprises the following steps: step S1: pre-training based on a deep learning model by using a training data set to obtain an application configuration model library between different applications, an optimal initial storage space and an optimal mapping address; step S2: monitoring the change state of the application of the computer chip in real time in the running process of the computer chip; step S3: when the application changes, searching an optimal initial storage space and an optimal mapping address from an application configuration model library according to the current application, and if the initial storage space is not searched, searching the optimal mapping address after the initial storage space is allocated; step S4: and configuring the DDR memory according to the initial memory space and the optimal mapping address which are searched currently, and returning to the step S2 until the control is exited. The invention can realize the intelligent dynamic control of DDR configuration, optimize DDR power consumption and improve the overall energy efficiency of the computer chip.
Description
Technical Field
The invention mainly relates to the technical field of computer chips, in particular to an intelligent control method and device for DDR (double data rate synchronous dynamic random access memory) power consumption optimization.
Background
In the operation process of the high-performance computer chip, the power consumption of the dynamic random access memory DDR occupies the vast majority of the whole power consumption of the chip. In order to reduce the overall power consumption of the high-performance computer chip, it is first necessary to reduce the power consumption of the dynamic random access memory DDR.
In the prior art, in the operation process of a high-performance computer chip, the use of a memory array and the configuration of a mapping address of a dynamic random access memory DDR are controlled according to a fixed mode, that is, the computer chip works in different applications, and the dynamic random access memory DDR uses the memory array and configures the mapping address in the same manner, so that the following problems exist:
1. the dynamic random access memory DDR comprises a plurality of components such as an address input/output buffer, a row/column address decoder, a memory array, a sensitive amplifier, a read-write control circuit and the like, in the running process of a computer chip, the requirements of different application modes on the memory space are different, and if all parts in the dynamic memory are in a working state, a large number of unused or nonsensical memory arrays and related circuits can be kept in the working state, so that a large amount of power consumption is wasted.
2. The address access rules of different applications to the dynamic memory are different, if the proper address mapping configuration can be determined, the frequency of Page Fast Hit (PFH) and Page Hit (PH) can be effectively improved, the frequency of Page Miss (PM) is reduced, the frequency of burst writing/reading use is improved, the number of times of reading/writing precharge can be effectively reduced, the reading/writing efficiency is improved, and meanwhile, the power consumption is further reduced, so that if the uniform address mapping configuration is adopted under different applications, a great amount of power consumption waste is caused.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems existing in the prior art, the invention provides the intelligent control method and the device for DDR power consumption optimization, which have the advantages of simple implementation method, low cost, low power consumption and high overall energy efficiency of a computer chip.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
an intelligent control method for DDR power consumption optimization includes the steps:
step S1: pre-training based on a deep learning model by using a training data set to obtain application configuration model libraries of corresponding relations between different applications and the optimal initial storage space size and between different applications and the optimal mapping addresses for accessing the DDR memory space, wherein the training data set comprises data of the optimal initial storage space size and the optimal mapping addresses for accessing the DDR memory space, which enable the computer chip to have the lowest power consumption under various applications;
step S2: in the running process of the computer chip, monitoring the change state of the application where the computer chip is located in real time;
step S3: when the application where the computer chip is located is monitored to change, searching an optimal initial storage space matched with the current application and an optimal mapping address for accessing the DDR memory space from the application configuration model library according to the current application, and after the initial storage space is allocated for the current application if the initial storage space is not searched, searching the optimal mapping address which enables the power consumption of the current computer chip to be lowest by continuously adjusting the mapping address for accessing the DDR memory space;
step S4: and (3) configuring the DDR memory according to the initial memory space searched currently, accessing the DDR memory according to the optimal mapping address searched, and returning to execute the step (S2) until the control is exited.
Further, in step S1, the size of the initial storage space and the mapping address of the access DDR memory space are adjusted multiple times under different applications, and the power consumption of the computer chip is obtained and judged after each adjustment, if it is judged that the power consumption of the computer chip is in the lowest state and the power consumption variation after the adjustment is continuously specified multiple times is within the preset range, it is judged that the computer chip reaches the power consumption optimal state, and the optimal initial storage space size and the optimal mapping address corresponding to the current application are obtained.
Further, in step S2, if it is monitored that the application where the computer chip is located is not changed during the operation of the computer chip, the active storage array that is currently opened is maintained, and the inactive storage array is closed.
Further, in the step S3, the step of searching the optimal mapping address for minimizing the power consumption of the current computer chip by continuously adjusting the mapping address for accessing the DDR memory space includes:
s301, setting an initial mapping address;
s302, accessing the DDR memory according to the current mapping address;
and S303, judging whether the power consumption of the current computer chip reaches the lowest state and continuously designating the power consumption variation after the adjustment for a plurality of times to be in a preset range, if not, adjusting the current mapping address according to a preset step length, and then returning to the step S302, and if so, outputting the current mapping address as the optimal mapping address obtained by searching.
Further, step S301 includes: and searching the application with the highest similarity with the current application from the application configuration model library, acquiring an optimal mapping address corresponding to the searched application, and taking the optimal mapping address as an initial mapping address of the current application.
Further, in step S3, if it is determined that the target application exceeds the preset number of times, the optimal initial storage space is not searched from the application configuration model library, and the optimal mapping address of the DDR memory space is accessed, the method further includes updating the correspondence between the target application and the initial storage space allocated correspondingly, and between the target application and the searched optimal mapping address to the application configuration model library.
Further, in step S4, after configuring the DDR memory according to the initial memory space searched at present, it is further determined whether the current memory space is sufficient, if yes, step S2 is returned, otherwise, an instruction for expanding the memory array is issued, and the memory array with the specified size is controlled to be opened and closed so as to be allocated to the current application.
An intelligent control device for DDR power consumption optimization, comprising:
the pre-training module is used for pre-training based on a deep learning model by using a training data set to obtain an application configuration model library of the corresponding relation between different applications and the optimal initial storage space size and between different applications and the optimal mapping address of the access memory space, wherein the training data set comprises data of the optimal initial storage space size and the optimal mapping address of the access memory space which enable the power consumption of a computer chip to be lowest under various applications;
the application state monitoring module is used for monitoring the change state of the application where the computer chip is located in real time in the running process of the computer chip;
the application configuration searching module searches an optimal initial storage space matched with the current application and an optimal mapping address for accessing the memory space from the application configuration model library according to the current application when the change of the application in which the computer chip is positioned is monitored, and searches the optimal mapping address which enables the power consumption of the current DDR memory to be lowest by continuously adjusting the mapping address for accessing the memory space after the initial storage space is allocated for the current application if the optimal mapping address is not searched;
and the application configuration adjustment module is used for configuring the DDR memory according to the initial storage space searched currently, accessing the DDR memory according to the optimal mapping address searched, and returning to the execution application state monitoring module until the control is exited.
Further, the system also comprises a power consumption monitoring module which is respectively connected with the pre-training module and the application configuration searching module and is used for acquiring the real-time operation power consumption of the DDR memory and the real-time operation power consumption of other circuits except the DDR memory in the computer chip and calculating to obtain the total power consumption of the computer chip.
A computer chip comprising a DDR memory, further comprising a controller coupled to the DDR memory, the controller for executing the computer program to perform a method as described above.
Compared with the prior art, the invention has the advantages that: the invention forms an application configuration model library by pre-training the optimal initial storage space size and the optimal mapping address which enable the power consumption of the computer chip to be lowest under different applications and learning the corresponding relation between the initial storage space size and the mapping address which affect the power consumption of the computer chip under different applications, and dynamically invokes the application configuration model library according to different applications in the real-time running process of the computer chip, and autonomously and dynamically adjusts the storage array size and the mapping address of the dynamic random access memory DDR according to the application configuration model library, so that the self-adaptive regulation and control form the optimal initial storage space size and the optimal mapping address which are matched with the current application, thereby greatly reducing the overall power consumption of the computer chip and improving the energy efficiency of the whole computer.
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Fig. 1 is a schematic diagram of an implementation flow of an intelligent control method for DDR power consumption optimization in this embodiment.
Fig. 2 is a schematic diagram of an implementation flow of intelligent control of a storage space of a storage array in a computer chip in this embodiment.
Fig. 3 is a schematic flow chart of the implementation of intelligent control of the mapped address of access to the DDR memory in the present embodiment.
Fig. 4 is a schematic diagram showing the overall structure of a computer chip in an embodiment of the present invention.
Detailed Description
The invention is further described below in connection with the drawings and the specific preferred embodiments, but the scope of protection of the invention is not limited thereby.
The memory requirements for different application modes vary in size, and the size of the memory requirements depends on a number of factors, such as the amount of data, the complexity of the code, the complexity of the algorithm, and the type of application. For example, taking an application on a personal notebook computer as an example, if a text editing application, such as WPS, office, etc., is opened, the application mainly stores some text content, format information, pictures, links, etc., and the requirement for memory space is relatively low; for game applications, image applications (such as Adobe Photoshop, GIMP, etc.), scientific applications (such as MATLAB, numPy/SciPy), such applications may involve storing history information, a lot of data, intermediate results, computational models, etc., the memory space requirements are high.
The address access rules of different applications to the dynamic memory are also different, and the access modes of the application programs can be beneficial to optimizing the memory performance and selecting a proper storage mode, so that the efficient reading and writing of data can be ensured. For example, for large database applications (such as oracle, mysql, etc.), a complex data structure needs to be maintained in the memory, and information such as indexes may be maintained in the storage space, so for such applications, if the indexes can be quickly mapped to find the specific addresses of the required data, the efficiency is higher than that of the diffuse non-purpose searching, and if the address mapping can be adjusted to quickly find the areas where the DDR stores the indexes, the efficiency of the application can be effectively improved.
Compared with single byte writing/reading, the same effect is achieved, if the proper address mapping configuration can be determined, the reading and writing efficiency is higher, and the power consumption is lower. For example, if the DDR memory uses burst access when accessing a certain data volume, 8 or 4 memory cells can be determined according to the access column address when accessing any time; conversely, if DDR uses more single byte write/read, it may be necessary to reselect row/column (row) and even page (page) after each access is completed, so that there is a charge-discharge operation, which results in reduced efficiency and increased DDR power consumption, and therefore needs to be as adjacent as possible when storing related data.
Considering the above relation between the application and the memory, the DDR power consumption of the dynamic random access memory has a larger proportion in the total power consumption of the computer chip, and in order to reduce the overall power consumption of the computer chip, the DDR power consumption of the dynamic random access memory needs to be optimized. As shown in fig. 1, the steps of the intelligent control method for DDR power consumption optimization in this embodiment include:
step S1: pre-training based on a deep learning model by using a training data set to obtain application configuration model libraries of corresponding relations between different applications and the optimal initial storage space size and between different applications and the optimal mapping addresses for accessing the DDR memory space, wherein the training data set comprises data of the optimal initial storage space size and the optimal mapping addresses for accessing the DDR memory space, which enable the computer chip to have the lowest power consumption under various applications;
step S2: in the running process of the computer chip, monitoring the change state of the application where the computer chip is located in real time;
step S3: when the application where the computer chip is located is monitored to change, searching an optimal initial storage space matched with the current application from an application configuration model library according to the current application, and accessing an optimal mapping address of the DDR memory space, and after the initial storage space is allocated for the current application if the optimal mapping address is not searched, searching an optimal mapping address which enables the power consumption of the current computer chip to be lowest by continuously adjusting the mapping address accessing the DDR memory space;
step S4: and (3) configuring the DDR memory according to the initial memory space searched currently, accessing the DDR memory according to the optimal mapping address searched, and returning to execute the step (S2) until the control is exited.
According to the embodiment, the optimal initial storage space size and the optimal mapping address which enable the power consumption of the computer chip to be lowest under different applications are pre-trained, the corresponding relation between the initial storage space size and the mapping address which affect the power consumption of the computer chip under different applications is learned, an application configuration model library is formed, the application configuration model library is dynamically called according to different applications in the real-time running process of the computer chip, and the storage array size and the mapping address of the dynamic random access memory DDR are autonomously and dynamically adjusted according to the application configuration model library, so that the optimal initial storage space size and the optimal mapping address which are matched with the current application are formed through self-adaptive regulation, the overall power consumption of the computer chip is greatly reduced, the energy efficiency of the whole computer is improved, and the lowest power consumption is achieved under the condition of meeting the requirements of different applications.
In step S1 of this embodiment, the size of the initial storage space and the mapping address of the access DDR memory space are adjusted multiple times under different applications, and the power consumption of the computer chip is obtained after each adjustment to determine, if it is determined that the power consumption of the computer chip is in the lowest state and the power consumption variation after the adjustment is continuously specified multiple times is within the preset range, the computer chip is determined to reach the power consumption optimal state, so as to obtain the optimal initial storage space size and the optimal mapping address corresponding to the current application, that is, the initial storage space size and the mapping address are determined under the condition that the subsequent multiple applications consume the corresponding optimal effect on the basis of the initial array power consumption.
In a specific application embodiment, a power consumption monitoring module is integrated on a computer chip to monitor the power consumption of a DDR memory and a rest circuit in the running process of the computer chip respectively, so as to calculate the total power consumption of the computer chip; in the pre-training stage, the mapping address and the initial storage array size of the DDR module are respectively and repeatedly adjusted under various common applications of the high-performance computer chip, wherein the storage space size is kept unchanged when the optimal mapping address is searched, and the mapping address is ensured to be unchanged when the optimal storage space size is searched; and controlling to configure the DDR memory according to the adjusted mapping address and the initial memory array size, judging whether the power consumption of the computer chip is at the lowest or not according to the power consumption information fed back by the power consumption monitoring module, adjusting the DDR memory space size and the mapping address according to the power consumption feedback, recording the optimal initial memory array size and the optimal mapping address which can enable the whole power consumption of the computer chip to be optimal under each working application, forming a training data set, and pre-training the formed training data set by using a self-learning and deep learning method to obtain an initial application configuration model library. In the application configuration model library, the corresponding relation between different applications and the optimal mapping address and between different applications and the optimal initial storage array space are formed.
In step S2 of this embodiment, if it is monitored that the application where the computer chip is located is not changed during the running process of the computer chip, the active storage array that is currently opened is maintained, and the inactive storage array is closed, so that the current application requirement can be maintained, effective data is ensured not to be lost, and meanwhile, unnecessary storage array usage is reduced as much as possible. The term "useless" refers to no data stored, previous data failed, or data of the storage array that need not be preserved.
In step S3 of this embodiment, if the current application is not in the application configuration model library, searching for the optimal mapping address with the lowest power consumption of the current computer chip by continuously adjusting the mapping address accessing the DDR memory space, that is, dynamically adjusting in real time to search for the optimal mapping address, including:
s301, setting an initial mapping address;
s302, accessing the DDR memory according to the current mapping address;
and S303, judging whether the power consumption of the current computer chip reaches the lowest state and continuously designating the power consumption variation after the adjustment for a plurality of times to be in a preset range, if not, adjusting the current mapping address according to a preset step length, and then returning to the step S302, and if so, outputting the current mapping address as the searched optimal mapping address.
In the above step S301 of the present embodiment, specifically, an application with the highest similarity to the current application is found out from the application configuration model library, and the optimal mapping address corresponding to the found application is obtained, and the optimal mapping address is used as the initial mapping address of the current application. If the current application is not in the application configuration model library, in order to avoid blindness of initial mapping address setting, the application closest to the current application can be first searched from the application configuration model library, the power consumption requirements similar to and corresponding to the application type are usually relatively close, and the optimal mapping address corresponding to the closest application is used as the initial mapping address of the current application, so that the efficiency of mapping address searching can be accelerated.
In step S3 of this embodiment, if it is determined that there is a target application that exceeds the preset number of times, the optimal initial storage space is not searched from the application configuration model library, and the optimal mapping address of the DDR memory space is accessed, that is, the target application is not in the application configuration model library and the target application frequently appears multiple times, the method further includes updating the correspondence between the target application and the corresponding allocated initial storage space and the correspondence between the target application and the searched optimal mapping address to the application configuration model library. The updating mode can be directly added into the application configuration model library, if the storage space of the application configuration model library is insufficient, the information corresponding to the application with low frequency is deleted, or a rolling updating mode can be adopted, namely, the application to be updated replaces the application with the lowest frequency in the application configuration model library each time, and the application can be specifically configured according to actual requirements.
In step S4 of this embodiment, after configuring the DDR memory according to the initial storage space that is currently searched, determining whether the current storage space is sufficient, if yes, returning to step S2, otherwise, issuing an instruction to expand the storage array, and controlling to open and close the storage array with the specified size to be allocated to the current application, so as to reasonably adjust the size of the storage space according to the requirement of the application, thereby significantly reducing power consumption.
As shown in fig. 2, considering that the requirements of different applications on the memory space are different, the embodiment realizes the intelligent control of the memory array of the DDR memory by opening or closing the memory array with corresponding size according to the requirements of different applications. The method comprises the steps of pre-training an application configuration model library under a common computer application through autonomous learning and deep learning in advance, namely finding out the optimal initial storage array size required by the application under most conditions according to the principle of the second law and the eighth law, and determining the optimal initial space size under the application according to feedback information of power consumption. In the running process of the computer chip, the storage arrays with corresponding sizes are opened or closed for different applications according to the application configuration model library, and the opened storage arrays are maintained in the process, so that effective data are not lost, and useless storage arrays are closed (completely powered off and do not perform precharge operation). If the application configuration model library does not have the current application, the initial storage space is directly allocated. When the computer application needs more storage space, an instruction for expanding the storage array is sent out, and the size of the storage space is adjusted.
As shown in fig. 3, the rule of accessing the memory space by different applications is different, and the power consumption can be reduced by adaptively adjusting the optimal address mapping under different applications. For a certain computer application, it is first checked whether it exists in the application configuration model library, and if so, the address mapping is directly adjusted to the best mapped address of the application. If the application is not in the configuration library, control dynamically adjusts the mapping address to search for the best mapping address. If the application condition occurs for a plurality of times, namely the application is frequently used, the optimal mapping address of the application is updated into the configuration library. After the adjustment is completed, the computer application is checked again, and the above steps are repeated circularly to realize the self-adaptive adjustment of the computer application and the dynamic memory mapping address.
The intelligent control device facing DDR power consumption optimization in the embodiment comprises:
the pre-training module is used for pre-training based on a deep learning model by using a training data set to obtain an application configuration model library of the corresponding relation between different applications and the optimal initial storage space size and between different applications and the optimal mapping address of the access memory space, wherein the training data set comprises data of the optimal initial storage space size and the optimal mapping address of the access memory space which enable the power consumption of the computer chip to be lowest under various applications;
the application state monitoring module is used for monitoring the change state of the application where the computer chip is located in real time in the running process of the computer chip;
the application configuration searching module searches an optimal initial storage space matched with the current application and an optimal mapping address for accessing the memory space from the application configuration model library according to the current application when the change of the application in which the computer chip is positioned is monitored, and searches the optimal mapping address which enables the power consumption of the current DDR memory to be lowest by continuously adjusting the mapping address for accessing the memory space after the initial storage space is allocated for the current application if the optimal mapping address is not searched;
and the application configuration adjustment module is used for configuring the DDR memory according to the initial storage space searched currently, accessing the DDR memory according to the optimal mapping address searched, and returning to the execution application state monitoring module until the control is exited.
In this embodiment, the power consumption monitoring module is further connected to the pre-training module and the application configuration searching module, so as to obtain real-time operation power consumption of the DDR memory in the computer chip and real-time operation power consumption of other circuits except the DDR memory, and calculate the total power consumption of the computer chip.
In a specific application embodiment, as shown in fig. 4, the DDR memory includes a controller, a PHY, an address input buffer, an address strobe (Bank/row/column), a memory array and charge-discharge circuit, a sense amplifier, a read-write control circuit, an input/output buffer, a register, and the like, which are sequentially connected. The pre-training module, the application state monitoring module and the application configuration adjusting module are integrated in one controller chip, and meanwhile, a power consumption judging module is integrated in the computer chip to be used for monitoring the power consumption of the DDR memory and other circuits in real time, further, the total power consumption of the whole computer chip is calculated, chip power consumption information is fed back to the controller chip, and the controller chip adaptively adjusts the mapping address and the initial storage space size of the DDR memory according to different applications based on the power consumption feedback information. In the pre-training stage, the controller chip judges the performance of the current mapping address and the initial storage space according to the power consumption information fed back by the power consumption monitoring module by adjusting the mapping address and the initial storage space for a plurality of times under various common applications until the power consumption of the chip is not obviously optimized, the adjusted address is used as the optimal mapping address of the application and the modulated initial storage space is used as the optimal initial storage space of the application, and the two addresses are recorded and stored to finally form an application configuration model library so as to be used for quickly adjusting the address mapping and opening the proper storage space to reduce the power consumption when different applications are switched.
After the pre-training is finished, the controller chip is put into practical use. In actual use, the controller chip checks in real time whether the current application of the computer chip is changed. If the application is unchanged, the controller chip will control the DDR to maintain the current configuration, maintain the existing active memory array, and decide whether to enlarge the memory array according to the memory usage of the current application. If the application changes, then it continues to determine if the new application exists in the configuration library. If a new application exists in the configuration library, the controller chip will open the optimal initial storage space for that application and close the storage array that was not used by the previous application based on the information in the configuration library. Otherwise, the controller chip will allocate an initial memory space (i.e., an unknown new application allocates a certain memory space first). And for the new application which is used for multiple times, if the application configuration model library does not have corresponding information, the optimal initial storage space size is obtained according to statistics of multiple use conditions, and the data is updated into the configuration library. After the adjustment is finished, checking whether the current application of the computer changes or not again, and repeating the steps circularly to finish the self-adaptive adjustment of the DDR storage space size when the application of the computer changes.
In the running process of the computer chip, the output of the controller chip is used as a control signal to be transmitted to each component of the DDR module to control the mapping address, the storage array size, the read-write behavior and the like. Specifically, address mapping adjustment is performed according to different applications, current power consumption is used as a reference, and the adjustment is adopted only when the adjusted power consumption is smaller than the previous power consumption. And simultaneously, the use and the closing of the storage array are adaptively controlled, the array for storing effective data is maintained, the useless array is closed, and if the application is switched, the initial array of the application is distributed in time. Finally, the DDR module and related components after adjustment are controlled to cause the change of the power consumption of the computer, the power consumption change is fed back to the power consumption judging module, the processed power consumption information is transmitted to the controller chip, the controller chip determines whether to adjust again and how to adjust, iterative optimization is continuously carried out, and a control loop which is iterated repeatedly and automatically adapts is formed.
The embodiment also provides a computer chip comprising a DDR memory and a controller connected with the DDR memory, wherein the controller is used for executing a computer program to execute the method.
It will be understood that the method in this embodiment may be performed by a single device, for example, a computer or a server, or may be implemented by a plurality of devices in a distributed scenario, where one device of the plurality of devices may perform only one or more steps in the method in this embodiment, and the plurality of devices interact to implement the method. The processor may be implemented as a general-purpose CPU, a microprocessor, an application-specific integrated circuit, or one or more integrated circuits, etc. for executing the relevant program to implement the methods described in this embodiment. The memory may be implemented in the form of read-only memory ROM, random access memory RAM, static storage devices, dynamic storage devices, etc. The memory may store an operating system and other application programs, and when the methods of the present embodiments are implemented in software or firmware, the associated program code is stored in the memory and invoked for execution by the processor.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the invention without departing from the principles thereof are intended to be within the scope of the invention as set forth in the following claims.
Claims (10)
1. The intelligent control method for DDR power consumption optimization is characterized by comprising the following steps:
step S1: pre-training based on a deep learning model by using a training data set to obtain application configuration model libraries of corresponding relations between different applications and the optimal initial storage space size and between different applications and the optimal mapping addresses for accessing the DDR memory space, wherein the training data set comprises data of the optimal initial storage space size and the optimal mapping addresses for accessing the DDR memory space, which enable the computer chip to have the lowest power consumption under various applications;
step S2: in the running process of the computer chip, monitoring the change state of the application where the computer chip is located in real time;
step S3: when the application where the computer chip is located is monitored to change, searching an optimal initial storage space matched with the current application and an optimal mapping address for accessing the DDR memory space from the application configuration model library according to the current application, and after the initial storage space is allocated for the current application if the initial storage space is not searched, searching the optimal mapping address which enables the power consumption of the current computer chip to be lowest by continuously adjusting the mapping address for accessing the DDR memory space;
step S4: and (3) configuring the DDR memory according to the initial memory space searched currently, accessing the DDR memory according to the optimal mapping address searched, and returning to execute the step (S2) until the control is exited.
2. The intelligent control method for DDR power consumption optimization according to claim 1, wherein in step S1, the initial memory space size and the mapping address of the access DDR memory space are adjusted for multiple times under different applications, the power consumption of the computer chip is obtained for judgment after each adjustment, and if the power consumption of the computer chip is judged to be in the lowest state and the power consumption variation after continuous appointed adjustment is in the preset range, the computer chip is judged to reach the power consumption optimal state, and the optimal initial memory space size and the optimal mapping address corresponding to the current application are obtained.
3. The intelligent control method for DDR power consumption optimization according to claim 1, wherein in step S2, if no change in the application where the computer chip is located is monitored during the operation of the computer chip, the active memory array that is currently open is maintained, and the inactive memory array is closed.
4. The intelligent control method for DDR power consumption optimization according to claim 1, wherein in step S3, the step of searching for the optimal mapped address that minimizes the power consumption of the current computer chip by continuously adjusting the mapped address that accesses the DDR memory space comprises:
s301, setting an initial mapping address;
s302, accessing the DDR memory according to the current mapping address;
and S303, judging whether the power consumption of the current computer chip reaches the lowest state and continuously designating the power consumption variation after the adjustment for a plurality of times to be in a preset range, if not, adjusting the current mapping address according to a preset step length, and then returning to the step S302, and if so, outputting the current mapping address as the optimal mapping address obtained by searching.
5. The intelligent control method for DDR power consumption optimization according to claim 4, wherein step S301 comprises: and searching the application with the highest similarity with the current application from the application configuration model library, acquiring an optimal mapping address corresponding to the searched application, and taking the optimal mapping address as an initial mapping address of the current application.
6. The intelligent control method for DDR power consumption optimization according to any one of claims 1 to 5, wherein in step S3, if it is determined that there is a target application exceeding the preset number of times, the optimal initial storage space is not searched from the application configuration model library, the optimal mapping address of the DDR memory space is accessed, and further comprising updating the correspondence between the target application and the corresponding allocated initial storage space and between the target application and the searched optimal mapping address to the application configuration model library.
7. The intelligent control method for DDR power consumption optimization according to any one of claims 1 to 5, wherein in step S4, after configuring the DDR memory according to the initial memory space currently searched, further comprises determining whether the current memory space is sufficient, if yes, returning to step S2, otherwise, issuing an instruction for expanding the memory array, and controlling to open and close the memory array with the specified size to be allocated to the current application.
8. DDR power consumption optimization-oriented intelligent control device is characterized by comprising:
the pre-training module is used for pre-training based on a deep learning model by using a training data set to obtain an application configuration model library of the corresponding relation between different applications and the optimal initial storage space size and between different applications and the optimal mapping address of the access memory space, wherein the training data set comprises data of the optimal initial storage space size and the optimal mapping address of the access memory space which enable the power consumption of a computer chip to be lowest under various applications;
the application state monitoring module is used for monitoring the change state of the application where the computer chip is located in real time in the running process of the computer chip;
the application configuration searching module searches an optimal initial storage space matched with the current application and an optimal mapping address for accessing the memory space from the application configuration model library according to the current application when the change of the application in which the computer chip is positioned is monitored, and searches the optimal mapping address which enables the power consumption of the current DDR memory to be lowest by continuously adjusting the mapping address for accessing the memory space after the initial storage space is allocated for the current application if the optimal mapping address is not searched;
and the application configuration adjustment module is used for configuring the DDR memory according to the initial storage space searched currently, accessing the DDR memory according to the optimal mapping address searched, and returning to the execution application state monitoring module until the control is exited.
9. The intelligent control device for optimizing DDR power consumption according to claim 8, further comprising a power consumption monitoring module connected with the pre-training module and the application configuration searching module respectively, wherein the power consumption monitoring module is used for obtaining real-time operation power consumption of the DDR memory and real-time operation power consumption of other circuits except the DDR memory in the computer chip, and calculating to obtain total power consumption of the computer chip.
10. A computer chip comprising a DDR memory, further comprising a controller coupled to the DDR memory, the controller configured to execute the computer program to perform the method of any of claims 1-7.
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