CN117412617B

CN117412617B - Laminated solar cell, manufacturing method thereof, photovoltaic module and photovoltaic system

Info

Publication number: CN117412617B
Application number: CN202311726633.6A
Authority: CN
Inventors: 徐业; 崔标; 陈兰芬
Original assignee: Trina Solar Co Ltd
Current assignee: Trina Solar Co Ltd
Priority date: 2023-12-15
Filing date: 2023-12-15
Publication date: 2024-04-19
Anticipated expiration: 2043-12-15
Also published as: CN117412617A

Abstract

The application relates to the technical field of solar cells, in particular to a laminated solar cell, a manufacturing method thereof, a photovoltaic module and a photovoltaic system. In an embodiment of the application, the stacked solar cell at least comprises a first cell, a connection layer and a second cell, wherein the orthographic projections of the first cell and the second cell on the reference plane have overlapping projections. By configuring the area of the orthographic projection of the connection layer on the reference surface to be smaller than the area of the overlapping projection, the connection layer does not cover the side surfaces of the first cell and the second cell facing each other, and the portions of the side surfaces of the first cell and the second cell facing each other can be in contact with each other. Therefore, the optical parasitic absorption of the connecting layer is reduced, the optical loss of the laminated solar cell is further improved, and the short-circuit current density between the first cell and the second cell is improved, so that the efficiency of the laminated solar cell is improved.

Description

Laminated solar cell, manufacturing method thereof, photovoltaic module and photovoltaic system

Technical Field

The application relates to the technical field of solar cells, in particular to a laminated solar cell, a manufacturing method thereof, a photovoltaic module and a photovoltaic system.

Background

Typically, the stacked solar cells connect the bottom cell and the top cell through a connection layer. However, the connection layer easily causes optical loss of the stacked solar cell, thereby affecting the efficiency of the stacked solar cell.

Disclosure of Invention

Accordingly, there is a need for a stacked solar cell, a method of manufacturing the same, a photovoltaic module, and a photovoltaic system that improve optical loss of the stacked solar cell and improve efficiency of the stacked solar cell.

According to an aspect of the present application, an embodiment of the present application provides a stacked solar cell including a first cell, a connection layer, and a second cell, which are sequentially stacked in a first direction; orthographic projections of the first cell and the second cell on the reference plane have overlapping projections; the first direction is the thickness direction of the laminated solar cell, and the reference surface is a plane perpendicular to the first direction;

The orthographic projection of the connecting layer on the reference surface is positioned in the overlapping projection range, and the orthographic projection area of the connecting layer on the reference surface is smaller than the overlapping projection area;

portions of one side surfaces of the first and second batteries facing each other are in contact with each other.

In one embodiment, at least part of the outline of the orthographic projection of the connection layer on the reference plane is located within the outer outline of the overlapping projections.

In one embodiment, the orthographic projection of the connecting layer on the reference plane has a contour which lies entirely within the outer contour of the overlapping projections.

In one embodiment, the portion of the orthographic projection profile of the connection layer on the reference surface is located within the outer contour of the overlapping projections; the remaining part of the orthographic projection of the connecting layer on the reference plane and the part of the outer contour of the overlapping projection coincide with each other.

In one embodiment, the overlapping projections include a first overlapping projection and a second overlapping projection, the first overlapping projection overlapping with an orthographic projection of the connection layer on the reference plane; the orthographic projection of the portion of the side surfaces of the first cell and the second cell facing each other, which are in contact with each other, on the reference plane is located within the second overlapping projection.

In one embodiment, one of the first overlapping projection and the second overlapping projection comprises a plurality of sub-overlapping projections, at least part of the sub-overlapping projections of the plurality of sub-overlapping projections being arranged in a preset law.

In one embodiment, the preset rule includes at least one of unidirectional arrangement and array arrangement.

In one embodiment, at least some of the sub-overlapping projections are arranged in rows along the second direction and in columns along the third direction;

The second direction and the third direction intersect each other and are both perpendicular to the first direction.

In one embodiment, the at least partially overlapping projections comprise a plurality of first overlapping projections and a plurality of second overlapping projections;

All the first sub-overlapping projections are arranged in an extending mode along the fourth direction and are arranged at intervals along the fifth direction; all the second sub-overlapping projections are arranged at intervals along the fourth direction; each second sub-overlap projection is connected with any one of all the first sub-overlap projections;

The fourth direction and the fifth direction intersect each other and are both perpendicular to the first direction.

In one embodiment, the first overlapping projection comprises a plurality of sub-overlapping projections;

the connecting layer comprises a plurality of connecting parts, and the orthographic projection of the connecting parts on the reference plane defines a plurality of sub-overlapping projections.

In one embodiment, the shape of the cross section of the connecting portion along the first preset direction includes at least one of a regular pattern and an irregular pattern;

The first preset direction and the first direction are perpendicular to each other.

In one embodiment, the second overlapping projection comprises a plurality of sub-overlapping projections;

The connecting layer is provided with a plurality of openings, and the orthographic projection of the plurality of openings on the reference surface defines a plurality of sub-overlapping projections.

In one embodiment, the shape of the cross section of the opening along the second preset direction comprises any one or more of a regular pattern and an irregular pattern;

The second preset direction and the first direction are perpendicular to each other.

In one embodiment, the shape of the sub-overlapping projections includes any one or more combinations of regular patterns, irregular patterns.

In one embodiment, the second cell includes a first charge transport layer laminated to a side of the connection layer facing away from the first cell; a portion of the first charge transport layer is in contact with the connection layer and another portion is in contact with the first cell;

wherein the conductivity of the first charge transport layer is greater than 10 ^-5 S/cm and less than 10S/cm.

When the size of the first charge transport layer along the first direction is 300nm-700nm, the transmittance of the first charge transport layer is 1% -100%; when the size of the first charge transport layer along the first direction is 700nm-1200nm, the transmittance of the first charge transport layer is 95% -100%.

In one embodiment, the ratio of the orthographic projected area of the connecting layer on the reference plane to the overlapping projected area is a preset ratio q; the preset ratio q satisfies the condition: q is more than or equal to 0.1 and less than 1.

In one embodiment, the first cell has a first surface disposed toward the second cell; the first surface has a first side facing the second cell and a second side facing away from the second cell;

wherein the connecting layer is positioned on the first side of the first surface; or alternatively

One part of the connecting layer is positioned on the first side of the first surface, and the other part of the connecting layer is positioned on the second side of the first surface.

In one embodiment, the material of the connection layer is transparent conductive oxide.

In one embodiment, the material of the connection layer includes any one or more of indium tin oxide, aluminum doped zinc oxide, indium doped zinc oxide, and fluorine doped tin oxide.

In one embodiment, the dimension of the connection layer along the first direction is greater than 0nm and less than or equal to 100nm.

In one embodiment, the stacked solar cell further comprises a transparent conductive layer;

the transparent conductive layer is connected between the connection layer and the first cell, and portions of one side surfaces of the transparent conductive layer and the second cell facing each other are in contact with each other.

In one embodiment, the transparent conductive layer is made of transparent conductive oxide, and the connecting layer is made of metal.

In one embodiment, the transparent conductive layer is made of any one or more of indium tin oxide, aluminum doped zinc oxide, indium doped zinc oxide, and fluorine doped tin oxide; and/or

The material of the connecting layer comprises any one or more of gold, silver, copper, iron, aluminum and platinum.

In one embodiment, the dimension of the connection layer along the first direction is greater than 0nm and less than or equal to 20nm;

the transparent conductive layer has a dimension along the first direction greater than 0nm and less than or equal to 100nm.

In one embodiment, the first cell is one of a heterojunction cell, a tunnel oxide passivation contact cell, or an emitter backside passivation cell, and the second cell is a perovskite cell.

According to another aspect of the present application, an embodiment of the present application provides a method for manufacturing a stacked solar cell, including:

Providing a first battery;

forming a connection layer on one side of the first cell in the first direction; orthographic projection of the connecting layer on the reference surface is positioned in an orthographic projection range of the first battery on the reference surface; the area of orthographic projection of the connecting layer on the reference surface is smaller than that of the first battery;

manufacturing a second cell on one side of the connecting layer, which is away from the first cell, to form a laminated solar cell; orthographic projections of the first cell and the second cell on the reference plane overlap each other, and portions of the side surfaces of the first cell and the second cell facing each other are in contact with each other;

The first direction is the thickness direction of the laminated solar cell, and the reference plane is a plane perpendicular to the first direction.

In one embodiment, before forming the connection layer on one side of the first cell in the first direction, the method includes:

Forming a transparent conductive layer on one side of the first cell along the first direction;

the connecting layer is formed on one side of the transparent conducting layer, which is away from the first battery.

In one embodiment, forming a connection layer on one side of the first cell in the first direction includes:

Forming a connecting layer on one side of the first battery along the first direction through a preset process; the preset process comprises any one or more of a mask process and a laser etching process.

According to yet another aspect of the present application, embodiments of the present application provide a photovoltaic module comprising the stacked solar cell of any of the above embodiments; or alternatively

The laminated solar cell manufactured by the manufacturing method of the laminated solar cell in any embodiment is included.

According to still another aspect of the present application, an embodiment of the present application provides a photovoltaic system including the photovoltaic module of any one of the above embodiments.

In the laminated solar cell, the manufacturing method thereof, the photovoltaic module and the photovoltaic system, the laminated solar cell at least comprises a first cell, a connecting layer and a second cell, and orthographic projections of the first cell and the second cell on a reference plane have overlapped projections. By configuring the area of the orthographic projection of the connection layer on the reference surface to be smaller than the area of the overlapping projection, the connection layer does not cover the side surfaces of the first cell and the second cell facing each other, and the portions of the side surfaces of the first cell and the second cell facing each other can be in contact with each other. Therefore, the optical parasitic absorption of the connecting layer is reduced, the optical loss of the laminated solar cell is further improved, and the short-circuit current density between the first cell and the second cell is improved, so that the efficiency of the laminated solar cell is improved.

Additional aspects and advantages of embodiments of the application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of embodiments of the application.

Drawings

FIG. 1 is a schematic cross-sectional view of a stacked solar cell according to an embodiment of the present application;

FIG. 2 is a schematic view of overlapping projections according to an embodiment of the present application;

FIG. 3 is a schematic top view of a connection layer and a first doped semiconductor layer according to an embodiment of the present application;

FIG. 4 is a schematic top view of a connection layer and a first doped semiconductor layer according to another embodiment of the present application;

FIG. 5 is a schematic top view of a connection layer and a first doped semiconductor layer according to another embodiment of the present application;

FIG. 6 is a schematic view of overlapping projections according to another embodiment of the present application;

FIG. 7 is a schematic cross-sectional view illustrating a connection layer and a first doped semiconductor layer according to an embodiment of the present application;

FIG. 8 is a schematic cross-sectional view illustrating a connection layer and a first doped semiconductor layer according to an embodiment of the present application;

FIG. 9 is a schematic cross-sectional view of a connection layer mated with a first doped semiconductor layer in accordance with another embodiment of the present application;

FIG. 10 is a schematic cross-sectional view of a connection layer mated with a first doped semiconductor layer in accordance with another embodiment of the present application;

FIG. 11 is a schematic view of overlapping projections according to yet another embodiment of the present application;

FIG. 12 is a schematic cross-sectional view of a connecting layer according to an embodiment of the present application;

FIG. 13 is a schematic cross-sectional view of a connecting layer according to an embodiment of the present application;

FIG. 14 is a schematic diagram showing a connection layer and a first charge transport layer used in combination according to an embodiment of the application;

FIG. 15 is a schematic cross-sectional view of a stacked solar cell in accordance with yet another embodiment of the application;

FIG. 16 is a schematic view of a partial enlarged structure at A in FIG. 1;

FIG. 17 is a schematic view of a partially enlarged structure at B in FIG. 15;

FIG. 18 is a schematic cross-sectional view of a stacked solar cell in accordance with another embodiment of the application;

FIG. 19 is a schematic view of a partially enlarged structure at C in FIG. 18;

FIG. 20 is a schematic flow chart of a method for fabricating a stacked solar cell according to an embodiment of the application;

Fig. 21 is a flowchart illustrating a step SJ of a method for fabricating a stacked solar cell according to an embodiment of the application.

Reference numerals illustrate:

the laminated solar cell 100, the first cell 110, the substrate 111, the light receiving surface m1, the backlight surface m2, the first intrinsic semiconductor layer 112a, the first doped semiconductor layer 113a, the second intrinsic semiconductor layer 112b, the second doped semiconductor layer 113b, the first transparent electrode layer 114, the first gate line E1, the connection layer 120, the first dimension h1, the opening x, the connection 121, the first connection 121a, the second connection 121b, the second cell 130, the first charge transport layer 131, the third dimension h3, the charge modifying layer 132, the light absorbing layer 133, the second charge transport layer 134a, the first sub charge transport layer 134b, the second transparent electrode layer 135, the back subtracting layer 136, the second gate line E2, the transparent conductive layer 140, the second dimension h2, the first surface s, the first side c1, the second side c2, the first direction F1, the second direction F2, the third direction F3, the fourth direction F4, the fifth direction F5, the third direction E, the third direction T5, the first overlapping projection T, the third overlapping projection T2, the third overlapping projection T, the Ta2, the third overlapping projection T, the step Ta, the overlapping Ta2, the overlapping projection T, the overlapping step, the Ta, the overlapping step, the first overlapping Ta, and the overlapping Ta, the first projection T, and the third overlapping step, and the third projection.

Detailed Description

In order that the above objects, features and advantages of the application will be readily understood, a more particular description of the application will be rendered by reference to the appended drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. The present application may be embodied in many other forms than described herein and similarly modified by those skilled in the art without departing from the spirit of the application, whereby the application is not limited to the specific embodiments disclosed below.

In the description of the present application, it should be understood that, if any, these terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., are used herein with respect to the orientation or positional relationship shown in the drawings, these terms refer to the orientation or positional relationship for convenience of description and simplicity of description only, and do not indicate or imply that the apparatus or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the application.

Furthermore, the terms "first," "second," and the like, if any, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the terms "plurality" and "a plurality" if any, mean at least two, such as two, three, etc., unless specifically defined otherwise.

In the present application, unless explicitly stated and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly. For example, the two parts can be fixedly connected, detachably connected or integrated; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. It is noted that in the following description and in the appended claims, the term "electrically connected" between one feature and another feature includes not only the direct contact of one feature with another feature to form an electrical energy transmission or current transfer path, but also the intermediate feature between one feature and another feature, the one feature, the other feature, and the intermediate feature therebetween forming an electrical energy transmission or current transfer path, to effect electrical energy transmission or transfer. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.

In the present application, unless expressly stated or limited otherwise, the meaning of a first feature being "on" or "off" a second feature, and the like, is that the first and second features are either in direct contact or in indirect contact through an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.

It will be understood that if an element is referred to as being "fixed" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. If an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like as used herein, if any, are for descriptive purposes only and do not represent a unique embodiment.

Fig. 1 is a schematic diagram showing a cross-sectional structure of a stacked solar cell 100 according to an embodiment of the present application; FIG. 2 shows a schematic diagram of overlapping projections T in an embodiment of the application; for convenience of explanation, only matters related to the embodiments of the present application are shown.

Referring to fig. 1, an embodiment of the present application provides a stacked solar cell 100, which includes a first cell 110, a connection layer 120, and a second cell 130 stacked in sequence along a first direction F1. The first direction F1 is the thickness direction of the stacked solar cell 100. That is, the thickness direction of the first cell 110, the thickness direction of each layer in the first cell 110, the thickness direction of the connection layer 120, and the thickness direction of each layer in the second cell 130 are all the first direction F1.

One of the first cell 110 and the second cell 130 is a top cell in the stacked solar cell 100, and the other is a bottom cell in the stacked solar cell 100. In an embodiment of the present application, the first cell 110 is a top cell in the stacked solar cell 100, and the other is a top cell in the stacked solar cell 100. Illustratively, the first cell 110 may be one of a heterojunction cell, a tunneling oxide passivation contact cell, or an emitter backside passivation cell, and the second cell 130 may be a perovskite cell. That is, the second cell 130 having a wider band gap is deposited on the first cell 110, so that a stacked cell can be formed, solar energy can be utilized to a greater extent, spectral response can be widened, and efficiency of the device can be improved. For example, in an embodiment of the present application, the first cell 110 is a heterojunction cell and the second cell 130 is a perovskite cell.

Referring to fig. 2 in combination, the orthographic projections of the first cell 110 and the second cell 130 on the reference plane E have overlapping projections T. The reference plane E is a plane perpendicular to the first direction F1. That is, the first cell 110 and the second cell 130 are opposite to each other in the first direction F1, and the area of the orthographic projection of the first cell 110 on the reference plane E and the area of the orthographic projection of the second cell 130 on the reference plane E are equal, and are both the areas of the overlapping projections T. In fig. 2, the second direction F2 is illustrated as a width direction of the stacked solar cell 100, the third direction F3 is a length direction of the stacked solar cell 100, the first direction F1, the second direction F2, and the third direction F3 are perpendicular to each other, and the second direction F2 and the third direction F3 are parallel to the reference plane E.

The connection layer 120 may be used to modify a side surface of the first cell 110 facing the second cell 130 in order to prepare the second cell 130. In addition, the connection layer 120 may also improve passivation performance and interface contact performance of the first cell 110 affected by the preparation of the second cell 130. Specifically, electrons and holes of the second cell 130 may be recombined in the connection layer 120, so that the current of the first cell 110 and the current of the second cell 130 are identical as much as possible. The connection layer 120 has a certain longitudinal conductivity, which is advantageous for charge transport.

The orthographic projection of the connection layer 120 on the reference plane E is located within the overlapping projection T, and the orthographic projection of the connection layer 120 on the reference plane E has an area smaller than the overlapping projection T. Portions of one side surfaces of the first and second batteries 110 and 130 facing each other are in contact with each other. It will be appreciated that, since the area of the orthographic projection of the connection layer 120 on the reference plane E is smaller than the area of the overlapping projection T, the connection layer 120 does not entirely cover the side surfaces of the first and second cells 110 and 130 facing each other, so that portions of the side surfaces of the first and second cells 110 and 130 facing each other can be in contact with each other.

Therefore, since the connection layer 120 does not cover the surface of the first cell 110 facing the second cell 130, the optical parasitic absorption of the connection layer 120 is reduced, the optical loss of the stacked solar cell 100 is improved, and the short-circuit current density between the first cell 110 and the second cell 130 is increased, thereby improving the efficiency of the stacked solar cell 100.

For further description of other embodiments of the present application, the first cell 110 is taken as a heterojunction cell, the second cell 130 is taken as a perovskite cell, and the layer structures of the first cell 110 and the second cell 130 are described as examples, but not limited thereto.

In some embodiments, referring to fig. 1, the first battery 110 includes a substrate 111, a first intrinsic semiconductor layer 112a, a first doped semiconductor layer 113a, a second intrinsic semiconductor layer 112b, a second doped semiconductor layer 113b, a first transparent electrode layer 114, and a first gate line e1.

The substrate 111 is used for receiving incident light and generating photo-generated carriers. The substrate 111 may be selected according to actual needs. Illustratively, the substrate 111 may be a silicon substrate. The doping type of the substrate is not particularly limited. For example, the substrate 111 may be an N-type doped silicon substrate, or may be a P-type doped silicon substrate. In the embodiment of the present application, this is not particularly limited. In an embodiment of the present application, the substrate 111 may be an N-type monocrystalline silicon wafer.

The substrate 111 has a light receiving surface m1 and a backlight surface m2 disposed opposite to each other in the first direction F1. It is understood that the light receiving surface m1 and the backlight surface m2 are relatively, and the light receiving surface m1 specifically refers to a surface on which sunlight mainly irradiates in a solar cell or on the substrate 111 in a photovoltaic module. The light receiving surface m1 is generally provided with a suede structure, and the suede structure can increase the light absorption area, improve the photo-generated current and help to improve the efficiency of the battery.

The first intrinsic semiconductor layer 112a and the first doped semiconductor layer 113a are sequentially stacked on the light receiving surface m1 of the substrate 111 along the first direction F1 to realize photoelectric conversion on the light receiving surface m1 side of the substrate 111. The second intrinsic semiconductor layer 112b, the second doped semiconductor layer 113b, the first transparent electrode layer 114, and the first gate line e1 are sequentially stacked on the backlight surface m2 of the substrate 111 along the first direction F1 to realize photoelectric conversion on the backlight surface m2 side of the substrate 111.

The first intrinsic semiconductor layer 112a may be made of one or more combinations of intrinsic amorphous silicon, intrinsic nanocrystalline silicon, intrinsic microcrystalline silicon, intrinsic silicon carbide, intrinsic silicon oxide, and intrinsic hydrogenated silicon. The second intrinsic semiconductor layer 112b may be made of one or more combinations of intrinsic amorphous silicon, intrinsic nanocrystalline silicon, intrinsic microcrystalline silicon, intrinsic silicon carbide, and intrinsic silicon oxide intrinsic hydrogenated silicon. In an embodiment of the present application, the first and second intrinsic semiconductor layers 112a and 112b are both intrinsic hydrogenated amorphous silicon layers.

The first doped semiconductor layer 113a and the second doped semiconductor layer 113b function as hole and electron transport layers, respectively, and the doping polarities of the first doped semiconductor layer 113a and the second doped semiconductor layer 113b are opposite. That is, the doping types of the first doped semiconductor layer 113a and the second doped semiconductor layer 113b are different. The first doped semiconductor layer 113a may be an N-type doped semiconductor layer, and the second doped semiconductor layer 113b may be a P-type doped semiconductor layer. Of course, the first doped semiconductor layer 113a may be a P-type doped semiconductor layer, and the second doped semiconductor layer 113b may be an N-type doped semiconductor layer. In the embodiment of the present application, the first doped semiconductor layer 113a is one of an N-type amorphous silicon layer, an N-type microcrystalline silicon layer, or an N-type nanocrystalline silicon layer, and the second doped semiconductor layer 113b is one of a P-type amorphous silicon layer, a P-type microcrystalline silicon layer, or a P-type nanocrystalline silicon layer. The flexible setting can be performed according to specific use conditions, and the embodiment of the application is not particularly limited thereto.

In some embodiments, referring to fig. 1, the second battery 130 includes a first charge transport layer 131, a charge modifying layer 132, a light absorbing layer 133, a second charge transport layer 134, a second transparent electrode layer 135, and a second gate line e2 stacked in order along a first direction F1. The second transparent electrode layer 135 may be provided with an anti-reflection layer 136 at a region where the second gate line e2 is not provided at a side facing away from the second charge transport layer 134. The first charge transport layer 131 and the second charge transport layer 134 may transport carriers. A portion of the first charge transport layer 131 is in contact with the connection layer 120, and another portion is in contact with the first battery 110. That is, another portion of the first charge transport layer 131 is in contact with the first surface s of the first doped semiconductor layer 113 a.

Sunlight can pass through the second transparent electrode layer 135, so that the light absorbing layer 133 is conveniently irradiated with sunlight, thereby generating photocurrent in the stacked solar cell 100. Specifically, the light absorbing layer 133 may generate electron-hole pairs under irradiation of sunlight. Both electrons and holes may be referred to as carriers. Illustratively, the light absorbing layer 133 may be a perovskite layer.

The perovskite in the light absorbing layer 133 has the chemical formula ABX ₃. Wherein A comprises an organic cation, an inorganic cation or a cation mixed with organic and inorganic, B comprises an organic cation, an inorganic cation or a cation mixed with organic and inorganic, and X comprises an organic anion, an inorganic anion or an anion mixed with organic and inorganic.

Illustratively, a comprises any one or a combination of at least two of FA ⁺、MA⁺、Cs⁺ or Rb ⁺, B comprises any one or a combination of at least two of Pb ²⁺、Sn²⁺ or Sr ²⁺, and X comprises any one or a combination of at least two of Br ^-、I^- or CI ^-. In the above embodiment, the perovskite material having the corresponding ion may be selected to prepare the perovskite layer (i.e., the light absorbing layer 133) according to actual needs.

As such, the first battery 110 and the second battery 130 as needed can be obtained according to the above-illustrated structure. It is to be understood that, according to the actual use situation, the required film layers may be disposed in the first battery 110 and the second battery 130 or the corresponding film layers may be reduced, which is not limited herein. In the case of the first and second batteries 110 and 130 illustrated above, the connection layer 120 is electrically connected between the first charge transport layer 131 and the first doped semiconductor layer 113a, and portions of the surfaces of the first charge transport layer 131 and the first doped semiconductor layer 113a facing each other are in contact with each other.

FIG. 3 is a schematic top view of the connection layer 120 and the first doped semiconductor layer 113a according to an embodiment of the present application; fig. 4 is a schematic top view of a connection layer 120 mated with a first doped semiconductor layer 113a according to another embodiment of the present application; fig. 5 is a schematic top view of a connection layer 120 and a first doped semiconductor layer 113a according to another embodiment of the present application; for convenience of explanation, only matters related to the embodiments of the present application are shown.

In some embodiments, referring to fig. 1 and 2, at least a portion of the outline of the orthographic projection of the connection layer 120 on the reference plane E is located within the outer outline of the overlapping projection T. In particular to some embodiments, the outline of the orthographic projection of the connection layer 120 on the reference plane E is entirely within the outer outline of the overlapping projection T. Accordingly, taking fig. 3 and fig. 4 as an example, referring to fig. 1 in combination, the first doped semiconductor layer 113a has a first surface s facing the first charge transport layer 131, and the connection layer 120 is located on the first surface s; here, in a top view, a case where the boundary of the connection layer 120 is located within the boundary of the first doped semiconductor layer 113a is illustrated. In particular to other embodiments, the portion of the outline of the orthographic projection of the connection layer 120 on the reference plane E is located within the outer outline of the overlapping projection T; the remaining part of the front-projected contour of the connection layer 120 on the reference plane E and the part of the outer contour of the overlapping projection T coincide with each other. Accordingly, taking fig. 5 as an example, the connection layer 120 is located on the first surface s of the first doped semiconductor layer 113 a; in a top view, a portion of the boundary of the connection layer 120 is located within the boundary of the first doped semiconductor layer 113a, and the remaining boundary of the connection layer 120 and the boundary of the first doped semiconductor layer 113a overlap each other.

Of course, in other embodiments, the outer contour of the orthographic projection of the connection layer 120 on the reference plane E and the outer contour of the overlapping projection T coincide with each other. It is understood that the front projected profile of the connection layer 120 on the reference plane E may include an outer profile, and may also include an outer profile and an inner profile. The number of the orthographic projection contours of the connection layer 120 on the reference plane E may be one or more. Taking the connection layer 120 illustrated in fig. 3 and 4 as an example, referring to fig. 2, the outline of the front projection of the connection layer 120 on the reference plane E includes a plurality of outer outlines. Taking the connection layer 120 illustrated in fig. 5 as an example, the outline of the front projection of the connection layer 120 on the reference plane E includes a plurality of outer outlines and a plurality of inner outlines.

In this manner, the connection layer 120 may be flexibly disposed according to actual use conditions, so long as the connection layer 120 does not completely cover the first surface s of the first doped semiconductor layer 113a, which is not particularly limited herein.

In some embodiments, please continue to refer to fig. 1 in combination with fig. 2, the overlapping projections T include a first overlapping projection T1 and a second overlapping projection T2. The first overlap projection T1 overlaps the orthographic projection of the connection layer 120 on the reference plane E. The orthographic projection of the portion where the side surfaces of the first cell 110 and the second cell 130 facing each other are in contact with each other on the reference plane E is located within the second overlap projection T2. The orthographic projection of the portion where the side surfaces of the first and second batteries 110 and 130 facing each other are in contact with each other at the reference plane E may be entirely overlapped with the second overlap projection T2. That is, the orthographic projection of the portion where the first charge transport layer 131 and the first doped semiconductor layer 113a are in contact with each other on the side surfaces facing each other completely overlaps the second overlap projection T2 on the reference plane E.

Since the connection layer 120 does not completely cover the first surface s of the first doped semiconductor layer 113a, a corresponding space (e.g., hole, notch, etc.) is formed on the connection layer 120 or the periphery of the connection layer 120 and the first surface s define a corresponding space, and the first charge transport layer 131 may be filled in the corresponding space and contact with the first surface s of the first doped semiconductor layer 113 a. As such, by constructing the structure of the connection layer 120, the morphology and the construction in which the first and second cells 110 and 130 are in contact with each other can be controlled.

In some embodiments, please continue to refer to fig. 1 and 2, one of the first overlapping projection T1 and the second overlapping projection T2 includes a plurality of sub-overlapping projections Ta, at least a portion of the sub-overlapping projections Ta of the plurality of sub-overlapping projections Ta are arranged according to a predetermined rule. That is, the partial sub-overlapping projections Ta in the plurality of sub-overlapping projections Ta may be arranged with a predetermined rule, or the plurality of sub-overlapping projections Ta may all be arranged with a predetermined rule.

It should be noted that the preset rule refers to a specific arrangement rule preset for the sub-overlapping projection Ta. The arrangement rule can be set according to actual use conditions. For the arrangement of the at least partially overlapping projections Ta, the number of preset rules may be one or more, and the type of preset rules may be one or more.

Illustratively, the preset rule includes at least one of a unidirectional arrangement and an array arrangement. The array arrangement can be a rectangular array or a circular array. That is, in all the sub-overlapping projections Ta arranged in a predetermined rule, the sub-overlapping projections Ta may be arranged in a single direction, may be arranged in an array, or may be arranged in a single direction in a part or in an array. Under the condition that the preset rules are arranged in a single direction, the number of the preset rules is one, and the type of the preset rules is one. In the case that the preset rules are arranged in an array, the number of the preset rules can be regarded as one, and the type of the preset rules is one; of course, the array arrangement can be regarded as two unidirectional arrangements, at this time, the number of preset rules is two, and the type of the preset rules is one. In other examples, the preset rule may further include an arrangement according to a preset pattern, a repeated arrangement according to a preset pattern, and the like. According to the preset pattern, a plurality of sub-overlapping projections Ta are arranged along a preset path to form the preset pattern. The shape of the preset path may be circular, triangular, rectangular, or the like, and is not particularly limited herein. The repeated arrangement according to the preset pattern means that the plurality of sub-overlapping projections Ta are arranged to form a plurality of preset patterns. The repetition of the preset pattern may also be performed according to a certain rule, and is not particularly limited herein.

Therefore, according to the actual use condition, the required preset rule can be correspondingly selected. In the case where the at least partially overlapping projections Ta are arranged in a predetermined pattern, not only the manufacturing and shaping is facilitated, but also the control of the configuration of the connection layer 120 is facilitated.

In some embodiments, please continue to refer to fig. 1-4, at least some of the sub-overlapping projections Ta are arranged in rows along the second direction F2 and in columns along the third direction F3. The second direction F2 and the third direction F3 intersect each other and are both perpendicular to the first direction F1. The second direction F2 and the third direction F3 may be perpendicular to each other. For example, the second direction F2 may be a width direction of the laminated solar cell 100 illustrated in some of the foregoing embodiments, and the third direction F3 may be a length direction of the laminated solar cell 100 illustrated in some of the foregoing embodiments.

It is understood that, for each row of sub-overlapping projections Ta, the row of sub-overlapping projections Ta is arranged in a single direction. For each column of sub-overlapping projections Ta, the arrangement mode of the column of sub-overlapping projections Ta is that the sub-overlapping projections Ta are arranged in a single direction. In the case where the second direction F2 and the third direction F3 are perpendicular to each other, the arrangement of the at least partially overlapping projections Ta is a rectangular array arrangement.

FIG. 6 shows a schematic diagram of an overlapping projection T in another embodiment of the application; for convenience of explanation, only matters related to the embodiments of the present application are shown.

In some embodiments, please continue with reference to fig. 1 and 5, and with reference to fig. 6, at least a portion of the sub-overlap projections Ta include a plurality of first sub-overlap projections Ta1 and a plurality of second sub-overlap projections Ta2. All the first sub-overlap projections Ta1 are arranged extending in the fourth direction F4 and are arranged at intervals in the fifth direction F5. All the second sub-overlap projections Ta2 are arranged at intervals along the fourth direction F4. Each second sub-overlap projection Ta2 is connected to any one of all the first sub-overlap projections Ta 1. The fourth direction F4 and the fifth direction F5 intersect each other and are both perpendicular to the first direction F1. In the embodiment of the present application, the fourth direction F4 is the third direction F3, the fifth direction F5 is the second direction F2, and the fourth direction F4 and the fifth direction F5 are perpendicular to each other, and the second sub-overlapping projection Ta2 extends along the fifth direction F5.

It is understood that, for the plurality of first sub-overlapping projections Ta1, the first sub-overlapping projections Ta1 are arranged in a single direction. For the plurality of second sub-overlapping projections Ta2, the arrangement manner of the second sub-overlapping projections Ta2 is a single-direction arrangement. The arrangement direction of the first sub-overlap projection Ta1 and the arrangement direction of the second sub-overlap projection Ta2 are different.

In this way, by configuring the sub-overlapping projections Ta to have different structures and different arrangements, not only processing and manufacturing are facilitated, but also optical parasitic absorption of the connection layer 120 is facilitated to be controlled by a preset structure and a preset rule.

In some embodiments, please continue to refer to fig. 1-5, the first overlapping projection T1 includes a plurality of sub-overlapping projections Ta. The connection layer 120 includes a plurality of connection portions 121, and a plurality of sub-overlapping projections Ta are defined by orthographic projections of the plurality of connection portions 121 on the reference plane E.

Specifically, taking fig. 2 as an example, in the case where the plurality of sub-overlap projections Ta are independent of each other, the plurality of sub-overlap projections Ta are defined by a plurality of connection portions 121 independent of each other, and as shown in fig. 3, no connection is made between the plurality of connection portions 121. Each connecting portion 121 corresponds to one sub-overlapping projection Ta, and the second overlapping projection T2 can be regarded as a projection having a hollowed-out area, and the sub-overlapping projection Ta is correspondingly located on the hollowed-out area. Taking fig. 6 as an example, in the case where the sub-overlapping projection Ta includes a first sub-overlapping projection Ta1 and a second sub-overlapping projection Ta2, the plurality of first sub-overlapping projections Ta1 are defined by a plurality of first connecting portions 121a that are independent of each other, and the plurality of second sub-overlapping projections Ta2 are defined by a plurality of second connecting portions 121b that are independent of each other. Referring to fig. 5 in combination, all the first connection parts 121a are disposed to extend in the fourth direction F4 and are spaced apart in the fifth direction F5. All the second connection parts 121b are arranged at intervals along the fourth direction F4. Each of the second connection parts 121b is connected to any one of all the first connection parts 121 a. The fourth direction F4 and the fifth direction F5 intersect each other and are both perpendicular to the first direction F1. In the case illustrated in fig. 5 and 6, the first overlapping projection T1 can be regarded as a projection with a hollowed-out area and a notched area, which is formed by the first sub-overlapping projection Ta1 and the second sub-overlapping projection Ta2, and a part of the second overlapping projection T2 is located in the hollowed-out area and a part is located in the notched area. The second overlapping projections T2 located in the hollowed-out area may be regarded as being arranged in an array arrangement.

In this way, by providing the connection layer 120 in the form of a plurality of connection portions 121, a corresponding arrangement can be achieved by means of the connection portions 121.

FIG. 7 is a schematic cross-sectional view of the connection layer 120 mated with the first doped semiconductor layer 113a in an embodiment of the present application; FIG. 8 is a schematic cross-sectional view of the connection layer 120 mated with the first doped semiconductor layer 113a in an embodiment of the present application; fig. 9 is a schematic cross-sectional view showing the cooperation of the connection layer 120 and the first doped semiconductor layer 113a according to still another embodiment of the present application; fig. 10 is a schematic cross-sectional view showing the cooperation of the connection layer 120 and the first doped semiconductor layer 113a according to another embodiment of the present application; for convenience of explanation, only matters related to the embodiments of the present application are shown.

In some embodiments, referring to fig. 7 to 10, a cross section of the connection portion 121 along the first preset direction includes at least one of a regular pattern and an irregular pattern. The first preset direction and the first direction F1 are perpendicular to each other.

In fig. 7 to 10, a case where the first preset direction and the second direction F2 are parallel to each other is illustrated. The regular pattern comprises any one or more of a combination of circles, triangles, rectangles, ovals, trapezoids. That is, the shapes of all the connection portions 121 may be the same, may not be the same, or may be different. Fig. 7 to 10 illustrate a case where the shapes of the cross sections of the connection portions 121 in the first preset direction are identical. Wherein fig. 7 and 8 illustrate different embodiments of the shape of the cross section of the connection part 121 illustrated in fig. 3 along the first preset direction, the shape being rectangular and semicircular, respectively; fig. 9 illustrates a case where the connection part 121 illustrated in fig. 4 has a triangular cross-section along a first predetermined direction; fig. 10 illustrates a case where the cross-section of the second connection portion 121b along the first predetermined direction in fig. 5 is rectangular, and the first connection portion 121a may be considered with reference thereto, and detailed description thereof will be omitted.

In this way, the shape of the corresponding connection portion 121 can be flexibly set and selected according to the use requirement.

FIG. 11 shows a schematic view of an overlapping projection T in a further embodiment of the application; FIG. 12 is a schematic cross-sectional view of the connection layer 120 at a single viewing angle according to an embodiment of the present application; FIG. 13 is a schematic cross-sectional view of the connection layer 120 from another perspective in accordance with an embodiment of the present application; for convenience of explanation, only matters related to the embodiments of the present application are shown. Fig. 12 shows a top view, and fig. 13 shows a front view.

In some embodiments, referring to fig. 11, the second overlapping projection T2 includes a plurality of sub-overlapping projections Ta. Referring to fig. 12 and 13 in combination, the connection layer 120 is provided with a plurality of openings x, and orthographic projections of the plurality of openings x on the reference plane E define a plurality of sub-overlapping projections Ta. That is, each aperture x corresponds to a sub-overlap projection Ta. The coverage area of the connection layer 120 on the first surface s of the first doped semiconductor layer 113a may be defined by an opening ratio. In this manner, the area of the connection layer 120 covering the first surface s of the first doped semiconductor layer 113a may be reduced by providing the opening x on the connection layer 120.

In some embodiments, referring to fig. 11 to 13, the cross-section of the opening x along the second preset direction includes any one or more of a regular pattern and an irregular pattern. The second preset direction and the first direction F1 are perpendicular to each other. In the embodiment of the present application, the case where the second preset direction is parallel to the second direction F2 is illustrated. The shape of the cross section of the opening x along the second preset direction comprises any one or more of a regular pattern and an irregular pattern. In fig. 13, a case is illustrated in which the shape of the cross section of the opening x in the second direction F2 is a regular pattern, and the cross section shape of each opening x is the same, the regular pattern being a rectangle.

Therefore, the shape of the corresponding opening x can be flexibly set and selected according to the use requirement.

In some embodiments, please continue with fig. 2-6, and fig. 11 and 12, the shape of the sub-overlap projection Ta includes any one or more of a regular pattern and an irregular pattern. Illustratively, the regular pattern includes any one or a combination of circles, triangles, rectangles, ovals, trapezoids. In the embodiment of the present application, a case where the shape of the sub-overlap projection Ta is a regular pattern is illustrated. Taking fig. 3 as an example, a case where the shape of the sub-overlapping projection Ta corresponding to the connection portion 121 is circular is illustrated. Taking fig. 4 as an example, a case where the shape of the sub-overlapping projection Ta corresponding to the connection portion 121 is rectangular is illustrated. Taking fig. 5 as an example, a case is illustrated in which the first sub-overlapping projection Ta1 and the second sub-overlapping projection Ta2 corresponding to the first connection portion 121a and the second connection portion 121b respectively form a grid pattern.

In this way, the shape of the connection layer 120 can be flexibly set according to the use requirement.

FIG. 14 is a schematic diagram showing the use of the connection layer 120 and the first charge transport layer 131 in combination in accordance with one embodiment of the present application; for convenience of explanation, only matters related to the embodiments of the present application are shown.

In some embodiments, referring to fig. 1, the conductivity of the first charge transport layer 131 is greater than 10 ^-5 S/cm and less than 10S/cm. In this way, the transfer of charge in the first charge transfer layer 131 is facilitated. Specifically, referring to fig. 14 in combination, arrows show the direction of charge transport, electrons and holes of the second cell 130 may be recombined in the connection layer 120, and in the case where the conductivity of the first charge transport layer 131 is improved, charges at a contact portion of the first charge transport layer 131 and the first doped semiconductor layer 113a may be more rapidly laterally transported to the connection layer 120 to be recombined. Thereby facilitating electrical connection between the first battery 110 and the second battery 130.

In some embodiments, please continue to refer to fig. 1, the ratio of the area of the orthographic projection of the connection layer 120 on the reference plane E to the area of the overlapping projection T is a predetermined ratio q. The preset ratio q satisfies the condition: q is more than or equal to 0.1 and less than 1. Illustratively, the preset ratio q may be 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.75, 0.8, 0.9, or 1. In this manner, the recombination of charges at the connection layer 120 can be facilitated while improving the optical parasitic absorption of the connection layer 120 by controlling the magnitude of the preset ratio q.

Fig. 15 is a schematic diagram showing a cross-sectional structure of a stacked solar cell 100 according to still another embodiment of the present application; for convenience of explanation, only matters related to the embodiments of the present application are shown.

In some embodiments, referring to fig. 1, the first battery 110 has a first surface s disposed toward the second battery 130. Illustratively, the first surface s is the first surface s of the first doped semiconductor layer 113a illustrated in some of the foregoing embodiments. The first surface s has a first side c1 facing the second cell 130 and a second side c2 facing away from the second cell 130. Taking fig. 1 as an example, the connection layer 120 is located on the first side c1 of the first surface s. Taking fig. 15 as an example, a portion of the connection layer 120 is located on the first side c1 of the first surface s, another portion is located on the second side c2 of the first surface s, that is, a portion of the connection layer 120 is located in the first doped semiconductor layer 113a, and another portion is located in the first charge transport layer 131.

In this way, the connection layer 120 capable of reducing parasitic absorption can be obtained by configuring the position of the connection layer 120 with respect to the first surface s. In the case where a part of the connection layer 120 is located on the first side c1 of the first surface s and another part is located on the second side c2 of the first surface s, the contact area can be further increased, and the compound ability of the connection layer 120 can be further improved.

In some embodiments, referring to fig. 1 and 15, the material of the connection layer 120 is transparent conductive oxide. Illustratively, the material of the connection layer 120 includes any one or more of indium tin oxide, aluminum doped zinc oxide, indium doped zinc oxide, fluorine doped tin oxide. The connection layer 120 may be formed in a single-layer structure or a multi-layer structure. The material of the single layer structure may include one or more of the foregoing materials, and the multi-layer structure may be a stacked structure of an indium tin oxide layer and an aluminum doped zinc oxide layer. There is no particular limitation herein.

In this way, by setting the material of the connection layer 120 to be transparent conductive oxide, not only the composite requirement can be satisfied, but also the parasitic absorption can be further reduced.

FIG. 16 shows a schematic view of a partial enlarged structure at A in FIG. 1; FIG. 17 is a schematic view showing a partially enlarged structure at B in FIG. 15; for convenience of explanation, only matters related to the embodiments of the present application are shown.

In some embodiments, please continue to refer to fig. 1 and 15, and refer to fig. 16 and 17, the dimension of the connection layer 120 along the first direction F1 is a first dimension h1 (i.e. the thickness of the connection layer 120). The first dimension h1 is greater than 0nm and less than or equal to 100nm. Illustratively, the first dimension h1 may be 1nm, 20nm, 30nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, or 100nm.

In this manner, not only is the longitudinal transport of charge facilitated, but the continuous connection layer 120 is also facilitated to be fabricated.

Fig. 18 is a schematic diagram showing a cross-sectional structure of a stacked solar cell 100 according to another embodiment of the present application; FIG. 19 is a schematic view showing a partially enlarged structure at C in FIG. 18; for convenience of explanation, only matters related to the embodiments of the present application are shown.

In some embodiments, referring to fig. 18 and 19, the stacked solar cell 100 further includes a transparent conductive layer 140. The transparent conductive layer 140 is connected between the connection layer 120 and the first cell 110, and portions of one side surfaces of the transparent conductive layer 140 and the second cell 130 facing each other are in contact with each other. That is, the transparent conductive layer 140 is disposed on a side surface of the first doped semiconductor layer 113a facing away from the first intrinsic semiconductor, and a side surface of the transparent conductive layer 140 facing away from the first doped semiconductor layer 113a is the first surface s.

In this manner, the recombination capability can be further improved by means of the transparent conductive layer 140.

In some embodiments, referring to fig. 18 and 19, the transparent conductive layer 140 is made of transparent conductive oxide, and the connection layer 120 is made of metal. Illustratively, the transparent conductive layer 140 includes any one or more of indium tin oxide, aluminum doped zinc oxide, indium doped zinc oxide, fluorine doped tin oxide. Illustratively, the material of the connection layer 120 includes any one or more of gold, silver, copper, iron, aluminum, and platinum. Thus, the material of the transparent conductive layer 140 and the material of the connection layer 120 can be flexibly selected according to the requirement.

In some embodiments, please continue to refer to fig. 18 and 19, the first dimension h1 is greater than 0nm and less than or equal to 20nm. The transparent conductive layer 140 has a dimension along the first direction F1 of a second dimension h2 (i.e., a thickness of the transparent conductive layer 140), and the second dimension h2 is greater than 0nm and less than or equal to 100nm. Illustratively, the first dimension h1 may be 1nm, 2nm, 4nm, 6nm, 7nm, 9nm, 11nm, 13nm, 14nm, 16nm, 17nm, 19nm, or 20nm, and the second dimension h2 may be 1nm, 20nm, 30nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, or 100nm.

In this manner, not only is the longitudinal transport of charge facilitated, but the continuous connection layer 120 and transparent conductive layer 140 are also facilitated to be fabricated.

In some embodiments, please refer to fig. 16, 17 and 19, the dimension of the first charge transport layer 131 along the first direction F1 (i.e. the thickness of the first charge transport layer 131) is the third dimension h3. When the third dimension h3 is 300nm to 700nm, the transmittance of the first charge transport layer 131 is 1% to 100%. When the third dimension h3 is 700nm to 1200nm, the transmittance of the first charge transport layer 131 is 95% to 100%.

In this way, by controlling both the size and the transmittance of the first charge transport layer 131 in the first direction F1, the transport of charges is facilitated.

Fig. 20 is a schematic flow chart of a method for manufacturing a stacked solar cell 100 according to an embodiment of the application; for convenience of explanation, only matters related to the embodiments of the present application are shown.

Based on the same inventive concept, please refer to fig. 20 in combination with fig. 1, an embodiment of the present application provides a method for manufacturing a stacked solar cell 100, which includes the following steps:

step SG, providing a first battery 110;

Step SH, forming a connection layer 120 on one side of the first cell 110 along the first direction F1; the front projection of the connection layer 120 on the reference plane E is located within the front projection range of the first battery 110 on the reference plane E; the area of the orthographic projection of the connection layer 120 on the reference plane E is smaller than the area of the orthographic projection of the first battery 110 on the reference plane E; the first direction F1 is a thickness direction of the stacked solar cell 100, and the reference plane E is a plane perpendicular to the first direction F1;

step SI, manufacturing a second cell 130 on a side of the connection layer 120 facing away from the first cell 110, to form a laminated solar cell 100; the orthographic projections of the first cell 110 and the second cell 130 on the reference plane E overlap each other, and portions of the side surfaces of the first cell 110 and the second cell 130 facing each other contact each other.

In step SG, the relevant implementation of the first battery 110 may be referred to as illustrated in some of the foregoing examples. Here, the related structure of the first battery 110 illustrated in the foregoing embodiments is taken as an example of the first battery 110 as a heterojunction battery, and is described as an example.

The substrate 111 of the first battery 110 may be an N-type monocrystalline silicon wafer, and the thickness may be 10 μm-500 μm, and the doping concentration may be 1×10 ¹⁰cm^-3~1×10¹⁸cm^-3.

The first intrinsic semiconductor layer 112a and the second intrinsic semiconductor layer 112b may be intrinsic amorphous silicon layers, and may be prepared by one or more of a PECVD (PLASMA ENHANCED CHEMICAL vapor deposition) process, a cat-CVD (CATALYTIC CVD) process, a HWCVD (hot-wire chemical vapor deposition) process. The thickness of the first intrinsic semiconductor layer 112a and the thickness of the second intrinsic semiconductor layer 112b may each be 0.5nm to 20nm.

The first doped semiconductor layer 113a and the second doped semiconductor layer 113b may be doped amorphous silicon layers, and may be prepared by one or more of PECVD (PLASMA ENHANCED CHEMICAL vapor deposition) process, cat-CVD (CATALYTIC CVD) process, HWCVD (hot-Wire ChemicalVapor Deposition) process, and hot wire chemical vapor deposition process. The thickness of the first doped semiconductor layer 113a and the thickness of the second doped semiconductor layer 113b may each be 0.5nm to 20nm. The doping concentration of the first doped semiconductor layer 113a and the doping concentration of the second doped semiconductor layer 113b may be 1×10 ¹⁸cm^-3~1×10²¹cm^-3, and the doping atoms may be boron, phosphorus, gallium, carbon, oxygen, or the like.

Note that, the relevant materials may be selected correspondingly according to the types of the first intrinsic semiconductor layer 112a, the second intrinsic semiconductor layer 112b, the first doped semiconductor layer 113a, and the second doped semiconductor layer 113 b.

The first transparent electrode layer 114 may be prepared by one or more of ALD (Atomic Layer Deposition) process, PECVD (PLASMA ENHANCED CHEMICAL vapor deposition) process, spin-coating process, sputtering process, or thermal evaporation process, and the material of the first transparent electrode layer 114 may be one or more of SnO ₂、TiO₂, IZO, AZO, graphene, or silver nanowire, and the thickness of the first transparent electrode layer 114 may be 1nm to 500nm.

The material of the first gate line e1 includes at least one of Au, ag, cu, ni or Al. The first gate line e1 may be manufactured through a screen printing process, an electroplating process, a laser transfer process, or a thermal evaporation process. The thickness of the first gate line e1 may be 1nm to 500nm.

In step SH, the connection layer 120 may be formed on one side of the first cell 110 in the first direction F1 through a preset process. The preset process comprises any one or more of a mask process and a laser etching process. The related implementation and related advantages of the connection layer 120 may be referred to those illustrated in the foregoing embodiments, and will not be described herein.

In step SI, the first charge transport layer 131 may be a hole transport layer, and the charge modification layer 132 may be a hole modification layer. The first charge transport layer 131 may be prepared using one or more of a spin coating process, a thermal evaporation process, a blade coating process, a coating process, or a printing process. The material of the first charge transport layer 131 is one or more of Sprio-OMeTAD, PTAA, niO _x、P3HT、PEDOT:PSS、CuSCN、CuAlO₂ or spiro-TTB, and the thickness of the first charge transport layer 131 may be 1nm to 500nm.

The light absorbing layer 133 may be a perovskite layer, and may be prepared by one or more of a spin coating process, a spray pyrolysis process, a thermal evaporation process, a doctor blading process, a coating process, or a printing process. The material of the light absorbing layer 133 may be implemented with reference to the descriptions of the foregoing embodiments, which will not be described herein. The thickness of the light absorbing layer 133 may be 100nm to 1000nm.

The second charge transport layer 134 may have a single-layer structure or a multi-layer structure. The second charge transport layer 134 may be an electron transport layer and may be prepared by one or more of a solution process, a magnetron sputtering process, a spray pyrolysis process, a thermal evaporation process, an atomic layer deposition process, a doctor blading process, a coating process, or a printing process. The material of the second charge transport layer 134 may be one or more of SnO ₂、TiO₂、ZnO₂, ITO, FTO, IZO, fullerene and derivatives, baSnO ₃, or AZO, and the thickness of the second charge transport layer 134 may be 1nm to 500nm.

The second transparent electrode layer 135 may be prepared using one or more of ALD process, PECVD (process, spin-coating process, sputtering process, or thermal evaporation process), the material of the first transparent electrode layer 114 may be one or more of SnO ₂、TiO₂, IZO, AZO, graphene, or silver nanowire, and the thickness of the first transparent electrode layer 114 may be 1nm to 500nm.

The anti-reflective layer 136 may be formed using one or more of an evaporation process, a sputtering process, or an ALD process. The material of the anti-reflection layer 136 may be one or more of LiF, mgF ₂、Si₃N₄、SiO₂, or a textured flexible film. The thickness of the anti-reflection layer 136 may be 0.1nm to 5mm.

The material of the second gate line e2 includes at least one of Au, ag, cu, ni or Al. The second gate line e2 may be manufactured through a screen printing process, an electroplating process, a laser transfer process, or a thermal evaporation process. The thickness of the second gate line e2 may be 1nm to 500nm.

Thus, the first cell 110, the connection layer 120, and the second cell 130 can be fabricated in the manner schematically described above, and the stacked solar cell 100 can be obtained. The above-described related embodiments and related advantages of the connection layer 120 are similar to those of the fabricated stacked solar cell 100, and are not described in detail herein.

Fig. 21 is a schematic flow chart of step SJ of a method for manufacturing a stacked solar cell 100 according to an embodiment of the application; for convenience of explanation, only matters related to the embodiments of the present application are shown.

In some embodiments, please refer to fig. 21 in combination with fig. 18 and 19, before step SH, the method comprises the following steps:

in step SJ, the transparent conductive layer 140 is formed on one side of the first cell 110 along the first direction F1.

It will be appreciated that the connection layer 120 is fabricated after the transparent conductive layer 140 is fabricated on the side of the first doped semiconductor layer 113a facing away from the first intrinsic semiconductor layer 112 a. That is, the connection layer 120 is formed at a side of the transparent conductive layer 140 facing away from the first cell 110. In addition, regarding the related implementation and advantages of the transparent conductive layer 140, reference may be made to what is illustrated in the foregoing examples, and details thereof are not repeated herein.

Thus, by fabricating the respective layer structures in the stacked solar cell 100 as illustrated in the above embodiments, the corresponding stacked solar cell 100 can be fabricated.

It should be noted that some steps or stages shown in the foregoing are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with other steps or at least a part of the steps or stages in other steps. May be selected according to the specific use requirements and is not particularly limited herein.

The laminated solar cell according to the embodiments of the present application will be exemplarily described with reference to the structure of the laminated solar cell and the method of manufacturing the laminated solar cell and the related comparative examples, which are illustrated in some of the embodiments described above.

In the comparative example, the first cell was a heterojunction cell, the substrate was an n-type silicon wafer, the thickness of the substrate was 280 μm, the doping concentration was 1×10 ¹⁵cm^-3, and corresponding intrinsic amorphous silicon layers were prepared on the above substrate by a PECVD process, and the thickness of each intrinsic amorphous silicon layer was 2nm. Subsequently, a doped amorphous silicon layer on the front and back sides of the substrate is prepared. Wherein the concentration of the p-type doped amorphous silicon layer is 1×10 ¹⁸cm^-3, the thickness is 10nm, the concentration of the n-type doped amorphous silicon layer is 1×10 ¹⁸cm^-3, and the thickness is 5nm. Subsequently, an ICO transparent conductive oxide having a thickness of 40nm was deposited on the p-type doped amorphous silicon layer using a PVD process, and an IZO layer having a thickness of 20nm was deposited on the n-type amorphous silicon layer. Subsequently, a NiO _x layer having a thickness of 10nm was deposited on the IZO layer, the electrical conductivity of the NiO _x layer was 1S/cm, and a perovskite layer having a thickness of 800nm, the composition of which was FA _0.8MA_0.15Cs_0.5PbI_2.25Br_0.75, was prepared on the NiO _x layer. Subsequently, a C ₆₀ layer with a thickness of 15nm was produced by an evaporation process, and a SnO ₂ layer with a thickness of 20nm was deposited by an atomic layer deposition process. Subsequently, an IZO layer having a thickness of 40nm was deposited by PVD process. Finally, the silver grid line electrode is manufactured through an evaporation process.

In example 1, taking fig. 1 as an example, unlike the above comparative example, a 1 μm×1 μm hollowed-out mask is used to deposit an IZO layer (i.e., the connection layer 120) of 30 nm, and the preset ratio q is 0.5.

In example 2, taking fig. 15 as an example, unlike the above comparative example, after the n-type doped amorphous silicon layer (i.e., the first doped semiconductor layer 113 a) is prepared, grooves with a depth of 2nm and a length and width of 1 μm are manufactured by using a laser process, the grooves are arranged in a square array, and the preset ratio q is 0.5. Subsequently, an IZO layer (i.e., the connection layer 120) with a thickness of 30 nm is deposited by using a mask plate hollowed out by 1 [ mu ] m×1 [ mu ] m.

In example 3, taking fig. 18 as an example, an IZO layer (i.e., transparent conductive layer 140) having a thickness of 10 nm a is deposited on the n-type doped amorphous silicon layer, unlike the above comparative example. Subsequently, an IZO layer (namely the connecting layer 120) with the thickness of 20 nm is deposited by adopting a mask plate hollowed by 1 mu m multiplied by 1 mu m, and the preset ratio q is 0.5.

The power of the prepared batteries in comparative examples and examples 1 to 3 was tested under AM1.5G simulated sunlight at 25 ℃, and the test results are shown in Table 1.

TABLE 1

As can be seen from table 1, the stacked solar cells provided in examples 1 to 3 were better in efficiency as a whole than the comparative examples. The stacked solar cells provided in embodiments 1 and 2 can reduce parasitic absorption, so that the short-circuit current density of the cell is improved, and the cell efficiency is further improved; the stacked solar cell provided in embodiment 3 forms a better tunneling composite structure (i.e., the connection layer 120 and the transparent conductive layer 140 illustrated in fig. 18), which improves the fill factor and thus the cell efficiency. It can be seen that the stacked solar cell provided by the embodiment of the application has more advantages.

Based on the same inventive concept, the embodiments of the present application provide a photovoltaic module including the stacked solar cell in any of the above embodiments; or a laminated solar cell manufactured by the manufacturing method of the laminated solar cell in any embodiment.

Further, a plurality of stacked solar cells may be provided, and the stacked solar cells may be electrically connected in a whole or multiple-piece manner to form a plurality of cell strings, and the plurality of cell strings may be electrically connected in series and/or parallel. The photovoltaic module may further include an encapsulation layer for covering a surface of the cell string, and a cover plate for covering a surface of the encapsulation layer remote from the cell string. Specifically, in some embodiments, multiple battery strings may be electrically connected by conductive charges. The encapsulation layer covers the surface of the stacked solar cell. The encapsulation layer may be an organic encapsulation film such as an ethylene-vinyl acetate copolymer film, a polyethylene octene co-elastomer film, or a polyethylene terephthalate film, for example. The cover plate can be a glass cover plate, a plastic cover plate and the like with a light transmission function.

The advantages of the laminated solar cell in any of the above embodiments, or the advantages of the laminated solar cell manufactured by the method for manufacturing a laminated solar cell in any of the above embodiments, are similar, and are not described in detail herein.

Based on the same inventive concept, the embodiment of the application provides a photovoltaic system, which comprises the photovoltaic module in any embodiment. The photovoltaic module has the advantages that the photovoltaic system also has, and the description thereof is omitted.

It will be appreciated that the photovoltaic system may be employed in photovoltaic power plants, e.g., ground power plants, rooftop power plants, surface power plants, etc., as well as in devices or apparatus that utilize solar energy for generating electricity, e.g., consumer solar power sources, solar street lamps, solar automobiles, solar energy buildings, etc. Of course, it is understood that the application scenario of the photovoltaic system is not limited thereto, that is, the photovoltaic system may be applied to all fields where solar energy is required to generate electricity. Taking a photovoltaic power generation system network as an example, the photovoltaic system can comprise a photovoltaic array, a confluence box and an inverter, wherein the photovoltaic array can be an array combination of a plurality of photovoltaic modules, for example, the photovoltaic modules can form a plurality of photovoltaic arrays, the photovoltaic arrays are connected with the confluence box, the confluence box can confluence currents generated by the photovoltaic arrays, and the confluence currents flow through the inverter to be converted into alternating currents required by a commercial power grid and then are connected with the commercial power network so as to realize solar power supply.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims

1. A laminated solar cell, comprising a first cell, a connection layer and a second cell which are laminated in sequence along a first direction; orthographic projections of the first battery and the second battery on a reference plane have overlapping projections; the first direction is the thickness direction of the laminated solar cell, and the reference surface is a plane perpendicular to the first direction;

the orthographic projection of the connecting layer on the reference surface is positioned in the overlapping projection range, and the orthographic projection area of the connecting layer on the reference surface is smaller than the overlapping projection area; portions of one side surfaces of the first and second batteries facing each other are in contact with each other;

The first battery has a first surface disposed toward the second battery; the first surface has a first side facing the second cell and a second side facing away from the second cell; a portion of the connection layer is located on the first side of the first surface and another portion is located on the second side of the first surface.

2. The laminated solar cell according to claim 1, wherein at least part of the outline of the orthographic projection of the connection layer on the reference plane is located within the outer outline of the overlapping projections.

3. The laminated solar cell according to claim 2, wherein the orthographic profile of the connection layer on the reference plane lies entirely within the outer profile of the overlapping projections; or alternatively

The part of the orthographic projection outline of the connecting layer on the reference surface is positioned in the outer outline of the overlapped projection; the remaining part of the orthographic projection of the connecting layer on the reference plane and the part of the outer contour of the overlapping projection coincide with each other.

4. The laminated solar cell of claim 1, wherein the overlapping projections comprise a first overlapping projection and a second overlapping projection, the first overlapping projection overlapping with an orthographic projection of the connection layer on the reference plane; an orthographic projection of a portion of the first battery and the second battery, where the surfaces of the sides facing each other are in contact with each other, on the reference plane is located within the second overlapping projection.

5. The laminated solar cell of claim 4, wherein one of the first overlapping projection and the second overlapping projection comprises a plurality of sub-overlapping projections, at least some of the plurality of sub-overlapping projections being arranged in a preset pattern.

6. The laminated solar cell according to claim 5, wherein the predetermined rule includes at least one of arrangement in a single direction and arrangement in an array.

7. The laminated solar cell of claim 5, wherein the at least partially overlapping projections are arranged in rows along a second direction and in columns along a third direction; the second direction and the third direction intersect each other and are both perpendicular to the first direction; or alternatively

The at least partially overlapping projections include a plurality of first overlapping projections and a plurality of second overlapping projections; all the first sub-overlapping projections extend along the fourth direction and are arranged at intervals along the fifth direction; all of the second sub-overlapping projections are spaced apart along the fourth direction; each of the second sub-overlapping projections is connected to any one of all of the first sub-overlapping projections; the fourth direction and the fifth direction intersect each other and are both perpendicular to the first direction.

8. The laminated solar cell of claim 5, wherein the first overlapping projection comprises a plurality of sub-overlapping projections;

The connection layer comprises a plurality of connection parts, and orthographic projections of the connection parts on the reference surface define a plurality of sub-overlapping projections.

9. The laminated solar cell according to claim 8, wherein a shape of a cross section of the connection portion in the first preset direction includes at least one of a regular pattern and an irregular pattern;

10. The laminated solar cell of claim 5, wherein the second overlapping projection comprises a plurality of sub-overlapping projections;

And a plurality of openings are formed in the connecting layer, and orthographic projections of the plurality of openings on the reference surface define a plurality of sub-overlapping projections.

11. The laminated solar cell according to claim 10, wherein the shape of the cross section of the opening along the second preset direction includes any one or a combination of a regular pattern and an irregular pattern;

12. The laminated solar cell of claim 5, wherein the shape of the sub-overlapping projections comprises any one or a combination of regular patterns and irregular patterns.

13. The tandem solar cell according to any one of the claims 1-12, wherein said second cell comprises a first charge transport layer laminated to a side of said connection layer facing away from said first cell; a portion of the first charge transport layer is in contact with the connection layer and another portion is in contact with the first battery;

14. The tandem solar cell according to any one of the claims 1-12, wherein said second cell comprises a first charge transport layer laminated to a side of said connection layer facing away from said first cell; a portion of the first charge transport layer is in contact with the connection layer and another portion is in contact with the first battery;

15. The laminated solar cell according to any one of claims 1 to 12, wherein the ratio of the area of orthographic projection of the connection layer on the reference plane to the area of overlapping projection is a preset ratio q; the preset ratio q satisfies the condition: q is more than or equal to 0.1 and less than 1.

16. The laminated solar cell according to any one of claims 1 to 12, wherein the material of the connection layer is a transparent conductive oxide.

17. The solar cell according to claim 16, wherein the material of the connection layer comprises any one or more of indium tin oxide, aluminum doped zinc oxide, indium doped zinc oxide, fluorine doped tin oxide.

18. The laminated solar cell according to any one of claims 1 to 12, wherein the dimension of the connection layer in the first direction is greater than 0nm and less than or equal to 100nm.

19. The stacked solar cell of any one of claims 1-12, wherein the first cell is one of a heterojunction cell, a tunnel oxide passivation contact cell, or an emitter backside passivation cell, and the second cell is a perovskite cell.

20. A method of manufacturing a stacked solar cell, comprising:

Providing a first battery;

Forming a connection layer on one side of the first battery along a first direction; the orthographic projection of the connecting layer on the reference surface is positioned in the orthographic projection range of the first battery on the reference surface; the area of the orthographic projection of the connecting layer on the reference surface is smaller than the area of the orthographic projection of the first battery on the reference surface;

Manufacturing a second cell on one side of the connecting layer, which is away from the first cell, to form a laminated solar cell; orthographic projections of the first battery and the second battery on the reference surface overlap each other, and portions of the side surfaces of the first battery and the second battery facing each other are in contact with each other; the first battery has a first surface disposed toward the second battery; the first surface has a first side facing the second cell and a second side facing away from the second cell; a portion of the connection layer is located on the first side of the first surface, and another portion is located on the second side of the first surface;

The first direction is the thickness direction of the laminated solar cell, and the reference surface is a plane perpendicular to the first direction.

21. The method of manufacturing a stacked solar cell according to claim 20, wherein before forming a connection layer on one side of the first cell in the first direction, the method comprises:

Wherein the connecting layer is formed on one side of the transparent conductive layer, which is away from the first battery.

22. The method of manufacturing a stacked solar cell as claimed in claim 20 or 21, wherein forming a connection layer on one side of the first cell in the first direction comprises:

forming the connecting layer on one side of the first battery along the first direction through a preset process; the preset process comprises any one or more of a mask process and a laser etching process.

23. A photovoltaic module comprising a laminated solar cell according to any one of claims 1-19; or alternatively

A laminated solar cell manufactured by a manufacturing method comprising the laminated solar cell according to any one of claims 20 to 22.

24. A photovoltaic system comprising the photovoltaic module of claim 23.