CN117411983A - System and method for dynamic merging - Google Patents
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Abstract
Systems and methods for dynamic merging are disclosed. In some embodiments, the method comprises: dividing a first pre-image frame into a first plurality of cells; and processing each of the first plurality of tiles to form a respective sub-array of pixels, the first plurality of tiles comprising: a first grid having a first size, and a second grid having a second size different from the first size.
Description
The present application claims priority from U.S. application Ser. No. 63/389,253, filed on 7.14 of 2022, and U.S. application Ser. No. 17/821,765, filed on 8.23 of 2022, the disclosures of which are incorporated herein by reference for all purposes.
Technical Field
One or more aspects in accordance with embodiments of the present disclosure relate to graphics processing, and more particularly, to systems and methods for dynamic binning.
Background
A Graphics Processor (GPU) may be employed to generate a two-dimensional image from a three-dimensional wire frame model (wireframe model). Such processing may require a significant amount of computation to be performed for each image frame, and the available time may be a video frame time (e.g., the inverse of the video frame rate).
Aspects of the present disclosure relate to this general technical environment.
Disclosure of Invention
According to an embodiment of the present disclosure, there is provided a method including: dividing a first pre-image frame into a first plurality of cells; and processing each of the tiles to form a respective sub-array of pixels, the first plurality of tiles comprising: a first grid having a first size, and a second grid having a second size different from the first size.
In some embodiments, the method further comprises: dividing the second pre-image frame into a second plurality of cells; and processing each of the second plurality of tiles to form a respective sub-array of pixels, wherein the step of dividing the second pre-image frame is different from the step of dividing the first pre-image frame.
In some embodiments, the first dimension comprises: a horizontal dimension that is greater than a horizontal dimension of the second dimension, and a vertical dimension that is greater than a vertical dimension of the second dimension; the first grid has a center a first distance from a center of the first pre-image frame; and the second frame has a center that is a second distance from the center of the first pre-image frame, the second distance being less than the first distance.
In some embodiments, each of the first plurality of cells having a center that is a distance greater than a threshold distance from a center of the first pre-image frame has a size comprising: a horizontal dimension that is greater than a horizontal dimension of the second dimension, and a vertical dimension that is greater than a vertical dimension of the second dimension.
In some embodiments, the first plurality of cells further includes a third cell having a third size different from the first size and different from the second size.
In some embodiments, the third dimension comprises: a horizontal dimension that is greater than a horizontal dimension of the first dimension, and a vertical dimension that is greater than a vertical dimension of the first dimension; and the third frame has a center that is a third distance from the center of the first pre-image frame, the third distance being greater than the first distance.
In some embodiments, the first distance is a weighted chebyshev distance.
In some embodiments, the first grid includes N pixels and N vertices; the second grid comprises M pixels and M vertexes; n is greater than 2M; and n is less than 1.5m.
In some embodiments, the first pre-image frame comprises a plurality of pixels; the first plurality of tiles includes a first subset of tiles, the tiles of the first subset together including 0.2 of pixels of the first pre-image frame; and each of the first subset of the cells does not contain a vertex.
According to an embodiment of the present disclosure, there is provided a system including: a processing circuit; and a memory operably connected to the processing circuit and storing instructions that, when executed by the processing circuit, cause the system to perform a method comprising: dividing a first pre-image frame into a first plurality of cells; and processing each of the tiles to form a respective sub-array of pixels, the first plurality of tiles comprising: a first grid having a first size, and a second grid having a second size different from the first size.
In some embodiments, the method further comprises: dividing the second pre-image frame into a second plurality of cells; and processing each of the second plurality of tiles to form a respective sub-array of pixels, wherein the step of dividing the second pre-image frame is different from the step of dividing the first pre-image frame.
In some embodiments, the first dimension comprises: a horizontal dimension that is greater than a horizontal dimension of the second dimension, and a vertical dimension that is greater than a vertical dimension of the second dimension; the first grid has a center a first distance from a center of the first pre-image frame; and the second frame has a center that is a second distance from the center of the first pre-image frame, the second distance being less than the first distance.
In some embodiments, each of the first plurality of cells having a center that is a distance greater than a threshold distance from a center of the first pre-image frame has a size comprising: a horizontal dimension that is greater than a horizontal dimension of the second dimension, and a vertical dimension that is greater than a vertical dimension of the second dimension.
In some embodiments, the first plurality of cells further includes a third cell having a third size different from the first size and different from the second size.
In some embodiments, the third dimension comprises: a horizontal dimension that is greater than a horizontal dimension of the first dimension, and a vertical dimension that is greater than a vertical dimension of the first dimension; and the third frame has a center that is a third distance from the center of the first pre-image frame, the third distance being greater than the first distance.
In some embodiments, the first distance is a weighted chebyshev distance.
In some embodiments, the first grid includes N pixels and N vertices; the second grid comprises M pixels and M vertexes; n is greater than 2M; and n is less than 1.5m.
In some embodiments, the first pre-image frame comprises a plurality of pixels; the first plurality of tiles includes a first subset of tiles, the tiles of the first subset together including 0.2 of pixels of the first pre-image frame; and each of the first subset of the cells does not contain a vertex.
According to an embodiment of the present disclosure, there is provided a system including: means for processing; and a memory operatively connected to the means for processing and storing instructions that, when executed by the means for processing, cause the system to perform a method comprising: dividing a first pre-image frame into a first plurality of cells; and processing each of the tiles to form a respective sub-array of pixels, the first plurality of tiles comprising: a first grid having a first size, and a second grid having a second size different from the first size.
In some embodiments, the method further comprises: dividing the second pre-image frame into a second plurality of cells; and processing each of the second plurality of tiles to form a respective sub-array of pixels, wherein a first tile comprises pixels in a first pre-image frame having a first pair of coordinates; and a third of the second plurality of cells has a second size different from the first size and includes pixels in the second pre-image frame having coordinates equal to the first pair of coordinates.
Drawings
These and other features and advantages of the present disclosure will be appreciated and understood with reference to the specification, claims and appended drawings, wherein,
FIG. 1 is a block diagram of a portion of a graphics processing system according to an embodiment of the present disclosure;
FIG. 2A is a flow chart of a portion of a method for video frame processing according to an embodiment of the present disclosure;
FIG. 2B is a buffer diagram according to an embodiment of the present disclosure;
FIG. 3A is a schematic illustration of an image according to an embodiment of the present disclosure;
FIG. 3B is a schematic diagram of an image showing a grid according to an embodiment of the present disclosure;
FIG. 3C is a schematic diagram of an image showing a grid according to an embodiment of the present disclosure;
FIG. 3D is a schematic diagram of an image showing a grid according to an embodiment of the present disclosure;
FIG. 4A is a flow chart of a method according to an embodiment of the present disclosure; and
fig. 4B is a flow chart of a method according to an embodiment of the present disclosure.
Detailed Description
The detailed description set forth below in connection with the appended drawings is intended as a description of exemplary embodiments of the systems and methods for merging provided in accordance with the present disclosure and is not intended to represent the only forms in which the present disclosure may be constructed or utilized. The description sets forth the features of the present disclosure in connection with the illustrated embodiments. It is to be understood, however, that the same or equivalent functions and structures may be accomplished by different embodiments that are also intended to be encompassed within the scope of the disclosure. As shown elsewhere herein, like element numbers are intended to represent like elements or features.
A Graphics Processor (GPU) may be well suited to performing graphics processing operations (e.g., rendering a two-dimensional image from a wire frame model, including a two-dimensional array of pixels (e.g., made up of a two-dimensional array of pixels), the wire frame model may include a plurality of triangles in three-dimensional space (e.g., made up of a plurality of triangles in three-dimensional space).
The rendering of an image or "rendering buffer" may include a number of steps (such as those shown in fig. 2A). As shown, these steps may include a vertex processing step 205, a "clipping, culling, and projecting" step 210, and a merging step 215. The merging step 215 may use the "pre-image frame" as input, which may include inputs including vertices, vertex attributes, and other data corresponding to the rectangular image being rendered. As used herein, an "image" is an array of (e.g., rectangular) pixels produced by a rendering process that may use a pre-image frame as input. The merging step 215 may involve dividing or "splitting" an image region (rectangular region corresponding to a rendered image) into a plurality of rectangular regions, each of which may be referred to as a "grid" or "tile". The remaining processing steps (steps 220 through 240) may then be performed one cell at a time. The rendering of each tile may produce an array of pixels, which is a sub-array of the rendered image. For example, if GPU 105 includes multiple cores, each core may process a corresponding drawing at any time, then several drawing may be processed in parallel. As shown, the steps performed for each of the tiles may include, but are not limited to, a rasterization step (raster step) 220, an early Z (early Z) step 225, a pixel processing step 230, a late Z (late Z) step 235, and a blending step 240. The steps (steps 220 to 240) performed for each cell may use a consolidated storage as shown in fig. 2B; the merge store may include a draw buffer (draw buffer) 250 and an index buffer 255 for the n+1 tiles.
In some embodiments, the cells may be selected to have different sizes, or the segmentation of one pre-image frame may be different from the segmentation of another pre-image frame (e.g., the size of the cells (or the number of cells) may vary from one frame to the next). As used herein, the segmentation of a first pre-image frame may be referred to as "distinct" from the segmentation of a second pre-image frame if any of the tiles in the first pre-image frame overlap (have common pixels) with more than one of the tiles in the second pre-image frame. In one example, if a first frame in a first pre-image frame (the first frame having a first size) includes pixels in the first pre-image frame having a first pair of coordinates and a second frame in a second pre-image frame (the second frame having a second size different from the first size) includes pixels in the second pre-image frame having coordinates equal to the first pair of coordinates, then the segmentation of the first pre-image frame may be referred to as "different from the segmentation of the second pre-image frame. Fig. 3A shows an example of several objects 305 to be rendered to form an image on a uniformly colored background 310. Fig. 3B, 3C, and 3D illustrate merging that may be performed in various embodiments. Each cell will be rectangular and may be defined by the coordinates of its corners (corner), where the coordinates of the corners of the cell are pixel offsets in the rendered image, where the pixel offsets include pixels that share an edge pixel offset. Each grid may have two dimensions: vertical (height) dimensions and horizontal (width) dimensions. Each cell may have an area (area is defined as the number of pixels in the cell in the rendered image). Each bin may have a center (center may be defined as a median pixel offset with respect to height and width, or as the centroid of the bin); the coordinates of the center need not be an integer (e.g., if the grid has a width or height of an even number of pixels).
Fig. 3B illustrates a merge resulting from a method that may be referred to as "gaze point importance (foveated importance)" merge. The merging method uses a smaller bin closer to the center of the pre-image frame and a larger bin farther from the center of the pre-image frame. For example, each cell having a center that is a distance from the center of the pre-image frame that is less than or equal to the threshold may be a first size, and each cell having a center that is a distance from the center of the pre-image frame that is greater than the threshold may be a second size that is greater than the first size. A larger bin may be larger than a smaller bin in both height and width. If Euclidean measure of distance is used (Euclidean measure), the boundary between the region with fewer pixels and the region with more pixels may be approximately circular. If a Manhattan measure of distance is used (Manhattan measure), the boundary may be square rotated 45 degrees with respect to the horizontal and vertical axes. If a chebyshev measure of distance (Chebyshev measure) is used, the boundary may be square, and if a weighted chebyshev measure of distance (where the distance D between the first and second points is defined by d=max (a|x 2 –x 1 |+|y 2 –y 1 I) is given, wherein (x) 1 ,y 1 ) Is the coordinates of the first point, (x 2 ,y 2 ) Is the coordinates of the second point and a is the normal number), the boundary may be rectangular (as shown in fig. 3B). In some embodiments, more than one threshold and a corresponding number of boundaries may be used (e.g., two threshold distances and two corresponding boundaries, as shown in fig. 3B). The outermost cells may be truncated by the edges of the pre-image frame (as shown in fig. 3B).
Fig. 3C illustrates a merge resulting from a method that may be referred to as a "vertex count heuristic (vertex count heuristic)" merge. In this merging method, the grid may be smaller in the region of the pre-image frame having high density of triangle vertices. In this embodiment, if the pre-image frame contains more than a threshold number of triangle vertices, it may be divided into two (e.g., equal-sized) bins, and thereafter each bin having more than the threshold number of triangle vertices may be recursively divided into two (e.g., equal-sized) bins (e.g., using alternating vertical and horizontal division lines). As a result of using this merging method, the number of triangle vertices per bin may be approximately the same across the pre-image frame, even though some bins may be significantly larger than others. For example, the first cells may be twice as large as the second cells (as measured by their respective areas) while including less than 1.5 times the triangle vertices of the second cells. In some embodiments, the number of triangles is used instead of the number of triangle vertices to achieve a similar effect. In such embodiments, the number of triangles in the cells may be defined as the number of triangles at least partially in the cells (such that triangles partially in the cells and partially outside the cells are included in the triangle count of the cells).
Fig. 3D illustrates the merging resulting from a method that may be referred to as maximizing the empty rectangle. In this merging method, a rectangular grid may be selected to fill each available vertex-free area, provided that the grid size required to do so is not less than the threshold minimum grid size.
The use of vertex count heuristic merging may improve wave concurrency (wave concurrency). For example, each of several tiles may be assigned to a respective core of GPU 105. In this case, if the number of triangle vertices in all the tiles is approximately the same, then the multiple cores may all complete the rendering task at approximately the same time (thereby maximizing computation density, hiding any bubbles in the pipeline, and improving wave concurrency). In some embodiments, the use of merging using a method that maximizes the empty rectangle may improve processing efficiency by separating a set of tiles that may together include a large number of pixels (e.g., 20% of the pixels of the pre-image frame) and may also not include vertices. The grid without vertices is eliminated from further processing, improving computation time by reducing the overhead of exchanging the grid.
In some embodiments, a merge decision for one pre-image frame is made based on characteristics of a previously rendered pre-image frame (e.g., a pre-image frame immediately preceding the current pre-image frame). When rendering the pre-image frame, an analysis of triangle vertices or triangles in the pre-image frame may be used to determine how to partition the pre-image frame into bins, and a set of bins derived in this way may be stored as a histogram-based look-up map, which may then be used to perform merging on one or more subsequent image frames. The lookup map may be a list of cells, where each entry includes, for example, the coordinates of one corner of the cell and the size of the cell. An inverse look-up map may also be generated and stored; the inverse lookup map may indicate, for each pixel in the pre-image frame, an identifier (e.g., index) of the cell to which it belongs.
In some embodiments, the set of tiles into which the pre-image frames are partitioned may change relatively infrequently (e.g., once every K pre-image frames, where K is an integer between 3 and 1000), or the set of tiles may be static (e.g., if gaze point importance merging is used).
Fig. 4A is a flow chart of a method according to some embodiments. At 405, a determination is made as to whether dynamic merging (as opposed to static merging) will be used (i.e., whether the cell size changes with the current frame); if so, at 410, a variable-size grid (or "tile") is generated based on a merging method (such as one of the merging methods described above), and the pre-image frame is partitioned into multiple grids according to a lookup map. At 412, the tile (or an update to the tile) may be stored in the lookup map 415. If dynamic merging is not used during the current frame, then at 420, the pre-image frame is partitioned into multiple tiles using the look-up map 415. At 425, the remaining steps of the Graphics (GFX) pipeline are performed.
Fig. 4B is a flow chart of a method according to some embodiments. The method may include partitioning the first pre-image frame into a first plurality of tiles at 450 and processing each of the tiles to form a respective sub-array of pixels at 455. The first plurality of cells may include a first cell having a first size and a second cell having a second size different from the first size. As used herein, the size of a first cell is different from the size of a second cell if (i) the height of the first cell is different from the height of the second cell and/or (ii) the width of the first cell is different from the width of the second cell. In some embodiments, the step of partitioning into tiles may be the same for a set of frames (e.g., as described above, the step of partitioning into tiles may change only once per K frames).
As used herein, a portion of an item "means at least some of the item" and thus may represent less than all of the item. Thus, the "part of a thing" includes the whole thing as a special case (i.e., the whole thing is an example of a part of a thing). As used herein, when the second parameter is "within" the first parameter X, it means that the second parameter is at least X-Y and the second parameter is at most x+y. As used herein, when the second number is within "Y% of the first number, it means that the second number is at least (1-Y/100) times the first number, and the second number is at most (1+Y/100) times the first number. As used herein, the term "or" should be interpreted as "and/or" such that, for example, "a or B" represents any one of "a", "B" and "a and B".
The terms "processing circuitry" and "means for processing" are used herein to refer to any combination of hardware, firmware, and software, or to processing data or digital signals. The processing circuit hardware may include, for example, application Specific Integrated Circuits (ASICs), general-purpose or special-purpose Central Processing Units (CPUs), digital Signal Processors (DSPs), graphics Processors (GPUs), and programmable logic devices, such as Field Programmable Gate Arrays (FPGAs). In processing circuitry, as used herein, each function is performed by hardware configured to perform the function (i.e., hardwired), or by more general purpose hardware configured to execute instructions stored in a non-transitory storage medium, such as a CPU. The processing circuitry may be fabricated on a single Printed Circuit Board (PCB) or distributed over several interconnected PCBs. The processing circuitry may include other processing circuitry (e.g., the processing circuitry may include two processing circuits interconnected on a PCB: an FPGA and a CPU).
As used herein, the term "array" refers to an ordered set of numbers, regardless of how stored (e.g., in consecutive memory locations, or in a linked list). As used herein, when a method (e.g., adjustment) or a first parameter (e.g., a first variable) is referred to as being "based on" a second parameter (e.g., a second variable), it means that the second parameter is an input to the method or affects the first parameter (e.g., the second parameter may be an input (e.g., a unique input or one of several inputs) that is a function of calculating the first parameter, or the first parameter may be equal to the second parameter, or the first parameter may be the same as the second parameter (e.g., stored in memory at the same location or locations as the second parameter)).
It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Accordingly, a first element, component, region, layer or section discussed herein could be termed a second element, component, region, layer or section without departing from the spirit and scope of the inventive concept.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the terms "substantially," "about," and the like are used as approximate terms, rather than degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.
As used herein, the singular is intended to include the plural unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. An entire column of elements is modified when a representation such as "at least one of … …" follows a column of elements, without modifying individual elements in the column. Furthermore, the use of "may" when describing embodiments of the inventive concepts means "one or more embodiments of the present disclosure. Furthermore, the term "exemplary" is intended to mean exemplary or illustrative. As used herein, the term "use" may be considered synonymous with the term "utilization".
It will be understood that when an element or layer is referred to as being "on," "connected to," "coupled to" or "adjacent to" another element or layer, it can be directly on, connected to, coupled to or adjacent to the other element or layer, or one or more intervening elements or layers may be present. In contrast, when an element or layer is referred to as being "directly on," "directly connected to," "directly coupled to," or "directly adjacent to" another element or layer, there are no intervening elements or layers present.
Any numerical range recited herein is intended to include all sub-ranges subsumed with the same numerical precision within the recited range. For example, a range of "1.0 to 10.0" or "between 1.0 and 10.0" is intended to include all subranges between (and inclusive of) the recited minimum value of 1.0 and the recited maximum value of 10.0 (i.e., having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6). Similarly, a range described as "within 35% of 10" is intended to include all subranges (i.e., having a minimum value equal to or greater than 6.5 and a maximum value equal to or less than 13.5, such as, for example, 7.4 to 10.6) between (i.e., (1-35/100) times 10) the recited minimum value 6.5 and (i.e., (1+35/100) times 10) the recited maximum value. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein, and any minimum numerical limitation recited in the present specification is intended to include all higher numerical limitations subsumed therein.
Although exemplary embodiments of systems and methods for merging have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Thus, it will be appreciated that systems and methods for merging constructed in accordance with the principles of the present disclosure may be implemented in a manner different from that specifically described herein. The invention is also defined in the appended claims and equivalents thereof.
Claims (20)
1. A method for dynamic merging, comprising:
dividing a first pre-image frame into a first plurality of cells; and
processing each of the first plurality of tiles to form a respective sub-array of pixels,
the first plurality of cells includes:
a first grid having a first size, an
The second grid has a second size different from the first size.
2. The method of claim 1, further comprising:
dividing the second pre-image frame into a second plurality of cells; and
processing each of the second plurality of tiles to form a respective sub-array of pixels,
wherein the step of dividing the second pre-image frame is different from the step of dividing the first pre-image frame.
3. The method of claim 1, wherein,
the first dimension includes a horizontal dimension and a vertical dimension, wherein,
the horizontal dimension of the first dimension is greater than the horizontal dimension of the second dimension, and/or
The vertical dimension of the first dimension is greater than the vertical dimension of the second dimension;
the first grid has a center a first distance from a center of the first pre-image frame; and is also provided with
The second frame has a center that is a second distance from the center of the first pre-image frame, the second distance being less than the first distance.
4. The method of claim 3, wherein each of the first plurality of cells having a center that is a distance greater than a threshold distance from a center of the first pre-image frame has a size comprising a horizontal size and a vertical size, wherein,
the horizontal dimension is greater than the horizontal dimension of the second dimension, and/or
The vertical dimension is greater than the vertical dimension of the second dimension.
5. A method according to claim 3, wherein the first plurality of cells further comprises a third cell having a third size different from the first size and different from the second size.
6. The method of claim 5, wherein,
the third dimension includes a horizontal dimension and a vertical dimension, wherein,
the horizontal dimension of the third dimension is greater than the horizontal dimension of the first dimension, and/or
The vertical dimension of the third dimension is greater than the vertical dimension of the first dimension; and is also provided with
The third frame has a center that is a third distance from the center of the first pre-image frame, the third distance being greater than the first distance.
7. A method according to claim 3, wherein the first distance is a weighted chebyshev distance.
8. The method of claim 1, wherein,
the first grid comprises N pixels and N vertexes;
the second grid comprises M pixels and M vertexes;
n is greater than 2M; and is also provided with
n is less than 1.5m, wherein each of N, M, n and m is a positive integer.
9. The method of claim 1, wherein,
the first pre-image frame includes a plurality of pixels;
the first plurality of tiles includes a first subset of tiles, the tiles of the first subset together comprising 20% of the pixels of the first pre-image frame; and is also provided with
Each of the first subset of the cells does not contain a vertex.
10. A system for dynamic merging, comprising:
a processing circuit; and
a memory operably connected to processing circuitry and storing instructions that, when executed by the processing circuitry, cause the system to perform a method comprising:
dividing a first pre-image frame into a first plurality of cells; and
processing each of the first plurality of tiles to form a respective sub-array of pixels,
the first plurality of cells includes:
a first grid having a first size, an
The second grid has a second size different from the first size.
11. The system of claim 10, wherein the method further comprises:
dividing the second pre-image frame into a second plurality of cells; and
processing each of the second plurality of tiles to form a respective sub-array of pixels,
wherein the step of dividing the second pre-image frame is different from the step of dividing the first pre-image frame.
12. The system of claim 10, wherein,
the first dimension includes a horizontal dimension and a vertical dimension, wherein,
the horizontal dimension of the first dimension is greater than the horizontal dimension of the second dimension, and/or
The vertical dimension of the first dimension is greater than the vertical dimension of the second dimension;
the first grid has a center a first distance from a center of the first pre-image frame; and is also provided with
The second frame has a center that is a second distance from the center of the first pre-image frame, the second distance being less than the first distance.
13. The system of claim 12, wherein each of the cells of the first plurality of cells having a center that is a distance greater than a threshold distance from a center of the first pre-image frame has a size comprising a horizontal size and a vertical size, wherein the horizontal size is greater than a horizontal size of the second size, and/or
The vertical dimension is greater than the vertical dimension of the second dimension.
14. The system of claim 12, wherein the first plurality of cells further comprises a third cell having a third size different from the first size and different from the second size.
15. The system of claim 14, wherein,
the third dimension includes a horizontal dimension and a vertical dimension, wherein,
the horizontal dimension of the third dimension is greater than the horizontal dimension of the first dimension, and/or
The vertical dimension of the third dimension is greater than the vertical dimension of the first dimension; and
the third frame has a center that is a third distance from the center of the first pre-image frame, the third distance being greater than the first distance.
16. The system of claim 12, wherein the first distance is a weighted chebyshev distance.
17. The system of claim 10, wherein,
the first grid comprises N pixels and N vertexes;
the second grid comprises M pixels and M vertexes;
n is greater than 2M; and is also provided with
n is less than 1.5m, wherein each of N, M, n and m is a positive integer.
18. The system of claim 10, wherein,
the first pre-image frame includes a plurality of pixels;
the first plurality of tiles includes a first subset of tiles, the tiles of the first subset together comprising 20% of the pixels of the first pre-image frame; and is also provided with
Each of the first subset of the cells does not contain a vertex.
19. A system for dynamic merging, comprising:
a processor configured to:
dividing a first pre-image frame into a first plurality of cells; and
processing each of the first plurality of tiles to form a respective sub-array of pixels,
the first plurality of cells includes:
a first grid having a first size, an
The second grid has a second size different from the first size.
20. The system of claim 19, wherein the processor is further configured to:
dividing the second pre-image frame into a second plurality of cells; and is also provided with
Processing each of the second plurality of tiles to form a respective sub-array of pixels,
wherein the first frame comprises pixels in the first pre-image frame having a first pair of coordinates; and is also provided with
A third of the second plurality of cells has a second size different from the first size and includes pixels in the second pre-image frame having coordinates equal to the first pair of coordinates.
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| US63/389,253 | 2022-07-14 | ||
| US17/821,765 | 2022-08-23 | ||
| US17/821,765 US20240020806A1 (en) | 2022-07-14 | 2022-08-23 | System and method for dynamic binning |
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| CN117411983A true CN117411983A (en) | 2024-01-16 |
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