CN117411750A - Data receiving device - Google Patents

Abstract

The present disclosure provides a data receiving apparatus for use in wired high-speed data transmission. The data receiving apparatus according to the present disclosure includes: a first conversion unit configured to convert an input serial signal into a first parallel signal by an analog equalization manner; a second conversion unit configured to convert the input serial signal into a second parallel signal by digital equalization; and a selection unit configured to select one of the first parallel signal and the second parallel signal as an output parallel signal according to a preset condition. The data receiving apparatus according to the present disclosure may select to perform an equalization operation on an input serial signal in an analog manner or a digital manner according to at least one of a nyquist frequency, a modulation mode, and an error rate, etc., which are preset conditions, thereby achieving a balance of performance and power consumption in a single data receiving apparatus.

Description

Data receiving device

Technical Field

The present disclosure relates to the technical field of data processing, and in particular, to a data receiving apparatus for use in wired high-speed data transmission.

Background

In the existing high-speed data receiving device for wired data transmission, particularly under the condition that the nyquist frequency range of a high-speed input signal is large, or multiple modulation modes are required to be supported, or the insertion loss of a transmission channel is unknown, a single equalizer cannot meet the requirements of high performance and low power consumption at the same time.

The above information disclosed in this background section is only for the understanding of the background of the inventive concept and thus may contain information that does not form the prior art.

Disclosure of Invention

In order to solve the above problems in the prior art, the present disclosure proposes a novel high-speed data receiving device.

According to an aspect of the present disclosure, there is provided a data receiving apparatus including: a first conversion unit configured to convert an input serial signal into a first parallel signal by an analog equalization manner; a second conversion unit configured to convert the input serial signal into a second parallel signal by digital equalization; and a selection unit configured to select one of the first parallel signal and the second parallel signal as an output parallel signal according to a preset condition.

The data receiving apparatus according to the present disclosure may select to perform an equalization operation on an input serial signal in an analog manner or a digital manner according to at least one of a nyquist frequency, a modulation mode, and an error rate, etc., which are preset conditions, thereby achieving a balance of performance and power consumption in a single data receiving apparatus.

However, the effects of the present disclosure are not limited to the above-described effects, and various extensions may be made without departing from the spirit and scope of the present disclosure. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the invention.

Fig. 1 is a diagram showing a configuration of a data receiving apparatus according to an embodiment of the present disclosure.

Fig. 2 is a diagram illustrating a more detailed configuration of a data receiving apparatus according to an embodiment of the present disclosure.

Fig. 3 is a diagram showing a configuration of a front-end equalization unit according to an embodiment of the present disclosure.

Fig. 4 is a diagram showing a configuration of a first equalization subunit according to an embodiment of the present disclosure.

Fig. 5 is a diagram showing a configuration of an analog-to-digital conversion subunit according to an embodiment of the present disclosure.

Fig. 6 is a diagram illustrating a configuration of a second equalization subunit according to an embodiment of the present disclosure.

Fig. 7 is a diagram showing a configuration of a selection unit according to an embodiment of the present disclosure.

Fig. 8 is a diagram showing a configuration of a selection unit according to another embodiment of the present disclosure.

Detailed Description

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments of the present disclosure. As used herein, an "embodiment" is a non-limiting example of an apparatus or method employing one or more of the inventive concepts disclosed herein. It may be evident, however, that the exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, certain features of other exemplary embodiments may be used or implemented in some exemplary embodiments without departing from the inventive concept.

Unless otherwise indicated, the described exemplary embodiments should be understood to provide exemplary features of varying detail in some ways that the inventive concept may be practiced. Thus, unless otherwise indicated, features, components, modules, regions, and/or aspects of the embodiments (hereinafter referred to individually or collectively as "elements") may be otherwise combined, separated, interchanged, and/or rearranged without departing from the inventive concepts.

For the purposes of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" may be construed as any combination of two or more of X only, Y only, Z only, or X, Y and Z, such as XYZ, XYY, YZ and ZZ. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms "comprises" and/or "comprising," when used in this specification, mean that there are stated features, steps, operations, elements, components, and/or groups thereof, but that the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof is not precluded.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout.

A data receiving device in a wired high-speed data transmission needs to correctly receive a high-speed input signal. Insertion loss of the high-speed input serial signal in the transmission channel is generally compensated for by an equalizer in the high-speed data receiving apparatus. The continuous time linear equalizer (Continuous Time Linear Equalizer, CTLE) is a linear equalizer composed of analog circuits, and has a simple structure and low power consumption, but has a limited equalizing ability. In addition, the Analog decision feedback equalizer (Analog Decision Feedback Equalier, analog DFE) is a nonlinear equalizer that can effectively reduce intersymbol interference (Inter Symbol Interference, ISI) in transmission.

In many applications, to increase equalization performance, a continuous-time linear equalizer and an analog decision feedback equalizer are connected in series and used simultaneously. As the nyquist frequency of high-speed input signals increases, the timing of the feedback loop in an analog decision feedback equalizer becomes increasingly difficult to satisfy. To reduce the nyquist frequency, high-speed wired transmission also often uses a modulation mode of N-Level Pulse-Amplitude Modulation N-Level (PAM-N). For example, the nyquist frequency in PAM-4 modulation mode is reduced by half compared to the nyquist frequency of Non-Return-to-Zero (NRZ) modulation mode, thus alleviating the timing requirements of the feedback loop in an analog decision feedback equalizer. However, the PAM-4 high speed input signal includes four level signals, and PAM-4 modulation increases the complexity of the analog decision feedback equalizer circuit compared to two level signals in the NRZ modulation mode.

With the progress of semiconductor technology, the scale of digital circuits is gradually increased, the processing capacity is increased, and high-speed signals can be balanced by a digital equalizer. The Digital equalizer may take the form of not only a Digital decision feedback equalizer (Digital DFE) but also a Digital feedforward equalizer (Digital Feed Forward Equalizer, digital FFE), thus further increasing the equalization capability. Moreover, as the supply voltage is lower, the power consumption of the digital equalizer is gradually reduced. Thus, digital equalizers replace analog decision feedback equalizers in some application scenarios. It should be noted that digital equalizers require an analog-to-digital converter to convert the high-speed analog signal to a digital signal.

While both analog decision feedback equalizer and digital equalizer can reduce intersymbol interference of the transmission, their principles of operation are not identical. First, the circuit of the analog decision feedback equalizer is relatively simple, and particularly in NRZ modulation mode, the circuit power consumption is low. In contrast, the overall circuit of a digital equalizer plus the required high-speed analog-to-digital converter is relatively complex, particularly in processes where the semiconductor process is not sufficiently advanced, e.g., greater than 14nm, and the circuit power consumption is large. Second, powerful digital signal processing can make the performance of the digital equalizer better than that of an analog decision feedback equalizer, and thus can overcome more insertion loss in the transmission channel. Furthermore, analog decision feedback equalizers operate at nyquist frequencies, and their feedback loops need to meet demanding timing requirements and are therefore not suitable for operation at particularly high nyquist frequencies. In contrast, the input signal of the digital equalizer is a digital signal obtained by a high-speed analog-to-digital converter, and the operating frequency of the digital equalizer can be lower than the nyquist frequency of the high-speed input signal, so that the timing requirement of the feedback loop in the digital equalizer is more easily satisfied.

In some applications, high-speed data receiving devices are required to operate over a wide nyquist operating frequency range. The high-speed data receiving apparatus also needs to support a plurality of modulation modes. Moreover, the high-speed data receiving apparatus cannot predict the insertion loss in the transmission channel. When the insertion loss in the transmission channel is large, it is difficult for the continuous-time linear equalizer or the analog decision feedback equalizer to meet the performance requirements of the receiving device, overcoming all the channel attenuation. At this time, the digital equalizer is more satisfactory in performance, but its power consumption is generally larger. When the nyquist frequency is low, the modulation mode is relatively simple (e.g. NRZ), or the insertion loss of the transmission channel is relatively small, the continuous-time linear equalizer or the analog decision feedback equalizer can already meet the performance requirement of the high-speed data receiving device, and then the digital equalizer is used again to bring additional power consumption.

Therefore, the high-speed data receiving apparatus needs to balance the contradiction between performance and power consumption. To this end, the present disclosure proposes a data receiving apparatus capable of achieving a balance between performance and power consumption.

The data receiving apparatus of the present disclosure will be described in more detail with reference to the accompanying drawings in conjunction with the detailed description.

Fig. 1 shows a diagram of a configuration of a data receiving apparatus 10 according to an embodiment of the present disclosure. Further, fig. 2 shows a diagram of a more detailed configuration of the data receiving apparatus 10 according to the embodiment of the present disclosure.

Referring to fig. 1, according to an embodiment of the present disclosure, a data receiving apparatus 10 may include: a first conversion unit 700 that converts the input serial signal 11 into the first parallel signal 61 by analog equalization; a second conversion unit 800 that converts the input serial signal 11 into a second parallel signal 62 by digital equalization; and a selection unit 600 that selects one of the first parallel signal 61 and the second parallel signal 62 as the output parallel signal 63 according to a preset condition.

Further, as shown in fig. 2, according to an embodiment of the present disclosure, the data receiving apparatus 10 may further include a front-end equalization unit 100 that performs an analog equalization operation on the input serial signal 11 to generate a front-end equalized serial signal 12, and supplies the front-end equalized serial signal 12 to the first and second conversion units 700 and 800, respectively. The front-end equalization unit 100 will be described in more detail below in connection with fig. 3.

As shown in fig. 2, according to an embodiment of the present disclosure, the first conversion unit 700 may include: a first equalization subunit 200 that performs an analog equalization operation on the front-end equalized serial signal 12 to generate a first equalized serial signal 31; and a serial-to-parallel conversion subunit 300 that performs a serial-to-parallel operation on the first balanced serial signal 31 to output the first parallel signal 61. The first equalization subunit 200 will be described in more detail below in connection with fig. 4.

Those skilled in the art will recognize that the first equalization subunit 200 is optional and not required. In other words, in certain embodiments of the present disclosure, when the data receiving apparatus 10 includes the front-end equalization unit 100, the first equalization subunit 200 may be omitted.

Further, as shown in fig. 2, according to an embodiment of the present disclosure, the second conversion unit 800 may include: an analog-to-digital conversion subunit 400 that converts the front-end equalization serial signal 12 into a digital converted signal 51; and a digital equalization subunit 500 that performs a digital equalization operation on the digital converted signal 51 to output a second parallel signal 62. The analog-to-digital conversion sub-unit 400 and the digital equalization sub-unit 500 will be described in more detail below in connection with fig. 5 and 6, respectively.

Fig. 3 shows a diagram of the configuration of the front-end equalization unit 100 according to an embodiment of the present disclosure.

As shown in fig. 3, the front-end equalization unit 100 may be implemented by an analog front-end equalizer, which may include a continuous-time linear equalizer (CTLE) 101 and a variable gain amplifier (Variable Gain Amplifier, VGA) 102, according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, the continuous-time linear equalizer 101 may receive an input serial signal 11 at a high speed, perform a linear equalization operation on the input serial signal 11, and provide an output signal to the variable gain amplifier 102. According to an embodiment of the present disclosure, the variable gain amplifier 102 may perform a gain amplification or gain reduction operation on the output signal of the continuous-time linear equalizer 101 for controlling the amplitude of the front-end equalization serial signal 12 as its output.

Alternatively, according to an embodiment of the present disclosure, the front-end equalization unit 100 may include a continuous-time linear equalizer 101 instead of the variable gain amplifier 102. In this alternative embodiment, the continuous-time linear equalizer 101 may perform a linear equalization operation on the input serial signal 11 and front-end equalize the serial signal 12.

Alternatively, according to an embodiment of the present disclosure, the variable gain amplifier 102 may receive the input serial signal 11 at a high speed, i.e., first perform a gain amplification or gain reduction operation on the input serial signal 11 for controlling the amplitude of its output and provide its output signal to the continuous-time linear equalizer 101. According to this alternative embodiment, the continuous-time linear equalizer 101 may then perform a linear equalization operation on the output signal of the variable gain amplifier 102 and output it as the front-end equalized serial signal 12.

According to embodiments of the present disclosure, the front-end equalization unit 100 may comprise a cascade of a plurality of continuous-time linear equalizers 101.

Furthermore, according to embodiments of the present disclosure, the front-end equalization unit 100 may include a cascade of a plurality of variable gain amplifiers 102.

Fig. 4 shows a diagram of a configuration of a first equalization subunit 200 according to an embodiment of the present disclosure.

As shown in fig. 4, according to an embodiment of the present disclosure, the first equalization subunit 200 may be implemented by an analog decision feedback equalizer, which may include a first amplifier 201 and a pre-determined analog decision feedback equalizer 202.

According to an embodiment of the present disclosure, as shown in fig. 4, the first amplifier 201 may receive the front-end balanced serial signal 12, perform a gain amplification or gain reduction operation on the front-end balanced serial signal 12, and control the amplitude of the first amplified signal 23 output as it.

According to an embodiment of the present disclosure, as shown in fig. 4, the first amplifier 201 may also receive a first enable signal 21, and the first enable signal 21 may control the operation enable of the first amplifier 201. Specifically, for example, when the first enable signal 21 is at a high level, the first amplifier 201 may operate normally, and when the first enable signal 21 is at a low level, the first amplifier 201 may not operate.

According to embodiments of the present disclosure, as shown in fig. 4, the first amplified signal 23 may be provided to a pre-decision analog decision feedback equalizer 202, and the pre-decision analog decision feedback equalizer 202 performs an analog decision feedback equalization operation on the first amplified signal 23 to output a high-speed equalized signal 31.

In accordance with an embodiment of the present disclosure, as shown in fig. 4, the pre-decision analog decision feedback equalizer 202 may be a full-speed, second-order pre-decision analog decision feedback equalizer supporting NRZ modulation mode, which includes three summers (i.e., a first summer, a second summer, and a third summer), three flip-flops (i.e., a first flip-flop, a second flip-flop, and a third flip-flop), one selector, and one multiplier.

According to an embodiment of the present disclosure, as shown in fig. 4, the first-order coefficient of the pre-determined analog decision feedback equalizer 202 is h1, the second-order coefficient is h2, and h2 is the multiplication coefficient of the multiplier.

According to an embodiment of the present disclosure, as shown in fig. 4, the pre-decision analog decision feedback equalizer 202 may include three summers, with a first summer summing the positive pre-decisions of coefficient h1, a second summer summing the negative pre-decisions of coefficient h1, and a third summer summing the feedback of coefficient h 2.

According to an embodiment of the present disclosure, as shown in fig. 4, the first amplified signal 23 may be input to a third summer, and the high-speed equalized signal 31 is also input to the third summer through feedback of a coefficient h2, summed with the first amplified signal 23, and the result of the third summer is input to the first summer and the second summer.

According to an embodiment of the present disclosure, as shown in fig. 4, the first summer sums the result of the third summer and the positive pre-determination of the coefficient h1, and outputs the result to the first flip-flop.

According to an embodiment of the present disclosure, as shown in fig. 4, the second summer sums the result of the third summer and the negative pre-determination of the coefficient h1, and outputs the result to the second flip-flop.

According to an embodiment of the present disclosure, as shown in fig. 4, the first and second flip-flops are connected to a selector that selects one of the result of the first flip-flop or the result of the second flip-flop according to the high-speed equalized signal 31 and outputs it to a third flip-flop. According to an embodiment of the present disclosure, the output of the third flip-flop is the high speed equalized signal 31.

According to an embodiment of the present disclosure, as shown in fig. 4, the first flip-flop, the second flip-flop, and the third flip-flop may each be connected to the first clock signal 22. According to an embodiment of the present disclosure, the first clock signal 22 may be generated by a Clock Data Recovery (CDR) unit (not shown) that may receive the output parallel signal 63 of the data receiving apparatus 10 according to the present disclosure and recover the first clock signal 22 therefrom. According to embodiments of the present disclosure, the first flip-flop, the second flip-flop, and the third flip-flop may sample their inputs when the first clock signal 22 is at a high level. In view of the fact that clock data recovery units are known to those skilled in the art, their details will not be described in greater detail herein for the sake of brevity.

According to an embodiment of the present disclosure, as shown in fig. 4, the first summer, the second summer, and the third summer may each be connected to a first enable signal 21, the first enable signal 21 controlling the operational enablement of the three summers. For example, when the first enable signal 21 is high, all three summers are operating normally, and when the first enable signal 21 is low, none of the three summers are operating.

According to an embodiment of the present disclosure, the first equalization subunit 200 may include only the pre-decision analog decision feedback equalizer 202 without the first amplifier 201. In this alternative embodiment, the pre-determined analog decision feedback equalizer 202 may directly receive the front-end equalized serial signal 12.

According to an embodiment of the present disclosure, the first equalization subunit 200 may comprise a cascade of a plurality of first amplifiers 201.

Those skilled in the art will recognize that the first equalization subunit 200 is not limited to implementation by an analog decision feedback equalizer, i.e., is not limited to use with an analog decision feedback equalization method. For example, the pre-decision analog decision feedback equalizer 202 may be a first-order or multi-order analog decision feedback equalizer. Further, for example, the pre-decision analog decision feedback equalizer 202 may be a first-order or multi-order analog decision feedback equalizer supporting PAM-N modulation mode.

Fig. 5 shows a diagram of a configuration of an analog-to-digital conversion subunit 400 according to an embodiment of the present disclosure.

As shown in fig. 5, according to an embodiment of the present disclosure, the analog-to-digital conversion subunit 400 may be implemented by the analog-to-digital conversion subunit 400, which may include a second amplifier 401, an Interleaved sampling analog-to-digital converter (Time-Interleaved ADC) 402, and a clock signal generator 403.

According to an embodiment of the present disclosure, as shown in fig. 5, the second amplifier 401 may receive the front-end balanced serial signal 12, perform a gain amplification or gain reduction operation on the front-end balanced serial signal 12, for controlling the amplitude of the second amplified signal 43 output as it.

According to an embodiment of the present disclosure, as shown in fig. 5, the second amplifier 401 may also receive a second enable signal 41, and the second enable signal 41 may control the operation enable of the second amplifier 401. Specifically, for example, when the second enable signal 41 is at a high level, the second amplifier 401 may operate normally, and when the second enable signal 41 is at a low level, the second amplifier 401 may not operate.

According to an embodiment of the present disclosure, as shown in fig. 5, a clock signal generator 403 may generate the clock signal required for the interleaved sampling analog-to-digital converter 402.

According to an embodiment of the present disclosure, as shown in fig. 5, the clock signal generator 403 may receive the second enable signal 41 and the second clock signal 42. According to an embodiment of the present disclosure, the second clock signal 42 may also be generated by a Clock Data Recovery (CDR) unit (not shown) that may receive the output parallel signal 63 of the data receiving apparatus 10 according to the present disclosure and recover the second clock signal 42 therefrom. The clock signal generator 403 may generate the first sampling clock signal 44, the second sampling clock signal 45, the third sampling clock signal 46, the fourth sampling clock signal 47, and the synchronizing clock signal 48 from the second enable signal 41 and the second clock signal 42.

For example, as shown in the timing chart below in fig. 5, when the second enable signal 41 is at a low level, the first sampling clock signal 44, the second sampling clock signal 45, the third sampling clock signal 46, the fourth sampling clock signal 47, and the synchronizing clock signal 48 are all at a low level.

Further, as shown in the timing chart below in fig. 5, when the second enable signal 41 is at a high level, the frequencies of the first sampling clock signal 44, the second sampling clock signal 45, the third sampling clock signal 46, the fourth sampling clock signal 47, and the synchronizing clock signal 48 generated by the clock signal generator 403 are four-divided by the second clock signal 42, wherein the high level of the first sampling clock signal 44, the high level of the second sampling clock signal 45, the high level of the third sampling clock signal 46, and the high level of the fourth sampling clock signal 47 do not overlap each other.

According to an embodiment of the present disclosure, as shown in fig. 5, the second amplified signal 43 may be input to an interleaved sampled analog-to-digital converter 402.

According to an embodiment of the present disclosure, as shown in fig. 5, the interleaved sampled analog-to-digital converter 402 may also receive the second enable signal 41. For example, when the second enable signal 41 is at a high level, the interleaved sampling analog-to-digital converter 402 may operate normally, i.e., perform interleaved sampling on the second amplified signal 43 and convert the sampled signal to the digital converted signal 51, and when the second enable signal 41 is at a low level, the interleaved sampling analog-to-digital converter 402 may not operate.

According to an embodiment of the present disclosure, as shown in FIG. 5, an interleaved sampling analog-to-digital converter 402 may include four sample-holders (S/H), namely a first S/H, a second S/H, a third S/H, and a fourth S/H. Furthermore, according to embodiments of the present disclosure, as shown in fig. 5, the interleaved sampling analog-to-digital converter 402 may further include four sub analog-to-digital converters (ADCs), namely a first ADC, a second ADC, a third ADC, and a fourth ADC. Furthermore, according to embodiments of the present disclosure, as shown in fig. 5, the interleaved sampling analog-to-digital converter 402 may also include a synchronizer.

According to an embodiment of the present disclosure, the interleaved sampling analog-to-digital converter 402 performs interleaved sampling on the second amplified signal 43 when the first sampling clock signal 44 is high, the second sampling clock signal 45 is high, the third sampling clock signal 46 is high, and the fourth sampling clock signal 47 is high, respectively.

According to an embodiment of the present disclosure, as shown in fig. 5, the first S/H receives the second amplified signal 43, samples the second amplified signal 43 when the first sampling clock signal 44 is at a high level, and holds the sampling result of the first S/H when the first sampling clock signal 44 is at a low level. According to an embodiment of the present disclosure, as shown in fig. 5, the output of the first S/H is provided to the first ADC, which also receives the reference voltage vref and the first sampling clock signal 44, performs analog-to-digital conversion on the output of the first S/H and outputs the result to the synchronizer when the first sampling clock signal 44 is at a high level.

According to an embodiment of the present disclosure, as shown in fig. 5, the second S/H receives the second amplified signal 43, samples the second amplified signal 43 when the second sampling clock signal 45 is at a high level, and holds the sampling result of the second S/H when the second sampling clock signal 45 is at a low level. According to an embodiment of the present disclosure, as shown in fig. 5, the output of the second S/H is provided to the second ADC, which also receives the reference voltage vref and the second sampling clock signal 45, performs analog-to-digital conversion on the output of the second S/H and outputs the result to the synchronizer when the second sampling clock signal 45 is at a high level.

According to an embodiment of the present disclosure, as shown in fig. 5, the third S/H receives the second amplified signal 43, samples the second amplified signal 43 when the third sampling clock signal 46 is at a high level, and holds the sampling result of the third S/H when the third sampling clock signal 46 is at a low level. According to an embodiment of the present disclosure, as shown in fig. 5, the output of the third S/H is provided to a third ADC, which also receives the reference voltage vref and the third sampling clock signal 46, performs analog-to-digital conversion on the output of the third S/H and outputs the result to the synchronizer when the third sampling clock signal 46 is at a high level.

According to an embodiment of the present disclosure, as shown in fig. 5, the fourth S/H receives the second amplified signal 43, samples the second amplified signal 43 when the fourth sampling clock signal 47 is at a high level, and holds the sampling result of the fourth S/H when the fourth sampling clock signal 47 is at a low level. According to an embodiment of the present disclosure, as shown in fig. 5, the output of the fourth S/H is provided to the fourth ADC, which also receives the reference voltage vref and the fourth sampling clock signal 47, performs analog-to-digital conversion on the output of the fourth S/H and outputs the result to the synchronizer when the fourth sampling clock signal 47 is at a high level.

According to an embodiment of the present disclosure, as shown in fig. 5, the synchronizer is connected to the first ADC, the second ADC, the third ADC, the fourth ADC, and the synchronization clock signal 48, performs a synchronization operation on the output of the first ADC, the output of the second ADC, the output of the third ADC, and the output of the fourth ADC, and generates the digital conversion signal 51 when the synchronization clock signal 48 is a rising edge. According to embodiments of the present disclosure, digital converted signal 51 may be a divide-by-four digital signal equivalent to front-end equalized serial signal 12.

According to an embodiment of the present disclosure, the analog-to-digital conversion subunit 400 may not include the second amplifier 401. In this alternative embodiment, the sample-interleaved analog-to-digital converter 402 may directly receive the front-end equalized serial signal 12.

According to an embodiment of the present disclosure, the analog-to-digital conversion subunit 400 may comprise a cascade of a plurality of second amplifiers 401.

Those skilled in the art will recognize that analog-to-digital conversion subunit 400 is not limited to use with the high-speed analog-to-digital conversion method described above based on a high-speed analog-to-digital converter.

According to embodiments of the present disclosure, interleaved sample analog-to-digital converter 402 may include a plurality of interleaved sample analog-to-digital converters in series to further reduce the frequency of digital converted signal 51.

According to embodiments of the present disclosure, the interleaved sample analog-to-digital converter 402 may be a direct-comparison ADC (Flash ADC) or an interleaved sample direct-comparison ADC.

According to embodiments of the present disclosure, interleaved sampling analog-to-digital converter 402 may be a Pipelined ADC (Pipelined-ADC) or a Pipelined ADC of interleaved samples.

According to embodiments of the present disclosure, the interleaved sample analog-to-digital converter 402 may be a successive approximation ADC (SAR ADC) or a successive approximation ADC of interleaved samples.

Fig. 6 is a diagram illustrating a configuration of a second equalization subunit 500 according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, the second equalization subunit 500 may be implemented by a Digital equalizer, which may include a Digital feedforward equalizer (Digital FFE) 501 and a Digital decision feedback equalizer (Digital DFE) 502.

According to an embodiment of the present disclosure, as shown in fig. 6, a digital feedforward equalizer 501 may receive a digital converted signal 51 and perform a digital feedforward equalization operation on the digital converted signal 51. Subsequently, the output signal of the digital feedforward equalizer 501 may be provided to a digital decision feedback equalizer 502, the digital decision feedback equalizer 502 performing a digital decision feedback equalization operation on the output signal of the digital feedforward equalizer 501 and outputting a second parallel signal 62.

Alternatively, the digital equalizer used to implement the second equalization subunit 500 may include only the digital feedforward equalizer 501 and not the digital decision feedback equalizer 502, according to embodiments of the present disclosure. In this alternative embodiment, the digital feedforward equalizer 501 directly outputs the second parallel signal 62.

Alternatively, the digital equalizer used to implement the second equalization subunit 500 may include only the digital decision feedback equalizer 502 and not the digital feedforward equalizer 501, according to embodiments of the present disclosure. In this alternative embodiment, digital decision feedback equalizer 502 may perform a digital equalization operation on digital converted signal 51 and output second parallel signal 62.

Alternatively, according to an embodiment of the present disclosure, the digital decision feedback equalizer 502 may receive the digital converted signal 51 and perform a digital decision feedback equalization operation on the digital converted signal 51. The output signal of the digital decision feedback equalizer 502 may then be provided to a digital feedforward equalizer 501, the digital feedforward equalizer 501 performing a digital feedforward equalization operation on the output signal of the digital decision feedback equalizer 502 and outputting a second parallel signal 62.

According to embodiments of the present disclosure, the digital equalizer used to implement the second equalization subunit 500 may include a cascade of a plurality of digital feedforward equalizers 501.

According to an embodiment of the present disclosure, the digital equalizer used to implement the second equalization subunit 500 includes a cascade of a plurality of digital decision feedback equalizers 502.

Fig. 7 shows a diagram of a configuration of a selection unit 600 according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, as shown in fig. 7, the selection unit 600 may include a data selector 601.

According to an embodiment of the present disclosure, as shown in fig. 7, the data selector 601 may receive the first and second parallel signals 61 and 62 and the selection signal 64.

According to an embodiment of the present disclosure, the data selector 601 may select one of the first parallel signal 61 or the second parallel signal 62 according to the selection signal 64 and output it as the output parallel signal 63.

According to an embodiment of the present disclosure, the selection signal 64 may be provided from outside the data receiving apparatus 10.

According to an embodiment of the present disclosure, the selection signal 64 may be provided from a built-in memory of the data receiving apparatus 10.

According to an embodiment of the present disclosure, the selection signal 64 may be set according to a preset condition, wherein the preset condition may be selected from at least one of: nyquist frequency, modulation mode and bit error rate.

Specifically, according to embodiments of the present disclosure, the selection signal 64 may be set according to the nyquist frequency of the input serial signal 11.

According to an embodiment of the present disclosure, the data selector 601 may select the first parallel signal 61 according to the selection signal 64 when the nyquist frequency of the input serial signal 11 is lower than a preset nyquist frequency threshold.

Further, according to an embodiment of the present disclosure, when the nyquist frequency of the input serial signal 11 is higher than a preset nyquist frequency threshold value, the data selector 601 may select the second parallel signal 62 according to the selection signal 64.

According to embodiments of the present disclosure, the selection signal 64 may be set according to a modulation mode.

According to an embodiment of the present disclosure, when the modulation mode is the NRZ mode, the data selector 601 may select the first parallel signal 61 according to the selection signal 64.

Further, according to an embodiment of the present disclosure, when the preset modulation mode is a PAM-N (N > 2) mode, the data selector 601 may select the second parallel signal 62 according to the selection signal 64.

According to embodiments of the present disclosure, the selection signal 64 may be set according to both the nyquist frequency and the modulation mode of the input serial signal 11.

According to an embodiment of the present disclosure, when the nyquist frequency of the input serial signal 11 is lower than a preset nyquist frequency threshold and the preset modulation mode is the NRZ mode, the data selector 601 may select the first parallel signal 61 according to the selection signal 64.

Further, according to an embodiment of the present disclosure, when the nyquist frequency of the input serial signal 11 is higher than a preset nyquist frequency threshold and the modulation mode is a PAM-N (N > 2) mode, the data selector 601 may select the second parallel signal according to the selection signal 64.

Fig. 8 is a diagram showing a configuration of a selection unit 600 according to another embodiment of the present disclosure.

According to an embodiment of the present disclosure, as shown in fig. 8, the selection unit 600 may further include an error rate detector 602 in addition to the data selector 601.

According to an embodiment of the present disclosure, as shown in fig. 8, the bit error rate detector 602 may detect bit error rates of the first parallel signal 61 and the second parallel signal 62 and output the selection signal 64 according to the detection result. As described above, the data selector 601 may select one of the first parallel signal 61 or the second parallel signal 62 according to the selection signal 64 and output it as the output parallel signal 63.

According to an embodiment of the present disclosure, the error rate detector 602 may perform calculation of an error correction code or an error detection code on the input serial signal 11 according to the error correction code or the error detection code included in the input serial signal 11 to obtain error data, and calculate an error rate therefrom. Common error correction codes or error detection codes include ECC, CRC, and the like, and the present disclosure is not particularly limited as to the type of error correction code or error detection code.

According to an embodiment of the present disclosure, the data selector 601 may select the first parallel signal 61 according to the selection signal 64 when the error rate of the first parallel signal 61 is less than or equal to the error rate of the second parallel signal 62.

According to an embodiment of the present disclosure, when the error rate of the first parallel signal 61 is greater than or equal to the error rate of the second parallel signal 62, the data selector 601 may select the second parallel signal 62 according to the selection signal 64.

Alternatively, according to embodiments of the present disclosure, the bit error rate detector 602 may perform detection of the bit error rate only on the first parallel signal 61. In this alternative embodiment, the data selector 601 may select the first parallel signal 61 according to the selection signal 64 when the error rate of the first parallel signal 61 is less than or equal to a first preset threshold. In addition, the data selector 601 may select the second parallel signal 62 according to the selection signal 64 when the error rate of the first parallel signal 61 is greater than a first preset threshold.

Alternatively, according to embodiments of the present disclosure, the bit error rate detector 602 may perform bit error rate detection only on the second parallel signal 62. In this alternative embodiment, the data selector 601 may select the second parallel signal 62 according to the selection signal 64 when the error rate of the second parallel signal 62 is less than or equal to a second preset threshold. In addition, the data selector 601 may select the first parallel signal 61 according to the selection signal 64 when the error rate of the second parallel signal 62 is greater than a second preset threshold.

Although not shown in the drawings, according to an embodiment of the present disclosure, the selection unit 600 may be configured to disable the second conversion unit 800 when the first parallel signal 61 is selected and disable the first conversion unit 700 when the second parallel signal 62 is selected.

For example, according to an embodiment of the present disclosure, when the selection unit 600 selects the first parallel signal 61, the selection unit 600 may generate the second enable signal 41 of a low level such that the circuit unit such as the second amplifier 401 is not operated, thereby disabling the second conversion unit 800.

Further, for example, according to an embodiment of the present disclosure, when the selection unit 600 selects the second parallel signal 62, the selection unit 600 may generate the first enable signal 21 of a low level such that the circuit units such as the first amplifier 401 are not operated, thereby disabling the first conversion unit 700.

The data receiving apparatus according to the present disclosure may select to perform an equalization operation on an input serial signal in an analog manner or a digital manner according to at least one of a nyquist frequency, a modulation mode, and an error rate, etc., which are preset conditions, thereby achieving a balance of performance and power consumption in a single data receiving apparatus.

The foregoing has been presented for purposes of illustration a limited number of possible embodiments of the present disclosure. Although the present disclosure has been described with reference to embodiments thereof, those skilled in the art will appreciate that various modifications and changes can be made to the embodiments of the disclosure without departing from the spirit and scope of the disclosure as disclosed in the appended claims.

Although numerous details are contained herein, these details should not be construed as limitations on the scope of the disclosure or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described herein in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Claims (9)

1. A data receiving apparatus comprising:

a first conversion unit configured to convert an input serial signal into a first parallel signal by an analog equalization manner;

a second conversion unit configured to convert the input serial signal into a second parallel signal by digital equalization; and

and a selection unit configured to select one of the first parallel signal and the second parallel signal as an output parallel signal according to a preset condition.

2. The data receiving apparatus according to claim 1, further comprising:

a front-end equalization unit configured to perform an analog equalization operation on the input serial signal to generate a front-end equalized serial signal, and to supply the front-end equalized serial signal to the first conversion unit and the second conversion unit, respectively.

3. The data receiving apparatus of claim 2, wherein the front-end equalization unit comprises a continuous-time linear equalizer and a variable gain amplifier.

4. The data receiving apparatus according to claim 1, wherein the first conversion unit includes:

a first equalization subunit configured to perform an analog equalization operation on the input serial signal to generate a first equalized serial signal; and

and a serial-to-parallel conversion subunit configured to perform a serial-to-parallel operation on the first balanced serial signal to output the first parallel signal.

5. The data receiving apparatus of claim 4, wherein the first equalization subunit is implemented by an analog decision feedback equalizer.

6. The data receiving apparatus according to claim 1, wherein the second conversion unit includes:

an analog-to-digital conversion subunit configured to convert the input serial signal into a digital converted signal; and

a digital equalization subunit configured to perform a digital equalization operation on the digital converted signal to output the second parallel signal.

7. The data receiving device of claim 6, wherein the digital equalization subunit comprises a digital feedforward equalizer and/or a digital decision feedback equalizer.

8. The data receiving apparatus according to claim 1, wherein the selecting unit is configured to:

disabling the second conversion unit when the first parallel signal is selected, an

The first conversion unit is disabled when the second parallel signal is selected.

9. The data receiving apparatus according to claim 1, wherein the preset condition is selected from at least one of: nyquist frequency, modulation mode and bit error rate.