CN117411458A - Attenuator with adjustable input impedance - Google Patents
Attenuator with adjustable input impedance Download PDFInfo
- Publication number
- CN117411458A CN117411458A CN202211209096.3A CN202211209096A CN117411458A CN 117411458 A CN117411458 A CN 117411458A CN 202211209096 A CN202211209096 A CN 202211209096A CN 117411458 A CN117411458 A CN 117411458A
- Authority
- CN
- China
- Prior art keywords
- branch
- attenuator
- switch
- circuit
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 description 15
- 101100165799 Arabidopsis thaliana CYP86A2 gene Proteins 0.000 description 6
- 230000008569 process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/24—Frequency-independent attenuators
Landscapes
- Attenuators (AREA)
Abstract
The invention provides an input impedance adjustable attenuator, comprising: each circuit page comprises a first branch, a second branch, a third branch and a fourth branch, wherein the first branch comprises a first resistor and a first switch which are connected in series, the second branch comprises a second resistor and a second switch which are connected in series, a first end and a second end of the third branch are respectively arranged between the first resistor and the first switch and between the second resistor and the second switch, and a first end and a second end of the fourth branch are respectively connected with control ends of the first switch and the second switch; the numerical control circuits are in one-to-one correspondence with the N parallel circuit pages, the numerical control circuits are used for providing first control signals and second control signals, the first control signals are used for controlling the on-off states of the third branch circuits, and the second control signals are used for controlling the on-off states of the fourth branch circuits.
Description
Technical Field
The invention relates to the technical field of attenuators, in particular to an attenuator with adjustable input impedance.
Background
Compared with a T-type or pi-type attenuator, the parallel-type attenuator can obtain larger attenuation without extremely small resistance value, and can better resist process fluctuation, for example, the parallel-type attenuator can buffer impedance change under the condition that the resistance value fluctuates by +/-20%, so that the parallel-type attenuator is widely applied in the field of chip design.
The existing parallel attenuator only carries out signal attenuation under fixed input impedance, is difficult to adapt to application scenes with different input impedance values, and has the problem of poor adaptability.
Disclosure of Invention
The embodiment of the invention provides an attenuator with adjustable input impedance, which aims to solve the problem of poor adaptability of the attenuator in the prior art.
An embodiment of the present invention provides an input impedance adjustable attenuator, including:
each circuit page comprises a first branch, a second branch, a third branch and a fourth branch, wherein the first branch comprises a first resistor and a first switch which are connected in series, the second branch comprises a second resistor and a second switch which are connected in series, the first end of the third branch is connected with a connection point between the first resistor and the first switch, the second end of the third branch is connected with a connection point between the second resistor and the second switch, the first end of the fourth branch is connected with a control end of the first switch, the second end of the fourth branch is connected with a control end of the second switch, and N is a positive integer;
the numerical control circuits are in one-to-one correspondence with the N parallel circuit pages, the numerical control circuits are used for providing a first control signal and a second control signal, the first control signal is used for controlling the on-off state of the third branch, and the second control signal is used for controlling the on-off state of the fourth branch.
Optionally, the first control signal and the second control signal are independent of each other.
Optionally, the N parallel circuit pages include M-1 parallel circuit pages, M-1 is a positive integer smaller than N, M is the number of input impedances to be matched, and the first control signals and the second control signals provided by the numerical control circuits corresponding to the M-1 parallel circuit pages are mutually independent.
Optionally, the first control signal and the second control signal provided by the numerical control circuit corresponding to the N-m+1 parallel circuit pages in the N parallel circuit pages are mutually opposite signals.
Optionally, in the case that the M-1 parallel circuit pages are all conductive, the input impedance of the attenuator is the smallest input impedance of the M input impedances to be matched.
Optionally, in the case that the M-1 parallel circuit pages are all open, the input impedance of the attenuator is the largest input impedance of the M input impedances to be matched.
Optionally, the attenuator further includes an impedance matching sheet, the impedance matching sheet is connected in parallel with an nth circuit page of the N parallel circuit pages, and the resistance values and circuit structures of the nth circuit page and the impedance matching sheet are the same.
Optionally, the third branch includes a third resistor, a third switch and a fourth resistor that are sequentially connected in series, and a control end of the third switch is used for receiving the first control signal.
Optionally, the fourth branch includes a fifth resistor and a sixth resistor connected in series, and a connection end of the fifth resistor and the sixth resistor is used for receiving the second control signal.
Optionally, the first switch, the second switch and the third switch are field effect transistors.
In the embodiment of the invention, based on the architecture of the parallel attenuator, on the premise of keeping the advantages and the complexity of the parallel attenuator, the numerical control circuit can respectively control the on-off states of the third branch and the fourth branch of the corresponding circuit pages through the first control signal and the second control signal, so that the on-off state of each circuit page is realized, and N parallel circuit pages can be determined according to the number of input impedance to be matched; and the number of the on circuit pages and the number of the off circuit pages in the N parallel circuit pages are controlled according to the resistance value of each input impedance to be matched, so that the adaptability of the attenuator in various scenes of the input impedance to be matched is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an input impedance adjustable attenuator according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a second embodiment of an input impedance adjustable attenuator according to the present invention;
fig. 3 is a schematic diagram of a control flow of a digital control circuit of an attenuator with adjustable input impedance according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
An embodiment of the present invention provides an input impedance adjustable attenuator, as shown in fig. 1 to 3, including:
each circuit page comprises a first branch, a second branch, a third branch and a fourth branch, wherein the first branch comprises a first resistor R1 and a first switch K1 which are connected in series, the second branch comprises a second resistor R2 and a second switch K2 which are connected in series, the first end of the third branch is connected with a connection point between the first resistor R1 and the first switch K1, the second end of the third branch is connected with a connection point between the second resistor R2 and the second switch K2, the first end of the fourth branch is connected with a control end of the first switch K1, and the second end of the fourth branch is connected with a control end of the second switch K2;
the numerical control circuits are in one-to-one correspondence with the N parallel circuit pages, the numerical control circuits are used for providing a first control signal and a second control signal, the first control signal is used for controlling the on-off state of the third branch, and the second control signal is used for controlling the on-off state of the fourth branch.
In the embodiment, based on the architecture of the parallel attenuator, on the premise of keeping the advantages and the complexity of the parallel attenuator, the numerical control circuit can respectively control the on-off states of the third branch and the fourth branch of the corresponding circuit pages through the first control signal and the second control signal, so that the on-off states of the circuit pages are realized, and N parallel circuit pages can be determined according to the number of input impedances to be matched; and the number of the on circuit pages and the number of the off circuit pages in the N parallel circuit pages are controlled according to the resistance value of each input impedance to be matched, so that the adaptability of the attenuator in various scenes of the input impedance to be matched is improved.
In some alternative embodiments, the digitally controlled circuit includes a first inverter C1 and a second inverter C2, the first inverter C1 is electrically connected to the third terminal of the third branch in the circuit page corresponding to the digitally controlled circuit, and the second inverter C2 is electrically connected to the third terminal of the fourth branch in the circuit page corresponding to the digitally controlled circuit, so that the digitally controlled circuit may provide the first control signal and the second control signal through the first inverter C1 and the second inverter C2, respectively.
Specifically, by setting the first inverter C1 and the second inverter C2, the first inverter C1 is connected to the third end of the third branch, the second inverter C2 is connected to the third end of the fourth branch, the first control signal and the second control signal may be control signals based on voltage signals or numerical control modes, and the first control signal provided by the first inverter C1 and the second control signal provided by the second inverter C2 respectively control the on-off state of each circuit page, so as to realize on (or called on) or off (or called off) of each circuit page, thus, N parallel circuit pages can be determined according to the number of input impedances to be matched; and the number of the opened circuit pages and the number of the closed circuit pages in the N parallel circuit pages are controlled according to the resistance value of each input impedance to be matched, so that the adaptability of the attenuator in various scenes of the input impedance to be matched is improved.
The first terminal of the first switch K1 may be connected to the first radio frequency input end of the current circuit page through the first resistor R1, and the second terminal of the first switch K1 may be connected to the first radio frequency output end of the current circuit page; the first terminal of the second switch K2 can be connected to the second radio frequency input end of the current circuit page through the second resistor R2, and the second terminal of the second switch K2 can be connected to the second radio frequency output end of the current circuit page; the third terminal of the first switch K1 is a control end thereof, the third terminal of the first switch K1 is connected with the first end of the fourth branch, the third terminal of the second switch K2 is a control end thereof, and the third terminal of the second switch K2 is connected with the second end of the fourth branch.
The third branch circuit comprises a third resistor R3, a third switch K3 and a fourth resistor R4 which are sequentially connected in series, and a control end of the third switch K3 is used for receiving the first control signal. The first terminal and the second terminal of the third switch K3 are respectively connected with the third resistor R3 and the fourth resistor R4, the third terminal of the third switch K3 is a control end thereof, and the third terminal of the third switch K3 is electrically connected with the first inverter C1 through the seventh resistor R7, so that the first inverter C1 can control the level of the third branch based on the first control signal.
The fourth branch circuit comprises a fifth resistor R5 and a sixth resistor R6 which are connected in series, and the connection ends of the fifth resistor R5 and the sixth resistor R6 are used for receiving the second control signal. The third end of the fourth branch is located at the connection end between the fifth resistor R5 and the sixth resistor R6, so that the second inverter C2 can control the level of the fourth branch based on the second control signal, and thus the on-off state of the current circuit page can be controlled through the level of the third branch and the level of the fourth branch.
The first switch K1, the second switch K2, and the third switch K3 may be field effect transistors (MOSFETs, MOS), and the minimum resistance value of the attenuator may be changed by a method in which the MOS transistor switches off a circuit page of the minimum resistance.
Wherein the method comprises the steps ofThe input and output of the parallel attenuator can be differential, attenuation is realized by parallel current splitting, and the output current I out And an in-out current I in The ratio between them may be:
I out /I in ＝R in /R inx //…//R iny ；
wherein R is in May be an input impedance R inx Input resistance of x-th circuit page of N parallel circuit pages, R iny The input resistance of the y-th circuit page of the N parallel circuit pages may be. When the input impedance is the target impedance, the attenuation gear can be adjusted by the control signal of the numerical control circuit.
In the case where input impedance matching is required, the following formula is used:
Z in-6dB ＝2R in ||4R in ||8R in ||16R in ||32R in ||...||2 n-1 R in ||2 n R in ||2 n R in ＝R in ；
it can be seen that the input impedance of the N parallel circuit pages is adjusted to be the minimum input impedance of the multiple input impedances to be matched, so that the matching requirement of other input impedances can be satisfied.
Specifically, the first control signal can be sent through the first inverter C1, the second control signal can be sent through the second inverter C2, and the on-off state of the circuit pages corresponding to the numerical control circuit is controlled based on the first control signal and the second control signal, so that the number of the opened circuit pages and the number of the closed circuit pages in the N parallel circuit pages are adjusted, a plurality of input impedances are adapted, and the adaptability of the attenuator under various input impedance scenes needing to be matched is improved.
In some alternative embodiments, the first control signal and the second control signal are independent of each other, in other words, the first inverter C1 and the second inverter C2 have independent control signals, and based on the independent first control signal and the independent second control signal, the on-off state of the circuit page corresponding to the numerical control circuit is controlled.
Specifically, when the first control signal and the second control signal are both 0, the on-off state of the circuit page corresponding to the numerical control circuit is controlled to be off (or called to be closed); when the first control signal is 0 and the second control signal is 1, the on-off state of the circuit page corresponding to the numerical control circuit is controlled to be on (or called on), and the circuit page is a conducting page; when the first control signal is 1 and the second control signal is 0, the on-off state of the circuit page corresponding to the numerical control circuit is controlled to be on, and the circuit page is an impedance matching page.
The conducting page is used for being connected to a next-stage circuit, and current flows out of the page; the current flows through the impedance matching page, which is used to match the input impedance.
In this way, the first control signal and the second control signal are mutually independent, that is, the first inverter C1 and the second inverter C2 have independent control signals to better control the on-off state of the circuit page, so that convenience in matching input impedance is improved, and adaptability of the attenuator in various scenes of input impedance to be matched is improved.
In other alternative embodiments, the N parallel circuit pages include M-1 parallel circuit pages, M-1 is a positive integer smaller than N, M is the number of input impedances to be matched, the first control signals and the second control signals provided by the numerical control circuits corresponding to the M-1 parallel circuit pages are independent of each other, in other words, the first inverter C1 and the second inverter C2 in the numerical control circuits corresponding to the M-1 parallel circuit pages have independent control signals.
Compared with the scheme that each numerical control circuit corresponding to N parallel circuit pages one by one adopts independent control signals, according to the number M of input impedance to be matched, the first control signals and the second control signals of the numerical control circuits corresponding to M-1 parallel circuit pages are determined to adopt independent control signals, so that redundancy is reduced, circuit design is simplified, and response speed of the attenuator is improved.
If each numerical control circuit corresponding to the N parallel circuit pages one by one is controlled by adopting the reciprocal control signals, the current circuit page is communicated to a later circuit or to virtual ground. This makes the current circuit incapable of full turn-off, and thus cannot match the input impedance.
In one example, according to the number M of input impedances to be matched, M-1 parallel circuit pages in the N parallel circuit pages are determined as closable circuit pages, namely, M-1 parallel circuit pages have independent control signals. The first inverter C1 and the second inverter C2 in the numerical control circuit corresponding to the M-1 parallel circuit pages can be provided with a digital control input first control signal ATTm and a second control signal ATTm'. When ATTm and ATTm' are both 0, the circuit page is closed; when ATTm and ATTm' are not all 0, the circuit page is opened. When ATTm is 0 and ATTm' is 1, the circuit page is a conducting page; when ATTm is 1 and ATTm' is 0, the circuit page is a impedance matching page.
In an example, the first control signals and the first control signals provided by the numerical control circuits corresponding to the N-M+1 parallel circuit pages are mutually inverted signals, in other words, the first inverter and the second inverter in the numerical control circuits corresponding to the N-M+1 parallel circuit pages can adopt mutually inverted digital control to input the first control signals ATTn and the second control signalsWhen ATTn is 0, the page is considered to be a conductive page, and current flows from the page when the next stage circuit is connected. When ATTn is 1, the page is an impedance matching page, and current flows through the page to ground, achieving matching of the input impedance. The attenuation gear can be adjusted by the control signal of each numerical control circuit for any one of the plurality of input impedances to be matched. The correspondence between the control word of the attenuator and the attenuation value can be seen in the following table 1:
TABLE 1
Wherein a control word of 1 indicates a voltage of 2.5V required for the switching tube to conduct. At this time, the control as shown in table 1 can be realized by using a three-bit control word and a custom 38 decoding circuit. If finer gear is desired, more control words may be used for control.
In an example, in the case where the M-1 parallel circuit pages are all on (or open), the input impedance of the attenuator is the smallest of the M input impedances to be matched.
The input impedance of the attenuator is adjusted to be the minimum input impedance of M input impedances to be matched, so that the matching requirement of other input impedances can be met. In order to keep the attenuator architecture unchanged, a method of turning off a circuit page of the minimum resistance by a switch to change the minimum resistance value is proposed.
Specifically, since there are M input impedances to be matched, it can be determined that M-1 parallel circuit pages have independent control signals, namely control levels ATTm and ATTm'; can be matched to the value Rin according to the minimum required input impedance min The resistance of the first resistor R1 of the first circuit page of the M-1 parallel circuit pages is Rin min 2 ohms and has control levels ATT1 and ATT1'; when the first page (m=1) to the M-1 pages of the M-1 parallel circuit pages are all opened, an input impedance of Rin is obtained min Ohm, when m=1 pages are closed and m=2 to M-1 pages are open, an input impedance of 2 x rin is obtained min Ohmic; when m=1 and m=2 pages are both closed, and when m=3 to M-1 pages are open, an input impedance of 4×rin is obtained min Ohmic.
And so on:
Z in-6dB ＝2R in ||4R in ||8R in ||16R in ||32R in ||...||2 n-1 R in ||2 n R in ||2 n R in ＝R in ；
Z in2-6dB ＝4R in ||8R in ||16R in ||32R in ||...||2 n-1 R in ||2 n R in ||2 n R in ＝2R in ；
Z in3-6dB ＝8R in ||16R in ||32R in ||...||2 n-1 R in ||2 n R in ||2 n R in ＝4R in ；
therefore, the number of the opened circuit pages and the number of the closed circuit pages in the M-1 parallel circuit pages are adjusted to adapt to a plurality of input impedances, and the adaptability of the attenuator in various input impedance scenes needing to be matched is improved.
When the M-1 parallel circuit pages are all disconnected (or closed), the input impedance of the attenuator is the largest input impedance of M input impedances to be matched. And confirming the minimum attenuation gear according to the maximum input impedance in M input impedances to be matched, namely starting an M th page in N parallel circuit pages, wherein 6dB attenuation can be increased when one page of parallel resistor is added, namely the maximum attenuation value is (N-M+1) 6dB. The value of n for the minimum attenuation range circuit page can thus be determined. Starting from page M (containing), the corresponding control levels are ATTn andthe corresponding control levels for the first page through page M-1 are ATTm and ATTm'. Under the condition that the M-1 parallel circuit pages are all closed, namely when the input impedance of the attenuator is the largest input impedance of M input impedances to be matched, the n value of the minimum attenuation gear circuit page is determined according to the maximum attenuation value requirement, so that under the condition that the maximum input impedance meets the maximum attenuation value requirement, other input impedances to be matched can meet the corresponding attenuation value requirement, and the adaptability of the attenuator in various scenes of the input impedances to be matched is improved.
In an embodiment, the attenuator further includes an impedance matching sheet, the impedance matching sheet is connected in parallel with an nth circuit page of the N parallel circuit pages, and the resistance values and circuit structures of the nth circuit page and the impedance matching sheet are the same, and matching of input impedance is achieved through the impedance matching sheet.
As shown in fig. 3, determining the number M of input impedance steps to be matched by the attenuator, M being a positive integer; in the case where M is equal to 1, then signal attenuation is performed in the production scenario of the corresponding target input impedance, at which time no impedance matching adjustment technique is required.
In case M is greater than 1, i.e. the attenuator has a plurality of input impedances to be matched, then M-1 parallel circuit pages can be determined according to the M input impedances to be matched, and M-1 parallel circuit pages have independent control signals, i.e. control levels ATTm and ATTm'. Under the condition that each numerical control circuit controls M-1 parallel circuit pages to be in conduction through control levels ATTm and ATTm '(namely, ATTm and ATTm' are not all 0), an adjustable impedance minimum value exists in the attenuator at the moment, so that the adjustable impedance minimum value of the attenuator is matched with the minimum input impedance of M input impedances to be matched.
For example, in a typical chip circuit design, the differential lines have three choices of 50 ohms, 100 ohms and 200 ohms, where M may be equal to 3. A parallel attenuator with adjustable input impedance is designed to match these 3 input impedance requirements. Since the minimum required input impedance match is 50 ohms, 2 parallel circuit pages are required with independent control signals, i.e. m=1, and with control levels ATT1 and ATT1', since there is 3-speed impedance to match; when m=2, there are control levels ATT2 and ATT2'. When m=1 page and m=2 page are both open, the input impedance is available as 50 ohms, and when m=1 page is closed and m=2 page is open, the input impedance is available as 100 ohms; when both m=1 and m=2 pages are closed, the input impedance is 200 ohms.
Then, under the condition of the maximum input impedance to be matched, the n value of the minimum attenuation gear circuit page is determined according to the maximum attenuation value. Starting on page M, each time a parallel resistor is added, the attenuation of 6dB can be increased, and the maximum attenuation value can be (N-m+1) ×6db. The value of n for the minimum attenuation range circuit page can thus be determined. Starting from page M (containing), the corresponding control levels are ATTn andthe corresponding control levels for the first page through page M-1 are ATTm and ATTm'. By means of the fact that the M-1 parallel circuit pages are all closed, i.e. the input impedance of the attenuator is MWhen the input impedance is the largest, the n value of the minimum attenuation gear circuit page is determined according to the largest attenuation value requirement, so that other input impedances needing to be matched can also meet the corresponding attenuation value requirement under the condition that the largest input impedance meets the largest attenuation value requirement, and the adaptability of the attenuator under various input impedance needing to be matched is improved.
For example, in the case of a maximum required matching input impedance of 200 ohms, i.e., m=1 and m=2 pages are both closed, i.e., ATT1 and ATT1 'are both 0, ATT2 and ATT2' are both 0, and according to the maximum attenuation value (e.g., 24 dB), the n value of the minimum attenuation range circuit page can be determined to be 6, so n=6 is the minimum range; and adding one page with the same resistance value and the same circuit as the minimum shift page to serve as an impedance matching page, wherein the numerical control circuit is n=7 so as to realize matching of input impedance.
Wherein, the control of attenuation and input impedance can be realized by a numerical control circuit, and the control word can be seen in the following table 2:
TABLE 2
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present invention is not limited to performing the functions in the order discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present invention.
The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.
Claims (10)
1. An input impedance adjustable attenuator comprising:
each circuit page comprises a first branch, a second branch, a third branch and a fourth branch, wherein the first branch comprises a first resistor and a first switch which are connected in series, the second branch comprises a second resistor and a second switch which are connected in series, the first end of the third branch is connected with a connection point between the first resistor and the first switch, the second end of the third branch is connected with a connection point between the second resistor and the second switch, the first end of the fourth branch is connected with a control end of the first switch, the second end of the fourth branch is connected with a control end of the second switch, and N is a positive integer;
the numerical control circuits are in one-to-one correspondence with the N parallel circuit pages, the numerical control circuits are used for providing a first control signal and a second control signal, the first control signal is used for controlling the on-off state of the third branch, and the second control signal is used for controlling the on-off state of the fourth branch.
2. The attenuator of claim 1, wherein the first control signal and the second control signal are independent of each other.
3. The attenuator of claim 1, wherein the N parallel circuit pages include M-1 parallel circuit pages, M-1 is a positive integer less than N, M is a number of input impedances to be matched, and the first control signals and the second control signals provided by the numerical control circuits corresponding to the M-1 parallel circuit pages are independent of each other.
4. The attenuator of claim 3, wherein the first control signals and the second control signals provided by the numerical control circuits corresponding to N-m+1 parallel circuit pages of the N parallel circuit pages are mutually inverted signals.
5. An attenuator according to claim 3, wherein the input impedance of the attenuator is the smallest of the M input impedances to be matched in the case where the M-1 parallel circuit pages are all on.
6. The attenuator of claim 5, wherein the input impedance of the attenuator is the largest of the M input impedances to be matched in the event that the M-1 parallel circuit pages are all open.
7. The attenuator of claim 1 further comprising an impedance matching page connected in parallel with an nth circuit page of the N parallel circuit pages, and the nth circuit page has the same resistance and circuit configuration as the impedance matching page.
8. The attenuator of claim 1, wherein the third branch includes a third resistor, a third switch, and a fourth resistor connected in series in sequence, a control terminal of the third switch being configured to receive the first control signal.
9. The attenuator of claim 1, wherein the fourth branch comprises a fifth resistor and a sixth resistor in series, the connection terminals of the fifth resistor and the sixth resistor being configured to receive the second control signal.
10. The attenuator of claim 8, wherein the first switch, the second switch, and the third switch are field effect transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211209096.3A CN117411458A (en) | 2022-09-30 | 2022-09-30 | Attenuator with adjustable input impedance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211209096.3A CN117411458A (en) | 2022-09-30 | 2022-09-30 | Attenuator with adjustable input impedance |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117411458A true CN117411458A (en) | 2024-01-16 |
Family
ID=89493207
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211209096.3A Pending CN117411458A (en) | 2022-09-30 | 2022-09-30 | Attenuator with adjustable input impedance |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117411458A (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7205817B1 (en) * | 2004-03-30 | 2007-04-17 | Maxim Integrated Products, Inc. | Analog control integrated FET based variable attenuators |
| CN101558559A (en) * | 2007-08-11 | 2009-10-14 | 阎跃军 | Variable attenuator |
| CN102790626A (en) * | 2011-05-19 | 2012-11-21 | 联发科技股份有限公司 | Signal transceiver |
| CN104079858A (en) * | 2014-07-14 | 2014-10-01 | 天津瑞发科半导体技术有限公司 | Backward signal transmitting and mixing device |
| US20200106476A1 (en) * | 2018-09-28 | 2020-04-02 | Huawei Technologies Co., Ltd. | Composite right-hand left-hand distributed attenuator |
| CN111130503A (en) * | 2020-03-30 | 2020-05-08 | 南京汇君半导体科技有限公司 | Low-phase-difference numerical control radio frequency attenuator |
| CN111404511A (en) * | 2020-05-19 | 2020-07-10 | 成都天锐星通科技有限公司 | Ultra-wideband high-precision differential attenuator |
| CN112350686A (en) * | 2020-10-31 | 2021-02-09 | 拓维电子科技(上海)有限公司 | Differential numerical control attenuator based on inductance compensation |
| CN113328729A (en) * | 2021-06-21 | 2021-08-31 | 东南大学 | Passive numerical control attenuator with temperature process angle error compensation function |
| CN113608000A (en) * | 2021-07-19 | 2021-11-05 | 深圳麦科信科技有限公司 | Differential circuit, differential probe and oscilloscope assembly |
| US20220200578A1 (en) * | 2020-12-23 | 2022-06-23 | Daniel Gruber | Attenuator circuit, receiver, base station, mobile device and method for operating an attenuator circuit |
-
2022
- 2022-09-30 CN CN202211209096.3A patent/CN117411458A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7205817B1 (en) * | 2004-03-30 | 2007-04-17 | Maxim Integrated Products, Inc. | Analog control integrated FET based variable attenuators |
| CN101558559A (en) * | 2007-08-11 | 2009-10-14 | 阎跃军 | Variable attenuator |
| CN102790626A (en) * | 2011-05-19 | 2012-11-21 | 联发科技股份有限公司 | Signal transceiver |
| CN104079858A (en) * | 2014-07-14 | 2014-10-01 | 天津瑞发科半导体技术有限公司 | Backward signal transmitting and mixing device |
| US20200106476A1 (en) * | 2018-09-28 | 2020-04-02 | Huawei Technologies Co., Ltd. | Composite right-hand left-hand distributed attenuator |
| CN111130503A (en) * | 2020-03-30 | 2020-05-08 | 南京汇君半导体科技有限公司 | Low-phase-difference numerical control radio frequency attenuator |
| CN111404511A (en) * | 2020-05-19 | 2020-07-10 | 成都天锐星通科技有限公司 | Ultra-wideband high-precision differential attenuator |
| CN112350686A (en) * | 2020-10-31 | 2021-02-09 | 拓维电子科技(上海)有限公司 | Differential numerical control attenuator based on inductance compensation |
| US20220200578A1 (en) * | 2020-12-23 | 2022-06-23 | Daniel Gruber | Attenuator circuit, receiver, base station, mobile device and method for operating an attenuator circuit |
| CN113328729A (en) * | 2021-06-21 | 2021-08-31 | 东南大学 | Passive numerical control attenuator with temperature process angle error compensation function |
| CN113608000A (en) * | 2021-07-19 | 2021-11-05 | 深圳麦科信科技有限公司 | Differential circuit, differential probe and oscilloscope assembly |
Non-Patent Citations (3)
| Title |
|---|
| JING XU等: "A Ku-band CMOS 6-bit Digital-Controlled Phase-Invariant Variable Gain Amplifier and Attenuator", 2019 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS, TECHNOLOGIES AND APPLICATIONS (ICTA), 28 February 2020 (2020-02-28), pages 5 - 6 * |
| 徐永祥等: "5～40 GHz CMOS衰减器的设计与实现", 半导体技术, 3 August 2018 (2018-08-03), pages 591 - 597 * |
| 柯强等: "一种高线性度宽带可编程增益放大器", 电子技术应用, 3 August 2016 (2016-08-03), pages 30 - 33 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10193515B2 (en) | Continuous time linear equalizer with two adaptive zero frequency locations | |
| US7675380B2 (en) | Integrated digitally controlled linear-in-decibels attenuator | |
| KR100791934B1 (en) | High amplitude output buffer circuit for high speed system | |
| US5563557A (en) | Attenuator having a plurality of current source circuits | |
| EP0474337A1 (en) | Switched low-loss attenuator | |
| JPH06120011A (en) | Variable signal attenuator | |
| WO2001013513A1 (en) | Programmable low noise cmos differential voltage controlled logarithmic attenuator and method | |
| EP0664937A1 (en) | Line driver with adaptive output impedance | |
| US9537685B2 (en) | Continuous time linear equalization for current-mode logic with transformer | |
| EP0091160A1 (en) | Circuit for amplifying and/or attenuating a signal | |
| KR930001597A (en) | Digital-to-Analog Converter with Resistance Network | |
| GB1591918A (en) | Current mirror amplifier circuit | |
| US5708391A (en) | High frequency differential filter with CMOS control | |
| US6552519B1 (en) | Variable impedance network for an integrated circuit | |
| US5006735A (en) | Method and apparatus for compensating a solid state attenuator | |
| US7843261B2 (en) | Resistor network for programmable transconductance stage | |
| US7609097B2 (en) | Driver circuit and a method for matching the output impedance of a driver circuit with a load impedance | |
| US20040141552A1 (en) | Programmable receive-side channel equalizer | |
| CN117411458A (en) | Attenuator with adjustable input impedance | |
| US5144154A (en) | Range changing using N and P channel FETS | |
| US20070176664A1 (en) | Programmable gain attenuator for track and hold amplifiers | |
| CN116436481A (en) | Transmitter circuit | |
| US10374842B2 (en) | Equalization for transmitter input buffer array | |
| CN116203295A (en) | Variable resistance circuit, electronic device and vehicle | |
| JP2004194118A (en) | Soft change-over switch and analog signal processing circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |