CN117410330A - Semiconductor device and forming method thereof - Google Patents

Semiconductor device and forming method thereof Download PDF

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Publication number
CN117410330A
CN117410330A CN202311350390.0A CN202311350390A CN117410330A CN 117410330 A CN117410330 A CN 117410330A CN 202311350390 A CN202311350390 A CN 202311350390A CN 117410330 A CN117410330 A CN 117410330A
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China
Prior art keywords
dielectric layer
nitride semiconductor
layer
gate electrode
semiconductor layer
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Chinese (zh)
Inventor
刘阳
赵起越
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Innoscience Suzhou Semiconductor Co Ltd
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Innoscience Suzhou Semiconductor Co Ltd
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Priority to CN202311350390.0A priority Critical patent/CN117410330A/en
Publication of CN117410330A publication Critical patent/CN117410330A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, a gate electrode, and a field plate. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a band gap greater than that of the first nitride semiconductor layer. The third nitride semiconductor layer is doped and disposed on the second nitride semiconductor layer. The gate electrode is disposed on the third nitride semiconductor layer. The field plate covers the gate electrode. The distance between the field plate and the side surface of the gate electrode is non-uniform.

Description

Semiconductor device and forming method thereof
Technical Field
The present disclosure relates to a semiconductor device and a method of forming the same, and more particularly to a semiconductor device including a first dielectric layer.
Background
Components comprising direct bandgap semiconductors, such as semiconductor components comprising group III-V materials or group III-V compounds (class: group III-V compounds), may operate or work under a variety of conditions or in a variety of environments (e.g., at different voltages and frequencies).
The semiconductor components may include heterojunction bipolar transistors (HBTs, heterojunction bipolar transistor), heterojunction field effect transistors (HFETs, heterojunction field effect transistor), high-electron-mobility transistor, modulation-doped field effect transistors (MODFETs), and the like.
Disclosure of Invention
According to some embodiments of the present disclosure, a semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, a gate electrode, and a field plate. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a band gap greater than that of the first nitride semiconductor layer. The third nitride semiconductor layer is doped and disposed on the second nitride semiconductor layer. The gate electrode is disposed on the third nitride semiconductor layer. The field plate covers the gate electrode. The distance between the field plate and the side surface of the gate electrode is non-uniform.
According to some embodiments of the present disclosure, a method of manufacturing a semiconductor device includes: providing a substrate; forming a first nitride semiconductor layer on a substrate; forming a second nitride semiconductor layer on the first nitride semiconductor layer, the band gap of which is larger than that of the first nitride semiconductor layer; forming a third nitride semiconductor layer on the second nitride semiconductor layer, which is doped with a dopant; and forming a gate electrode on the third nitride semiconductor layer; a field plate is formed overlying the gate electrode, wherein a distance between the field plate and a side surface of the gate electrode is non-uniform.
According to some embodiments of the present disclosure, a semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, a gate electrode, a first dielectric layer, and a field plate. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a band gap greater than that of the first nitride semiconductor layer. The third nitride semiconductor layer is doped and disposed on the second nitride semiconductor layer. The gate electrode is disposed on the third nitride semiconductor layer. The first dielectric layer is disposed on a side surface of the gate electrode. The field plate covers the gate electrode, wherein a side surface of the gate electrode is separated from the field plate by a first dielectric layer.
The present disclosure provides a semiconductor device. The semiconductor device may include a first dielectric layer for adjusting a distance between the field plate and the gate electrode or for adjusting a distance between the field plate and the depletion layer. Since the dielectric constant of the dielectric layer between the field plate and the gate electrode (or depletion layer) can affect the electrical properties of the semiconductor device, particularly for materials having a large dielectric constant, if the thickness of the material varies slightly, the electrical properties of the semiconductor device as a whole can be severely affected. The semiconductor device disclosed by the invention can adjust the distance between the field plate and the gate electrode (or the depletion layer) through the first dielectric layer, so that the electric property of the semiconductor device can be adjusted in a fine-tuning way easily through the outline of the first dielectric layer, and the performance of the semiconductor device can be optimized under the condition that the thickness of the whole semiconductor device is not influenced.
Drawings
The aspects of the disclosure may be readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.
Fig. 1 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
Fig. 2 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
Fig. 3 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
Fig. 4A is a top view of a semiconductor device according to some embodiments of the present disclosure.
Fig. 4B is a cross-sectional view of the semiconductor device shown in fig. 4A along line A-A', in accordance with some embodiments of the present disclosure.
Fig. 5 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
Fig. 6A, 6B, 6C, and 6D illustrate various stages of a method for fabricating a semiconductor device according to some embodiments of the disclosure.
Common reference numerals are used throughout the drawings and the detailed description to refer to the same or like components. The present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In this disclosure, references to forming or disposing a first feature on or over a second feature may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself limit the relationship between the various embodiments and/or configurations discussed.
Embodiments of the present disclosure are discussed in detail below. However, it is to be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The particular embodiments discussed are illustrative only and are not limiting of the scope of the present disclosure.
The present disclosure provides a semiconductor device. The semiconductor device may include a first dielectric layer (spacer) to adjust a distance between the field plate and the gate electrode or to adjust a distance between the field plate and the depletion layer. Since the dielectric constant of the dielectric layer between the field plate and the gate electrode (or depletion layer) can affect the electrical properties of the semiconductor device, particularly for materials having a large dielectric constant, if the thickness of the material varies slightly, the electrical properties of the semiconductor device as a whole can be severely affected. The semiconductor device disclosed by the invention can adjust the distance between the field plate and the gate electrode (or the depletion layer) through the first dielectric layer, so that the electric property of the semiconductor device can be adjusted in a fine-tuning way easily through the outline of the first dielectric layer, and the performance of the semiconductor device can be optimized under the condition that the thickness of the whole semiconductor device is not influenced. The semiconductor device of the present disclosure may be applied to, but is not limited to, HEMT devices, particularly low voltage HEMT devices, high voltage HEMT devices, and Radio Frequency (RF) HEMT devices.
Fig. 1 is a cross-sectional view of a semiconductor device 1a according to some embodiments of the present disclosure. The semiconductor device 1a may include a substrate 12, a first nitride semiconductor layer 14, a second nitride semiconductor layer 16, a third nitride semiconductor layer 18, a gate electrode 20, a dielectric layer 30, a first dielectric layer 41, an electrode 51 (e.g., drain or source), a field plate 511, an electrode 52 (e.g., source or drain), and a dielectric structure 60.
Substrate 12 may include, but is not limited to, silicon (Si), doped Si, silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs), or other semiconductor material. Substrate 12 may include, but is not limited to, sapphire, silicon-on-insulator (SOI, silicon on insulator), or other suitable materials.
The first nitride semiconductor layer 14 (or channel layer) may be disposed on the substrate 12. The first nitride semiconductor layer 14 may include a group III-V layer. The first nitride semiconductor layer 14 may include, but is not limited to, group III nitrides, such as the compound InaAlbGa1-a-bN, where a+b+.ltoreq.1. The group III nitride further includes, but is not limited to, for example, the compound AlaGa (1-a) N, where a+.1. The first nitride semiconductor layer 14 may include a gallium nitride (GaN) layer. The energy gap of GaN is about 3.4eV.
The second nitride semiconductor layer 16 (or a barrier layer) may be disposed on the first nitride semiconductor layer 14. The second nitride semiconductor layer 16 may include a group III-V layer. The second nitride semiconductor layer 16 may include, but is not limited to, group III nitrides, such as the compound InaAlbGa1-a-bN, where a+b+.ltoreq.1. The group III nitride may further include, but is not limited to, for example, the compound AlaGa (1-a) N, where a+.1. The energy gap of the second nitride semiconductor layer 16 may be larger than that of the first nitride semiconductor layer 14. The second nitride semiconductor layer 16 may include an aluminum gallium nitride (AlGaN) layer. The energy gap of AlGaN is about 4.0eV.
A heterojunction may be formed between the second nitride semiconductor layer 16 and the first nitride semiconductor layer 14, and polarization of the heterojunction forms a two-dimensional electron gas (two-dimensional electron gas,2 DEG) region in the first nitride semiconductor layer 14.
A third nitride semiconductor layer 18 may be disposed on the second nitride semiconductor layer 16. The third nitride semiconductor layer 18 may be in direct contact with the second nitride semiconductor layer 16. The third nitride semiconductor layer 18 may be disposed between the gate electrode 20 and the second nitride semiconductor layer 16. The third nitride semiconductor layer 18 may be doped with impurities (dopant). The third nitride semiconductor layer 18 may include a p-type dopant. The third nitride semiconductor layer 18 may include a p-type doped GaN layer, a p-type doped AlGaN layer, a p-type doped AlN layer, or other suitable III-V layer. The p-type dopant may include magnesium (Mg), beryllium (Be), zinc (Zn), and cadmium (Cd). The third nitride semiconductor layer 18 may be configured to control the concentration of 2DEG in the first nitride semiconductor layer 14. The third nitride semiconductor layer 18 may be used to deplete the 2DEG directly under the third nitride semiconductor layer 18. The third nitride semiconductor layer 18 may have a surface (or upper surface 18s 1) remote from the second nitride semiconductor layer 16. The third nitride semiconductor layer 18 may have a surface 18s2 (or a side surface 18s 2) adjacent to the surface.
The gate electrode 20 may be disposed on the second nitride semiconductor layer 16. The gate electrode 20 may be disposed on the third nitride semiconductor layer 18. The gate electrode 20 may be disposed between the electrode 51 and the electrode 52. The gate electrode 20 may include a metal. The gate electrode 20 may comprise titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), lead (Pb), molybdenum (Mo) and compounds thereof (such as, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), other conductive nitrides or conductive oxides), metal alloys (such as aluminum copper alloy (Al-Cu)), or other suitable materials. The gate electrode 20 may have a surface (or upper surface 20s 1) remote from the third nitride semiconductor layer 18. The gate electrode 20 may have a surface (or side surface 20s 2) that extends between the surface 18s1 of the third nitride semiconductor layer 18 and the surface 20s2 of the gate electrode 20.
A dielectric layer 30 may be disposed on the second nitride semiconductor layer 16. The dielectric layer 30 may contact the second nitride semiconductor layer 16. A dielectric layer 30 may be disposed on the third nitride semiconductor layer 18. The dielectric layer 30 may contact the surface 18s1 of the third nitride semiconductor layer 18. The dielectric layer 30 may contact the surface 18s2 of the third nitride semiconductor layer 18. A dielectric layer 30 may be disposed on the gate electrode 20. Dielectric layer 30 may contact surface 20s1 of gate electrode 20. Dielectric layer 30 may contact surface 20s2 of gate electrode 20. The dielectric layer 30 may be conformally disposed on the second nitride semiconductor layer 16, the third nitride semiconductor layer 18, and the gate electrode 20. The dielectric layer 30 may be disposed between the third nitride semiconductor layer 18 and the field plate 511 in the X-axis direction. The dielectric layer 30 may be disposed between the third nitride semiconductor layer 18 and the field plate 511 in the Y-axis direction. The dielectric layer 30 may be disposed between the gate electrode 20 and the field plate 511 in the X-axis direction.
The dielectric layer 30 may be used to modulate the electric field of the semiconductor device 1a. The dielectric layer 30 may be used to adjust the electric field between the field plate 511 and the second nitride semiconductor layer 16 and the vicinity thereof. The dielectric layer 30 may be used to adjust the electric field between the field plate 511 and the third nitride semiconductor layer 18 and the vicinity thereof. The dielectric layer 30 may be used to modulate the electric field between the field plate 511 and the gate electrode 20 and adjacent thereto. The dielectric layer 30 may be used to adjust the dielectric constant of the region between the field plate 511 and the second nitride semiconductor layer 16. The dielectric layer 30 may be used to adjust the dielectric constant of the region between the field plate 511 and the third nitride semiconductor layer 18. The dielectric layer 30 may be used to adjust the dielectric constant of the region between the field plate 511 and the gate electrode 20. Dielectric layer 30 may comprise a high-k dielectric material. The k value of the high-k dielectric material may be greater than about 5. Dielectric layer 30 may comprise a low-k dielectric material. The k value of the low-k dielectric material may be less than about 5. Dielectric layer 30 may comprise an oxide, nitride, oxynitride, or other suitable material. Dielectric layer 30 may have a surface 30s1 (or upper surface). The surface 30s1 of the dielectric layer 30 and the third nitride semiconductor layer 18 have a thickness T1 therebetween in the X-axis direction. The thickness T1 may be substantially uniform (uniform). The thickness T1 does not substantially vary with the position of the surface 30s1 of the dielectric layer 30.
First dielectric layer 41 may be disposed on dielectric layer 30. The first dielectric layer 41 may cover a portion of the surface of the dielectric layer 30. The surface 30s1 of the dielectric layer 30 may be uncovered by the first dielectric layer 41. First dielectric layer 41 may contact dielectric layer 30. The first dielectric layer 41 may be disposed on the third nitride semiconductor layer 18. The first dielectric layer 41 may be disposed between the third nitride semiconductor layer 18 and the electrode 51. The first dielectric layer 41 may cover the surface 18s1 of the third nitride semiconductor layer 18. The first dielectric layer 41 may cover the surface 18s2 of the third nitride semiconductor layer 18. The first dielectric layer 41 may be disposed between the gate electrode 20 and the electrode 51. The first dielectric layer 41 may cover the surface 20s2 of the gate electrode 20. The surface 20s1 of the cap gate electrode 20 may be uncovered by the first dielectric layer 41. The first dielectric layer 41 may be separated from the second nitride semiconductor layer 16 by the dielectric layer 30. The first dielectric layer 41 may be separated from the third nitride semiconductor layer 18 by the dielectric layer 30. First dielectric layer 41 may be separated from gate electrode 20 by dielectric layer 30.
The first dielectric layer 41 may be used to adjust the distance between the field plate 511 and the third nitride semiconductor layer 18. The first dielectric layer 41 may be used to adjust the distance between the field plate 511 and the surface 18s1 of the third nitride semiconductor layer 18. The first dielectric layer 41 may be used to adjust the distance between the field plate 511 and the surface 18s2 of the third nitride semiconductor layer 18. The first dielectric layer 41 may be used to adjust the distance between the field plate 511 and the gate electrode 20. The first dielectric layer 41 may be used to adjust the distance between the field plate 511 and the surface 20s2 of the gate electrode 20. The first dielectric layer 41 may comprise a dielectric layer. The first dielectric layer 41 may comprise a high-k dielectric material. The first dielectric layer 41 may comprise a low-k dielectric material. First dielectric layer 41 may comprise an oxide, nitride, oxynitride, or other suitable material. The dielectric constant of the first dielectric layer 41 may be smaller than that of the dielectric layer 30. The difference between the dielectric constant of first dielectric layer 41 and the dielectric constant of dielectric layer 30 may be greater than about 2, such as 2, 2.5, 3, 3.5, 4, 4.5, 5, or more. The first dielectric layer 41 may have a surface 41s1 (or an outer side surface 41s 1). Surface 41s1 may face electrode 51. Surface 41s1 may face away from gate electrode 20. The surface 41s1 of the first dielectric layer 41 and the dielectric layer 30 have a thickness T2 therebetween in the X-axis direction. The thickness T2 may be substantially non-uniform. The thickness T2 varies substantially with the position of the surface 41s1 of the first dielectric layer 41. The thickness between the surface 41s1 of the first dielectric layer 41 and the gate electrode 20 may be non-uniform. The thickness of the first dielectric layer 41 along the X-axis direction may be greater than the thickness of the dielectric layer 30 along the X-axis direction. The thickness of the first dielectric layer 41 in the Y-axis direction may be greater than the thickness of the dielectric layer 30 in the Y-axis direction. The first dielectric layer 41 may have a top P1. The height (elevation) of the top P1 of the first dielectric layer 41 may be substantially the same as the height of the surface 30s1 of the dielectric layer 30.
The electrode 51 may be disposed on the second nitride semiconductor layer 16. The electrode 51 may be in contact with the second nitride semiconductor layer 16. The electrode 51 may comprise, for example, but not limited to, a conductive material. The conductive material may comprise a metal, an alloy, a doped semiconductive material (e.g., doped crystalline silicon), or other suitable conductive material, such as Ti, al, ni, cu, au, pt, pd, W, tiN or other suitable material. The electrode 51 may comprise a multi-layer structure. For example, the electrode 51 may comprise a structure of two layers of different materials.
The electrode 52 may be disposed on the second nitride semiconductor layer 16. The electrode 52 may be in contact with the second nitride semiconductor layer 16. The electrode 52 may comprise, for example, but not limited to, a conductive material. The conductive material may comprise a metal, an alloy, a doped semiconductive material (e.g., doped crystalline silicon), or other suitable conductive material, such as Ti, al, ni, cu, au, pt, pd, W, tiN or other suitable material. The structure of electrode 52 may be similar or identical to the structure of electrode 51.
The field plate 511 may extend from the electrode 51 toward the third nitride semiconductor layer 18. The field plate 511 may extend from the electrode 51 toward the gate electrode 20. The field plate 511 may be connected to an electrode 51. A field plate 511 may be disposed on the dielectric layer 30. The field plate 511 may be disposed on the surface 30s1 of the dielectric layer 30. The field plate 511 may be disposed on the first dielectric layer 41. The field plate 511 may be disposed on the surface 41s1 of the first dielectric layer 41. The field plate 511 may be used to adjust the electric field of the semiconductor device 1a. The field plate 511 may have a surface 511s1 (or an inside surface). Surface 511s1 may face gate electrode 20. The surface 511s1 may face the third nitride semiconductor layer 18. The distance between the surface 511s1 of the field plate 511 and the surface 18s1 of the third nitride semiconductor layer 18 may be non-uniform. The distance between the surface 511s1 of the field plate 511 and the surface 18s2 of the third nitride semiconductor layer 18 may be non-uniform. The distance between the surface 511s1 of the field plate 511 and the surface 20s1 of the gate electrode 20 may be uniform. The distance between the surface 511s1 of the field plate 511 and the surface 20s2 of the gate electrode 20 may be non-uniform. The field plates 511 may contact the dielectric layer 30. The field plate 511 may contact the first dielectric layer 41.
A dielectric structure 60 may be disposed on the second nitride semiconductor layer 16. Dielectric structure 60 may cover gate electrode 20. Dielectric structure 60 may cover electrode 51. Dielectric structure 60 may cover electrode 52. Dielectric structure 60 may comprise a high-k dielectric material. Dielectric structure 60 may comprise a low-k dielectric material. Dielectric structure 60 may comprise an oxide, nitride, oxynitride, or other suitable material. Dielectric structure 60 may include multiple dielectric layers. The materials of the dielectric layers may be partially identical. The materials of the dielectric layers may be partially different. The adjacent dielectric layers may have incomplete boundaries between them (e.g., a portion of the boundary between the interfaces may be confirmed by scanning electron microscopy (scanning electron microscope, SEM), and another portion of the boundary may not be observed by SEM). The adjacent dielectric layers may have substantially no boundary therebetween.
In the present disclosure, the semiconductor device 1a may include a first dielectric layer 41 for adjusting a distance between the field plate 511 and the third nitride semiconductor layer 18. The first dielectric layer 41 can be used to adjust the distance between the field plate 511 and the gate electrode 20. The first dielectric layer 41 has a smaller dielectric constant than the dielectric layer 30, and the thickness of the first dielectric layer 41 has a relatively smaller influence on the overall semiconductor device 1a, so that the electrical properties of the semiconductor device can be easily tuned by adjusting the thickness or profile of the first dielectric layer 41, and the performance of the semiconductor device can be optimized without affecting the thickness of the overall semiconductor device. In the semiconductor device of the comparative example, the dielectric constant between the field plate and the gate electrode (or depletion layer) is not adjusted by a plurality of dielectric layers having different thicknesses, and the distance between the field plate and the gate electrode (or depletion layer) is substantially fixed, making it difficult to fine-tune the electrical properties of the semiconductor device as a whole.
Fig. 2 is a cross-sectional view of a semiconductor device 1b according to some embodiments of the present disclosure. The structure of the semiconductor device 1b may be similar to that of the semiconductor device 1a, except for the following.
The semiconductor device 1b may include a second dielectric layer 42. The material or structure of second dielectric layer 42 may be the same as or similar to first dielectric layer 41. The second dielectric layer 42 may have a top P2. The height of the top P2 of the second dielectric layer 42 may be different from the height of the surface 30s1 of the dielectric layer 30. The height of the top P2 of the second dielectric layer 42 may be lower than the height of the surface 30s1 of the dielectric layer 30. The top P2 of the second dielectric layer 42 may have a height higher than the surface 20s1 of the gate electrode 20.
The field plates 511 may have a stepped structure (stepped structure). The stepped structure of the field plate 511 may be located directly above the top P2 of the second dielectric layer 42.
The height of the top P2 of the second dielectric layer 42 is adjustable, and by adjusting the height of the top P2 of the second dielectric layer 42, the electrical property of the semiconductor device 1b can be optimized.
Fig. 3 is a cross-sectional view of a semiconductor device 1c according to some embodiments of the present disclosure. The structure of the semiconductor device 1c may be similar to that of the semiconductor device 1a, except for the following.
The semiconductor device 1c may include a third dielectric layer 43 and a fourth dielectric layer 44. The material of the third dielectric layer 43 may be the same as or similar to the first dielectric layer 41. The material of fourth dielectric layer 44 may be the same as or similar to first dielectric layer 41. The material of the third dielectric layer 43 may be the same as the material of the fourth dielectric layer 44. The material of the third dielectric layer 43 may be different from the material of the fourth dielectric layer 44.
The third dielectric layer 43 may be disposed on the surface 18s1 of the third nitride semiconductor layer 18. The third dielectric layer 43 may cover the surface 18s1 of the third nitride semiconductor layer 18. The third dielectric layer 43 may not cover the surface 18s2 of the third nitride semiconductor layer 18. The third dielectric layer 43 may cover the surface 20s2 of the gate electrode 20.
A fourth dielectric layer 44 may be disposed on the second nitride semiconductor layer 16. The fourth dielectric layer 44 may cover the surface 18s2 of the third nitride semiconductor layer 18. The fourth dielectric layer 44 may not cover the surface 18s1 of the third nitride semiconductor layer 18. The fourth dielectric layer 44 may not cover the surface 20s2 of the gate electrode 20. The fourth dielectric layer 44 may be spaced apart from the third dielectric layer 43. The field plate 511 may be in contact with the dielectric layer 30 between the third dielectric layer 43 and the fourth dielectric layer 44.
By providing the third dielectric layer 43 and the fourth dielectric layer 44 separated from the third dielectric layer 43, the profile of the field plate 511 can be adjusted to optimize the electrical properties of the semiconductor device 1c.
Fig. 4A is a top view of a semiconductor device 1d according to some embodiments of the present disclosure. The structure of the semiconductor device 1d may be similar to that of the semiconductor device 1a, except for the following.
The semiconductor device 1d may include a first dielectric layer 45. The material of first dielectric layer 45 may be the same as or similar to first dielectric layer 41. The first dielectric layer 45 may include a plurality of portions 45e spaced apart from each other.
The semiconductor device 1d may include an air gap 71. The air gap 71 may be located between adjacent two portions 45e. The length of the first dielectric layer 45 in the X-axis direction is substantially equal to the length of the air gap 71 in the X-axis direction.
Referring to fig. 4B, a cross-sectional view of the semiconductor device 1d shown in fig. 4A along line segment A-A' is shown.
The air gap 71 may be defined by a surface 511s1 of the field plate 511 and an outer side surface (not labeled) of the dielectric layer 30. The surface 511s1 of the field plate 511 may be exposed to the air gap 71. A portion of the outside surface of the dielectric layer 30 may be exposed to the air gap 71. The air gap 71 may overlap with the surface 20s2 of the gate electrode 20 in the X-axis direction. The air gap 71 may overlap with the surface 18s1 of the third nitride semiconductor layer 18 in the Y-axis direction. The air gap 71 may overlap with the surface 18s2 of the third nitride semiconductor layer 18 in the X-axis direction. The field plate 511 may be separated from a portion of the dielectric layer 30 by an air gap 71. An air gap 71 may be located between the field plate 511 and the dielectric layer 30. An air gap 71 may be located between the field plate 511 and the second nitride semiconductor layer 16. An air gap 71 may be located between the field plate 511 and the third nitride semiconductor layer 18. An air gap 71 may be located between the field plate 511 and the gate electrode 20.
The air gap 71 has a relatively low dielectric constant compared to the first dielectric layer 45, and the electrical properties of the semiconductor device 1d can be adjusted by adjusting the layout (layout) of the air gap 71 and the first dielectric layer 45.
Fig. 5 is a cross-sectional view of a semiconductor device 1e according to some embodiments of the present disclosure. The structure of the semiconductor device 1e may be similar to that of the semiconductor device 1d, except for the following.
The surface 511s1 of the field plate 511 may be relatively rough. The surface 511s1 of the field plate 511 may have a surface roughness greater than that of the surface 30s1 of the dielectric layer 30.
The field plate 511 may include a protrusion 511p. The protrusion 511p may extend from the field plate 511 toward the third nitride semiconductor layer 18. The protrusion 511p may cover the surface 20s2 of the gate electrode 20. The protrusion 511p may contact the dielectric layer 30.
Fig. 6A, 6B, 6C, and 6D illustrate various stages of a method for fabricating a semiconductor device according to some embodiments of the disclosure.
Referring to fig. 6A, a substrate 12 is provided. The first nitride semiconductor layer 14, the second nitride semiconductor layer 16, the third nitride semiconductor layer 18, and the gate electrode 20 may be formed on the substrate 12. The dielectric layer 30 may be conformally formed on the second nitride semiconductor layer 16, the third nitride semiconductor layer 18, and the gate electrode 20. The first nitride semiconductor layer 14, the second nitride semiconductor layer 16, the third nitride semiconductor layer 18, the gate electrode 20, and the dielectric layer 30 may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes.
Referring to fig. 6B, dielectric material 41' is formed. Dielectric material 41' may cover dielectric layer 30. The dielectric material 41' may comprise nitride, oxide, oxynitride or other suitable material. The dielectric material 41' may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable process.
Referring to fig. 6C, dielectric material 41' is patterned to form first dielectric layer 41 and expose surface 30s1 of dielectric layer 30. An etching process may be performed to pattern the dielectric material 41'.
Referring to fig. 6D, an electrode 51, a field plate 511, an electrode 52 and a dielectric structure 60 are formed to form the semiconductor device 1a shown in fig. 1.
With careful consideration, in the stage of fig. 6C, an etching process may be performed until the top of the first dielectric layer 41 is lower than the surface 30s1 of the dielectric layer 30, and then the electrode 51, the field plate 511, the electrode 52 and the dielectric structure 60 are formed, so that the semiconductor device 1b shown in fig. 2 may be obtained.
After forming the first dielectric layer 41 in the stage of fig. 6C, the first dielectric layer 41 may be further patterned by a photolithography process and an etching process, and the semiconductor device 1C shown in fig. 3 may be obtained.
After forming the first dielectric layer 41 in the stage of fig. 6C, a patterned shielding structure (not shown) may be formed to cover a portion of the first dielectric layer 41, and after forming the air gap 71 by etching, the shielding structure is removed, and the electrode 51, the field plate 511, the electrode 52 and the dielectric structure 60 are formed, so that the semiconductor device 1d shown in fig. 4B or the semiconductor device 1e shown in fig. 5 may be obtained.
Spatially relative terms, such as "under", "lower", "above", "upper", "lower", "left", "right", and the like, as used herein for convenience of description, may be used to describe one component or feature as illustrated in the figures relative to another component or feature. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 80 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present.
As used herein, the terms "about," "substantially," and "about" are used to describe and explain minor variations. When used in connection with an event or situation, the term may refer to instances where the event or situation occurs precisely as well as instances where the event or situation occurs in close proximity. As used herein with respect to a given value or range, the term "about" generally means within ±10%, 5%, 1% or 0.5% of the given value or range. Ranges can be expressed herein as from one endpoint to another endpoint, or between two endpoints. All ranges disclosed herein are inclusive of the endpoints unless otherwise indicated. The term "substantially coplanar" may refer to a difference in position of two surfaces located along a same plane being within a few micrometers (μm), such as a difference in position located along the same plane being within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm. When values or characteristics are said to be "substantially" the same, the term may refer to values within ±10%, 5%, 1% or 0.5% of the average value of the values.
The foregoing has outlined features of several embodiments and detailed aspects of the present disclosure. The embodiments described in this disclosure may be readily utilized as a basis for designing or modifying other processes and structures to carry out the same or similar purposes and/or to achieve the same or similar advantages of the embodiments presented herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made hereto without departing from the spirit and scope of the present disclosure.

Claims (25)

1. A semiconductor device, comprising:
a substrate;
a first nitride semiconductor layer disposed on the substrate;
a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer;
a third nitride semiconductor layer doped with impurities and provided on the second nitride semiconductor layer;
a gate electrode disposed on the third nitride semiconductor layer; and
a field plate covering the gate electrode, wherein a distance between the field plate and a side surface of the gate electrode is non-uniform.
2. The semiconductor device according to claim 1, wherein a distance between the field plate and a side surface of the third nitride semiconductor layer is non-uniform.
3. The semiconductor device according to claim 1, further comprising:
and a first dielectric layer disposed on the side surface of the gate electrode.
4. The semiconductor device of claim 3, wherein the first dielectric layer separates the field plate from the side surface of the gate electrode.
5. The semiconductor device according to claim 3, wherein a distance between a side surface of the first dielectric layer and the side surface of the gate electrode is non-uniform.
6. The semiconductor device according to claim 3, wherein a height of a top of the first dielectric layer is higher than a height of an upper surface of the gate electrode.
7. The semiconductor device according to claim 3, further comprising:
and the second dielectric layer is arranged between the gate electrode and the first dielectric layer.
8. The semiconductor device of claim 7, wherein the second dielectric layer is conformally disposed on an upper surface of the gate electrode and on the side surface.
9. The semiconductor device according to claim 7, wherein a dielectric constant of the second dielectric layer is larger than a dielectric constant of the first dielectric layer.
10. The semiconductor device of claim 9, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer.
11. The semiconductor device of claim 7, wherein a top of the first dielectric layer is substantially at the same height as an upper surface of the second dielectric layer.
12. The semiconductor device of claim 7, wherein a top of the first dielectric layer is lower than an upper surface of the second dielectric layer.
13. The semiconductor device according to claim 1, further comprising:
an air gap between the third nitride semiconductor layer and the field plate.
14. The semiconductor device according to claim 1, further comprising:
an air gap between the gate electrode and the field plate.
15. The semiconductor device of claim 1, wherein the field plate has a protrusion extending toward the substrate.
16. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a first nitride semiconductor layer on the substrate;
forming a second nitride semiconductor layer on the first nitride semiconductor layer, the band gap of which is larger than that of the first nitride semiconductor layer;
forming a third nitride semiconductor layer on the second nitride semiconductor layer, which is doped with a dopant;
forming a gate electrode on the third nitride semiconductor layer; and
a field plate is formed overlying the gate electrode, wherein a distance between the field plate and a side surface of the gate electrode is non-uniform.
17. The method as recited in claim 16, further comprising:
forming a first dielectric layer on the gate electrode and the third nitride semiconductor layer; and
forming a second dielectric layer on the first dielectric layer,
wherein the first dielectric layer and the second dielectric layer are located between the gate electrode and the field plate.
18. The method of claim 17, wherein the first dielectric layer has a dielectric constant that is greater than a dielectric constant of the second dielectric layer.
19. The method as recited in claim 17, further comprising:
a portion of the second dielectric layer is removed to form an air gap.
20. The method of claim 17, wherein forming the second dielectric layer comprises:
forming a dielectric material to cover the first dielectric layer; and
a portion of the dielectric material is removed exposing an upper surface of the first dielectric layer.
21. A semiconductor device, comprising:
a substrate;
a first nitride semiconductor layer disposed on the substrate;
a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer;
a third nitride semiconductor layer doped with impurities and provided on the second nitride semiconductor layer;
a gate electrode disposed on the third nitride semiconductor layer;
a first dielectric layer disposed on a side surface of the gate electrode; and
a field plate covering the gate electrode,
wherein the side surface of the gate electrode is separated from the field plate by the first dielectric layer.
22. The semiconductor device according to claim 21, wherein a height of a top portion of the first dielectric layer is higher than a height of an upper surface of the gate electrode.
23. The semiconductor device according to claim 21, wherein a distance between the first dielectric layer and a side surface of the gate electrode is non-uniform.
24. The semiconductor device according to claim 21, further comprising:
and a dielectric layer disposed between the gate electrode and the first dielectric layer, wherein a dielectric constant of the dielectric layer is different from a dielectric constant of the first dielectric layer.
25. The semiconductor device of claim 24, wherein the field plate contacts a side surface of the dielectric layer.
CN202311350390.0A 2023-10-18 2023-10-18 Semiconductor device and forming method thereof Pending CN117410330A (en)

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CN117410330A true CN117410330A (en) 2024-01-16

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