CN117409697A

CN117409697A - Scan driver for applying bias voltage and display device

Info

Publication number: CN117409697A
Application number: CN202310765274.9A
Authority: CN
Inventors: 姜章美; 金亨锡; 朴埈贤; 郑珉在; 田武经
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2022-07-14
Filing date: 2023-06-27
Publication date: 2024-01-16
Also published as: US20240021165A1; KR20240010635A

Abstract

The present disclosure provides a scan driver for applying a bias voltage and a display device. The scan driver includes a kth stage including: an input transmitting an input signal to a first node; a stress reducer disposed between the first node and the second node; a carry signal output unit receiving the high power voltage and the second clock signal and outputting the second clock signal; an output signal outputter receiving the high power supply voltage and the third clock signal and outputting the third clock signal; a keeper that transmits the first clock signal to the third node; and a stabilizer applying a first low power supply voltage to the third node and applying a high power supply voltage to the first node. The first clock signal and the second clock signal are switched between a high power supply voltage and a first low power supply voltage, the third clock signal is switched between a high power supply voltage and a second low power supply voltage, and the bias voltage is adjusted by changing the second low power supply voltage.

Description

Scan driver for applying bias voltage and display device

Technical Field

The present disclosure relates generally to a display device. More particularly, the present disclosure relates to a display device capable of applying a bias voltage to a specific node in a pixel circuit.

Background

In general, a display device may receive image data from a host processor (e.g., a Graphics Processing Unit (GPU), etc.), and may perform display operations based on the image data. Recently, a variable frame rate technique has been proposed: when the host processor changes the frame rate of the image frames constituting the image data according to the characteristics of the image to be displayed by the display operation, the frame rate of the image frames (e.g., the rendering speed of the GPU) is matched with the frame rate of the panel driving frames (i.e., the driving frequency of the display panel) by changing the frame rate of the panel driving frames for the display operation of the display device.

Recently, a scheme of changing the frame rate of a panel driving frame by causing a display device to increase or decrease a vertical blanking period (e.g., adjusting the number of self-scanning periods performed after a display scanning period) within the panel driving frame has been adopted as a variable frame rate technique. However, according to this scheme, when the frame rate of the panel driving frame decreases (i.e., when the driving time of the panel driving frame increases), flicker may occur on the display panel since the characteristics of the driving transistors included in the pixel circuits in the display panel are fixed to the hysteresis characteristics in a predetermined state during one panel driving frame.

Disclosure of Invention

An object of the present disclosure is to provide a scan driver for applying a bias voltage capable of applying an adjustable bias voltage to a specific node (e.g., a gate terminal of a driving transistor, etc.) in a pixel circuit included in a display panel.

It is another object of the present disclosure to provide a display device including a scan driver for applying a bias voltage.

According to an embodiment, a scan driver for applying a bias voltage may include first to nth stages, where n is an integer of 2 or more, configured to output first to nth output signals for applying the bias voltage to first to nth pixel rows, respectively. Here, the kth stage may include: an input configured to transmit an input signal to a first node in response to a first clock signal; a stress reducer disposed between the first node and the second node; a carry signal outputter configured to receive a high power supply voltage and a second clock signal, and to output the second clock signal as a kth carry signal via a first output node in response to a voltage of the second node; an output signal outputter configured to receive the high power supply voltage and a third clock signal, and to output the third clock signal as a kth output signal via a second output node in response to the voltage of the second node; a keeper configured to transmit the first clock signal to a third node in response to a voltage of the first node; and a stabilizer configured to apply a first low power supply voltage to the third node in response to the first clock signal and to apply the high power supply voltage to the first node in response to the second clock signal, wherein k is an integer of 1 to n. In addition, each of the first and second clock signals may be switched between the high and first low power supply voltages, the third clock signal may be switched between the high and second low power supply voltages, and the bias voltage may be adjusted by changing the second low power supply voltage.

In an embodiment, the input signal may include a scan start signal or a previous carry signal.

In an embodiment, the input may include: a first transistor includes a first terminal configured to receive the input signal, a second terminal connected to the first node, and a gate terminal configured to receive the first clock signal.

In an embodiment, the stress reducer may include: an eighth transistor includes a first terminal connected to the first node, a second terminal connected to the second node, and a gate terminal configured to receive the first low supply voltage.

In an embodiment, the carry signal outputter may include: a ninth transistor including a first terminal configured to receive the high power supply voltage, a second terminal connected to the first output node, and a gate terminal connected to the third node; and a tenth transistor including a first terminal connected to the first output node, a second terminal configured to receive the second clock signal, and a gate terminal connected to the second node.

In an embodiment, the output signal outputter may include: a sixth transistor including a first terminal configured to receive the high power supply voltage, a second terminal connected to the second output node, and a gate terminal connected to the third node; and a seventh transistor including a first terminal connected to the second output node, a second terminal configured to receive the third clock signal, and a gate terminal connected to the second node.

In an embodiment, the retainer may include: a fourth transistor includes a first terminal connected to the third node, a second terminal configured to receive the first clock signal, and a gate terminal connected to the first node.

In an embodiment, the stabilizer may include: a second transistor including a first terminal configured to receive the high power supply voltage, a second terminal, and a gate terminal connected to the third node; a third transistor including a first terminal connected to the second terminal of the second transistor, a second terminal connected to the first node, and a gate terminal configured to receive the second clock signal; a first capacitor including a first terminal configured to receive the high supply voltage and a second terminal connected to the third node; and a fifth transistor including a first terminal connected to the third node, a second terminal configured to receive the first low power supply voltage, and a gate terminal configured to receive the first clock signal.

In an embodiment, the scan driver may further include a bootstrap device disposed between the second node and the first output node.

In an embodiment, the bootstrap device may include: a second capacitor includes a first terminal connected to the second node and a second terminal connected to the first output node.

According to an embodiment, a scan driver for applying a bias voltage may include: first to nth stages, where n is an integer of 2 or more, configured to output first to nth output signals for applying the bias voltages to the first to nth pixel rows, respectively. Here, the kth stage may include: an input configured to transmit an input signal to a first node in response to a first clock signal; a stress reducer disposed between the first node and the second node; a carry signal outputter configured to receive a first high power supply voltage and a second clock signal, and to output the second clock signal as a kth carry signal via a first output node in response to a voltage of the second node; an output signal outputter configured to receive a second high power supply voltage and a third clock signal, and to output the third clock signal as a kth output signal via a second output node in response to the voltage of the second node; a keeper configured to transmit the first clock signal to a third node in response to a voltage of the first node; and a stabilizer configured to apply a first low power supply voltage to the third node in response to the first clock signal and to apply the first high power supply voltage to the first node in response to the second clock signal, wherein k is an integer of 1 to n. In addition, each of the first and second clock signals may be switched between the first high and low power supply voltages, the third clock signal may be switched between the second high and low power supply voltages, and the bias voltage may be adjusted by changing at least one of the second high and low power supply voltages.

In an embodiment, the carry signal outputter may include: a ninth transistor including a first terminal configured to receive the first high supply voltage, a second terminal connected to the first output node, and a gate terminal connected to the third node; and a tenth transistor including a first terminal connected to the first output node, a second terminal configured to receive the second clock signal, and a gate terminal connected to the second node.

In an embodiment, the output signal outputter may include: a sixth transistor including a first terminal configured to receive the second high supply voltage, a second terminal connected to the second output node, and a gate terminal connected to the third node; and a seventh transistor including a first terminal connected to the second output node, a second terminal configured to receive the third clock signal, and a gate terminal connected to the second node.

In an embodiment, the stabilizer may include: a second transistor including a first terminal configured to receive the first high power supply voltage, a second terminal, and a gate terminal connected to the third node; a third transistor including a first terminal connected to the second terminal of the second transistor, a second terminal connected to the first node, and a gate terminal configured to receive the second clock signal; a first capacitor including a first terminal configured to receive the first high supply voltage and a second terminal connected to the third node; and a fifth transistor having a first terminal connected to the third node, a second terminal configured to receive the first low power supply voltage, and a gate terminal configured to receive the first clock signal.

In an embodiment, the bootstrap may comprise a second capacitor comprising a first terminal connected to the second node and a second terminal connected to the first output node.

According to an embodiment, a display device may include: a display panel including a first pixel row to an n-th pixel row, where n is an integer of 2 or more, the first pixel row to the n-th pixel row including pixel circuits having a structure in which a bias voltage is applied to a gate terminal of a driving transistor via a boost capacitor; a display panel driver configured to drive the display panel; and a scan driver for applying a bias voltage, the scan driver including first to nth stages configured to output first to nth output signals for applying the bias voltage to the first to nth pixel rows, respectively. Here, the bias voltage may correspond to a difference between a high level voltage and a low level voltage of a kth output signal, where k is an integer of 1 to n, and may be adjusted by changing at least one of the high level voltage and the low level voltage.

In an embodiment, the kth stage may include: an input configured to transmit an input signal to a first node in response to a first clock signal; a stress reducer disposed between the first node and the second node; a carry signal outputter configured to receive a high power supply voltage and a second clock signal, and to output the second clock signal as a kth carry signal via a first output node in response to a voltage of the second node; an output signal outputter configured to receive the high power supply voltage and a third clock signal, and to output the third clock signal as the kth output signal via a second output node in response to the voltage of the second node; a keeper configured to transmit the first clock signal to a third node in response to a voltage of the first node; and a stabilizer configured to apply a first low power supply voltage to the third node in response to the first clock signal and to apply the high power supply voltage to the first node in response to the second clock signal. In addition, each of the first and second clock signals may be switched between the high and first low power supply voltages, the third clock signal may be switched between the high and second low power supply voltages, and the bias voltage may be adjusted by changing the second low power supply voltage.

In an embodiment, the kth stage may include: an input configured to transmit an input signal to a first node in response to a first clock signal; a stress reducer disposed between the first node and the second node; a carry signal outputter configured to receive a first high power supply voltage and a second clock signal, and to output the second clock signal as a kth carry signal via a first output node in response to a voltage of the second node; an output signal outputter configured to receive a second high power supply voltage and a third clock signal, and to output the third clock signal as the kth output signal via a second output node in response to the voltage of the second node; a keeper configured to transmit the first clock signal to a third node in response to a voltage of the first node; and a stabilizer configured to apply a first low power supply voltage to the third node in response to the first clock signal and to apply the first high power supply voltage to the first node in response to the second clock signal. In addition, each of the first and second clock signals may be switched between the first high and low power supply voltages, the third clock signal may be switched between the second high and low power supply voltages, and the bias voltage may be adjusted by changing at least one of the second high and low power supply voltages.

Accordingly, the scan driver for applying the bias voltage according to the embodiment may include first to nth stages configured to output first to nth output signals for applying the bias voltage to first to nth pixel rows, respectively. Here, the bias voltage may be variously adjusted by changing a high level voltage and/or a low level voltage of each of the first to nth output signals.

The kth stage among the first to nth stages may include: an input configured to transmit an input signal to a first node in response to a first clock signal; a stress reducer disposed between the first node and the second node; a carry signal outputter configured to receive a high power supply voltage and a second clock signal, and to output the second clock signal as a kth carry signal via a first output node in response to a voltage of the second node; an output signal outputter configured to receive the high power supply voltage and a third clock signal, and to output the third clock signal as the kth output signal via a second output node in response to the voltage of the second node; a keeper configured to transmit the first clock signal to a third node in response to a voltage of the first node; and a stabilizer configured to apply a first low power supply voltage to the third node in response to the first clock signal and to apply the high power supply voltage to the first node in response to the second clock signal. Here, each of the first and second clock signals may be switched between the high power supply voltage and the first low power supply voltage, the third clock signal may be switched between the high power supply voltage (i.e., the high level voltage of the kth output signal) and a second low power supply voltage (i.e., the low level voltage of the kth output signal), and the bias voltage may be adjusted by changing the second low power supply voltage. Accordingly, even if the frame rate of the panel driving frame for driving the display panel is changed (i.e., the driving frequency of the display panel is changed), it is possible to improve the hysteresis characteristic in which the characteristics of the driving transistor are fixed in a predetermined state.

Alternatively, the kth stage among the first to nth stages may include: an input configured to transmit an input signal to a first node in response to a first clock signal; a stress reducer disposed between the first node and the second node; a carry signal outputter configured to receive a first high power supply voltage and a second clock signal, and to output the second clock signal as a kth carry signal via a first output node in response to a voltage of the second node; an output signal outputter configured to receive a second high power supply voltage and a third clock signal, and to output the third clock signal as the kth output signal via a second output node in response to the voltage of the second node; a keeper configured to transmit the first clock signal to a third node in response to a voltage of the first node; and a stabilizer configured to apply a first low power supply voltage to the third node in response to the first clock signal and to apply the first high power supply voltage to the first node in response to the second clock signal. Here, each of the first and second clock signals may be switched between the first high power supply voltage and the first low power supply voltage, the third clock signal may be switched between the second high power supply voltage (i.e., the high level voltage of the kth output signal) and a second low power supply voltage (i.e., the low level voltage of the kth output signal), and the bias voltage may be adjusted by changing at least one of the second high power supply voltage and the second low power supply voltage. Accordingly, even if the frame rate of the panel driving frame for driving the display panel is changed, the hysteresis characteristic in which the characteristics of the driving transistor are fixed in a predetermined state can be improved.

In addition, the display device according to the embodiment may include the scan driver for applying the bias voltage, so that a high quality image may be displayed even if a variable frame rate technique is employed.

Drawings

Fig. 1 is a block diagram illustrating a display device according to an embodiment.

Fig. 2 is a diagram for describing a change in frame rate of a panel driving frame of the display device of fig. 1.

Fig. 3 is a circuit diagram showing an example of a pixel circuit included in the display device of fig. 1.

Fig. 4 is a circuit diagram showing another example of a pixel circuit included in the display device of fig. 1.

Fig. 5 is a timing chart showing signals applied to the pixel circuit of fig. 3 or the pixel circuit of fig. 4 in a display scan period.

Fig. 6 is a timing chart showing signals applied to the pixel circuit of fig. 3 or the pixel circuit of fig. 4 in a self-scanning period.

Fig. 7 is a block diagram illustrating an example of a scan driver for applying a bias voltage included in the display device of fig. 1.

Fig. 8 is a circuit diagram illustrating a kth stage included in the scan driver for applying a bias voltage of fig. 7.

Fig. 9 is a timing chart for describing the operation of the kth stage of fig. 8.

Fig. 10 is a diagram for explaining how the scan driver for applying bias voltages of fig. 7 adjusts bias voltages.

Fig. 11 is a block diagram illustrating another example of a scan driver for applying a bias voltage included in the display device of fig. 1.

Fig. 12 is a circuit diagram illustrating a kth stage included in the scan driver for applying a bias voltage of fig. 11.

Fig. 13 is a timing chart for describing the operation of the kth stage of fig. 12.

Fig. 14 is a diagram for explaining how the scan driver for applying bias voltages of fig. 11 adjusts bias voltages.

Fig. 15 is a block diagram illustrating an electronic device according to an embodiment.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

Fig. 1 is a block diagram illustrating a display device according to an embodiment, and fig. 2 is a diagram for describing a change in frame rate of a panel driving frame of the display device of fig. 1.

Referring to fig. 1 and 2, the display device 100 may include a display panel 110, a display panel driver 120, and a scan driver 130 for applying a bias voltage. Here, the display device 100 may display images at various driving frequencies according to driving conditions (i.e., drive the display panel 110 at various driving frequencies). Meanwhile, although the display panel driver 120 and the scan driver 130 for applying the bias voltage have been illustrated as separate components in fig. 1, the scan driver 130 for applying the bias voltage may be a component included in the display panel driver 120. In some embodiments, the display device 100 may be an organic light emitting display device or a quantum dot light emitting display device, but the display device 100 is not limited thereto.

The display panel 110 may include a plurality of pixel circuits 111. For example, the pixel circuit 111 may include a red pixel circuit, a green pixel circuit, and a blue pixel circuit. Here, each of the pixel circuits 111 may be connected to a data line configured to transmit a data signal VDATA (i.e., a data voltage), a gate line configured to transmit a gate signal GW, an initialization line configured to transmit an initialization signal GI, a compensation line configured to transmit a compensation signal GC, a connection line configured to transmit a connection signal GT, a transmission line configured to transmit an emission signal EM, and a bias line configured to transmit an output signal EB for applying a bias voltage.

The pixel circuit 111 may perform one display scan operation (i.e., represented by a display scan period D-SCN in fig. 2) when the driving time of the panel driving frame 1F for driving the display panel 110 is a reference driving time (or a minimum driving time), and may perform one display scan operation and at least one self scan operation (i.e., represented by a self scan period S-SCN in fig. 2) when the driving time of the panel driving frame 1F for driving the display panel 110 is greater than the reference driving time. Here, the display scanning operation may be an operation of receiving the data signal VDATA to cause the light emitting element (e.g., an organic light emitting diode) to emit light, and the self-scanning operation may be an operation of changing characteristics of the driving transistor included in the pixel circuit 111. In an embodiment, the pixel circuit 111 may separately perform the compensation operation and the data writing operation. To achieve this, the pixel circuit 111 may have a so-called 9T-3C structure including nine transistors and three capacitors. However, the above configuration will be described in detail with reference to fig. 3 and 4.

The pixel circuit 111 may have a structure in which a bias voltage is applied to a gate terminal of the driving transistor via a boost capacitor. The plurality of pixel circuits 111 may constitute a first pixel row to an n-th pixel row (where n is an integer of 2 or more) in the display panel 110. Here, the output signal EB for applying the bias voltage may be sequentially supplied to the first to nth pixel rows through the scan driver 130 for applying the bias voltage. For example, after the kth output signal EB (k) (refer to fig. 8) (where k is an integer of 1 to n) is supplied to the kth pixel row, the (k+1) th output signal may be supplied to the (k+1) th pixel row. Here, there may be a time interval of one horizontal period (1H) between a point of time at which the scan driver 130 for applying the bias voltage outputs the kth output signal EB (k) to the kth pixel row and a point of time at which the scan driver 130 for applying the bias voltage outputs the (k+1) th output signal to the (k+1) th pixel row.

The display panel driver 120 may drive the display panel 110. In an embodiment, the display panel driver 120 may include: a data driver configured to provide the data signal VDATA to the display panel 110 via the data line, a gate driver configured to provide the gate signal GW to the display panel 110 via the gate line, an initialization driver configured to provide the initialization signal GI to the display panel 110 via the initialization line, a compensation driver configured to provide the compensation signal GC to the display panel 110 via the compensation line, a connection driver configured to provide the connection signal GT to the display panel 110 via the connection line, an emission driver configured to provide the emission signal EM to the display panel 110 via the emission line, and a timing controller (also referred to as a display panel driving controller) configured to control the data driver, the gate driver, the initialization driver, the compensation driver, the connection driver, and the emission driver.

The timing controller may receive image data from a host processor (e.g., a graphics processing unit, etc.) via a predetermined interface. For example, the image data may include red image data, green image data, and blue image data. In some embodiments, the image data may also include white image data. As another example, the image data may include magenta image data, yellow image data, and cyan image data. The timing controller may provide the image data received from the host processor to the data driver, or may perform predetermined processing (e.g., brightness compensation, degradation compensation, etc.) on the image data received from the host processor, and provide the compensated image data to the data driver.

The data driver may provide the data signal VDATA to the display panel 110 via the data line. In detail, the data driver may generate the data signal VDATA (i.e., data voltage) by converting digital image data (or compensated image data) into analog voltages based on the image data (or compensated image data) received from the timing controller and a predetermined control signal (e.g., a horizontal start signal, a load signal, etc.), and may supply the data signal VDATA to the pixel circuit 111 included in the display panel 110.

The gate driver may provide the gate signal GW to the display panel 110 via a gate line. In detail, the gate driver may generate the gate signal GW based on a predetermined control signal (e.g., a vertical start signal, a gate clock signal, etc.) received from the timing controller, and may provide the gate signal GW to the pixel circuit 111 included in the display panel 110.

The initialization driver may provide an initialization signal GI to the display panel 110 via an initialization line. In detail, the initialization driver may generate an initialization signal GI based on a predetermined control signal received from the timing controller, and may provide the initialization signal GI to the pixel circuit 111 included in the display panel 110.

The compensation driver may provide the compensation signal GC to the display panel 110 via a compensation line. In detail, the compensation driver may generate the compensation signal GC based on a predetermined control signal received from the timing controller, and may provide the compensation signal GC to the pixel circuit 111 included in the display panel 110.

The connection driver may provide the connection signal GT to the display panel 110 via a connection line. In detail, the connection driver may generate the connection signal GT based on a predetermined control signal received from the timing controller, and may provide the connection signal GT to the pixel circuit 111 included in the display panel 110.

The emission driver may supply the emission signal EM to the display panel 110 via an emission line. In detail, the emission driver may generate the emission signal EM based on a predetermined control signal received from the timing controller, and may supply the emission signal EM to the pixel circuit 111 included in the display panel 110.

In some embodiments, some of the gate signal GW, the initialization signal GI, the compensation signal GC, the connection signal GT, and the emission signal EM may be omitted. In this case, the predetermined signal for performing a specific operation on a specific pixel row may be used for performing another specific operation on another specific pixel row. For example, the gate signal GW applied to a specific pixel row may be used as the initialization signal GI for another specific pixel row. Here, some of the gate driver, the initialization driver, the compensation driver, the connection driver, and the emission driver may be omitted in the display panel driver 120.

The scan driver 130 for applying the bias voltage may include first to nth stages configured to output signals EB for applying the bias voltage to first to nth pixel rows included in the display panel 110, respectively. Here, the bias voltage applied to a specific pixel row may correspond to a difference between a high level voltage and a low level voltage of the output signal EB output from the scan driver 130 for applying the bias voltage. Accordingly, the bias voltage applied to a specific pixel row may be variously adjusted as the high level voltage and/or the low level voltage of the output signal EB output from the scan driver 130 for applying the bias voltage varies. However, the above configuration will be described in detail with reference to fig. 7 to 14.

As described above, the display device 100 can cause the light emitting element included in the pixel circuit 111 to emit light in the display scan period D-SCN, and can change the characteristics of the driving transistor included in the pixel circuit 111 in the self-scan period S-SCN. For example, as shown in fig. 2, the display apparatus 100 may perform only one display scan period D-SCN at a maximum driving frequency of the display panel 110 (i.e., it is assumed that the maximum driving frequency of the display panel 110 is 240Hz in fig. 2), and may perform one display scan period D-SCN and at least one self-scan period S-SCN at driving frequencies of the display panel 110 other than the maximum driving frequency (i.e., 120Hz, 80Hz, 60Hz, 48Hz, 40Hz, etc.).

In detail, when the driving frequency of the display panel 110 is 240Hz, one panel driving frame 1F may include only one display scan period D-SCN; when the driving frequency of the display panel 110 is 120Hz, one panel driving frame 1F may include one display scan period D-SCN and one self-scan period S-SCN; when the driving frequency of the display panel 110 is 80Hz, one panel driving frame 1F may include one display scan period D-SCN and two self-scan periods S-SCN; when the driving frequency of the display panel 110 is 60Hz, one panel driving frame 1F may include one display scan period D-SCN and three self-scan periods S-SCN; when the driving frequency of the display panel 110 is 48Hz, one panel driving frame 1F may include one display scan period D-SCN and four self-scan periods S-SCN; and when the driving frequency of the display panel 110 is 40Hz, one panel driving frame 1F may include one display scan period D-SCN and five self-scan periods S-SCN. As described above, the display device 100 may change the driving frequency of the display panel 110 by adjusting the number of the self-scan periods S-SCN.

Referring to fig. 3, and also to fig. 1, the pixel circuit 111A may have a so-called 9T-3C structure in which a compensation operation and a data write operation are separately performed. In detail, the pixel circuit 111A may include a light emitting element EE, a first thin film transistor TT1, a second thin film transistor TT2, a third thin film transistor TT3, a fourth thin film transistor TT4, a fifth thin film transistor TT5, a sixth thin film transistor TT6, a seventh thin film transistor TT7, an eighth thin film transistor TT8, a ninth thin film transistor TT9, a storage capacitor CST, a holding capacitor CHOLD, and a bias capacitor CBIAS.

The first thin film transistor TT1 may include a gate terminal connected to the first pixel node N1, a first terminal configured to receive the first power supply voltage ELVDD, and a second terminal connected to the second pixel node N2. Here, the first thin film transistor TT1 may be turned on in response to the voltage stored in the storage capacitor CST (i.e., the voltage of the first pixel node N1) to flow a driving current to the light emitting element EE. In other words, the first thin film transistor TT1 may be referred to as a driving transistor. Meanwhile, a bias voltage corresponding to a difference between a high level voltage and a low level voltage of the output signal EB outputted from the scan driver 130 for applying the bias voltage may be indirectly (i.e., via the storage capacitor CST) applied to the gate terminal of the first thin film transistor TT1 (i.e., the first pixel node N1).

The second thin film transistor TT2 may include a gate terminal configured to receive the gate signal GW, a first terminal connected to a data line configured to transmit the data signal VDATA, and a second terminal connected to the fifth pixel node N5. Here, the second thin film transistor TT2 may be turned on in response to the gate signal GW to apply the data signal VDATA transmitted via the data line to the fourth pixel node N4 via the eighth thin film transistor TT 8.

The third thin film transistor TT3 may include a gate terminal configured to receive the compensation signal GC, a first terminal connected to the second pixel node N2, and a second terminal connected to the third pixel node N3. Here, the third thin film transistor TT3 may be turned on in response to the compensation signal GC to diode-connect the first thin film transistor TT1 via the ninth thin film transistor TT9 so as to compensate for the threshold voltage of the first thin film transistor TT1 (i.e., the driving transistor).

The fourth thin film transistor TT4 may include a gate terminal configured to receive the initialization signal GI, a first terminal connected to the third pixel node N3, and a second terminal configured to receive the initialization voltage VINT. Here, the fourth thin film transistor TT4 may be turned on in response to the initialization signal GI to apply the initialization voltage VINT to the first pixel node N1 via the ninth thin film transistor TT 9. Accordingly, the gate terminal (i.e., the first pixel node N1) of the first thin film transistor TT1 (i.e., the driving transistor) may be initialized.

The fifth thin film transistor TT5 may include a gate terminal configured to receive the compensation signal GC, a first terminal connected to the fifth pixel node N5, and a second terminal configured to receive the reference voltage VREF. Here, the fifth thin film transistor TT5 may be turned on in response to the compensation signal GC to apply the reference voltage VREF to the fourth pixel node N4 via the eighth thin film transistor TT 8. In an embodiment, the reference voltage VREF may be the first power supply voltage ELVDD.

The sixth thin film transistor TT6 may include a gate terminal configured to receive the emission signal EM, a first terminal connected to the second pixel node N2, and a second terminal connected to the anode of the light emitting element EE. Here, the sixth thin film transistor TT6 may be turned on in response to the emission signal EM to cause a driving current to flow to the light emitting element EE between the first power voltage ELVDD and the second power voltage ELVSS.

The seventh thin film transistor TT7 may include a gate terminal configured to receive the next initialization signal GI (n+1), a first terminal connected to the anode of the light emitting element EE, and a second terminal configured to receive the reset voltage vant. Here, the seventh thin film transistor TT7 may be turned on in response to the next initialization signal GI (n+1) to apply the reset voltage vant to the anode of the light emitting element EE. Thus, the anode of the light emitting element EE may be reset (or initialized). In some embodiments, a separate reset signal may be applied to the gate terminal of the seventh thin film transistor TT7 instead of the next initialization signal GI (n+1). In this case, the display panel driver 120 may further include a reset driver configured to generate a separate reset signal.

In an embodiment, the initialization voltage VINT applied to the first pixel node N1 via the fourth thin film transistor TT4 and the reset voltage vant applied to the anode of the light emitting element EE via the seventh thin film transistor TT7 may be the same. In another embodiment, the initialization voltage VINT applied to the first pixel node N1 via the fourth thin film transistor TT4 and the reset voltage vant applied to the anode of the light emitting element EE via the seventh thin film transistor TT7 may be different from each other.

The eighth thin film transistor TT8 may include a gate terminal configured to receive the connection signal GT, a first terminal connected to the fifth pixel node N5, and a second terminal connected to the fourth pixel node N4. Here, the eighth thin film transistor TT8 may be turned on in response to the connection signal GT to electrically connect the fifth pixel node N5 to the fourth pixel node N4. Meanwhile, when the eighth thin film transistor TT8 is turned off in response to the connection signal GT, the fifth pixel node N5 and the fourth pixel node N4 may be electrically disconnected from each other.

The ninth thin film transistor TT9 may include a gate terminal configured to receive the connection signal GT, a first terminal connected to the first pixel node N1, and a second terminal connected to the third pixel node N3. Here, the ninth thin film transistor TT9 may be turned on in response to the connection signal GT to electrically connect the first pixel node N1 to the third pixel node N3. Meanwhile, when the ninth thin film transistor TT9 is turned off in response to the connection signal GT, the first pixel node N1 and the third pixel node N3 may be electrically disconnected from each other.

The storage capacitor CST may include a first terminal connected to the fourth pixel node N4 and a second terminal connected to the first pixel node N1. Here, the storage capacitor CST may store a voltage generated by performing a threshold voltage compensation operation on the data signal VDATA (i.e., a data voltage) transmitted through the data line.

The holding capacitor CHOLD may include a first terminal configured to receive the first power supply voltage ELVDD and a second terminal connected to the fourth pixel node N4 (i.e., the first terminal of the storage capacitor CST). Here, the holding capacitor CHOLD may perform a holding operation on the voltage of the fourth pixel node N4.

The bias capacitor CBIAS may include a first terminal configured to receive the output signal EB output from the scan driver 130 for applying the bias voltage, and a second terminal connected to the fourth pixel node N4. Here, the bias capacitor CBIAS may perform the boosting operation with a bias voltage corresponding to a difference between a high level voltage and a low level voltage of the output signal EB output from the scan driver 130 for applying the bias voltage. Accordingly, the voltage of the fourth pixel node N4 may be boosted by the bias voltage corresponding to the difference between the high level voltage and the low level voltage of the output signal EB output from the scan driver 130 for applying the bias voltage, so that the voltage of the gate terminal of the first thin film transistor TT1 (i.e., the first pixel node N1) may also be indirectly boosted via the storage capacitor CST. Here, the scan driver 130 for applying the bias voltage may adjust the bias voltage by changing a high level voltage and/or a low level voltage of the output signal EB.

The light emitting element EE may include an anode connected to the second terminal of the sixth thin film transistor TT6 and the first terminal of the seventh thin film transistor TT7 and a cathode configured to receive the second power supply voltage ELVSS. Here, the light emitting element EE may emit light corresponding to a driving current controlled by the first thin film transistor TT1 (which is a driving transistor). In an embodiment, when the display device 100 is an organic light emitting display device, the light emitting element EE may be an organic light emitting diode. However, the light emitting element EE is not limited thereto.

Meanwhile, although it has been shown in fig. 3 that the first, second, third, fourth, fifth, sixth, and seventh thin film transistors TT1, TT2, TT3, TT4, TT5, TT6, and TT7 are P-channel metal oxide semiconductor (PMOS) transistors, and the eighth and ninth thin film transistors TT8 and TT9 are N-channel metal oxide semiconductor (NMOS) transistors, it will be understood that in some embodiments, each of the first to ninth thin film transistors TT1 to TT9 may be selectively implemented as a PMOS transistor or an NMOS transistor.

Referring to fig. 4, the pixel circuit 111B may have a so-called 9T-3C structure to separately perform a compensation operation and a data write operation. In detail, the pixel circuit 111B may include a light emitting element EE, a first thin film transistor TT1, a second thin film transistor TT2, a third thin film transistor TT3, a fourth thin film transistor TT4, a fifth thin film transistor TT5, a sixth thin film transistor TT6, a seventh thin film transistor TT7, an eighth thin film transistor TT8, a ninth thin film transistor TT9, a storage capacitor CST, a holding capacitor CHOLD, and a bias capacitor CBIAS. However, the structure of the pixel circuit 111B of fig. 4 may be the same as that of the pixel circuit 111A of fig. 3, except that the bias capacitor CBIAS is directly connected to the gate terminal of the driving transistor (i.e., the first thin film transistor TT 1). In describing the pixel circuit 111B of fig. 4, redundant description corresponding to the pixel circuit 111A of fig. 3 will be omitted.

As shown in fig. 4, the bias capacitor CBIAS may include a first terminal configured to receive the output signal EB output from the scan driver 130 (see fig. 1) for applying the bias voltage, and a second terminal connected to the first pixel node N1. Here, the bias capacitor CBIAS may perform the boosting operation with a bias voltage corresponding to a difference between a high level voltage and a low level voltage of the output signal EB output from the scan driver 130 for applying the bias voltage. Meanwhile, since the bias capacitor CBIAS is directly connected to the first pixel node N1, the voltage of the first pixel node N1 can be directly boosted. Accordingly, the voltage of the first pixel node N1 may be directly boosted by the bias voltage corresponding to the difference between the high level voltage and the low level voltage of the output signal EB output from the scan driver 130 for applying the bias voltage. Here, the scan driver 130 for applying the bias voltage may adjust the bias voltage by changing a high level voltage and/or a low level voltage of the output signal EB.

Meanwhile, although it has been also shown in fig. 4 that the first thin film transistor TT1, the second thin film transistor TT2, the third thin film transistor TT3, the fourth thin film transistor TT4, the fifth thin film transistor TT5, the sixth thin film transistor TT6, and the seventh thin film transistor TT7 are PMOS transistors, and the eighth thin film transistor TT8 and the ninth thin film transistor TT9 are NMOS transistors, it will be understood that each of the first to ninth thin film transistors TT1 to TT9 may be selectively implemented as a PMOS transistor or an NMOS transistor in some embodiments.

Referring to fig. 2, 3, 4, and 5, signals EM, GT, GI, GC, GW and EB applied to the pixel circuits 111A and 111B when the pixel circuits 111A and 111B perform a display scan operation in the display scan period D-SCN have been shown in the figures.

The emission signal EM may include an on-voltage period (i.e., a period corresponding to a low-level voltage in fig. 5) and an off-voltage period (i.e., a period corresponding to a high-level voltage in fig. 5) in the display scan period D-SCN in which the pixel circuits 111A and 111B perform the display scan operation. The sixth thin film transistor TT6 may be turned off in an off-voltage period in which the emission signal EM has a high-level voltage. Meanwhile, the sixth thin film transistor TT6 may be turned on in a turn-on voltage period in which the emission signal EM has a low level voltage.

The connection signal GT may also have a turn-on voltage period (i.e., a period corresponding to a high level voltage in fig. 5) in a previous turn-on voltage period in which the emission signal EM has a low level voltage. In other words, in the previous on-voltage period in which the emission signal EM has a low-level voltage, the eighth thin film transistor TT8 and the ninth thin film transistor TT9 may be turned on, so that the fifth pixel node N5 and the fourth pixel node N4 may be electrically connected to each other, and the first pixel node N1 and the third pixel node N3 may also be electrically connected to each other.

In addition, in the previous on-voltage period in which the emission signal EM has a low-level voltage, the initialization signal GI may have an on-voltage period (i.e., a period corresponding to three low-level voltages in fig. 5), the compensation signal GC may also have an on-voltage period (i.e., a period corresponding to three low-level voltages in fig. 5), and the gate signal GW may also have an on-voltage period (i.e., a period corresponding to one low-level voltage in fig. 5). In other words, when the eighth thin film transistor TT8 and the ninth thin film transistor TT9 are turned on, the initialization operation, the compensation operation, and the data write operation of the pixel circuits 111A and 111B can be sequentially performed. Here, since the compensation operation corresponding to the on-voltage period of the compensation signal GC and the data write operation corresponding to the on-voltage period of the gate signal GW are not simultaneously performed, the compensation operation and the data write operation can be separately performed in the pixel circuits 111A and 111B.

In detail, in a previous on-voltage period in which the emission signal EM has a low-level voltage, when the initialization signal GI is in the on-voltage period (i.e., a period corresponding to three low-level voltages in fig. 5), the fourth thin film transistor TT4 may be turned on so that the initialization voltage VINT may be applied to the first pixel node N1 via the ninth thin film transistor TT9 (at this time, the ninth thin film transistor TT9 has been turned on in response to the connection signal GT). In other words, the first pixel node N1 (i.e., the gate terminal of the first thin film transistor TT1, the first thin film transistor TT1 being a driving transistor) may be initialized by an initialization operation. Meanwhile, although it has been shown in fig. 5 that the pixel circuits 111A and 111B perform three initialization operations, the number of initialization operations is not limited thereto.

Meanwhile, when the next initialization signal GI (n+1) is in the on-voltage period, the seventh thin film transistor TT7 may be turned on so that the reset voltage vant may be applied to the anode of the light emitting element EE. In other words, the anode of the light emitting element EE may be reset (or initialized) by a reset operation. Meanwhile, since it has been shown in fig. 5 that the pixel circuits 111A and 111B perform three initialization operations, three reset operations may also be performed based on the next initialization signal GI (n+1), but the number of reset operations is not limited thereto. As described above, in some embodiments, the display apparatus 100 (see fig. 1) may generate a separate reset signal instead of the next initialization signal GI (n+1) to independently control the reset operation of the pixel circuits 111A and 111B.

In addition, in the previous on-voltage period in which the emission signal EM has a low-level voltage, when the compensation signal GC is in the on-voltage period (i.e., the period corresponding to the three low-level voltages in fig. 5), the fifth thin film transistor TT5 may be turned on so that the reference voltage VREF may be applied to the fourth pixel node N4, and the third thin film transistor TT3 is turned on so that the first thin film transistor TT1 may be diode-connected via the ninth thin film transistor TT9 (at this time, the ninth thin film transistor TT9 has been turned on in response to the connection signal GT). Here, the voltage of the fourth pixel node N4 may be the reference voltage VREF, and the voltage of the first pixel node N1 may be a value (i.e., elvdd+vth) obtained by adding the threshold voltage (Vth) of the first thin film transistor TT1 (at this time, since the first thin film transistor TT1 is a PMOS transistor, the threshold voltage (Vth) of the first thin film transistor TT1 has a negative value) to the first power supply voltage ELVDD.

Further, in the previous on-voltage period in which the emission signal EM has a low-level voltage, when the gate signal GW is in the on-voltage period (i.e., the period corresponding to the low-level voltage in fig. 5), the second thin film transistor TT2 may be turned on so that the data voltage VDATA may be applied to the fourth pixel node N4. Accordingly, the voltage of the first pixel node N1 may be a value (i.e., elvdd+vth+vdata-VREF) obtained by adding a value (i.e., VDATA-VREF) obtained by subtracting the reference voltage VREF from the data voltage VDATA due to the storage capacitor CST to a previous value (i.e., elvdd+vth). Here, the driving current controlled by the first thin film transistor TT1 may be proportional to the equation (Vgs-Vth)/(2) (Vgs is a voltage between the gate and source of the first thin film transistor TT1 at this time). Since the threshold voltage (Vth) of the first thin film transistor TT1 is removed from the above mathematical formula (i.e., the above mathematical formula is changed to (VDATA-VREF)/(2)), the threshold voltage (Vth) of the first thin film transistor TT1 can be compensated. In other words, the driving current controlled by the first thin film transistor TT1 may be determined based on the reference voltage VREF and the data voltage VDATA regardless of the threshold voltage (Vth) of the first thin film transistor TT 1.

Thereafter, in the off-voltage period in which the emission signal EM has a high-level voltage, the connection signal GT may be in the off-voltage period (i.e., a period corresponding to the low-level voltage in fig. 5). In other words, in the off-voltage period in which the emission signal EM has a high-level voltage, the eighth thin film transistor TT8 and the ninth thin film transistor TT9 may be turned off, so that the fifth pixel node N5 and the fourth pixel node N4 may be electrically disconnected from each other, and the first pixel node N1 and the third pixel node N3 may also be electrically disconnected from each other.

In addition, in the off-voltage period in which the emission signal EM has a high-level voltage, each of the initialization signal GI, the compensation signal GC, and the gate signal GW may also be in the off-voltage period (i.e., a period corresponding to the corresponding high-level voltage in fig. 5). In other words, the second thin film transistor TT2, the third thin film transistor TT3, the fourth thin film transistor TT4, the fifth thin film transistor TT5, the sixth thin film transistor TT6, the eighth thin film transistor TT8, and the ninth thin film transistor TT9 may also be all turned off.

In this state, since a predetermined period in which the output signal EB output from the scan driver 130 for applying the bias voltage (see fig. 1) has a low level voltage exists (i.e., the output signal EB output from the scan driver 130 for applying the bias voltage transitions from a high level voltage to a low level voltage and then transitions again to a high level voltage), the bias capacitor CBIAS may directly or indirectly boost the voltage of the gate terminal of the first thin film transistor TT1, which is the driving transistor, by using the bias voltage corresponding to the difference between the high level voltage and the low level voltage of the output signal EB output from the scan driver 130 for applying the bias voltage.

For example, since the bias capacitor CBIAS is connected to the fourth pixel node N4 in the pixel circuit 111A of fig. 3, the voltage of the first pixel node N1 (i.e., the gate terminal of the first thin film transistor TT1 as the driving transistor) may be boosted indirectly (i.e., via the storage capacitor CST) by a bias voltage corresponding to the difference between the high-level voltage and the low-level voltage of the output signal EB output from the scan driver 130 for applying the bias voltage. Meanwhile, since the bias capacitor CBIAS is directly connected to the first pixel node N1 in the pixel circuit 111B of fig. 4, the voltage of the first pixel node N1 (i.e., the gate terminal of the first thin film transistor TT1 as the driving transistor) may be directly boosted by a bias voltage corresponding to the difference between the high-level voltage and the low-level voltage of the output signal EB output from the scan driver 130 for applying the bias voltage.

Next, in the latter on-voltage period in which the emission signal EM has a low-level voltage, the connection signal GT may be in an off-voltage period (i.e., a period corresponding to the low-level voltage in fig. 5), and each of the initialization signal GI, the compensation signal GC, and the gate signal GW may also be in an off-voltage period (i.e., a period corresponding to the corresponding high-level voltage in fig. 5). Accordingly, the first thin film transistor TT1 may be turned on by the voltage stored in the storage capacitor CST to cause the driving current to flow to the light emitting element EE, so that an emission operation of causing the light emitting element EE to emit light corresponding to the driving current may be performed.

Referring to fig. 6, and also to fig. 1 to 4, signals EM, GT, GI, GC, GW and EB applied to the pixel circuits 111A and 111B when the pixel circuits 111A and 111B perform a self-scanning operation in the self-scanning period S-SCN have been shown in the drawings.

Each of the connection signal GT, the initialization signal GI, the compensation signal GC, and the gate signal GW may include only the off-voltage period in the self-scan period S-SCN. In other words, in the self-scan period S-SCN, each of the initialization signal GI, the compensation signal GC, and the gate signal GW may have a high level voltage, and the connection signal GT may have a low level voltage. Meanwhile, the emission signal EM may include both an off-voltage period (i.e., a period corresponding to a high-level voltage) and an on-voltage period (i.e., a period corresponding to a low-level voltage). Accordingly, the pixel circuits 111A and 111B can perform an emission operation in the self-scan period S-SCN without performing a data write operation.

Meanwhile, when the emission signal EM is in the off-voltage period, since a predetermined period in which the output signal EB output from the scan driver 130 for applying the bias voltage has a low level voltage exists (i.e., the output signal EB output from the scan driver 130 for applying the bias voltage is converted from a high level voltage to a low level voltage and then is converted again to a high level voltage), the voltage of the gate terminal of the first thin film transistor TT1 as the driving transistor may be directly or indirectly boosted by the bias voltage corresponding to the difference between the high level voltage and the low level voltage of the output signal EB output from the scan driver 130 for applying the bias voltage. Accordingly, even if the frame rate of the panel driving frame 1F for driving the display panel 110 is changed, the hysteresis characteristic in which the characteristic of the first thin film transistor TT1 as a driving transistor is fixed in a predetermined state can be improved. As a result, according to the display device 100, even if the variable frame rate technique is adopted, a high-quality image can be displayed.

As described above, by changing the high-level voltage and/or the low-level voltage of the output signal EB output from the scan driver 130 for applying the bias voltage, the bias voltage for boosting the voltage of the gate terminal of the first thin film transistor TT1 as the driving transistor can be easily adjusted.

Fig. 7 is a block diagram showing an example of a scan driver for applying a bias voltage included in the display device of fig. 1, fig. 8 is a circuit diagram showing a kth stage included in the scan driver for applying a bias voltage of fig. 7, fig. 9 is a timing chart for describing an operation of the kth stage of fig. 8, and fig. 10 is a diagram for explaining how the scan driver for applying a bias voltage of fig. 7 adjusts a bias voltage.

Referring to fig. 7 to 10, and also referring to fig. 1 to 4, the scan driver 130A for applying a bias voltage may include first to nth STAGEs STAGE (1) to n) (e.g., first, second, third, and nth STAGEs STAGE (3, … …, and n)), the first to nth STAGEs STAGE (1) to n) configured to output first to nth output signals EB (1) to EB (n) (e.g., first, second, third, and nth output signals EB (1, EB (2), … …, and EB (n)) for applying a bias voltage to first to nth pixel rows, respectively, wherein n is an integer of 2 or more.

The scan driver 130A for applying the bias voltage may receive the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3. However, since waveforms of the first, second, and third clock signals CLK1, CLK2, and CLK3 shown in fig. 9 have been provided for illustration purposes, waveforms of the first, second, and third clock signals CLK1, CLK2, and CLK3 applied to the scan driver 130A for applying the bias voltage are not limited thereto. Meanwhile, the first clock signal CLK1 may be selectively switched between the high power voltage VGH and the first low power voltage VGL, the second clock signal CLK2 may be selectively switched between the high power voltage VGH and the first low power voltage VGL, and the third clock signal CLK3 may be selectively switched between the high power voltage VGH and the second low power voltage VGL 2. Here, the second low power supply voltage VGL2 may be changed to adjust the bias voltage VBIAS for boosting the voltage of the gate terminal (i.e., the first pixel node N1) of the first thin film transistor TT1 as the driving transistor in the pixel circuit 111.

Meanwhile, as shown in fig. 7, each of the first to nth STAGEs STAGE (1) to (n) may receive the first and second clock signals CLK1 and CLK2 opposite to the adjacent STAGEs. Thus, when the first clock signal described in the claims is interpreted as the first clock signal CLK1, the second clock signal described in the claims may be interpreted as the second clock signal CLK2, and when the first clock signal described in the claims is interpreted as the second clock signal CLK2, the second clock signal described in the claims may be interpreted as the first clock signal CLK1. However, for convenience of description, in fig. 7 to 10, the first clock signal described in the claims will be described as the first clock signal CLK1, and the second clock signal described in the claims will be described as the second clock signal CLK2.

The kth STAGE (k) may receive the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the input signal IN (k), may provide the kth output signal EB (k) to the pixel circuits 111 included IN the kth pixel row, and may output the kth carry signal CR (k) to the next STAGE (i.e., (k+1) th STAGE). Here, the first STAGE (1) may receive the scan start signal FLM as the input signal IN (k), and the kth STAGE (k) may receive the (k-1) th carry signal output from the previous STAGE (i.e., the (k-1) th STAGE) as the input signal IN (k), where k is an integer of 2 to n.

As described above, the kth STAGE (k) may supply the kth output signal EB (k) to the pixel circuits 111 included in the kth pixel row. Accordingly, the voltage of the gate terminal (i.e., the first pixel node N1) of the first thin film transistor TT1 (which is a driving transistor) of each of the pixel circuits 111 included in the kth pixel row may be boosted by the bias voltage VBIAS corresponding to the difference between the high-level voltage and the low-level voltage of the kth output signal EB (k). Here, the high level voltage of the kth output signal EB (k) may be the high power supply voltage VGH of the third clock signal CLK3, and the low level voltage of the kth output signal EB (k) may be the second low power supply voltage VGL2 of the third clock signal CLK 3.

In detail, as shown in fig. 8, the kth STAGE (k) may include an inputter 210, a stress reducer 220, a bootstrap 230, a carry signal outputter 240, an output signal outputter 245, a holder 250, and a stabilizer 260.

The inputter 210 may transmit the input signal IN (k) to the first node IN1 IN response to the first clock signal CLK 1. IN an embodiment, the input 210 may include a first transistor T1, the first transistor T1 including a first terminal configured to receive the input signal IN (k), a second terminal connected to the first node IN1, and a gate terminal configured to receive the first clock signal CLK 1. Meanwhile, the input signal IN (k) may be the scan start signal FLM or a previous carry signal. IN detail, when the kth STAGE (k) is the first STAGE (1), the input signal IN (k) may be the scan start signal FLM, and when the kth STAGE (k) is not the first STAGE (1), the input signal IN (k) may be the (k-1) th carry signal output from the previous STAGE (i.e., the (k-1) th STAGE).

The stress reducer 220 may be disposed between the first node IN1 and the second node IN2, and may transmit an input signal IN (k) received by the inputter 210 from the first node IN1 to the second node IN2. IN an embodiment, the stress reducer 220 may include an eighth transistor T8, the eighth transistor T8 including a first terminal connected to the first node IN1, a second terminal connected to the second node IN2, and a gate terminal configured to receive the first low supply voltage VGL. When the second node IN2 is bootstrapped such that the voltage V-IN2 of the second node IN2 may have the second low level voltage 2L, the stress reducer 220 may not transmit the voltage V-IN2 of the second node IN2 having the second low level voltage 2L to the first node IN1, so that voltage stress applied to the transistors (i.e., the first transistor T1, the third transistor T3, and the fourth transistor T4) connected to the first node IN1 may be reduced.

The bootstrap 230 may be disposed between the second node IN2 and the first output node ON 1. The bootstrap 230 may bootstrap the second node IN2 to change the voltage V-IN2 of the second node IN2 from the first low level voltage L to a second low level voltage 2L lower than the first low level voltage L. For example, as shown in fig. 9, the first low level voltage L may be a first low power supply voltage VGL, and the second low level voltage 2L may be a voltage lower than the first low power supply voltage VGL (e.g., a value having a large absolute value when the first low power supply voltage VGL has a negative value). Here, the difference between the first low level voltage L and the second low level voltage 2L may correspond to the difference between the high power supply voltage VGH and the first low power supply voltage VGL, but is not limited thereto. IN an embodiment, the bootstrap 230 may include a second capacitor C2, the second capacitor C2 including a first terminal connected to the second node IN2 and a second terminal connected to the first output node ON 1.

The carry signal outputter 240 may receive the high power supply voltage VGH and the second clock signal CLK2, and may output the second clock signal CLK2 as the kth carry signal CR (k) via the first output node ON1 IN response to the voltage V-IN2 of the second node IN2 (e.g., IN response to the voltage V-IN2 of the second node IN2 having the second low level voltage 2L when the second node IN2 is bootstrapped). IN an embodiment, the carry signal outputter 240 may include a ninth transistor T9 and a tenth transistor T10, the ninth transistor T9 including a first terminal configured to receive the high power supply voltage VGH, a second terminal connected to the first output node ON1, and a gate terminal connected to the third node IN3, and the tenth transistor T10 including a first terminal connected to the first output node ON1, a second terminal configured to receive the second clock signal CLK2, and a gate terminal connected to the second node IN 2. As described above, since the second clock signal CLK2 switches between the high power voltage VGH and the first low power voltage VGL, the kth carry signal CR (k) may have the high power voltage VGH or the first low power voltage VGL.

The output signal outputter 245 may receive the high power supply voltage VGH and the third clock signal CLK3, and may output the third clock signal CLK3 as a kth output signal EB (k) via the second output node ON2 IN response to the voltage V-IN2 of the second node IN2 (e.g., IN response to the voltage V-IN2 of the second node IN2 having the second low level voltage 2L when the second node IN2 is bootstrapped). IN an embodiment, the output signal outputter 245 may include a sixth transistor T6 and a seventh transistor T7, the sixth transistor T6 including a first terminal configured to receive the high power supply voltage VGH, a second terminal connected to the second output node ON2, and a gate terminal connected to the third node IN3, and the seventh transistor T7 including a first terminal connected to the second output node ON2, a second terminal configured to receive the third clock signal CLK3, and a gate terminal connected to the second node IN 2. As described above, since the third clock signal CLK3 switches between the high power supply voltage VGH and the second low power supply voltage VGL2, the kth output signal EB (k) may have the high power supply voltage VGH or the second low power supply voltage VGL2.

Here, since the high power supply voltage VGH is commonly used in the carry signal outputter 240 and the output signal outputter 245, the high power supply voltage VGH may be fixed. Meanwhile, since the second low power supply voltage VGL2 is used only in the output signal follower 245, the second low power supply voltage VGL2 may be changed (i.e., indicated by "adjustable" in fig. 10) when it is necessary to adjust the bias voltage VBIAS for directly or indirectly boosting the voltage of the gate terminal of the driving transistor in the pixel circuit 111. In addition, since the high level voltage (i.e., the high power supply voltage VGH) of the third clock signal CLK3 applied to the output signal outputter 245 and the high power supply voltage VGH applied to the output signal outputter 245 are the same, distortion may not occur in the high level voltage of the kth output signal EB (k). Meanwhile, as shown in fig. 10, since the bias voltage VBIAS for directly or indirectly boosting the voltage of the gate terminal of the driving transistor in the pixel circuit 111 corresponds to the difference between the high-level voltage (i.e., the high power supply voltage VGH) and the low-level voltage (i.e., the second low power supply voltage VGL 2) of the kth output signal EB (k), the scan driver 130A for applying the bias voltage may change the low-level voltage (i.e., the second low power supply voltage VGL 2) of the kth output signal EB (k) in order to easily adjust the bias voltage VBIAS for directly or indirectly boosting the voltage of the gate terminal of the driving transistor in the pixel circuit 111.

The keeper 250 may transmit the first clock signal CLK1 to the third node IN3 IN response to the voltage V-IN1 of the first node IN1. IN an embodiment, the keeper 250 may include a fourth transistor T4, the fourth transistor T4 including a first terminal connected to the third node IN3, a second terminal configured to receive the first clock signal CLK1, and a gate terminal connected to the first node IN1. As described above, since the second clock signal CLK2 switches between the high power supply voltage VGH and the first low power supply voltage VGL, the holder 250 may hold the third node IN3 at the high level voltage H (e.g., the high power supply voltage VGH) when the kth output signal EB (k) and the kth carry signal CR (k) are output.

The stabilizer 260 may apply the first low power supply voltage VGL to the third node IN3 IN response to the first clock signal CLK1, and may apply the high power supply voltage VGH to the first node IN1 IN response to the second clock signal CLK 2. IN an embodiment, the stabilizer 260 may include a second transistor T2, a third transistor T3, a first capacitor C1, and a fifth transistor T5, the second transistor T2 including a first terminal configured to receive the high power supply voltage VGH, a second terminal connected to the first terminal of the third transistor T3, and a gate terminal connected to the third node IN3, the third transistor T3 including a first terminal connected to the second terminal of the second transistor T2, a second terminal connected to the first node IN1, and a gate terminal configured to receive the second clock signal CLK2, the first capacitor C1 including a first terminal configured to receive the high power supply voltage VGH and a second terminal connected to the third node IN3, and the fifth transistor T5 including a first terminal connected to the third node IN3, a second terminal configured to receive the first low power supply voltage VGL, and a gate terminal configured to receive the first clock signal CLK 1.

Hereinafter, an operation of the kth STAGE (k) included in the scan driver 130A for applying the bias voltage will be described with reference to fig. 8 and 9. However, as shown in fig. 8 and 9, in the following description, it will be assumed that all the transistors T1 to T10 are PMOS transistors, the first low-level voltage L corresponds to the first low-power supply voltage VGL, the second low-level voltage 2L corresponds to a voltage lower than the first low-power supply voltage VGL, and the high-level voltage H corresponds to the high-power supply voltage VGH.

The kth STAGE (k) may receive the input signal IN (k), the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3.

IN a period from the first time point TP1 to the second time point TP2, the input signal IN (k) having the first low power supply voltage VGL may be applied, and the first clock signal CLK1 having the first low power supply voltage VGL may be applied. The first transistor T1 may transmit the input signal IN (k) to the first node IN1 IN response to the first clock signal CLK1 having the first low power supply voltage VGL, and the voltage V-IN1 of the first node IN1 may be changed from the high level voltage H corresponding to the high power supply voltage VGH to the first low level voltage L corresponding to the first low power supply voltage VGL. IN addition, the eighth transistor T8 may transmit the input signal IN (k) from the first node IN1 to the second node IN2 IN response to the first low power supply voltage VGL, so that the voltage V-IN2 of the second node IN2 may be changed from the high level voltage H corresponding to the high power supply voltage VGH to the first low level voltage L corresponding to the first low power supply voltage VGL.

The first clock signal CLK1 may be changed from the first low power supply voltage VGL to the high power supply voltage VGH at the second time point TP2, and the first clock signal CLK1 having the high power supply voltage VGH may be applied in a period from the second time point TP2 to the third time point TP 3. The fourth transistor T4 transmits the first clock signal CLK1 having the high power supply voltage VGH to the third node IN3 IN response to the voltage V-IN1 of the first node IN1 having the first low power supply voltage L, so that the voltage V-IN3 of the third node IN3 may be changed from the first low level voltage L corresponding to the first low power supply voltage VGL to the high level voltage H corresponding to the high power supply voltage VGH.

The second clock signal CLK2 may be changed from the high power supply voltage VGH to the first low power supply voltage VGL at the third time point TP3, and the second clock signal CLK2 having the first low power supply voltage VGL may be applied in a period from the third time point TP3 to the fourth time point TP 4. The tenth transistor T10 may transmit the second clock signal CLK2 having the first low power supply voltage VGL to the first output node ON1 IN response to the voltage V-IN2 of the second node IN2, so that the second clock signal CLK2 having the first low power supply voltage VGL may be output as the kth carry signal CR (k) from the first output node ON 1.

Meanwhile, when the voltage of the first output node ON1 (i.e., the voltage of the second terminal of the second capacitor C2) is changed from the high power supply voltage VGH to the first low power supply voltage VGL, the voltage V-IN2 of the second node IN2 (i.e., the voltage of the first terminal of the second capacitor C2) may be changed from the first low level voltage L corresponding to the first low power supply voltage VGL to the second low level voltage 2L lower than the first low power supply voltage VGL. In the embodiment, the difference between the first low level voltage L and the second low level voltage 2L may correspond to the difference between the high power supply voltage VGH and the first low power supply voltage VGL, but is not limited thereto. Meanwhile, the operation of changing the voltage V-IN2 of the second node IN2 from the first low level voltage L to the second low level voltage 2L may be referred to as a bootstrap operation, and the second capacitor C2 may be referred to as a bootstrap capacitor. IN addition, the eighth transistor T8 may not transmit the voltage V-IN2 of the second node IN2 having the second low level voltage 2L to the first node IN1, so that voltage stress applied to the transistors (i.e., the first transistor T1, the third transistor T3, and the fourth transistor T4) connected to the first node IN1 may be reduced. Accordingly, the eighth transistor T8 may be referred to as a stress relieving transistor.

In addition, the third clock signal CLK3 may be changed from the high power supply voltage VGH to the second low power supply voltage VGL2 at the third time point TP3, and the third clock signal CLK3 having the second low power supply voltage VGL2 may be applied in a period from the third time point TP3 to the fourth time point TP 4. The seventh transistor T7 may transmit the third clock signal CLK3 having the second low power supply voltage VGL2 to the second output node ON2 IN response to the voltage V-IN2 of the second node IN2, so that the third clock signal CLK3 having the second low power supply voltage VGL2 may be output from the second output node ON2 as the kth output signal EB (k).

Meanwhile, when the kth output signal EB (k) and the kth carry signal CR (k) are output, the fourth transistor T4 including the gate terminal configured to receive the voltage V-IN1 of the first node IN1 having the first low level voltage L may be turned on, so that the first clock signal CLK1 having the high power supply voltage VGH may be applied to the third node IN3. Accordingly, the voltage V-IN3 of the third node IN3 may be maintained at the high level voltage H corresponding to the high power supply voltage VGH. IN addition, since the voltage V-IN3 of the third node IN3 has the high level voltage H when the kth output signal EB (k) and the kth carry signal CR (k) are output, the sixth transistor T6 and the ninth transistor T9 including the gate terminal configured to receive the voltage V-IN3 of the third node IN3 may be turned off.

When the second clock signal CLK2 changes from the first low power voltage VGL to the high power voltage VGH at the fourth time point TP4, the kth carry signal CR (k) output from the first output node ON1 may change from the first low power voltage VGL to the high power voltage VGH. Here, when the voltage of the first output node ON1 (i.e., the voltage of the second terminal of the second capacitor C2) is changed from the first low power supply voltage VGL to the high power supply voltage VGH, the voltage of the first terminal of the second capacitor C2 (i.e., the voltage V-IN2 of the second node IN 2) may be changed from the second low level voltage 2L corresponding to a voltage lower than the first low power supply voltage VGL to the first low level voltage L corresponding to the first low power supply voltage VGL.

In addition, when the third clock signal CLK3 changes from the second low power supply voltage VGL2 to the high power supply voltage VGH at the fourth time point TP4, the kth output signal EB (k) output from the second output node ON2 may also change from the second low power supply voltage VGL2 to the high power supply voltage VGH.

The first clock signal CLK1 may be changed from the high power supply voltage VGH to the first low power supply voltage VGL at the fifth time point TP5, and the first clock signal CLK1 having the first low power supply voltage VGL may be applied in a period from the fifth time point TP5 to the sixth time point TP 6. Accordingly, the first transistor T1 may change the voltage V-IN1 of the first node IN1 from the first low level voltage L to the high level voltage H IN response to the first clock signal CLK1 having the first low power supply voltage VGL (i.e., because the input signal IN (k) has the high power supply voltage VGH), and the eighth transistor T8 may change the voltage V-IN2 of the second node IN2 from the first low level voltage L to the high level voltage H IN response to the first low power supply voltage VGL. IN addition, the fifth transistor T5 may change the voltage V-IN3 of the third node IN3 from the high level voltage H to the first low level voltage L corresponding to the first low power supply voltage VGL IN response to the first clock signal CLK1 having the first low power supply voltage VGL. Meanwhile, the fifth transistor T5 may be turned on every time the first clock signal CLK1 has the first low power voltage VGL so as to apply the first low power voltage VGL to the third node IN3. The ninth transistor T9 may apply the high power supply voltage VGH to the first output node ON1 IN response to the voltage V-IN3 of the third node IN3 having the first low level voltage L, and the sixth transistor T6 may apply the high power supply voltage VGH to the second output node ON2 IN response to the voltage V-IN3 of the third node IN3 having the first low level voltage L.

The first clock signal CLK1 may be changed from the first low power supply voltage VGL to the high power supply voltage VGH at the sixth time point TP6, and the first clock signal CLK1 having the high power supply voltage VGH may be applied in a period from the sixth time point TP6 to the seventh time point TP 7.

The second clock signal CLK2 may be changed from the high power supply voltage VGH to the first low power supply voltage VGL at the seventh time point TP7, and the second clock signal CLK2 having the first low power supply voltage VGL may be applied in a period from the seventh time point TP7 to the eighth time point TP 8. The second transistor T2 may be turned on IN response to the voltage V-IN3 of the third node IN3 having the first low level voltage L, and the third transistor T3 may be turned on IN response to the second clock signal CLK2 having the first low level voltage L such that the high power supply voltage VGH may be applied to the first node IN1 through the second transistor T2 and the third transistor T3 so as to stabilize the voltage V-IN1 of the first node IN1 to the high level voltage H corresponding to the high power supply voltage VGH. IN addition, the eighth transistor T8 may be turned on IN response to the first low power supply voltage VGL such that the voltage V-IN2 of the second node IN2 may also be stabilized to a high level voltage H corresponding to the high power supply voltage VGH. Meanwhile, the third transistor T3 may be turned on every time the second clock signal CLK2 has the first low power supply voltage VGL so as to apply the high power supply voltage VGH to the first node IN1 and the second node IN2.

As described above, the kth STAGE (k) may include: an input 210 configured to transmit an input signal IN (k) to a first node IN1 IN response to a first clock signal CLK1, a stress reducer 220 disposed between the first node IN1 and a second node IN2, a keeper 250 configured to receive a high power supply voltage VGH and a second clock signal CLK2 and to output the second clock signal CLK2 as a kth carry signal CR (k) via the first output node ON1, an output signal output 245 configured to receive the high power supply voltage VGH and a third clock signal CLK3 and to output the third clock signal CLK3 as a kth output signal EB (k) via the second output node ON2 IN response to the voltage V-IN2 of the second node IN2, a keeper 250 configured to transmit the first clock signal VGH and the second clock signal CLK2 to the third node IN3 IN response to the voltage V-IN1 of the first node IN1, and to apply the first low power supply voltage VGL to the third node IN3 as a kth carry signal CR (k) via the first output node ON1 IN response to the second output node IN2, and to stabilize the first clock signal CLK 1.

Here, since each of the first and second clock signals CLK1 and CLK2 is switched between the high and first low power voltages VGH and VGL, and the third clock signal CLK3 is switched between the high and variable second low power voltages VGL2, the scan driver 130A for applying the bias voltage can easily adjust the bias voltage VBIAS for directly or indirectly boosting the voltage of the gate terminal of the driving transistor in the pixel circuit 111 by changing the second low power voltage VGL2 of the third clock signal CLK 3. As a result, according to the display apparatus 100 including the scan driver 130A for applying the bias voltage, even if the frame rate of the panel driving frame 1F for driving the display panel 110 is changed (i.e., the driving frequency of the display panel 110 is changed), the hysteresis characteristic in which the characteristic of the driving transistor is fixed in a predetermined state can be improved.

Fig. 11 is a block diagram showing another example of the scan driver for applying the bias voltage included in the display device of fig. 1, fig. 12 is a circuit diagram showing a kth stage included in the scan driver for applying the bias voltage of fig. 11, fig. 13 is a timing chart for describing an operation of the kth stage of fig. 12, and fig. 14 is a diagram for explaining how the scan driver for applying the bias voltage of fig. 11 adjusts the bias voltage.

Referring to fig. 11 to 14, and also referring to fig. 1 to 4, the scan driver 130B for applying a bias voltage may include first to nth STAGEs STAGE (1) to n) (e.g., first, second, third, and nth STAGEs STAGE (3, … …, and n)), the first to nth STAGEs STAGE (1) to n) configured to output first to nth output signals EB (1) to EB (n) (e.g., first, second, third, and nth output signals EB (1, EB (2), … …, and EB (n)) for applying a bias voltage to first to nth pixel rows, respectively, wherein n is an integer of 2 or more.

The scan driver 130B for applying the bias voltage may receive the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3. However, since waveforms of the first, second, and third clock signals CLK1, CLK2, and CLK3 shown in fig. 13 have been provided for illustration purposes, waveforms of the first, second, and third clock signals CLK1, CLK2, and CLK3 applied to the scan driver 130B for applying the bias voltage are not limited thereto. Meanwhile, the first clock signal CLK1 may be selectively switched between the first high power voltage VGH and the first low power voltage VGL, the second clock signal CLK2 may be selectively switched between the first high power voltage VGH and the first low power voltage VGL, and the third clock signal CLK3 may be selectively switched between the second high power voltage VGH2 and the second low power voltage VGL 2. Here, the second high power supply voltage VGH2 and the second low power supply voltage VGL2 may be changed (for example, at least one of the second high power supply voltage VGH2 and the second low power supply voltage VGL2 may be changed, or the second high power supply voltage VGH2 and the second low power supply voltage VGL2 may be changed simultaneously) to adjust the bias voltage VBIAS for boosting the voltage of the gate terminal (i.e., the first pixel node N1) of the first thin film transistor TT1 as the driving transistor in the pixel circuit 111.

Meanwhile, as shown in fig. 11, each of the first to nth STAGEs STAGE (1) to (n) may receive the first and second clock signals CLK1 and CLK2 opposite to the adjacent STAGEs. Thus, when the first clock signal described in the claims is interpreted as the first clock signal CLK1, the second clock signal described in the claims may be interpreted as the second clock signal CLK2, and when the first clock signal described in the claims is interpreted as the second clock signal CLK2, the second clock signal described in the claims may be interpreted as the first clock signal CLK1. However, for convenience of description, in fig. 11 to 14, the first clock signal described in the claims will be described as the first clock signal CLK1, and the second clock signal described in the claims will be described as the second clock signal CLK2.

As described above, the kth STAGE (k) may supply the kth output signal EB (k) to the pixel circuits 111 included in the kth pixel row. Accordingly, the voltage of the gate terminal (i.e., the first pixel node N1) of the first thin film transistor TT1 (i.e., the driving transistor) of each of the pixel circuits 111 included in the kth pixel row may be boosted by the bias voltage VBIAS corresponding to the difference between the high-level voltage and the low-level voltage of the kth output signal EB (k). Here, the high level voltage of the kth output signal EB (k) may be the second high supply voltage VGH2 of the third clock signal CLK3, and the low level voltage of the kth output signal EB (k) may be the second low supply voltage VGL2 of the third clock signal CLK 3.

In detail, as shown in fig. 12, the kth STAGE (k) may include an inputter 210, a stress reducer 220, a bootstrap 230, a carry signal outputter 240, an output signal outputter 245, a holder 250, and a stabilizer 260.

The bootstrap 230 may be disposed between the second node IN2 and the first output node ON 1. The bootstrap 230 may bootstrap the second node IN2 to change the voltage V-IN2 of the second node IN2 from the first low level voltage L to a second low level voltage 2L lower than the first low level voltage L. For example, as shown in fig. 13, the first low level voltage L may be a first low power supply voltage VGL, and the second low level voltage 2L may be a voltage lower than the first low power supply voltage VGL (e.g., a value having a large absolute value when the first low power supply voltage VGL has a negative value). Here, the difference between the first low level voltage L and the second low level voltage 2L may correspond to the difference between the first high power supply voltage VGH and the first low power supply voltage VGL, but is not limited thereto. IN an embodiment, the bootstrap 230 may include a second capacitor C2, the second capacitor C2 including a first terminal connected to the second node IN2 and a second terminal connected to the first output node ON 1.

The carry signal outputter 240 may receive the first high power supply voltage VGH and the second clock signal CLK2, and may output the second clock signal CLK2 as the kth carry signal CR (k) via the first output node ON1 IN response to the voltage V-IN2 of the second node IN2 (e.g., IN response to the voltage V-IN2 of the second node IN2 bootstrapped to have the second low level voltage 2L). IN an embodiment, the carry signal outputter 240 may include a ninth transistor T9 and a tenth transistor T10, the ninth transistor T9 including a first terminal configured to receive the first high power supply voltage VGH, a second terminal connected to the first output node ON1, and a gate terminal connected to the third node IN3, and the tenth transistor T10 including a first terminal connected to the first output node ON1, a second terminal configured to receive the second clock signal CLK2, and a gate terminal connected to the second node IN 2. As described above, since the second clock signal CLK2 switches between the first high power voltage VGH and the first low power voltage VGL, the kth carry signal CR (k) may have the first high power voltage VGH or the first low power voltage VGL.

The output signal outputter 245 may receive the second high power supply voltage VGH2 and the third clock signal CLK3, and may output the third clock signal CLK3 as the kth output signal EB (k) via the second output node ON2 IN response to the voltage V-IN2 of the second node IN2 (e.g., IN response to the voltage V-IN2 of the second node IN2 bootstrapped to have the second low level voltage 2L). IN an embodiment, the output signal outputter 245 may include a sixth transistor T6 and a seventh transistor T7, the sixth transistor T6 including a first terminal configured to receive the second high power supply voltage VGH2, a second terminal connected to the second output node ON2, and a gate terminal connected to the third node IN3, and the seventh transistor T7 including a first terminal connected to the second output node ON2, a second terminal configured to receive the third clock signal CLK3, and a gate terminal connected to the second node IN 2. As described above, since the third clock signal CLK3 switches between the second high power supply voltage VGH2 and the second low power supply voltage VGL2, the kth output signal EB (k) may have the second high power supply voltage VGH2 or the second low power supply voltage VGL2.

Here, since the first high power voltage VGH and the first low power voltage VGL are used in the carry signal outputter 240, the first high power voltage VGH may be fixed. Meanwhile, since the second high power supply voltage VGH2 and the second low power supply voltage VGL2 are used in the output signal outputter 245, the second low power supply voltage VGL2 may be changed (i.e., indicated by "adjustable" in fig. 14) when it is necessary to adjust the bias voltage VBIAS for directly or indirectly boosting the voltage of the gate terminal of the driving transistor in the pixel circuit 111. In addition, since the high level voltage (i.e., the second high power supply voltage VGH 2) of the third clock signal CLK3 applied to the output signal outputter 245 and the second high power supply voltage VGH2 applied to the output signal outputter 245 are the same, distortion may not occur in the high level voltage of the kth output signal EB (k). Meanwhile, as shown in fig. 14, since the bias voltage VBIAS for directly or indirectly boosting the voltage of the gate terminal of the driving transistor in the pixel circuit 111 corresponds to the difference between the high-level voltage (i.e., the second high power supply voltage VGH 2) and the low-level voltage (i.e., the second low power supply voltage VGL 2) of the k-th output signal EB (k), the scan driver 130B for applying the bias voltage may change the high-level voltage (i.e., the second high power supply voltage VGH 2) of the k-th output signal EB (k) and/or the low-level voltage (i.e., the second low power supply voltage VGL 2) of the k-th output signal EB (k) in order to easily adjust the bias voltage VBIAS for directly or indirectly boosting the voltage of the gate terminal of the driving transistor in the pixel circuit 111.

The keeper 250 may transmit the first clock signal CLK1 to the third node IN3 IN response to the voltage V-IN1 of the first node IN1. IN an embodiment, the keeper 250 may include a fourth transistor T4, the fourth transistor T4 including a first terminal connected to the third node IN3, a second terminal configured to receive the first clock signal CLK1, and a gate terminal connected to the first node IN1. As described above, since the second clock signal CLK2 switches between the first high power supply voltage VGH and the first low power supply voltage VGL, the holder 250 may hold the third node IN3 at the high level voltage H (e.g., the first high power supply voltage VGH) when the kth output signal EB (k) and the kth carry signal CR (k) are output.

The stabilizer 260 may apply the first low power supply voltage VGL to the third node IN3 IN response to the first clock signal CLK1, and may apply the first high power supply voltage VGH to the first node IN1 IN response to the second clock signal CLK 2. IN an embodiment, the stabilizer 260 may include a second transistor T2, a third transistor T3, a first capacitor C1, and a fifth transistor T5, the second transistor T2 including a first terminal configured to receive the first high power supply voltage VGH, a second terminal connected to the first terminal of the third transistor T3, and a gate terminal connected to the third node IN3, the third transistor T3 including a first terminal connected to the second terminal of the second transistor T2, a second terminal connected to the first node IN1, and a gate terminal configured to receive the second clock signal CLK2, the first capacitor C1 including a first terminal configured to receive the first high power supply voltage VGH and a second terminal connected to the third node IN3, and the fifth transistor T5 including a first terminal connected to the third node IN3, a second terminal configured to receive the first low power supply voltage VGL, and a gate terminal configured to receive the first clock signal CLK 1.

Hereinafter, an operation of the kth STAGE (k) included in the scan driver 130B for applying the bias voltage will be described with reference to fig. 12 and 13. However, as shown in fig. 12 and 13, in the following description, it will be assumed that all the transistors T1 to T10 are PMOS transistors, the first low-level voltage L corresponds to the first low-power supply voltage VGL, the second low-level voltage 2L corresponds to a voltage lower than the first low-power supply voltage VGL, and the high-level voltage H corresponds to the first high-power supply voltage VGH.

IN a period from the first time point TP1 to the second time point TP2, the input signal IN (k) having the first low power supply voltage VGL may be applied, and the first clock signal CLK1 having the first low power supply voltage VGL may be applied. The first transistor T1 may transmit the input signal IN (k) to the first node IN1 IN response to the first clock signal CLK1 having the first low power supply voltage VGL, and the voltage V-IN1 of the first node IN1 may be changed from the high level voltage H corresponding to the first high power supply voltage VGH to the first low level voltage L corresponding to the first low power supply voltage VGL. IN addition, the eighth transistor T8 may transmit the input signal IN (k) from the first node IN1 to the second node IN2 IN response to the first low power supply voltage VGL, so that the voltage V-IN2 of the second node IN2 may be changed from the high level voltage H corresponding to the first high power supply voltage VGH to the first low level voltage L corresponding to the first low power supply voltage VGL.

The first clock signal CLK1 may be changed from the first low power supply voltage VGL to the first high power supply voltage VGH at the second time point TP2, and the first clock signal CLK1 having the first high power supply voltage VGH may be applied in a period from the second time point TP2 to the third time point TP 3. The fourth transistor T4 transmits the first clock signal CLK1 having the first high power supply voltage VGH to the third node IN3 IN response to the voltage V-IN1 of the first node IN1 having the first low power supply voltage L, so that the voltage V-IN3 of the third node IN3 may be changed from the first low power supply voltage L corresponding to the first low power supply voltage VGL to the high power supply voltage H corresponding to the first high power supply voltage VGH.

The second clock signal CLK2 may be changed from the first high power voltage VGH to the first low power voltage VGL at the third time point TP3, and the second clock signal CLK2 having the first low power voltage VGL may be applied in a period from the third time point TP3 to the fourth time point TP 4. The tenth transistor T10 may transmit the second clock signal CLK2 having the first low power supply voltage VGL to the first output node ON1 IN response to the voltage V-IN2 of the second node IN2, so that the second clock signal CLK2 having the first low power supply voltage VGL may be output as the kth carry signal CR (k) from the first output node ON 1.

Meanwhile, when the voltage of the first output node ON1 (i.e., the voltage of the second terminal of the second capacitor C2) is changed from the first high power supply voltage VGH to the first low power supply voltage VGL, the voltage V-IN2 of the second node IN2 (i.e., the voltage of the first terminal of the second capacitor C2) may be changed from the first low level voltage L corresponding to the first low power supply voltage VGL to the second low level voltage 2L lower than the first low power supply voltage VGL. In an embodiment, a difference between the first low level voltage L and the second low level voltage 2L may correspond to a difference between the first high power supply voltage VGH and the first low power supply voltage VGL, but is not limited thereto. Meanwhile, the operation of changing the voltage V-IN2 of the second node IN2 from the first low level voltage L to the second low level voltage 2L may be referred to as a bootstrap operation, and the second capacitor C2 may be referred to as a bootstrap capacitor. IN addition, the eighth transistor T8 may not transmit the voltage V-IN2 of the second node IN2 having the second low level voltage 2L to the first node IN1, so that voltage stress applied to the transistors (i.e., the first transistor T1, the third transistor T3, and the fourth transistor T4) connected to the first node IN1 may be reduced. Accordingly, the eighth transistor T8 may be referred to as a stress relieving transistor.

In addition, the third clock signal CLK3 may be changed from the second high power supply voltage VGH2 to the second low power supply voltage VGL2 at the third time point TP3, and the third clock signal CLK3 having the second low power supply voltage VGL2 may be applied in a period from the third time point TP3 to the fourth time point TP 4. The seventh transistor T7 may transmit the third clock signal CLK3 having the second low power supply voltage VGL2 to the second output node ON2 IN response to the voltage V-IN2 of the second node IN2, so that the third clock signal CLK3 having the second low power supply voltage VGL2 may be output from the second output node ON2 as the kth output signal EB (k).

Meanwhile, when the kth output signal EB (k) and the kth carry signal CR (k) are output, the fourth transistor T4 including the gate terminal configured to receive the voltage V-IN1 of the first node IN1 having the first low level voltage L may be turned on, so that the first clock signal CLK1 having the first high power supply voltage VGH may be applied to the third node IN3. Accordingly, the voltage V-IN3 of the third node IN3 may be maintained at the high level voltage H corresponding to the first high power supply voltage VGH. IN addition, since the voltage V-IN3 of the third node IN3 has the high level voltage H when the kth output signal EB (k) and the kth carry signal CR (k) are output, the sixth transistor T6 and the ninth transistor T9 including the gate terminal configured to receive the voltage V-IN3 of the third node IN3 may be turned off.

When the second clock signal CLK2 changes from the first low power voltage VGL to the first high power voltage VGH at the fourth time point TP4, the kth carry signal CR (k) output from the first output node ON1 may change from the first low power voltage VGL to the first high power voltage VGH. Here, when the voltage of the first output node ON1 (i.e., the voltage of the second terminal of the second capacitor C2) is changed from the first low power supply voltage VGL to the first high power supply voltage VGH, the voltage of the first terminal of the second capacitor C2 (i.e., the voltage V-IN2 of the second node IN 2) may be changed from the second low level voltage 2L corresponding to a voltage lower than the first low power supply voltage VGL to the first low level voltage L corresponding to the first low power supply voltage VGL.

In addition, when the third clock signal CLK3 changes from the second low power supply voltage VGL2 to the second high power supply voltage VGH2 at the fourth time point TP4, the kth output signal EB (k) output from the second output node ON2 may also change from the second low power supply voltage VGL2 to the second high power supply voltage VGH2.

The first clock signal CLK1 may be changed from the first high power supply voltage VGH to the first low power supply voltage VGL at the fifth time point TP5, and the first clock signal CLK1 having the first low power supply voltage VGL may be applied in a period from the fifth time point TP5 to the sixth time point TP 6. Accordingly, the first transistor T1 may change the voltage V-IN1 of the first node IN1 from the first low level voltage L to the high level voltage H IN response to the first clock signal CLK1 having the first low power supply voltage VGL (i.e., because the input signal IN (k) has the first high power supply voltage VGH), and the eighth transistor T8 may change the voltage V-IN2 of the second node IN2 from the first low level voltage L to the high level voltage H IN response to the first low power supply voltage VGL. IN addition, the fifth transistor T5 may change the voltage V-IN3 of the third node IN3 from the high level voltage H to the first low level voltage L corresponding to the first low power supply voltage VGL IN response to the first clock signal CLK1 having the first low power supply voltage VGL. Meanwhile, the fifth transistor T5 may be turned on every time the first clock signal CLK1 has the first low power voltage VGL so as to apply the first low power voltage VGL to the third node IN3. The ninth transistor T9 may apply the first high power supply voltage VGH to the first output node ON1 IN response to the voltage V-IN3 of the third node IN3 having the first low level voltage L, and the sixth transistor T6 may apply the second high power supply voltage VGH2 to the second output node ON2 IN response to the voltage V-IN3 of the third node IN3 having the first low level voltage L.

The first clock signal CLK1 may be changed from the first low power supply voltage VGL to the first high power supply voltage VGH at the sixth time point TP6, and the first clock signal CLK1 having the first high power supply voltage VGH may be applied in a period from the sixth time point TP6 to the seventh time point TP 7.

The second clock signal CLK2 may be changed from the first high power supply voltage VGH to the first low power supply voltage VGL at the seventh time point TP7, and the second clock signal CLK2 having the first low power supply voltage VGL may be applied in a period from the seventh time point TP7 to the eighth time point TP 8. The second transistor T2 may be turned on IN response to the voltage V-IN3 of the third node IN3 having the first low level voltage L, and the third transistor T3 may be turned on IN response to the second clock signal CLK2 having the first low level voltage L such that the first high power supply voltage VGH may be applied to the first node IN1 through the second transistor T2 and the third transistor T3 so as to stabilize the voltage V-IN1 of the first node IN1 to the high level voltage H corresponding to the first high power supply voltage VGH. IN addition, the eighth transistor T8 may be turned on IN response to the first low power supply voltage VGL such that the voltage V-IN2 of the second node IN2 may also be stabilized to a high level voltage H corresponding to the first high power supply voltage VGH. Meanwhile, the third transistor T3 may be turned on whenever the second clock signal CLK2 has the first low power supply voltage VGL so as to apply the first high power supply voltage VGH to the first node IN1 and the second node IN2.

As described above, the kth STAGE (k) may include: an input 210 configured to transmit an input signal IN (k) to a first node IN1 IN response to a first clock signal CLK1, an output signal output 245 disposed between the first node IN1 and a second node IN2, a keeper 250 configured to receive a first high power supply voltage VGH and a second clock signal CLK2 and to output the second clock signal CLK2 as a kth carry signal CR (k) via a first output node ON1, and to output the second high power supply voltage VGH2 and a third clock signal CLK3 and to output the third clock signal CLK3 as a kth output signal EB (k) via a second output node ON2 IN response to the voltage V-IN2 of the second node IN1, a keeper 250 configured to transmit the first clock signal CLK1 to the third node IN3 IN response to the voltage V-IN1 of the first node IN1, and to apply the first low power supply voltage VGL to the first node VGH2 as a kth carry signal CR (k) via the first output node ON1, and to apply the first high power supply voltage VGH2 to the first node 260 IN response to the first clock signal IN response to the first output node IN 2.

Here, since each of the first and second clock signals CLK1 and CLK2 is switched between the first high and low power voltages VGH and VGL and the third clock signal CLK3 is switched between the variable second high and low power voltages VGH2 and VGL2, the scan driver 130B for applying the bias voltage may easily adjust the bias voltage VBIAS for directly or indirectly boosting the voltage of the gate terminal of the driving transistor in the pixel circuit 111 by changing the second high and low power voltages VGH2 and VGL2 of the third clock signal CLK 3. As a result, according to the display apparatus 100 including the scan driver 130B for applying the bias voltage, even if the frame rate of the panel driving frame 1F for driving the display panel 110 is changed (i.e., the driving frequency of the display panel 110 is changed), the hysteresis characteristic in which the characteristic of the driving transistor is fixed in a predetermined state can be improved.

Referring to fig. 15, an electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input/output (I/O) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be the display device 100 of fig. 1. In addition, the electronic device 1000 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal Serial Bus (USB) devices, and other electronic devices, among others. For example, the electronic device 1000 may be implemented as a smart phone, a cellular phone, a video phone, a smart tablet, a smart watch, a tablet Personal Computer (PC), a car navigation system, a computer monitor, a laptop computer, a Head Mounted Display (HMD) device, and so forth.

The processor 1010 may perform various computing functions. In an embodiment, the processor 1010 may be a microprocessor, a Central Processing Unit (CPU), an Application Processor (AP), or the like. The processor 1010 may be coupled to other components via address buses, control buses, data buses, and the like. Further, the processor 1010 may be coupled to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

Memory device 1020 may store data for the operation of electronic device 1000. For example, memory device 1020 may include at least one non-volatile memory device such as an Erasable Programmable Read Only Memory (EPROM) device, an Electrically Erasable Programmable Read Only Memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a Resistive Random Access Memory (RRAM) device, a Nano Floating Gate Memory (NFGM) device, a polymer random access memory (PoRAM) device, a Magnetic Random Access Memory (MRAM) device, and a Ferroelectric Random Access Memory (FRAM) device, and/or at least one volatile memory device such as a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, and a mobile DRAM device.

The storage 1030 may include a Solid State Drive (SSD) device, a Hard Disk Drive (HDD) device, a CD-ROM device, and the like.

The I/O device 1040 may include input devices such as keyboards, keypads, mouse devices, touch pads, touch screens, etc., and output devices such as printers and speakers, etc. In some embodiments, I/O device 1040 may include a display device 1060.

The power supply 1050 may provide power for the operation of the electronic device 1000.

The display device 1060 may display an image corresponding to visual information of the electronic device 1000. The display device 1060 may be connected to other components via a bus or other communication link. The display device 1060 may perform one display scan operation when the driving time of the panel driving frame is the reference driving time, and may perform one display scan operation and at least one self-scan operation when the driving time of the panel driving frame is greater than the reference driving time. Here, the display device 1060 may include a scan driver for applying a bias voltage configured to generate a bias voltage for boosting a voltage of a gate terminal of a driving transistor in a pixel circuit, so that even if a frame rate of a panel driving frame for driving a display panel is changed (i.e., a driving frequency of the display panel is changed), a hysteresis characteristic in which characteristics of the driving transistor are fixed in a predetermined state can be improved. Therefore, according to the display device 1060, a high-quality image can be displayed even if the variable frame rate technique is adopted.

In an embodiment, the scan driver for applying the bias voltage may include first to nth stages configured to output first to nth output signals for applying the bias voltage to first to nth pixel rows, respectively. The kth stage among the first to nth stages may include: an input configured to transmit an input signal to a first node in response to a first clock signal, a stress reducer disposed between the first node and a second node, a carry signal output configured to receive a high power supply voltage and a second clock signal and output the second clock signal as a kth carry signal via a first output node in response to a voltage of the second node, an output signal output configured to receive the high power supply voltage and a third clock signal and output the third clock signal as a kth output signal via a second output node in response to a voltage of the second node, a keeper configured to transmit the first clock signal to the third node in response to a voltage of the first node, and a stabilizer configured to apply a first low power supply voltage to the third node in response to the first clock signal and apply the high power supply voltage to the first node in response to the second clock signal. Here, each of the first clock signal and the second clock signal may be switched between a high power supply voltage and a first low power supply voltage, and the third clock signal may be switched between a high power supply voltage and an adjustable second low power supply voltage.

In another embodiment, the scan driver for applying the bias voltage may include first to nth stages configured to output first to nth output signals for applying the bias voltage to first to nth pixel rows, respectively. The first to nth stages may include: an input configured to transmit an input signal to a first node in response to a first clock signal, a stress reducer disposed between the first node and a second node, a carry signal output configured to receive a first high power supply voltage and a second clock signal and output the second clock signal as a kth carry signal via a first output node in response to a voltage of the second node, an output signal output configured to receive the second high power supply voltage and a third clock signal and output the third clock signal as a kth output signal via the second output node in response to a voltage of the second node, a keeper configured to transmit the first clock signal to the third node in response to a voltage of the first node, and a stabilizer configured to apply a first low power supply voltage to the third node in response to the first clock signal and apply the first high power supply voltage to the first node in response to the second clock signal. Here, each of the first clock signal and the second clock signal may be switched between a first high power supply voltage and a first low power supply voltage, and the third clock signal may be switched between an adjustable second high power supply voltage and an adjustable second low power supply voltage.

Since the structure and operation of the scan driver for applying the bias voltage are described above, repetitive description regarding the structure and operation of the scan driver for applying the bias voltage will not be repeated.

The present disclosure may be applied to a display device and an electronic device including the display device. For example, the present disclosure may be applied to cellular phones, smart phones, video phones, smart tablets, smart watches, tablet PCs, car navigation systems, televisions, computer monitors, laptop computers, head Mounted Display (HMD) devices, MP3 players, and the like.

The foregoing is illustrative of the present disclosure and is not to be construed as limiting the present disclosure. Although a few embodiments of the present disclosure have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of this disclosure. Accordingly, all such modifications are intended to be included within the scope of this disclosure as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of the present disclosure and is not to be construed as limited to the predetermined embodiments disclosed, and that modifications may be made to the embodiments of the present disclosure, as well as other embodiments.

Claims

1. A scan driver for applying a bias voltage, wherein the scan driver comprises:

first to nth stages, where n is an integer of 2 or more, configured to output first to nth output signals for applying the bias voltage to first to nth pixel rows, respectively,

wherein the kth stage comprises:

an input configured to transmit an input signal to a first node in response to a first clock signal;

a stress reducer disposed between the first node and a second node;

a carry signal outputter configured to receive a high power supply voltage and a second clock signal, and to output the second clock signal as a kth carry signal via a first output node in response to a voltage of the second node;

an output signal outputter configured to receive the high power supply voltage and a third clock signal, and to output the third clock signal as a kth output signal via a second output node in response to the voltage of the second node;

a keeper configured to transmit the first clock signal to a third node in response to a voltage of the first node; and

A stabilizer configured to apply a first low power supply voltage to the third node in response to the first clock signal and to apply the high power supply voltage to the first node in response to the second clock signal, and

wherein k is an integer of 1 to n, and each of the first and second clock signals selectively switches between the high power supply voltage and the first low power supply voltage, and the third clock signal selectively switches between the high power supply voltage and a second low power supply voltage different from the first low power supply voltage, and adjusts the bias voltage by changing the second low power supply voltage.

2. The scan driver of claim 1, wherein the input signal comprises a scan start signal or a previous carry signal.

3. The scan driver of claim 1, wherein the input comprises:

a first transistor having a first terminal configured to receive the input signal, a second terminal connected to the first node, and a gate terminal configured to receive the first clock signal.

4. The scan driver of claim 1, wherein the stress reducer comprises:

an eighth transistor having a first terminal connected to the first node, a second terminal connected to the second node, and a gate terminal configured to receive the first low supply voltage.

5. The scan driver of claim 1, wherein the carry signal outputter comprises:

a ninth transistor having a first terminal configured to receive the high supply voltage, a second terminal connected to the first output node, and a gate terminal connected to the third node; and

a tenth transistor having a first terminal connected to the first output node, a second terminal configured to receive the second clock signal, and a gate terminal connected to the second node.

6. The scan driver of claim 1, wherein the output signal outputter comprises:

a sixth transistor having a first terminal configured to receive the high supply voltage, a second terminal connected to the second output node, and a gate terminal connected to the third node; and

A seventh transistor having a first terminal connected to the second output node, a second terminal configured to receive the third clock signal, and a gate terminal connected to the second node.

7. The scan driver of claim 1, wherein the holder comprises:

a fourth transistor having a first terminal connected to the third node, a second terminal configured to receive the first clock signal, and a gate terminal connected to the first node.

8. The scan driver of claim 1, wherein the stabilizer comprises:

a second transistor having a first terminal configured to receive the high supply voltage, a second terminal, and a gate terminal connected to the third node;

a third transistor having a first terminal connected to the second terminal of the second transistor, a second terminal connected to the first node, and a gate terminal configured to receive the second clock signal;

a first capacitor having a first terminal configured to receive the high supply voltage and a second terminal connected to the third node; and

A fifth transistor having a first terminal connected to the third node, a second terminal configured to receive the first low supply voltage, and a gate terminal configured to receive the first clock signal.

9. The scan driver of claim 1, wherein the scan driver further comprises:

a bootstrap, the bootstrap being disposed between the second node and the first output node.

10. The scan driver of claim 9, wherein the bootstrap comprises:

a second capacitor having a first terminal connected to the second node and a second terminal connected to the first output node.

11. A scan driver for applying a bias voltage, wherein the scan driver comprises:

wherein the kth stage comprises:

A stress reducer disposed between the first node and a second node;

a carry signal outputter configured to receive a first high power supply voltage and a second clock signal, and to output the second clock signal as a kth carry signal via a first output node in response to a voltage of the second node;

an output signal outputter configured to receive a second high power supply voltage different from the first high power supply voltage and a third clock signal, and to output the third clock signal as a kth output signal via a second output node in response to the voltage of the second node;

a stabilizer configured to apply a first low power supply voltage to the third node in response to the first clock signal and to apply the first high power supply voltage to the first node in response to the second clock signal, and

wherein k is an integer of 1 to n, and each of the first clock signal and the second clock signal selectively switches between the first high power supply voltage and the first low power supply voltage, the third clock signal selectively switches between the second high power supply voltage and a second low power supply voltage different from the first low power supply voltage, and the bias voltage is adjusted by changing at least one of the second high power supply voltage and the second low power supply voltage or by changing the second high power supply voltage and the second low power supply voltage simultaneously.

12. The scan driver of claim 11, wherein the input signal comprises a scan start signal or a previous carry signal.

13. The scan driver of claim 11, wherein the input comprises:

14. The scan driver of claim 11, wherein the stress reducer comprises:

15. The scan driver of claim 11, wherein the carry signal outputter comprises:

a ninth transistor having a first terminal configured to receive the first high supply voltage, a second terminal connected to the first output node, and a gate terminal connected to the third node; and

16. The scan driver of claim 11, wherein the output signal outputter comprises:

a sixth transistor having a first terminal configured to receive the second high supply voltage, a second terminal connected to the second output node, and a gate terminal connected to the third node; and

17. The scan driver of claim 11, wherein the holder comprises:

a fourth transistor including a first terminal connected to the third node, a second terminal configured to receive the first clock signal, and a gate terminal connected to the first node.

18. The scan driver of claim 11, wherein the stabilizer comprises:

a second transistor having a first terminal configured to receive the first high supply voltage, a second terminal, and a gate terminal connected to the third node;

a first capacitor having a first terminal configured to receive the first high supply voltage and a second terminal connected to the third node; and

19. The scan driver of claim 11, wherein the scan driver further comprises:

20. The scan driver of claim 19, wherein the bootstrap comprises:

21. A display device, wherein the display device comprises:

A display panel including first to nth pixel rows, where n is an integer of 2 or more, the first to nth pixel rows including pixel circuits having a structure of applying a bias voltage to gate terminals of driving transistors via a boost capacitor;

a display panel driver configured to drive the display panel; and

a scan driver for applying a bias voltage, the scan driver including first to nth stages configured to output first to nth output signals for applying the bias voltage to the first to nth pixel rows, respectively,

wherein the bias voltage corresponds to a difference between a high level voltage and a low level voltage of a kth output signal, wherein k is an integer of 1 to n, and the bias voltage is adjusted by changing at least one of the high level voltage and the low level voltage or by changing the high level voltage and the low level voltage simultaneously.

22. The display device of claim 21, wherein the kth stage comprises:

a stress reducer disposed between the first node and a second node;

an output signal outputter configured to receive the high power supply voltage and a third clock signal, and to output the third clock signal as the kth output signal via a second output node in response to the voltage of the second node;

Wherein each of the first and second clock signals switches between the high and first low power supply voltages, the third clock signal switches between the high and second low power supply voltages different from the first low power supply voltage, and the bias voltage is adjusted by changing the second low power supply voltage.

23. The display apparatus of claim 22, wherein the input signal comprises a scan start signal or a previous carry signal.

24. The display device of claim 21, wherein the kth stage comprises:

a stress reducer disposed between the first node and a second node;

an output signal outputter configured to receive a second high power supply voltage different from the first high power supply voltage and a third clock signal, and to output the third clock signal as the kth output signal via a second output node in response to the voltage of the second node;

wherein each of the first and second clock signals switches between the first high and low power supply voltages, the third clock signal switches between the second high and low power supply voltages, and the bias voltage is adjusted by changing at least one of the second high and low power supply voltages or by changing the second high and low power supply voltages simultaneously.

25. The display device of claim 24, wherein the input signal comprises a scan start signal or a previous carry signal.