CN117408226B - Data analysis method, device and system for communication bus - Google Patents
Data analysis method, device and system for communication bus Download PDFInfo
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Abstract
The application relates to the technical field of digital verification, and discloses a data analysis method for a communication bus, which comprises the following steps: sending test cases to a bus analysis component according to a set time sequence; analyzing the test cases through a bus analysis component to obtain component analysis signals; the bus analysis component configures a benchmark reference model with the same function as a circuit to be tested of the communication bus configuration; synchronizing the component analysis signal to the analysis signal of the communication bus so that the communication bus performs data jump according to the component analysis signal. The method can overcome the problem of hysteresis of input and output data of the circuit to be tested relative to bus data of the communication bus, and improves the reliability of the communication bus test. The application also discloses a data analysis device and a system for the communication bus.
Description
Technical Field
The present application relates to the field of digital verification technologies, and for example, to a method, an apparatus, and a system for analyzing data of a communication bus.
Background
At present, the development trend of integrated circuits is that the design scale is larger and the complexity is higher, so that the cost of the current chip is also increased, and therefore, the verification of the circuit function performance is more important. Along with the continuous perfection of the circuit function, the variety and the number of test excitation sent to the circuit are increased, the verification process is more complicated, and the working scene of the circuit is more.
Related art a verification platform is built based on UVM (Universal Verification Methodology ), test stimulus is sent to the circuit under test through the platform, and error correction is typically performed by querying a simulation log and a simulation waveform.
In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:
Because the circuit to be tested can analyze and generate output data comprising instructions, addresses and input data internally after receiving input, and meanwhile, the output data can also synchronously respond after finishing the input, the checking of the input and output data of the circuit to be tested has certain hysteresis relative to the bus data of the communication bus, and the reliability of the communication bus test is affected.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the application and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.
Disclosure of Invention
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.
The embodiment of the disclosure provides a data analysis method, a device and a system for a communication bus, which are used for solving the problem of hysteresis of input and output data of a circuit to be tested relative to bus data of the communication bus and improving the reliability of the communication bus test.
In some embodiments, the method comprises: sending test cases to a bus analysis component according to a set time sequence; analyzing the test cases through a bus analysis component to obtain component analysis signals; the line analysis component configures a datum reference model with the same function as a circuit to be tested configured by the communication bus; synchronizing the component analysis signal to the analysis signal of the communication bus so that the communication bus performs data jump according to the component analysis signal.
In some embodiments, sending test cases to the bus resolution component at a set timing, comprising: determining a clock edge of a start clock cycle based on the set timing; and under the condition that the current moment is at the clock edge of the initial clock period, sending the test case to the bus analysis component.
In some embodiments, parsing the test cases to obtain component parse signals includes: analyzing the test case to obtain the instruction type of the test instruction in the test case; and obtaining a component analysis signal according to the instruction type of the test instruction.
In some embodiments, the component resolution signal is obtained from an instruction type of the test instruction, including one or more of the following: under the condition that the instruction type is a write instruction, analyzing the test case, obtaining a test analysis instruction, a test analysis address and first test analysis data, and taking the test analysis instruction, the test analysis address and the first test analysis data as component analysis signals; under the condition that the instruction type is an erasing instruction, analyzing the test case, obtaining a test analysis instruction and a test analysis address, and taking the test analysis instruction and the test analysis address as component analysis signals; under the condition that the instruction type is a read instruction, determining the read type of the read instruction, reading read data associated with the test case according to the read type, and taking the read data as a component analysis signal; analyzing the test instruction and obtaining second test analysis data under the condition that the instruction type is an instruction except a preset instruction, and taking the second test analysis data as a component analysis signal; the preset instructions comprise a write instruction, an erase instruction and a read instruction.
In some embodiments, synchronizing the component resolution signal to the resolution signal of the communication bus includes: the byte is used as a transmission unit, and the component analysis signal is driven to the analysis signal of the communication bus every N clock cycles.
In some embodiments, the communication bus performs data hopping according to the component resolution signal, including: after the component analysis signal is sent, obtaining the enabling state of the chip enabling signal; in the case where the enabled state indicates enabled, the data jump is performed according to the component parsing signal.
In some embodiments, further comprising: under the condition that the test cases are sent to the bus analysis component according to the set time sequence, the test cases are sent to the communication bus, so that a circuit to be tested of the communication bus analyzes the test cases and obtains bus analysis signals; and determining the analysis abnormal condition of the circuit to be tested according to the matching condition of the component analysis signal and the bus analysis signal.
In some embodiments, determining the analysis abnormal condition of the circuit to be tested according to the matching condition of the component analysis signal and the bus analysis signal includes: under the condition that the component analysis signal is not matched with the bus analysis signal, determining analysis abnormality of the circuit to be tested and determining the analysis abnormality position; and under the condition that the component analysis signal is matched with the bus analysis signal, determining that the circuit to be tested is accurate in analysis.
In some embodiments, the apparatus comprises: a processor and a memory storing program instructions, the processor being configured to perform a data parsing method for a communication bus as described above when the program instructions are executed.
In some embodiments, the system comprises: the verification platform is used for configuring test cases; the communication bus is connected with the verification platform and is used for configuring a circuit to be tested; the bus analysis component is connected with the verification platform and the communication bus and is used for configuring a benchmark reference model with the same function as a circuit to be tested configured by the communication bus; and the data analysis device for the communication bus is arranged on the verification platform.
The data analysis method, device and system for the communication bus provided by the embodiment of the disclosure can realize the following technical effects:
According to the embodiment of the disclosure, the test cases are sent to the bus analysis component according to the set time sequence, and the bus analysis component is used for taking the test cases as test excitation and analyzing the test cases to obtain component analysis signals. And synchronizing the component analysis signal to the analysis signal of the communication bus to enable the communication bus to carry out data jump according to the analysis signal. Because the bus analysis component is configured with the datum reference model with the same function as the circuit to be tested configured by the communication bus, analysis signals synchronized to the communication bus are completely synchronized with bus data of the communication bus, the problem of hysteresis of input and output data of the circuit to be tested relative to the bus data of the communication bus is solved, and the reliability of the communication bus test is improved.
The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:
FIG. 1 is a schematic diagram of a system environment of a data parsing system for a communication bus provided in an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a data parsing method for a communication bus according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of another method for data parsing for a communication bus according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of another method for data parsing for a communication bus according to an embodiment of the present disclosure;
FIG. 5-1 is a timing diagram of test stimulus for a communication bus provided by an embodiment of the present disclosure;
FIG. 5-2 is a timing diagram of a test response of a communication bus provided by an embodiment of the present disclosure;
Fig. 6 is a schematic diagram of a data parsing apparatus for a communication bus according to an embodiment of the disclosure.
Reference numerals:
100: a verification platform; 101: a bus parsing component; 103: a circuit to be tested;
1001: a drive assembly; 1002: a base reference model;
1003: a monitoring module; 1004: a scoring module;
200: a data parsing means for the communication bus;
700: a processor; 701: a memory; 702: a communication interface.
Detailed Description
So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.
The terms first, second and the like in the description and in the claims of the embodiments of the disclosure and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.
The term "plurality" means two or more, unless otherwise indicated.
In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents: a or B.
The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, a and/or B, represent: a or B, or, A and B.
The term "corresponding" may refer to an association or binding relationship, and the correspondence between a and B refers to an association or binding relationship between a and B.
FIG. 1 is a schematic diagram of a system environment for a data parsing system for a communication bus. Referring to fig. 1, the data analysis system for communication bus includes an authentication platform 100, a communication bus 703, and a bus analysis component 101. The communication bus 703 is connected to the verification platform 100 and is configured with the circuit 103 under test. The bus analysis component 101 is connected with the verification platform 100 and the communication bus 703, and configures a baseline reference model 1002 with the same function as the circuit 103 to be tested configured by the communication bus 703. The base reference model 1002 represents a model that functions identically to the circuit under test 103 configured by the communication bus 703. The bus parsing component 101 is configured to parse the test case and generate a component parse signal. The verification platform 100 may be a verification platform generated based on UVM building.
Optionally, the verification platform 100 includes a drive assembly 1001. The driving component 1001 is electrically connected to the communication bus 703 corresponding to the input end of the circuit to be tested 103, and the driving component 1001 is configured to drive the bus parsing component 101 to parse the test case and obtain a component parsing signal, synchronize the component parsing signal to the parsing signal of the communication bus 703 so that the communication bus 703 performs data skipping according to the component parsing signal, and send the test case to the communication bus 703 so that the circuit to be tested 103 of the communication bus 703 parses the test case and obtains a bus parsing signal.
Optionally, the verification platform 100 further includes a monitoring module 1003 and a scoring module 1004. The monitoring module 1003 is electrically connected to the communication bus 703 corresponding to the output terminal of the circuit 103 to be tested, and the monitoring module 1003 is configured to receive the component analysis signal and transmit the component analysis signal to the scoring module 1004, and is configured to detect the bus analysis signal output by the communication bus 703 corresponding to the output terminal of the circuit 103 to be tested.
The scoring module 1004 is electrically connected to the bus parsing component 101 and the monitoring module 1003, and the scoring module 1004 is configured to determine a parsing abnormal condition of the circuit 103 under test according to a matching condition of the component parsing signal and the bus parsing signal.
Optionally, the verification platform 100 further comprises a signal generator. The signal generator is electrically connected to the drive assembly 1001. The signal generator is configured to receive the excitation and generate a sinusoidal signal having a frequency of 20Hz to 200kHz corresponding to the excitation. The drive component 1001 builds test cases based on the sinusoidal signals generated by the signal generator.
Based on the above data parsing system for a communication bus, referring to fig. 2, an embodiment of the disclosure provides a data parsing method for a communication bus, including:
S01, the driving component sends test cases to the bus analysis component according to the set time sequence.
In this step, the test case includes a test stimulus input to the communication bus corresponding to the input end of the circuit to be tested, and/or a test response generated by analyzing the circuit to be tested after the test stimulus is input to the communication bus. The set timing represents a timing rule for transmitting test cases. In a specific application, the set timing is set by a tester.
S02, the driving component analyzes the test cases through the bus analysis component to obtain component analysis signals. The bus analysis component configures a datum reference model with the same function as a circuit to be tested of the communication bus configuration.
In this step, the bus analysis module 101 has a black box verification function. That is, after the test cases as test stimulus are input to the bus analysis module, only the input and output of data are focused, and the skip state of the intermediate signal generated in the bus analysis module is not focused. After input data is input to the bus analysis component, the input data is analyzed by the bus analysis component, and then output data is directly generated. When the output data is required to be output, the output data can be directly requested to the bus analysis component, so that the signal jump flow of the input data in the bus analysis component is omitted.
S03, the driving component synchronizes the component analysis signal to the analysis signal of the communication bus so that the communication bus performs data jumping according to the component analysis signal.
By adopting the data analysis method for the communication bus provided by the embodiment of the disclosure, the embodiment of the disclosure sends the test case to the bus analysis component according to the set time sequence, and the bus analysis component takes the test case as test excitation and analyzes the test case to obtain the component analysis signal. And synchronizing the component analysis signal to the analysis signal of the communication bus to enable the communication bus to carry out data jump according to the analysis signal. Because the bus analysis component is configured with the datum reference model with the same function as the circuit to be tested configured by the communication bus, analysis signals synchronized to the communication bus are completely synchronized with bus data of the communication bus, the problem of hysteresis of input and output data of the circuit to be tested relative to the bus data of the communication bus is solved, and the reliability of the communication bus test is improved.
Optionally, the driving component sends the test case to the bus parsing component according to the set time sequence, including:
the driving component determines a clock edge of the start clock period based on the set timing.
And the driving component sends the test case to the bus analysis component under the condition that the current moment is at the clock edge of the initial clock period. Wherein the start clock cycle represents the first clock cycle in the set timing.
In this way, after the driving component is controlled to determine the clock edge of the revealing clock period based on the set time sequence, when the current time is at the clock edge of the starting clock period, the test case is sent to the bus analysis component, so that the clock edge of the first clock period of the test case in the set time sequence is input to the bus analysis component, the driving component is facilitated to synchronize signals of the generated component analysis signals, the more accurate analysis signals are obtained, the high synchronization of the analysis signals of the communication bus and the bus data of the communication bus is realized, and the reliability of the communication bus test is facilitated to be improved. Meanwhile, the driving component sends the test case to the bus analysis component at the clock edge of the first clock period, and the analysis signal of the communication bus is completely synchronous with the bus data of the communication bus, so that the analysis signal of the component generated by the analysis of the bus analysis component can intuitively and accurately embody the information related to the test case, thereby providing great convenience for manually checking waveforms, reducing the difficulty of the communication bus test and further improving the reliability of the communication bus test.
Optionally, as shown in connection with fig. 3, the bus parsing component parses the test case to obtain a component parsing signal, including:
S11, the bus analysis component analyzes the test case to obtain the instruction type of the test instruction in the test case.
S12, the bus analysis component obtains a component analysis signal according to the instruction type of the test instruction.
In this way, the embodiment of the disclosure controls the bus analysis component to analyze the test case, obtains the instruction type of the test instruction in the test case, and obtains the component analysis signal according to the instruction type of the test instruction. Therefore, the instructions of different instruction types in the test case can be accurately classified, and the accuracy of component analysis signal generation is improved, so that the reliability of communication bus test is improved.
Optionally, the bus parsing component obtains a component parsing signal according to an instruction type of the test instruction, including one or more of the following manners:
And under the condition that the instruction type is a write instruction, the bus analysis component analyzes the test case, obtains a test analysis instruction, a test analysis address and first test analysis data, and takes the test analysis instruction, the test analysis address and the first test analysis data as component analysis signals.
And under the condition that the instruction type is the wiping instruction, the bus analysis component analyzes the test case, obtains a test analysis instruction and a test analysis address, and takes the test analysis instruction and the test analysis address as component analysis signals.
When the instruction type is a read instruction, the bus analysis component determines the read type of the read instruction, reads the read data associated with the test case according to the read type, and takes the read data as a component analysis signal.
And under the condition that the instruction type is the instruction except the preset instruction, the bus analysis component analyzes the test instruction and obtains second test analysis data, and the second test analysis data is used as a component analysis signal. The preset instructions comprise a write instruction, an erase instruction and a read instruction.
In this way, when the instruction type is a write instruction, the embodiment of the disclosure parses the test case and obtains a test parsing instruction, a test parsing address and first test parsing data, and uses the test parsing instruction, the test parsing address and the first test parsing data as component parsing signals; or when the instruction type is the wiping instruction, analyzing the test case, obtaining a test analysis instruction and a test analysis address, and taking the test analysis instruction and the test analysis address as component analysis signals; or when the instruction type is a read instruction, determining the read type of the read instruction, reading the read data related to the test case according to the read type, and taking the read data as a component analysis signal; or when the instruction type is the instruction except the preset instruction, analyzing the test instruction and obtaining second test analysis data. Therefore, the embodiment of the disclosure can obtain the test data related to the test case according to the specific instruction type of the test instruction and construct and generate the component analysis signal, thereby being beneficial to obtaining the accurate and effective component analysis signal and improving the reliability of the communication bus test.
In a specific example, the bus parsing component determines a read type of the read instruction and reads read data associated with the test case according to the read type, comprising:
and under the condition that the read type of the read instruction is determined to be memory read, the bus analysis component reads first storage data in the memory according to a memory address in a back door read mode, and takes the first storage data as read data associated with the test case.
In another specific example, the bus parsing component determines a read type of the read instruction and reads read data associated with the test case according to the read type, including:
And under the condition that the read type is determined to be register read, the bus analysis component reads second storage data in the register according to the register address, and takes the second storage data as read data related to the test case.
In this way, the embodiment of the disclosure can obtain the read data corresponding to the read type according to the specific read type of the read instruction, which is favorable for obtaining the test data associated with the test case and constructing the component analysis signal, thereby improving the accuracy of the component analysis signal.
Optionally, the driving component synchronizes the component parsing signal to a parsing signal of the communication bus, including:
the driving component takes bytes as a transmission unit, and drives the component analysis signal to the analysis signal of the communication bus every N clock cycles. Where a byte includes N clock cycles. In one specific example, N is 8. Note that N may be an even multiple of 8.
Therefore, the drive component is controlled to drive the component analysis signal to the analysis signal of the communication bus every N clock cycles by taking bytes as the transmission unit, and the analysis signal completely synchronous with the bus data of the communication bus can be obtained, so that the problem of hysteresis of the input and output data of the circuit to be tested relative to the bus data of the communication bus is solved, and the reliability of the communication bus test is further improved.
Optionally, the communication bus performs data skipping according to the component parsing signal, including:
After the component analysis signal is sent, the communication bus obtains the enabling state of the chip enabling signal.
And under the condition that the enabling state represents enabling, the communication bus performs data jumping according to the component analysis signal.
In this way, after the component analysis signal is sent, the embodiment of the disclosure obtains the enabling state of the chip enabling signal, and determines that the chip is valid when the enabling state represents enabling, at this time, the driving component performs data skip according to the component analysis signal. Therefore, after the bus analysis component analyzes the test case and obtains the component analysis signal, when the chip is determined to be effective, data skip is executed according to the component analysis signal, so that synchronous analysis of bus data of the communication bus is realized, and further the reliability of the communication bus test is improved.
In a specific example, the communication bus determines an enable state of the enable signal, comprising:
Determining that the enable state is enabled when the enable signal is low; or when the enable signal is pulled high or the enable signal is disabled, determining that the enable state is off. Wherein pulling high indicates a transition from a low level to a high level.
Optionally, the data parsing method for the communication bus further includes:
And the driving component synchronizes the component analysis signal to the analysis signal of the communication bus to obtain the enabling state of the chip enabling signal.
In the event that the enable state indicates off, the control bus resolution component resets.
Therefore, the verification personnel can conveniently continue the test verification operation of the communication bus.
Optionally, after the component parsing signal is sent, the communication bus obtains an enabling state of the chip enabling signal, including:
after the component analysis signal transmission is completed, the communication bus receives a signal output request, and the signal output request is generated when the communication bus determines that the component analysis signal transmission is completed.
The communication bus obtains an enable state of the chip enable signal in response to the signal output request.
In this way, after the component analysis signal is sent, the communication bus generates a signal output request to trigger the driving component to execute data skip according to the component analysis signal when the chip is determined to be effective, so that synchronous analysis of bus data of the communication bus is realized, and further reliability of communication bus test is improved.
Referring to fig. 4, another method for analyzing data of a communication bus according to an embodiment of the present disclosure includes:
S21, the driving component sends test cases to the bus analysis component according to the set time sequence.
S22, the driving component analyzes the test cases through the bus analysis component to obtain component analysis signals. The bus analysis component configures a datum reference model with the same function as a circuit to be tested of the communication bus configuration.
S23, the driving component synchronizes the component analysis signal to the analysis signal of the communication bus so that the communication bus performs data jumping according to the component analysis signal.
S24, under the condition that the test cases are sent to the bus analysis component according to the set time sequence, the driving component sends the test cases to the communication bus, so that the circuit to be tested of the communication bus analyzes the test cases and obtains bus analysis signals.
S25, determining the analysis abnormal condition of the circuit to be tested by the scoring module according to the matching condition of the component analysis signal and the bus analysis signal.
By adopting the data analysis method for the communication bus provided by the embodiment of the disclosure, the embodiment of the disclosure sends the test case to the bus analysis component according to the set time sequence, and the bus analysis component takes the test case as test excitation and analyzes the test case to obtain the component analysis signal. And synchronizing the component analysis signal to the analysis signal of the communication bus to enable the communication bus to carry out data jump according to the analysis signal. Meanwhile, when the test cases are sent to the bus analysis component according to the set time sequence, the driving component also sends the test cases to the communication bus, so that the circuit to be tested of the communication bus analyzes the test cases and obtains bus analysis signals. The scoring module can acquire the analysis abnormal condition of the circuit to be tested according to the matching condition of the component analysis signal and the bus analysis signal. Therefore, a verifier can obtain information related to the test case according to the matching condition of the signals, and can efficiently verify the error position when resolving the abnormality, thereby being beneficial to improving the test verification efficiency of the communication bus.
Optionally, the scoring module determines an analysis abnormal condition of the circuit to be tested according to a matching condition of the component analysis signal and the bus analysis signal, including:
under the condition that the component analysis signal is not matched with the bus analysis signal, the scoring module determines analysis abnormality of the circuit to be tested and determines the analysis abnormality position.
Under the condition that the component analysis signal is matched with the bus analysis signal, the scoring module determines that the circuit to be tested is accurate in analysis.
Therefore, the bus analysis component is configured with the standard reference model with the same function as the circuit to be tested configured by the communication bus, so that the test case can be accurately analyzed and a bus analysis signal matched with the component analysis signal can be generated when the circuit to be tested is normal in function. And when the circuit to be tested is abnormal in function, the test case cannot be accurately analyzed, and the generated bus analysis signal is not matched with the component analysis signal. Based on the above, the embodiment of the disclosure can determine that the circuit to be tested is abnormal in analysis and determine the position of the abnormal analysis when the component analysis signal is not matched with the bus analysis signal, and determine that the circuit to be tested is accurate in analysis when the component analysis signal is matched with the bus analysis signal. Therefore, a verifier can obtain information related to the test case according to the matching condition of the signals, and can efficiently verify the error position when resolving the abnormality, thereby being beneficial to improving the test verification efficiency of the communication bus.
Optionally, the scoring module determines whether the component resolution signal matches the bus resolution signal in the following manner:
And determining that the component analysis signal is matched with the bus analysis signal under the condition that the component analysis signal is identical with the bus analysis signal. Or alternatively
In the case where the component resolving signal is different from the bus resolving signal, it is determined that the component resolving signal does not match the bus resolving signal.
Optionally, the scoring module determines resolving the anomaly location, including: the scoring module determines the signal position of the bus analysis signal different from the component analysis signal; the scoring module determines an anomaly location based on the signal location. As an example, if the bus analysis signal is 0x55AA55 and the component analysis signal is 0xAAAA a, the scoring module determines the signal position corresponding to 0x55 in the bus analysis signal, and determines the abnormal position according to the signal position.
In practical application, FIG. 5-1 shows a timing diagram of test stimulus of a communication bus according to an embodiment of the present disclosure. Fig. 5-2 is a timing diagram of a test response of a communication bus provided by an embodiment of the present disclosure. As shown in connection with fig. 5-1 and 5-2, chip_select represents a chip select signal as a chip enable signal. clk represents the clock and one byte corresponds to 8 clock cycles. state represents instruction information of a test instruction in a test stimulus/test response, ins and addr represent instruction information as an instruction and an address respectively, and out represents instruction information as data.
As shown in fig. 5-1, bus_ datain represents a test stimulus when being input to a communication bus corresponding to an input terminal of a circuit to be tested, the instruction type of the test stimulus is an erase instruction and the test stimulus includes a test parse instruction 0x55 and a test parse address 0xAA5.
The det_in represents the bus input resolution signal corresponding to the test stimulus. The bus input analysis signal is 0x55AA55, and 0x55 is located in the 9 th to 16 th clock cycles, and 0x55AA is located in the 17 th to 24 th clock cycles.
Ref_ datain represents the component input parse signal generated by the bus parse component to parse the test stimulus bus_ datain described above. The component input parse signal is 0x55AA55 and is fully synchronized with the test stimulus bus_ datain when input to the communication bus corresponding to the input of the circuit under test.
As shown in fig. 5-2, bus_ dataout represents a test response that is generated by the circuit under test after inputting a test stimulus bus_ datain to the communication bus, i.e., bus_ dataout is bus data output by the communication bus corresponding to the output terminal of the circuit under test.
The det_out represents the bus output parse signal corresponding to the test response. The bus output parsing signal is output data 0x123456, and 0x12 is located at the 9 th to 16 th clock cycles, and 0x3456 is located at the 17 th to 24 th clock cycles.
Ref_ dataout represents a component output parse signal generated by the bus parse component to parse the test response bus_ dataout. The component outputs a parse signal of 0x123456 and is fully synchronized with the test response bus dataout.
As can be seen by comparing fig. 5-1 with fig. 5-2, the bus input parsing signal dut_in is generated by parsing the circuit under test after the test stimulus bus_ datain is transmitted, and the bus output parsing signal dut_out is generated by parsing the circuit under test after the test response bus_ dataout is transmitted, so the bus input parsing signal dut_in has hysteresis compared with the test stimulus bus_ datain, and the bus output parsing signal dut_out has hysteresis compared with the test response bus_ dataout. While the component input analytic signal ref_ datain generated by the bus analytic component is fully synchronized with the test stimulus bus_ datain, and the component output analytic signal ref_ dataout generated by the bus analytic component is fully synchronized with the test response bus_ dataout.
In this way, the driving component performs synchronous analysis processing with the clock clk by using the component input analysis signal ref_ datain and the component output analysis signal ref_ dataout generated by analyzing the bus analysis component, that is, when the chip selection signal is valid, the component input analysis signal ref_ datain is successfully synchronized with the analysis signal of the communication bus at the time corresponding to the clock edge of the first clock cycle, and the component output analysis signal ref_ dataout is successfully synchronized with the analysis signal of the communication bus at the time corresponding to the clock edge of the first clock cycle.
Referring to fig. 6, an embodiment of the present disclosure provides a data parsing apparatus 200 for a communication bus, including a processor (processor) 700 and a memory (memory) 701. Optionally, the apparatus 200 may further comprise a communication interface (Communication Interface) 702. The processor 700, the communication interface 702, and the memory 701 may communicate with each other through the communication bus 703. The communication interface 702 may be used for information transfer. The processor 700 may invoke logic instructions in the memory 701 to perform the data parsing method for the communication bus of the above-described embodiments.
Further, the logic instructions in the memory 701 may be implemented in the form of software functional units and may be stored in a computer readable storage medium when sold or used as a stand alone product.
The memory 701 is used as a computer readable storage medium for storing a software program, a computer executable program, and program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 700 executes the program instructions/modules stored in the memory 701 to perform functional applications and data processing, i.e., to implement the data parsing method for a communication bus in the above-described embodiments.
Memory 701 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for a function; the storage data area may store data created according to the use of the terminal device, etc. In addition, the memory 701 may include a high-speed random access memory, and may also include a nonvolatile memory.
Referring to fig. 1, the embodiment of the disclosure further provides a data parsing system for a communication bus, which includes a verification platform 100, a communication bus 703, a bus parsing component 101, and a data parsing device 200 for a communication bus. The communication bus 703 is connected to the verification platform 100 and is configured with the circuit 103 under test. The bus analysis component 101 is connected with the verification platform 100 and the communication bus 703, and configures a baseline reference model 1002 with the same function as the circuit 103 to be tested configured by the communication bus 703. The base reference model 1002 represents a model that functions identically to the circuit under test 103 configured by the communication bus 703. The bus parsing component 101 is configured to parse the test case and generate a component parse signal. The data analysis device 200 for a communication bus is mounted on the authentication platform 100. The mounting relationships described herein are not limited to placement within verification platform 100, but include mounting connections to other components of a data analysis system for a communication bus, including but not limited to physical, electrical, or signaling connections, etc. Those skilled in the art will appreciate that the data parsing device 200 for a communication bus may be adapted to a feasible system main body, thereby implementing other feasible embodiments.
Embodiments of the present disclosure provide a computer readable storage medium storing computer executable instructions configured to perform the above-described data parsing method for a communication bus.
Embodiments of the present disclosure may be embodied in a software product stored on a storage medium, including one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of a method according to embodiments of the present disclosure. While the aforementioned storage medium may be a non-transitory storage medium, such as: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may involve structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. Moreover, the terminology used in the present application is for the purpose of describing embodiments only and is not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a," "an," and "the" (the) are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this disclosure is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, when used in the present disclosure, the terms "comprises," "comprising," and/or variations thereof, mean that the recited features, integers, steps, operations, elements, and/or components are present, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Without further limitation, an element defined by the phrase "comprising one …" does not exclude the presence of other like elements in a process, method or apparatus that includes the element. In this context, each embodiment may be described with emphasis on the differences from the other embodiments, and the same similar parts between the various embodiments may be referred to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method sections disclosed in the embodiments, the description of the method sections may be referred to for relevance.
Those of skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. The skilled artisan may use different methods for each particular application to achieve the described functionality, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.
In the embodiments disclosed herein, the disclosed methods, articles of manufacture (including but not limited to devices, apparatuses, etc.) may be practiced in other ways. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the units may be merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form. The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to implement the present embodiment. In addition, each functional unit in the embodiments of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than that disclosed in the description, and sometimes no specific order exists between different operations or steps. For example, two consecutive operations or steps may actually be performed substantially in parallel, they may sometimes be performed in reverse order, which may be dependent on the functions involved. Each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Claims (8)
1. A data parsing method for a communication bus, comprising:
sending test cases to a bus analysis component according to a set time sequence;
Analyzing the test cases through a bus analysis component to obtain component analysis signals; the bus analysis component configures a benchmark reference model with the same function as a circuit to be tested of the communication bus configuration;
synchronizing the component analysis signal to an analysis signal of the communication bus so that the communication bus performs data jump according to the component analysis signal;
Analyzing the test case to obtain a component analysis signal, including:
Analyzing the test case to obtain the instruction type of the test instruction in the test case;
obtaining a component analysis signal according to the instruction type of the test instruction;
Synchronizing the component resolution signal to the resolution signal of the communication bus, comprising:
The byte is used as a transmission unit, and the component analysis signal is driven to the analysis signal of the communication bus every N clock cycles.
2. The parsing method of claim 1, wherein sending test cases to the bus parsing component at a set timing, comprises:
Determining a clock edge of a start clock cycle based on the set timing;
And under the condition that the current moment is at the clock edge of the initial clock period, sending the test case to the bus analysis component.
3. The parsing method of claim 1, wherein obtaining component parse signals based on instruction types of test instructions includes one or more of:
Under the condition that the instruction type is a write instruction, analyzing the test case, obtaining a test analysis instruction, a test analysis address and first test analysis data, and taking the test analysis instruction, the test analysis address and the first test analysis data as component analysis signals;
Under the condition that the instruction type is an erasing instruction, analyzing the test case, obtaining a test analysis instruction and a test analysis address, and taking the test analysis instruction and the test analysis address as component analysis signals;
under the condition that the instruction type is a read instruction, determining the read type of the read instruction, reading read data associated with the test case according to the read type, and taking the read data as a component analysis signal;
Analyzing the test instruction and obtaining second test analysis data under the condition that the instruction type is an instruction except a preset instruction, and taking the second test analysis data as a component analysis signal; the preset instructions comprise a write instruction, an erase instruction and a read instruction.
4. The parsing method of claim 1, wherein the communication bus performs data hopping based on the component parsing signal, comprising:
After the component analysis signal is sent, obtaining the enabling state of the chip enabling signal;
In the case where the enabled state indicates enabled, the data jump is performed according to the component parsing signal.
5. The method according to any one of claims 1 to 4, further comprising:
Under the condition that the test cases are sent to the bus analysis component according to the set time sequence, the test cases are sent to the communication bus, so that a circuit to be tested of the communication bus analyzes the test cases and obtains bus analysis signals;
and determining the analysis abnormal condition of the circuit to be tested according to the matching condition of the component analysis signal and the bus analysis signal.
6. The method according to claim 5, wherein determining the analysis abnormality of the circuit to be tested based on the matching of the component analysis signal and the bus analysis signal comprises:
under the condition that the component analysis signal is not matched with the bus analysis signal, determining analysis abnormality of the circuit to be tested and determining the analysis abnormality position;
And under the condition that the component analysis signal is matched with the bus analysis signal, determining that the circuit to be tested is accurate in analysis.
7. A data parsing apparatus for a communication bus, comprising a processor and a memory storing program instructions, wherein the processor is configured to perform the data parsing method for a communication bus according to any of claims 1 to 6 when the program instructions are executed.
8. A data parsing system for a communication bus, comprising:
the verification platform is used for configuring test cases;
the communication bus is connected with the verification platform and is used for configuring a circuit to be tested;
The bus analysis component is connected with the verification platform and the communication bus and is used for configuring a benchmark reference model with the same function as a circuit to be tested configured by the communication bus; and, a step of, in the first embodiment,
The data parsing device for a communication bus of claim 7, mounted to a verification platform.
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