CN117408219B - DDR signal Rtt terminal PCB board level layout wiring constraint method and electronic equipment - Google Patents
DDR signal Rtt terminal PCB board level layout wiring constraint method and electronic equipment Download PDFInfo
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Abstract
The invention discloses a DDR signal Rtt terminal PCB board level layout wiring constraint method and electronic equipment, wherein the method comprises the following steps: determining the total length of a first wire between a target PAD of a bare chip in a control chip and a first welding bump on a circuit packaging substrate of the control chip; determining a first total transmission delay on a first wire; determining a magnitude relation between a second total transmission delay and a first total transmission delay on a second wiring between the first welding bump and one end of the termination resistor; obtaining an initial magnitude relation between the total length of the second wire and the first wire according to the magnitude relation between the first signal transmission rate on the wire inside the control chip and the second signal transmission rate on the wire inside the PCB, the magnitude relation between the second and the first total transmission delays and the magnitude relation between the first and the second signal transmission rates; and determining the constraint condition of the total length of the second wiring according to the lumped parameter method and the initial size relation, and determining the optimal constraint condition of the leading-out position of the second wiring.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a DDR signal Rtt terminal PCB board level layout wiring constraint method and electronic equipment.
Background
Along with the development of cloud computing and big data application, the integration density of each main control chip is high. Following the continuous improvement of product performance, electronic systems are becoming increasingly bulky, data rates are continuously rising, and power supply rails are further reduced. For example, a Double Data Rate 2 (DDR 2) Rate 800Mbps,1.8V power supply; three generation memory (Double Data Rate 3, DDR 3) Rate 160 Mbps,1.5V power; while the Rate of four-generation memory (Double Data Rate 4, DDR 4) has reached 3200Mbps, the power supply is only 1.2V, so that later five-generation memory (Double Data Rate 5, DDR 5) faces higher Rate and lower power supply voltage, which makes the problem of DDR signal integrity increasingly prominent. DDR signal integrity designs are an indispensable place in printed circuit board (Printed Circuit Board, PCB) layout designs, requiring signal integrity engineers to place stringent constraints on layout.
In the market, if the controller (Integrated Circuit, IC) and DDR are internally integrated with an On-Die Termination (ODT) module, then the rt Termination is not required externally; if the ODT module is not integrated within the controller IC or DDR, it is necessary to make the rt termination at the PCB board level. At present, the engineering design has no definite constraint rule, and the rule is mainly based on the experience rule of engineers. The current general design generally follows that the closer the Rtt termination resistance is to the receiving end IC, the better the Rtt termination resistance is, the transmission distance from the packaging PKG to a bare chip (DIE) is not considered, quantitative description is not carried out according to engineering design conditions, and when the termination distance is transmitted, the delay is delayedLess than the encapsulated PKG distance transmission delay +.>At this time, signal reflection may deteriorate for the controller IC, thereby causing a signal integrity problem. Therefore, there is a need for routing the DDR signal Rtt to the layout of the PCB board levelQuantitative constraints.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a DDR signal Rtt terminal PCB board level layout wiring constraint method and electronic equipment.
The technical problems to be solved by the invention are realized by the following technical scheme:
a DDR signal rt terminated PCB board level place and route constraint method, the method comprising:
determining the total length of a first wire between a target PAD of a bare chip in a control chip and a first welding bump on a circuit packaging substrate of the control chip; the control chip is positioned on the PCB;
determining a first total transmission delay on the first wiring according to the total length of the first wiring;
determining a size relation between a second total transmission delay and the first total transmission delay on a second wiring between the first welding convex point and one end, which is not connected with a voltage source, of the termination resistor according to the characteristic that the termination resistor absorbs reflected signals at the tail end of a transmission link of the DDR signal; the first welding convex point is the only point connected with the termination resistor on the circuit packaging substrate;
determining the signal transmission rate on the internal wiring of the control chip to obtain a first signal transmission rate, and determining the signal transmission rate on the internal wiring of the PCB to obtain a second signal transmission rate;
obtaining an initial size relation between the total length of the second wire and the total length of the first wire according to the size relation between the second total transmission delay and the first total transmission delay, the size relation between the first signal transmission rate and the second signal transmission rate, the relation between the total length of the first wire and the first signal transmission rate and the first total transmission delay, and the relation between the total length of the second wire and the second signal transmission rate and the second total transmission delay;
and determining a constraint condition of the total length of the second wire and an optimal constraint condition of the leading-out position of the second wire according to a lumped parameter method, a preset data frequency upper limit of the DDR signal and the initial size relation.
In some embodiments, a magnitude relationship between the second total transmission delay and the first total transmission delay is: the second total transmission delay is greater than or equal to the first total transmission delay.
In some embodiments, the obtaining the initial magnitude relation between the total length of the second trace and the total length of the first trace according to the magnitude relation between the second total transmission delay and the first total transmission delay, the magnitude relation between the first signal transmission rate and the second signal transmission rate, the relation between the total length of the first trace and the first signal transmission rate and the first total transmission delay, and the relation between the total length of the second trace and the second signal transmission rate and the second total transmission delay includes:
according to the second total transmission delay being greater than or equal to the first total transmission delay, the first signal transmission rate being equal to the second signal transmission rate, the total length of the first trace being equal to the product between the first signal transmission rate and the first total transmission delay, and the total length of the second trace being equal to the product between the second signal transmission rate and the second total transmission delay, the initial magnitude relation between the total length of the second trace and the total length of the first trace is obtained as follows: the total length of the second wire is greater than or equal to the total length of the first wire.
In some embodiments, the determining the constraint condition of the total length of the second trace according to the lumped parameter method, the preset data frequency upper limit of the DDR signal, and the initial size relationship includes:
determining the wavelength according to the preset data frequency upper limit and the light speed of the DDR signal;
and determining the constraint condition of the total length of the second wire according to the relation among the wavelength, the initial size relation and the relation between the length of the wire and the signal attenuation degree by adopting a lumped parameter method.
In some embodiments, the constraint of the total length of the second trace includes:
；
；
wherein,representing the total length of said first trace, < >>Representing the total length of the second trace, < >>Representing the speed of light,/->Representing the upper limit of the frequency of the preset data, < >>Representing the wavelength;
the optimal constraint condition of the lead-out position of the second wiring comprises: and one end of the second wire, which is not connected with the termination resistor, is led out from the first welding bump.
In some embodiments, when a first die and a second die are included in the control chip, the target PAD is each PAD of a first PAD of the first die and a second PAD of the second die; when the control chip comprises the first bare chip or the second bare chip, the target PAD is the first PAD or the second PAD; wherein the packaging technology adopted by the first bare chip and the second bare chip is different.
In some embodiments, when the bare chip is packaged by a Wire Bond packaging process, determining a total length of a first trace between a target PAD of the bare chip in the control chip and a first solder bump on a circuit package substrate of the control chip includes:
acquiring the length of a Wire Bonding line between a target PAD of a bare chip in the control chip and a Finger endpoint on a circuit package substrate of the control chip from a package design file；
Obtaining the length of Trace line between the Finger terminal and the first solder bump on the circuit package substrate from the package design file；
Will beAnd->And, as the total length of the first trace between the target PAD and the first solder bump on the circuit package substrate.
In some embodiments, when the bare Chip is packaged by a Flip Chip packaging process, determining the total length of the first trace between the target PAD of the bare Chip in the control Chip and the first solder bump on the circuit package substrate of the control Chip includes:
obtaining the length of the wiring between the target PAD of the bare chip in the control chip and a second welding bump on the control chip from the packaging design file；
Acquiring the length of the wiring between the second welding convex point and the first welding convex point on the circuit packaging substrate from the packaging design file；
Will beAnd->And taking the total length of the first wire between the target PAD and the first welding convex point on the circuit package substrate as the total length of the first wire.
An electronic device, comprising: the device comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are communicated with each other through the communication bus;
the memory is used for storing a computer program;
the processor is used for realizing the steps of the DDR signal Rtt terminating PCB board level layout wiring constraint method when executing the program stored in the memory.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, when the DDR signal is subjected to the Rt termination layout wiring at the PCB level, the constraint condition of the total length of the section of wiring between one welding convex point of the control chip and the termination resistor and the optimal constraint condition of the leading-out position of one end of the section of wiring which is not connected with the termination resistor are determined through quantitative analysis and calculation, and the constraint condition is used for constraining the section of wiring in the layout wiring, so that the signal integrity allowance of the signal in the high-speed data transmission process can be improved, the reliability of the data transmission in the PCB is improved, and the accurate layout design guidance is provided for the termination of the DDR on the PCB in engineering.
The present invention will be described in further detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a schematic flow diagram of a method for restricting a layout and wiring of a board level of a PCB terminated by a DDR signal rt according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an exemplary DDR signal transmission link provided by an embodiment of the invention;
FIG. 3 is a schematic representation of the results of an exemplary signal integrity transient simulation experiment provided by an embodiment of the present invention;
FIG. 4 is a first resulting schematic of an exemplary signal integrity eye simulation experiment provided by an embodiment of the present invention;
FIG. 5 is a second resulting schematic of an exemplary signal integrity eye simulation experiment provided by an embodiment of the present invention;
FIG. 6 is a third resulting schematic of an exemplary signal integrity eye simulation experiment provided by an embodiment of the present invention;
FIG. 7 is a fourth resulting schematic of an exemplary signal integrity eye simulation experiment provided by an embodiment of the present invention;
fig. 8 is a fifth resulting schematic of an exemplary signal integrity eye simulation experiment provided by an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Fig. 1 is a flow chart of a method for restricting a layout and wiring of a board level of a DDR signal rt terminated PCB, which includes:
s101, determining the total length of a first wire between a target PAD of a bare chip in a control chip and a first welding bump on a circuit packaging substrate of the control chip; the control chip is located on the PCB.
Here, PAD refers to an input/output port of a chip.
Here, the first solder bump is any one of solder bumps on the circuit package substrate of the control chip, and for example, may be one solder bump at an edge position of the circuit package substrate of the control chip.
In some embodiments, when the first die and the second die are included in the control chip, the target PAD is each PAD of the first die and the second PAD of the second die. In some embodiments, when the first die or the second die is included in the control chip, the target PAD is the first PAD or the second PAD. The packaging technology adopted by the first bare chip and the second bare chip is different; for example, a first die is packaged using a Wire Bond packaging process, and a second die is packaged using a Flip Chip packaging process. The first PAD is a PAD of the first bare chip for transmitting DDR signals, and the second PAD is a PAD of the second bare chip for transmitting DDR signals.
Here, the total length of the first trace is determined according to the specific trace (i.e. the transmission link of the DDR signal in the control chip) between the target PAD of the bare chip and the first solder bump on the circuit package substrate when the control chip is packaged. For example, when the bare chip is packaged by a Wire Bond packaging process, the routing between the target PAD of the bare chip and the first solder bump on the circuit package substrate is specifically: the length of the Wire Bonding line between the target PAD and a Finger terminal on the circuit package substrate of the control chip and the Trace line between the Finger terminal and the first solder bump on the circuit package substrate are obtained from the package design fileAnd obtaining the length of Trace line between the Finger terminal and the first solder bump on the circuit package substrate from the package design file>Afterwards, will->And->And, as a total length of the first wiring between the target PAD and the first solder bump on the circuit package substrate +.>. For another example, when the bare Chip is packaged by using Flip Chip packaging technology, and the routing between the target PAD of the bare Chip and the first solder bump on the circuit package substrate is specifically: target PAD and controlThe length of the wiring between the target PAD of the bare chip in the control chip and the second solder bump on the control chip is obtained from the packaging design file>And obtaining the length of the wiring between the second welding convex point and the first welding convex point on the circuit package substrate from the package design file>Afterwards, will->And->And, as a total length of the first wiring between the target PAD and the first solder bump on the circuit package substrate +.>. Specifically, the second welding bump is one welding bump used for transmitting DDR signals on the control chip.
S102, determining a first total transmission delay on the first wiring according to the total length of the first wiring.
For example, continuing with the above example, when the first trace is formed of a length ofThe wiring and length of (2) are->The length of the wiring structure is +.>Can calculate the length as +.>Signal transmission on wiring of (a)Delay of delivery->And calculate length to be +.>Signal transmission delay on the wiring of (2)>Thereby obtaining a length +.>Is the total transmission delay of the first wire (called the first total transmission delay)>。
As another example, continuing with the above example, when the first trace is formed of a length ofThe wiring and the length of (a) areThe length of the wiring structure is +.>Can calculate the length as +.>Signal transmission delay on the wiring of (2)>And calculate length to be +.>Signal transmission delay on the wiring of (2)>Thereby obtaining a length +.>Total transmission delay of the first trace of (a)Time (called first total transmission delay)/(time delay)>。
Specifically, the formula for calculating the signal transmission delay of one wire is as follows:，/>wherein->Indicating the signal transmission rate on the trace, < >>Dielectric constant, which represents free space, ">Indicating the relative dielectric constant of the material of the trace, < >>Representing the magnetic permeability of free space->Indicating the relative permeability of the material of the track,/->Representing the length of the trace, +.>Representing the signal transmission delay of the trace.
S103, determining the magnitude relation between the second total transmission delay and the first total transmission delay on a second wiring between the first welding convex point and one end, which is not connected with a voltage source, of the termination resistor according to the characteristic that the termination resistor absorbs the reflected signal at the extreme end of the transmission link of the DDR signal; the first solder bump is the only point on the circuit package substrate that is connected to the termination resistor.
Specifically, in order for the termination resistor to absorb the reflected signal at the very end of the transmission link of the DDR signal, it is necessary to delay the second total transmission on the second traceAnd a first total transmission delay->The size relation between the two is as follows: />For example, a +>Is->Or->。
S104, determining the signal transmission rate on the wiring inside the control chip to obtain a first signal transmission rate, and determining the signal transmission rate on the wiring inside the PCB to obtain a second signal transmission rate.
Specifically, the above formula can be adoptedCalculating the signal transmission rate on the wiring inside the PCB, and taking the calculated signal transmission rate as a second signal transmission rate +.>And calculating the signal transmission rate on the internal wiring of the control chip by using the formula, and taking the calculated signal transmission rate as a first signal transmission rate +.>。
S105, obtaining an initial size relation between the total length of the second wire and the total length of the first wire according to the size relation between the second total transmission delay and the first total transmission delay, the size relation between the first signal transmission rate and the second signal transmission rate, the relation between the total length of the first wire and the first signal transmission rate and the first total transmission delay, and the relation between the total length of the second wire and the second signal transmission rate and the second total transmission delay.
Specifically, the total length of the first wireAnd a first signal transmission rate->And a first total transmission delay->The relation between the two is: />The method comprises the steps of carrying out a first treatment on the surface of the The total length of the second trace->And a second signal transmission rate->And a second total transmission delay->The relation between the two is: />The method comprises the steps of carrying out a first treatment on the surface of the Since DDR interface engineering can be approximated as:therefore, the total length of the first trace +.>Total length of the second wiring>The initial size relation between (i.e. total length of the second trace +.>Initial conditions that need to be met) are: />。
S106, determining a constraint condition of the total length of the second wiring and an optimal constraint condition of the leading-out position of the second wiring according to the lumped parameter method, the preset data frequency upper limit of the DDR signal and the initial size relation.
Specifically, the upper limit of the preset data frequency of the DDR signal can be utilizedAnd light speed +.>Determining wavelength->Then, the lumped parameter method is adopted according to the wavelength +.>Relation of initial size->And the relation between the length of the track and the degree of signal attenuation, determining the total length of the second track +.>Is a constraint on (c).
Specifically, the highest data frequency of DDR signals is determined according to actual design requirementsFor example, the first and second substrates may be coated, for example,since the data signal contains abundant high frequency components, there are: />Then according to the formulaThe formula can be obtained: />. Further, it will be less than +_ according to signal integrity engineering>The routing of (2) is approximately lumped parameters, and is therefore dependent on +.>The total length of the second trace can be obtained>One of the constraints of (2) is:. Further, due to the->Too long results in excessive attenuation of the signal, and therefore, the signal integrity engineering will continue to be less than +.>The trace of (2) is approximated as a lumped parameter, thereby obtaining the total length of the second trace +.>The second constraint of (2) is: />The method comprises the steps of carrying out a first treatment on the surface of the Finally, the total length of the second wiring is obtained>The constraint conditions of (2) are:。
after obtaining the total length of the second wiringAfter the constraint of (2), according to the constraint, it is known, <' > about->And->In positive correlation, also because +_ when the end of the second trace not connected with the termination resistor is led out from the first solder bump>The shortest, therefore, the optimal constraint condition for the final lead-out position of the second trace is: one end of the second wire, which is not connected with the terminating resistor, is led out from the first welding convex point.
Here, the constraint applies to termination routing scenarios for all signal types in DDR, e.g., unidirectional transmission control address lines (CA signals) and bidirectional transmission data/clock lines (DQ/DQs signals), etc.
According to the invention, when the DDR signal is subjected to the Rt termination layout wiring at the PCB level, the constraint condition of the total length of the section of wiring between one welding convex point of the control chip and the termination resistor and the optimal constraint condition of the leading-out position of one end of the section of wiring which is not connected with the termination resistor are determined through quantitative analysis and calculation, and the constraint condition is used for constraining the section of wiring in the layout wiring, so that the signal integrity allowance of the signal in the high-speed data transmission process can be improved, the reliability of the data transmission in the PCB is improved, and the accurate layout design guidance is provided for the termination of the DDR on the PCB in engineering.
The constraint method of the present invention is further described below by way of a specific example.
FIG. 2 is a schematic diagram of a DDR transmission link, as shown in FIG. 2, a controller chip (i.e. the control chip described above) and a DRAM chip are disposed on a PCB board, and there is no ODT function module in the DDR interface of the controller chip, the controller chip and the DRAM chip are packaged chips, and the controller chip includes a first bare chip DIE1 and a second bare chip DIE2, so as toAnd a circuit package Substrate-PKG. DIE1 is packaged using a Wire Bond packaging process, and DIE1 has multiple PADs, e.g., PADA, PADB, PADC, PADD. DIE2 is packaged using Flip Chip packaging process and DIE2 has multiple PADs, e.g., PADE, PADF, PADG, PADH. As shown in fig. 2, one unidirectional transmission link of the DDR signal is: starting from the PADA of DIE1, a pass length ofTo a Finger end point of the submount-PKG, starting from the Finger end point of the submount-PKG, through a length +.>To a Solder Ball at the edge position of the Substrate-PKG, then starting from the Solder Ball at the edge position of the Substrate-PKG, through a length of +.>To a termination resistor Rtt (the other end of the termination resistor Rtt is connected to a termination voltage source VTT) and starting from this Solder Ball at the edge position of the Substrate-PKG, through a length of +.>To the PADA of the DRAM chip, wherein the PADA of the DRAM chip is a Solder Ball. Another unidirectional transmission link of the DDR signal is: starting from the PADE of DIE2, the length is +.>To a Solder Bump, then from the Solder Bump through a length +.>To another Solder Ball at the edge position of the Substrate-PKG, then starting from this Solder Ball at the edge position of the Substrate-PKG, through a length of +.>The routing of (a) reaches the termination resistor Rtt, and starting from this Solder Ball at the edge position of the Substrate-PKG, the transit length is +.>To the pad of the DRAM chip. Due to->、/>、/>And->The length of (a) is already determined when packaging the controller chip, and for +.>And->There is also a special constraint method in the industry, so that only +.>And->Is of length +.>Or->The optimal constraint condition of the lead-out position of the wiring of the (C) is obtained. Determine->And->Is of length +.>Or->The method of optimizing the constraint condition of the lead-out position of the wiring of (a) is to determine +.>Constraint on length and determination of length +.>A method of optimizing constraints on lead-out positions of the tracks. Specifically, the determined->The constraint conditions of (2) are: />，/>The method comprises the steps of carrying out a first treatment on the surface of the Determined->The constraint conditions of (2) are: />，/>The method comprises the steps of carrying out a first treatment on the surface of the Length of->The optimal constraint conditions of the lead-out positions of the wiring of (a) are as follows: as shown in FIG. 2, the length is +.>One end of the trace of (1) which is not connected with the termination resistor Rtt is led out from one Solder Ball of the Substrate-PKG in figure 2; length of->The optimal constraint conditions of the lead-out positions of the wiring of (a) are as follows: as shown in fig. 2Length of->The end of the trace not connected to the termination resistor Rtt is led from the other Solder Ball of the Substrate-PKG in fig. 2.
In order to further explain the technical effects achieved by the constraint conditions determined by the invention, the invention respectively performs a signal integrity transient simulation experiment and an eye diagram simulation experiment through layout and wiring, wherein experimental parameters and simulation results of the signal integrity transient simulation experiment are shown in table 1 and fig. 3, and experimental parameters and simulation results of the signal integrity eye diagram simulation experiment are shown in table 2 and fig. 4-fig. 8.
TABLE 1
In fig. 3, the smaller the overshoot and collapse relative, the smaller the representative reflection, the better the signal quality, and the collapse value is preferentially measured under this interface, obviously whenWhen the signal quality is optimal.
TABLE 2
In fig. 4-8, the more eye pattern templates, the more severe the signal integrity degradation is, and the templates in fig. 4-8 are rectangular frames in the middle of each of fig. 4-8, obviously, when、/>、The eye pattern is not templated and thus the signal quality is good.
It should be noted that the terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying a number of technical features being indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
In the description, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. Some measures are described in mutually different embodiments, but this does not mean that these measures cannot be combined to produce a good effect.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (5)
1. A DDR signal rt terminated PCB board level place and route constraint method, the method comprising:
determining the total length of a first wire between a target PAD of a bare chip in a control chip and a first welding bump on a circuit packaging substrate of the control chip; the control chip is positioned on the PCB;
determining a first total transmission delay on the first wiring according to the total length of the first wiring;
determining a size relation between a second total transmission delay and the first total transmission delay on a second wiring between the first welding convex point and one end, which is not connected with a voltage source, of the termination resistor according to the characteristic that the termination resistor absorbs reflected signals at the tail end of a transmission link of the DDR signal; the first welding convex point is the only point connected with the termination resistor on the circuit packaging substrate; the magnitude relation between the second total transmission delay and the first total transmission delay is: the second total transmission delay is greater than or equal to the first total transmission delay;
determining the signal transmission rate on the internal wiring of the control chip to obtain a first signal transmission rate, and determining the signal transmission rate on the internal wiring of the PCB to obtain a second signal transmission rate;
according to the second total transmission delay being greater than or equal to the first total transmission delay, the first signal transmission rate being equal to the second signal transmission rate, the total length of the first trace being equal to the product between the first signal transmission rate and the first total transmission delay, and the total length of the second trace being equal to the product between the second signal transmission rate and the second total transmission delay, the initial magnitude relation between the total length of the second trace and the total length of the first trace is obtained as follows: the total length of the second wire is greater than or equal to that of the first wire;
determining the wavelength according to the preset data frequency upper limit and the light speed of the DDR signal;
determining a constraint condition of the total length of the second wire and an optimal constraint condition of the lead-out position of the second wire according to the wavelength, the initial size relation and the relation between the length of the wire and the signal attenuation degree by adopting a lumped parameter method;
wherein, the constraint condition of the total length of the second wire comprises:
wherein L is pkg Representing the total length of the first wiring, L tt Representing the total length of the second trace, C representing the speed of light, F bit Representing the preset data frequency upper limit, and lambda represents the wavelength;
the optimal constraint condition of the lead-out position of the second wiring comprises: and one end of the second wire, which is not connected with the termination resistor, is led out from the first welding bump.
2. The DDR signal rt terminated PCB board level place and route constraint method of claim 1, wherein when a first die and a second die are included in the control chip, the target PAD is each of a first PAD of the first die and a second PAD of the second die; when the control chip comprises the first bare chip or the second bare chip, the target PAD is the first PAD or the second PAD; wherein the packaging technology adopted by the first bare chip and the second bare chip is different.
3. The method of claim 1, wherein determining a total length of a first trace between a target PAD of a bare chip in a control chip and a first solder bump on a circuit package substrate of the control chip when the bare chip is packaged using a Wire Bond packaging process comprises:
acquiring a target PAD of a bare chip in the control chip and the control chip from a packaging design fileLength L of Wire Bonding line between Finger terminals on circuit package substrate a1 ；
Acquiring the length L of Trace line between the Finger terminal and the first solder bump on the circuit package substrate from the package design file a2 ；
Will L a1 And L is equal to a2 And, as the total length of the first trace between the target PAD and the first solder bump on the circuit package substrate.
4. The method of claim 1, wherein determining a total length of a first trace between a target PAD of a die in a control Chip and a first solder bump on a circuit package substrate of the control Chip when the die is packaged using a Flip Chip packaging process comprises:
acquiring the length L of a wiring between a target PAD of a bare chip in the control chip and a second welding bump on the control chip from a packaging design file e1 ；
Acquiring the length L of the wiring between the second welding convex point and the first welding convex point on the circuit packaging substrate from the packaging design file e2 ；
Will L e1 And L is equal to e2 And taking the total length of the first wire between the target PAD and the first welding convex point on the circuit package substrate as the total length of the first wire.
5. An electronic device comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;
the memory is used for storing a computer program;
the processor is configured to implement the method steps of any of claims 1-4 when executing a program stored on a memory.
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