CN117408212A - Layout method, device, equipment and storage medium for elements on printed circuit board - Google Patents
Layout method, device, equipment and storage medium for elements on printed circuit board Download PDFInfo
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- 238000012545 processing Methods 0.000 claims abstract description 90
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- 230000000007 visual effect Effects 0.000 claims description 18
- 238000012216 screening Methods 0.000 claims description 7
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
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- G06F2115/00—Details relating to the type of the circuit
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Abstract
The application belongs to the technical field of PCB layout design, and particularly relates to a layout method, device, equipment and storage medium of elements on a printed circuit board. According to the method, element data corresponding to a plurality of elements on a printed circuit board are obtained, a network table corresponding to the printed circuit board is generated according to the element data and a schematic diagram, connection states among the elements are determined according to the network table, an element guide diagram is generated according to the connection states and the element data corresponding to each element, the position relation between each element in the elements and other elements is determined according to the element guide diagram, and the elements are subjected to regional layout processing according to the position relation and the corresponding distance parameters to obtain a layout of the printed circuit board.
Description
Technical Field
The application belongs to the technical field of PCB layout design, and particularly relates to a layout method, device, equipment and storage medium of elements on a printed circuit board.
Background
A printed circuit board (Printed Circuit Board, abbreviated as PCB) is one of the important components of the electronics industry. The PCB is used as a support body of the electronic components, can replace complex wiring, and realizes the electrical connection among the electronic components in the circuit. The PCB consists of an insulating bottom plate, connecting wires and bonding pads for assembling and welding electronic elements, and has the dual functions of a conductive circuit and the insulating bottom plate. In the process of designing a PCB, improper layout causes circuit compatibility problems and signal integrity problems of the PCB, thereby causing failure of PCB design and affecting the manufacturing efficiency of the PCB.
In order to solve the problem that improper PCB layout can cause circuit compatibility problem and signal integrity problem of the PCB, the prior art proposes an automatic PCB layout method, layout patterns are randomly generated through PCB layout software, and the positions and directions of all electronic components in the randomly generated PCB layout are also random.
However, the existing automatic layout method of the PCB cannot automatically classify and layout the components according to different areas according to the performance of the circuit module; meanwhile, the existing automatic layout method of the PCB cannot realize the adjustment and optimization of the layout based on the influence of the layout distance between elements on the electrical performance of the elements in the layout process.
Disclosure of Invention
The application provides a layout method, a device, equipment and a storage medium of elements on a printed circuit board, which are used for solving the problem that the existing automatic layout method of a PCB can not automatically classify and layout the elements according to different areas according to the performance of a circuit module; meanwhile, the problem of adjusting and optimizing the layout based on the influence of the layout distance between the elements on the electrical performance thereof in the layout process cannot be realized.
In a first aspect, the present application provides a method for layout of components on a printed circuit board, the method comprising:
acquiring element data corresponding to a plurality of elements on a printed circuit board, and generating a network table corresponding to the printed circuit board according to the element data and a schematic diagram, wherein the network table is used for indicating the electrical connection relation among the elements;
determining connection states among the plurality of elements according to the network table, and generating an element attraction map according to the connection states and element data corresponding to each element, wherein the element attraction map is used for indicating position parameters and distance parameters between two elements with the connection states;
and determining the position relation between each element and other elements in the plurality of elements according to the element map, and carrying out regional layout processing on the plurality of elements according to the position relation and the corresponding distance parameters to obtain the layout of the printed circuit board.
Optionally, the generating an element map according to the connection state and the element data corresponding to each element includes:
inputting a plurality of elements and the connection state into an initial gravitational model to obtain an element visual view comprising the plurality of elements;
determining the length of a connecting line between any two elements according to element data corresponding to the any two elements with the connecting state;
the component map is generated based on the component view and the lengths of the plurality of connection lines.
Optionally, the determining, according to the netlist, a connection state between the plurality of elements includes:
traversing a plurality of sub-networks in the network table to obtain a plurality of corresponding elements in each sub-network;
screening the corresponding elements in each sub-network to eliminate repeated elements in the corresponding elements of the sub-network so as to obtain a plurality of target elements;
and performing connection processing on the plurality of target elements to obtain a connection state among the plurality of elements.
Optionally, the performing a regional layout process on the multiple elements according to the position relationship and the corresponding distance parameter to obtain a layout of the printed circuit board, including:
According to the position relation, dividing the printed circuit board into a plurality of areas;
and carrying out regional layout processing on the multiple elements according to the multiple areas and the distance parameters between any two elements with connection states in each area to obtain a printed circuit board layout.
Optionally, the performing a regional layout process on the multiple elements according to the multiple regions and distance parameters between any two elements in each region, where the distance parameters exist in a connection state, to obtain a layout of a printed circuit board, where the method includes:
according to the connection state between the elements corresponding to each region, determining a core element, wherein the core element is the element with the largest number of other elements connected in the corresponding region;
marking the core element, and performing preferential layout processing on the core element in a corresponding area on the printed circuit board;
and after the preferential layout processing is completed, performing layout processing on other elements in the corresponding area to obtain a printed circuit board layout.
Optionally, the performing layout processing on the other elements in the corresponding area to obtain a layout of the printed circuit board includes:
And carrying out layout processing on other elements according to the layout positions of the core elements and the distance parameters between the core elements and the other elements to obtain a printed circuit board layout.
In a second aspect, the present application provides a layout apparatus for components on a printed circuit board, the apparatus comprising:
the acquisition module is used for acquiring element data corresponding to a plurality of elements on the printed circuit board;
the generating module is used for generating a network table corresponding to the printed circuit board according to the plurality of element data and the schematic diagram, and the network table is used for indicating the electrical connection relation among the plurality of elements;
the processing module is used for determining the connection state among the plurality of elements according to the network table, and generating an element attraction map according to the connection state and element data corresponding to each element, wherein the element attraction map is used for indicating the position parameter and the distance parameter between two elements with the connection state;
the processing module is further configured to determine a positional relationship between each element of the plurality of elements and other elements according to the element map, and perform regional layout processing on the plurality of elements according to the positional relationship and the corresponding distance parameters, so as to obtain a layout of the printed circuit board.
Optionally, the processing module is further configured to input a plurality of elements and the connection states into an initial gravitational model, and obtain an element visual view including the plurality of elements;
the processing module is further used for determining the length of a connecting line between any two elements according to element data corresponding to the any two elements with the connecting state;
the generation module is also used for generating the element guide diagram according to the element visual view and the lengths of the connecting lines.
Optionally, the processing module is further configured to perform traversal processing on multiple sub-networks in the network table to obtain multiple corresponding elements in each sub-network;
the processing module is further configured to perform screening processing on the corresponding element in each sub-network, so as to reject the repeated element in the element corresponding to the sub-network, and obtain a plurality of target elements;
the processing module is further configured to perform connection processing on the plurality of target elements, so as to obtain a connection state between the plurality of elements.
Optionally, the processing module is further configured to divide a region of the printed circuit board according to the position relationship to obtain a plurality of regions;
The processing module is further used for carrying out regional layout processing on the plurality of elements according to the plurality of areas and the distance parameter between any two elements with connection states in each area, so as to obtain a printed circuit board layout.
Optionally, the processing module is further configured to determine a core element according to a connection state between elements corresponding to each region, where the core element is an element with the largest number of other elements connected in the corresponding region;
the processing module is also used for carrying out marking processing on the core element and carrying out preferential layout processing on the core element in a corresponding area on the printed circuit board;
and the processing module is also used for carrying out layout processing on other elements in the corresponding area after the preferential layout processing is completed, so as to obtain the layout of the printed circuit board.
Optionally, the processing module is further configured to perform layout processing on the other elements according to the layout position of the core element and the distance parameter between the core element and the other elements, so as to obtain a layout of the printed circuit board.
In a third aspect, the present application provides a layout apparatus for components on a printed circuit board, comprising:
A memory;
a processor;
wherein the memory stores computer-executable instructions;
the processor executes the computer-executable instructions stored in the memory to implement the layout method of the components on the printed circuit board as described in the first aspect and the various possible implementation manners of the first aspect.
In a fourth aspect, the present application provides a storage medium having stored thereon computer-executable instructions that are executed by a processor to implement a layout method for components on a printed circuit board as described in the first aspect and various possible implementations of the first aspect.
According to the layout method of the elements on the printed circuit board, element data corresponding to a plurality of elements on the printed circuit board are obtained, the network table corresponding to the printed circuit board is generated according to the element data and the schematic diagram, the connection state among the elements is determined according to the network table, the element diagram is generated according to the connection state and the element data corresponding to each element, the position relation between each element in the elements and other elements is determined according to the element diagram, and the elements are subjected to regional layout processing according to the position relation and the corresponding distance parameters to obtain the layout of the printed circuit board.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
FIG. 1 is a flow chart of a method for layout of components on a printed circuit board provided by the present application;
FIG. 2 is a second flowchart of a layout method of components on a printed circuit board provided by the present application;
FIG. 3 is a schematic diagram of an element diagram provided herein;
FIG. 4 is a schematic layout of components on a printed circuit board provided herein;
fig. 5 is a schematic structural view of a layout device of components on a printed circuit board provided in the present application;
fig. 6 is a schematic structural diagram of a layout apparatus for components on a printed circuit board provided in the present application.
Specific embodiments thereof have been shown by way of example in the drawings and will herein be described in more detail. These drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is apparent that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein.
In the embodiments of the present application, words such as "exemplary" or "such as" are used to mean examples, illustrations, or descriptions. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
A printed circuit board (Printed Circuit Board, abbreviated as PCB) is one of the important components of the electronics industry. The PCB is used as a support body of the electronic components, can replace complex wiring, and realizes the electrical connection among the electronic components in the circuit. The PCB consists of an insulating bottom plate, connecting wires and bonding pads for assembling and welding electronic elements, and has the dual functions of a conductive circuit and the insulating bottom plate. In the process of designing a PCB, improper layout causes circuit compatibility problems and signal integrity problems of the PCB, thereby causing failure of PCB design and affecting the manufacturing efficiency of the PCB.
In order to solve the problem that improper PCB layout can cause circuit compatibility problem and signal integrity problem of the PCB, the prior art proposes an automatic PCB layout method, layout patterns are randomly generated through PCB layout software, and the positions and directions of all electronic components in the randomly generated PCB layout are also random.
However, the existing automatic layout method of the PCB cannot automatically classify and layout the components according to different areas according to the performance of the circuit module, for example, the analog circuit and the digital circuit are divided and laid out according to different areas, and the method is mainly implemented by layout by designers with abundant design experience; meanwhile, the existing automatic layout method of the PCB cannot be used for checking the layout distance between the elements in the layout process, namely, the layout cannot be optimized according to the influence of the electrical performance between the elements.
In view of the above problems, the present application provides a layout method of elements on a printed circuit board, which generates a corresponding network table according to a schematic diagram of the printed circuit board, obtains connection relations between elements in the network table through the network table, generates element guide diagrams corresponding to the network table according to connection relations between the elements, obtains a positional relation between each element and other elements in a plurality of elements according to the element guide diagrams, and performs regional layout processing on the plurality of elements according to the positional relation and corresponding distance parameters to obtain a layout of the printed circuit board.
The following describes the technical solutions of the present application and how the technical solutions of the present application solve the above technical problems in detail with specific embodiments. The following embodiments may be implemented independently or combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.
Fig. 1 is a flowchart of a layout method of elements on a printed circuit board according to an embodiment of the present application, as shown in fig. 1, the layout method of elements on a printed circuit board according to the embodiment includes:
s101, acquiring element data corresponding to a plurality of elements on a printed circuit board, and generating a network table corresponding to the printed circuit board according to the element data and the schematic diagram.
The schematic diagram is used for representing the connection principle among all elements on the printed circuit board, and the logic structure and the working principle of the circuit can be known through the schematic diagram; the netlist is used for indicating the electrical connection relation among the plurality of elements; the component data refers to information corresponding to the components stored in the component library, and the component data may include, for example: system code, functional attributes, type, specification model, manufacturer, etc.
It can be understood that the network table is a bridge and a tie for connecting the schematic diagram design and the printed circuit board design, and the connection between the elements can be quickly found through the network table corresponding to the schematic diagram, thereby providing convenience for the subsequent layout of the elements on the printed circuit board.
In this step, the component data corresponding to the plurality of components on the printed circuit board may be obtained, for example, through a component library, and identification information of the corresponding plurality of components may be obtained according to the plurality of component data, where the identification information may be used to indicate the corresponding components in the network table. Since the schematic diagram is used for representing the connection principle between the elements on the printed circuit board, and in order to embody the logic structure of the circuit, the elements in the schematic diagram are electrically connected, so that according to the data of the elements and the schematic diagram, a text file reflecting the electrical connection relation between the elements, namely, a network table corresponding to the schematic diagram of the printed circuit board, can be obtained.
S102, determining connection states among the elements according to the network table, and generating an element guide diagram according to the connection states and element data corresponding to each element.
The element gravitation graph is used for indicating a position parameter and a distance parameter between two elements with connection states, the position parameter is used for indicating the position of the elements on a virtual visual layout of the printed circuit board, and the distance parameter is used for indicating the distance between the two elements with connection states.
It will be appreciated that the netlist is generated by a plurality of element data and schematic diagrams, and the netlist includes electrical connection relationships between a plurality of elements, so that the connection states between the elements can be obtained according to the netlist, that is, the current connection relationship between each element in the netlist and other elements is determined, and the connection relationship can be obtained according to pins of the elements, for example, when the netlist includes three elements: when U1, U2 and U3 are used, the three elements are respectively connected in the current network table through the following pins: the third pin of the U3 element, the fourth pin and the ninth pin of the U2 element, and the eighth pin of the U1 element.
Because the element data corresponding to each element includes element information such as functional attributes and types corresponding to the elements, after the connection states among the elements in the network table are determined, the connection states and the element data corresponding to each element can be input into an initial attraction model of the elements, and an element attraction map capable of indicating position parameters and distance parameters among the elements in the network table is generated, wherein the distance parameters can be obtained through the electrical performance of the elements and the influence of the electrical performance on the layout distance among the elements.
S103, determining the position relation between each element and other elements in the plurality of elements according to the element diagram, and carrying out regional layout processing on the plurality of elements according to the position relation and the corresponding distance parameters to obtain the layout of the printed circuit board.
The location relation between each element in the element diagram and other elements can be obtained according to the location parameter of each element in the element diagram, and the area to which the elements belong is determined according to the location relation, the type of the area can be obtained by dividing the layout of the printed circuit board according to the module circuits with different functions, and the area can be, for example: a high-speed circuit region, a medium-speed circuit region, and a low-speed circuit region; a strong current region, a weak current region, and a radiation device region; analog circuit area, digital circuit area, etc.
It can be understood that, according to the positional relationship, a corresponding region to which each element of the plurality of elements belongs may be obtained, so after determining the corresponding region to which each element of the plurality of elements belongs, layout processing may be performed on each element in the region according to a distance parameter between each element in the region, and after the layout processing is completed, a corresponding local layout of the printed circuit board is obtained.
The purpose of this step is to perform a zoning layout process on the plurality of elements through the positional relationship between each element and other elements and the corresponding distance parameters, so as to avoid the mutual interference among the digital circuit, the analog circuit, the high-speed circuit, the low-speed circuit, and the like, affecting the reliability of the printed circuit board when different types of circuits are laid out on the same printed circuit board.
According to the layout method of the elements on the printed circuit board, element data corresponding to a plurality of elements on the printed circuit board are obtained, a network table corresponding to the printed circuit board is generated according to the element data and the schematic diagram, connection states among the elements are determined according to the network table, element guide diagrams are generated according to the connection states and the element data corresponding to each element, the position relation between each element in the elements and other elements is determined according to the element guide diagrams, and the elements are subjected to regional layout processing according to the position relation and the corresponding distance parameters to obtain the layout of the printed circuit board.
Fig. 2 is a flowchart second of a layout method of components on a printed circuit board according to an embodiment of the present application. The present embodiment is a detailed description of a layout method of elements on a printed circuit board based on the embodiment of fig. 1. As shown in fig. 2, the layout method of elements on a printed circuit board provided in this embodiment includes:
s201, acquiring element data corresponding to a plurality of elements on a printed circuit board, and generating a network table corresponding to the printed circuit board according to the element data and the schematic diagram.
Step S201 is similar to step S101 described above, and will not be described again.
S202, traversing the multiple sub-networks in the network table to obtain a plurality of corresponding elements in each sub-network.
Wherein the plurality of sub-networks refer to a plurality of local networks for composing a network table.
It can be understood that the netlist includes information such as types, serial numbers, packaging forms and connection relations among all elements in the schematic diagram corresponding to the printed circuit board, so as to realize complete description of the schematic diagram, and the description of the netlist includes the following two aspects: information of all elements, including element identification, element pins, packaging forms and the like; connection information of all sub-networks, including network names, network nodes, etc.
In this step, traversing refers to dividing the network table into a plurality of sub-networks, and accessing information of all nodes in the plurality of sub-networks, that is, sequentially accessing each node in each sub-network with different network names, where the nodes refer to corresponding elements in the sub-networks, and the number of nodes is the same as the number of all elements in the network table.
Optionally, editing names, descriptions, labels and connection relations of nodes corresponding to a plurality of elements in the plurality of sub-networks can be performed.
S203, screening the corresponding elements in each sub-network to eliminate repeated elements in the corresponding elements of the sub-network, thereby obtaining a plurality of target elements.
When the element names corresponding to each element in the sub-network appear for a plurality of times, screening the repeated element names of the same element, and only reserving one element name corresponding to the element, wherein the element corresponding to the element name is a target element, namely each element has only one corresponding element name.
It can be understood that when describing the connection relationship between the elements in the schematic diagram, since the elements can be electrically connected through different pins, and each element has one or more pins to facilitate connection with other elements, that is, one element has a connection relationship with multiple elements, so as to implement the functional attribute of the element in different types of functional circuits, and each element has and only has one element name as the identifier of the element, therefore, each element acquired from the network table may have multiple repeated element names, at this time, the repeated element names of the element may be removed, and only one element name corresponding to the element is reserved.
The aim of the step is to obtain a plurality of target elements by eliminating repeated elements in elements corresponding to the sub-network, so that the connection relationship between the elements is more visual and clear when the elements are connected to generate the element visible view.
For example, all the element names in the sub-network N1 can be obtained by step S202 as follows: u1, U2, U3, however, it can be known from the schematic diagram that, in reality, there are only three elements in the sub-network N1, because the fourth pin and the ninth pin of U2 are both in the sub-network N1, and the network table has a phenomenon of repeatedly describing the names of the elements in order to embody the electrical connection relationship between the elements, so in this step, by performing screening processing on the elements U1, U2, and U3, the repeated element names U2 in the elements are removed, and the target elements corresponding to the sub-network N1 are obtained as follows: u1, U2 and U3.
S204, connecting the plurality of target elements to obtain the connection state among the plurality of elements,
and the corresponding elements in each sub-network are screened to obtain a plurality of target elements in a plurality of sub-networks in the network table, and the plurality of target elements corresponding to all the sub-networks are connected to obtain the connection state between the plurality of elements corresponding to the network table.
For example, the connection processing may be performed on the plurality of target elements according to the connection relationships between the plurality of elements in the netlist, so as to obtain the connection states between the plurality of elements. For example, the connection states between the target elements U1, U2, U3 in the sub-network N1 are: u1 is connected with U2, U2 is connected with U3, U1 is connected with U3.
S205, inputting the plurality of elements and the connection state into an initial gravitation model to obtain an element visual view comprising the plurality of elements.
The initial attraction model is used for reflecting the influence of the distance between any two elements with connection states on the electrical performance of the elements, and the attraction magnitude of the two elements with connection states has an association relationship with the type of the elements.
The initial gravitational model may be calculated, for example, using the following formula:
where r is the distance between any two elements in a connected state, F is the attractive force between any two elements in a connected state, G is the attractive force constant, e.g. 1, m 1 And m 2 Is a value determined by the electrical properties of any two components.
It can be appreciated that, the elements in the netlist and the connection states of the elements are input into the initial gravity model, so that element visual views corresponding to the elements can be obtained, wherein the element visual views are used for visualizing the connection modes among the elements with the connection states in the netlist.
S206, determining the length of a connecting line between any two elements according to element data corresponding to the any two elements with the connection state.
The initial gravitation model is used for reflecting the influence of the distance between any two elements with connection states on the electrical performance of the elements, and the distance between the elements with the two connection states can be used for determining the length of a connecting line between any two elements with the connection states in the layout process of a printed circuit board, so that element data corresponding to any two elements with the connection states can be input into the initial gravitation model to obtain the length of the connecting line between the any two elements.
The length of the connecting line between any two elements where a connection state exists can be calculated, for example, using the following formula:
where r is the distance between any two elements in a connected state, i.e. the length of the connecting line, F is the attractive force between any two elements in a connected state, where F can be preset to a fixed value, G is the attractive force constant, e.g. 1, m can be taken as a value 1 And m 2 Is a value determined based on the electrical properties of any two components.
It will be appreciated that the component data, such as the electrical performance types and functional attributes, corresponding to the component in the different types of circuit areas may be obtained from the circuit library. Wherein, the different types of circuit areas can be: a high current circuit region and a low current circuit region; a high-speed current circuit region and a low-speed current circuit region; analog circuit area, digital circuit area. The purpose of classifying the components according to different types of circuit areas is to enable the adjustment and optimization of the layout based on the influence of the layout distance between the components on the electrical performance thereof in the subsequent layout of the components of the printed circuit board.
Table 1 shows the electrical performance classification of the elements provided in this example:
TABLE 1
As shown in Table 1, m is the circuit element in the different circuit area, when the circuit area on the printed circuit board is the strong and weak current circuit area, m 1 And m 2 For two elements in a connected state, where m is 1 And m 2 For elements of the same type of electrical performance, i.e. weak-current circuit elements or strong-current circuit elements, then m 1 ×m 2 >0, thereby knowing m 1 And m 2 The attraction force between the two is large, and m is the connection state 1 And m 2 The element distance between the two elements is relatively close; if m is 1 And m 2 For elements of different types of electrical properties, i.e. m 1 Is a weak current circuit element, m 2 Is a high-current circuit element or m 1 Is a high-current circuit element, m 2 Is a weak current circuit element, then m 1 ×m 2 <0, thereby knowing m 1 And m 2 The attraction between the two is small, and m is the connection state 1 And m 2 The element distance between them is far.
When the circuit area on the printed circuit board is a high-speed and low-speed current circuit area, m 1 And m 2 For two elements in a connected state, where m is 1 And m 2 For elements of the same type of electrical performance, i.e. high-speed current circuit elements or low-speed current circuit elements, then m 1 ×m 2 >0, thereby knowing m 1 And m 2 The attraction force between the two is large, and m is the connection state 1 And m 2 The element distance between the two elements is relatively close; if m is 1 And m 2 For elements of different types of electrical properties, i.e. m 1 Is a high-speed current circuit element, m 2 Is a low-speed current circuit element or m 1 Is a low-speed current circuit element, m 2 Is a high-speed current circuit element, m 1 ×m 2 <0, thereby knowing m 1 And m 2 The attraction between the two is small, and m is the connection state 1 And m 2 The element distance between them is far.
When the circuit area on the printed circuit board is an analog and digital circuit area, m 1 And m 2 For two elements in a connected state, where m is 1 And m 2 For elements of the same type of electrical performance, i.e. analogue or digital, then m 1 ×m 2 >0, thereby knowing m 1 And m 2 The attraction force between the two is large, and m is the connection state 1 And m 2 The element distance between the two elements is relatively close; if m is 1 And m 2 For elements of different types of electrical properties, i.e. m 1 For analogue circuit elements, m 2 Is a digital circuit element or m 1 Is a digital circuit element, m 2 For an analog circuit element, then m 1 ×m 2 <0, thereby knowing m 1 And m 2 The attraction between the two is small, and m is the connection state 1 And m 2 The element distance between them is far.
S207, generating the element guide diagram according to the element visual view and the lengths of a plurality of connecting lines.
The element visual view only represents the connection state between a plurality of elements in the netlist, and the length of a connecting line between the plurality of elements, namely the distance between any two elements with connection states, cannot be represented, so that the element visual view can be updated according to the length of the plurality of connecting lines to generate a corresponding element diagram, wherein the element diagram is used for representing the connection state between the plurality of elements in the netlist and the length of the connecting line between the plurality of elements in the connection state.
FIG. 3 is a schematic diagram of an element diagram provided in this embodiment, as shown in FIG. 3, in which a plurality of elements on the element diagram are in an interconnected state, each element may be electrically connected to one or more elements at the same time, the number of connection lines between a single element and other elements is the same as the number of other elements connected to the element, and the length of the connection lines may also be obtained from FIG. 3; for example, the resistor 2 is connected to the diode, the capacitor 1, the transformer and the resistor 1, wherein the length of the connection line between the resistor 2 and the diode is v, the length of the connection line between the resistor 2 and the capacitor 1 is 2v, the length of the connection line between the resistor 2 and the resistor 1 is v, and the length of the connection line between the resistor 2 and the transformer is v.
S208, determining the position relation between each element and other elements in the plurality of elements according to the element guide diagram.
Step S208 is similar to step S103 described above, and will not be described again.
S209, dividing the printed circuit board into a plurality of areas according to the position relation.
The location parameters of each element in the network table may be obtained according to the element gravitation graph, the location relation between each element and other elements may be determined according to the location parameters, and the areas to which the plurality of elements belong may be determined according to the location relation and the data of the electrical performance such as the functional attribute of each element, where the types of the areas may be: a high-speed circuit region, a medium-speed circuit region, and a low-speed circuit region; a strong current region, a weak current region, and a radiation device region; analog circuit area, digital circuit area, etc.
S210, carrying out regional layout processing on the plurality of elements according to the plurality of areas and the distance parameter between any two elements with connection states in each area, and obtaining the layout of the printed circuit board.
The element gravitation diagram is used for indicating the position parameter and the distance parameter between two elements with connection states, so that a plurality of elements in the layout of the printed circuit board can be subjected to area division according to the element gravitation diagram, a plurality of different circuit areas are obtained, and the elements are subjected to area division layout processing to obtain the layout of the printed circuit board.
The purpose of this step is to perform the area layout processing on the components, so as to avoid the mutual interference when different types of circuits work, and to influence the normal work of the circuits, for example, in a printed circuit board with both digital circuits and analog circuits, noise generated by the digital circuits can influence the analog circuits, so that the small signal index of the analog circuits is poor.
For example, a specific implementation manner of performing a regional layout process on the multiple elements according to the multiple regions and the distance parameter between any two elements with connection states in each region to obtain a layout of a printed circuit board is given here, for example:
according to the connection state between the elements corresponding to each region, determining a core element, wherein the core element is the element with the largest number of other elements connected in the corresponding region; marking the core element, and performing preferential layout processing on the core element in a corresponding area on the printed circuit board; and after the preferential layout processing is completed, performing layout processing on other elements in the corresponding area to obtain a printed circuit board layout.
Fig. 4 is a schematic layout diagram of elements on a printed circuit board according to the present embodiment, as shown in fig. 4, for example, the core element in the area may be a transistor Q1, and three pins, namely, a pin 1, a pin 2 and a pin 3, are included in the transistor Q1, so as to perform preferential layout processing on the core element Q1.
Optionally, the layout processing is performed on other elements in the corresponding area to obtain a layout of the printed circuit board, for example, the layout processing may be performed on the other elements according to the layout position of the core element and the distance parameter between the core element and the other elements to obtain the layout of the printed circuit board. With continued reference to fig. 4, after the preferential layout processing of the core element Q1 is completed, the layout processing may be performed on other elements connected to the core element according to the location of the core element Q1 and the distance parameters between the core element Q1 and the other elements until the layout of the printed circuit board is obtained. The directions of the distance parameters v and 2v may be any directions around the core element Q1, and fig. 4 is a schematic diagram of only one layout form.
Optionally, after the preferential layout processing for the core element, a rectangular area may be shown in a frame around the core element on the virtual visualization layout, where the vertical direction and the horizontal direction may identify an area range where other elements in the area may be placed, where the area range is obtained according to the distance parameter between the core element and the other elements.
According to the layout method of the components on the printed circuit board, the network table corresponding to the printed circuit board is generated according to the component data and the schematic diagram, the sub-networks in the network table are traversed to obtain the corresponding components in each sub-network, the corresponding components in each sub-network are screened to obtain the target components, the target components are connected to obtain the connection state among the components, the components and the connection state are input into the initial gravitation model to obtain the component visual view including the components, the component data corresponding to any two components with the connection state are obtained according to the component data corresponding to any two components, determining the length of a connecting line between any two elements, generating an element guide diagram according to the element visual view and the lengths of a plurality of connecting lines, determining the position relation between each element in the plurality of elements and other elements according to the element guide diagram, dividing the printed circuit board into a plurality of areas according to the position relation, and carrying out area layout processing on the plurality of elements according to the plurality of areas and the distance parameter between any two elements with connection states in each area to obtain a printed circuit board layout, wherein the method realizes automatic classification layout of the elements according to different areas according to the performance of a circuit module, and simultaneously solves the problem of adjusting and optimizing layout according to the influence of the layout distance between the elements on the electrical performance of the elements.
Fig. 5 is a schematic structural diagram of a layout device of components on a printed circuit board provided by the present application. As shown in fig. 5, the layout apparatus 300 of components on a printed circuit board according to the present embodiment includes:
an acquiring module 301, configured to acquire component data corresponding to a plurality of components on a printed circuit board;
a generating module 302, configured to generate a netlist corresponding to the printed circuit board according to a plurality of element data and a schematic diagram, where the netlist is used to indicate an electrical connection relationship between the plurality of elements;
a processing module 303, configured to determine a connection state between the plurality of elements according to the netlist, and generate an element attraction map according to the connection state and element data corresponding to each element, where the element attraction map is used to indicate a location parameter and a distance parameter between two elements having a connection state;
the processing module 303 is further configured to determine a positional relationship between each element of the plurality of elements and other elements according to the element map, and perform a regional layout process on the plurality of elements according to the positional relationship and the corresponding distance parameter, so as to obtain a layout of the printed circuit board.
Optionally, the processing module 303 is further configured to input a plurality of elements and the connection states into an initial gravitational model, and obtain an element visual view including the plurality of elements;
the processing module 303 is further configured to determine a length of a connection line between any two elements according to element data corresponding to the any two elements in which a connection state exists;
the generating module 302 is further configured to generate the element map according to the element visual view and lengths of the plurality of connection lines.
Optionally, the processing module 303 is further configured to perform traversal processing on a plurality of sub-networks in the network table to obtain a plurality of corresponding elements in each sub-network;
the processing module 303 is further configured to perform screening processing on the corresponding element in each sub-network, so as to reject the repeated element in the element corresponding to the sub-network, and obtain a plurality of target elements;
the processing module 303 is further configured to perform connection processing on the plurality of target elements, so as to obtain a connection state between the plurality of elements.
Optionally, the processing module 303 is further configured to divide a region of the printed circuit board according to the position relationship to obtain a plurality of regions;
The processing module 303 is further configured to perform a regional layout process on the multiple elements according to the multiple areas and the distance parameter between any two elements in each area, where the distance parameter is in a connection state, so as to obtain a layout of the printed circuit board.
Optionally, the processing module 303 is further configured to determine a core element according to a connection state between elements corresponding to each area, where the core element is an element with the largest number of other elements connected in the corresponding area;
the processing module 303 is further configured to perform marking processing on the core element, and perform preferential layout processing on the core element in a corresponding area on the printed circuit board;
the processing module 303 is further configured to perform layout processing on other elements in the corresponding area after the preferential layout processing is completed, so as to obtain a layout of the printed circuit board.
Optionally, the processing module 303 is further configured to perform layout processing on the other elements according to the layout position of the core element and the distance parameter between the core element and the other elements, so as to obtain a layout of the printed circuit board.
Fig. 6 is a schematic structural diagram of a layout apparatus for components on a printed circuit board provided in the present application. As shown in fig. 6, the present application provides a layout apparatus of components on a printed circuit board, the layout apparatus 400 of components on a printed circuit board including: a receiver 401, a transmitter 402, a processor 403 and a memory 404.
A receiver 401 for receiving instructions and data;
a transmitter 402 for transmitting instructions and data;
memory 404 for storing computer-executable instructions;
a processor 403, configured to execute computer-executable instructions stored in the memory 404, to implement the steps executed by the layout method of the components on the printed circuit board in the above embodiment. Reference is made in particular to the description of the embodiments of the layout method of the components on the printed circuit board described above.
Alternatively, the memory 404 may be separate or integrated with the processor 403.
When the memory 404 is provided separately, the electronic device further comprises a bus for connecting the memory 404 and the processor 403.
The application also provides a computer readable storage medium, in which computer executable instructions are stored, which when executed by a processor, implement a layout method of components on a printed circuit board as executed by the layout device of components on a printed circuit board.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include storage media (or non-transitory media) and communication media (or transitory media). The term storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
While the present application has been described in connection with the preferred embodiments illustrated in the accompanying drawings, it will be readily understood by those skilled in the art that the scope of the application is not limited to such specific embodiments, and the above examples are intended to illustrate the technical aspects of the application, but not to limit it; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. A method of layout of components on a printed circuit board, the method comprising:
acquiring element data corresponding to a plurality of elements on a printed circuit board, and generating a network table corresponding to the printed circuit board according to the element data and a schematic diagram, wherein the network table is used for indicating the electrical connection relation among the elements;
determining connection states among the plurality of elements according to the network table, and generating an element attraction map according to the connection states and element data corresponding to each element, wherein the element attraction map is used for indicating position parameters and distance parameters between two elements with the connection states;
And determining the position relation between each element and other elements in the plurality of elements according to the element map, and carrying out regional layout processing on the plurality of elements according to the position relation and the corresponding distance parameters to obtain the layout of the printed circuit board.
2. The method of claim 1, wherein generating the component map based on the connection state and the component data corresponding to each component comprises:
inputting a plurality of elements and the connection state into an initial gravitational model to obtain an element visual view comprising the plurality of elements;
determining the length of a connecting line between any two elements according to element data corresponding to the any two elements with the connecting state;
the component map is generated based on the component view and the lengths of the plurality of connection lines.
3. The method of claim 2, wherein determining the connection state between the plurality of elements from the netlist comprises:
traversing a plurality of sub-networks in the network table to obtain a plurality of corresponding elements in each sub-network;
screening the corresponding elements in each sub-network to eliminate repeated elements in the corresponding elements of the sub-network so as to obtain a plurality of target elements;
And performing connection processing on the plurality of target elements to obtain a connection state among the plurality of elements.
4. The method according to claim 2, wherein the performing the regional layout processing on the plurality of elements according to the positional relationship and the corresponding distance parameters to obtain a printed circuit board layout comprises:
according to the position relation, dividing the printed circuit board into a plurality of areas;
and carrying out regional layout processing on the multiple elements according to the multiple areas and the distance parameters between any two elements with connection states in each area to obtain a printed circuit board layout.
5. The method according to claim 4, wherein the performing the area layout processing on the plurality of elements according to the plurality of areas and the distance parameter between any two elements having connection states in each area to obtain the layout of the printed circuit board includes:
according to the connection state between the elements corresponding to each region, determining a core element, wherein the core element is the element with the largest number of other elements connected in the corresponding region;
Marking the core element, and performing preferential layout processing on the core element in a corresponding area on the printed circuit board;
and after the preferential layout processing is completed, performing layout processing on other elements in the corresponding area to obtain a printed circuit board layout.
6. The method of claim 5, wherein performing layout processing on other components in the corresponding area to obtain a printed circuit board layout, comprises:
and carrying out layout processing on other elements according to the layout positions of the core elements and the distance parameters between the core elements and the other elements to obtain a printed circuit board layout.
7. A layout apparatus for components on a printed circuit board, comprising:
the acquisition module is used for acquiring element data corresponding to a plurality of elements on the printed circuit board;
the generating module is used for generating a network table corresponding to the printed circuit board according to the plurality of element data and the schematic diagram, and the network table is used for indicating the electrical connection relation among the plurality of elements;
the processing module is used for determining the connection state among the plurality of elements according to the network table, and generating an element attraction map according to the connection state and element data corresponding to each element, wherein the element attraction map is used for indicating the position parameter and the distance parameter between two elements with the connection state;
The processing module is further configured to determine a positional relationship between each element of the plurality of elements and other elements according to the element map, and perform regional layout processing on the plurality of elements according to the positional relationship and the corresponding distance parameters, so as to obtain a layout of the printed circuit board.
8. The apparatus of claim 7, wherein the device comprises a plurality of sensors,
the processing module is further used for inputting the plurality of elements and the connection state into an initial gravitation model to obtain an element visual view comprising the plurality of elements;
the processing module is further used for determining the length of a connecting line between any two elements according to element data corresponding to the any two elements with the connecting state;
the generation module is also used for generating the element guide diagram according to the element visual view and the lengths of the connecting lines.
9. A layout apparatus for components on a printed circuit board, comprising:
a memory;
a processor;
wherein the memory stores computer-executable instructions;
the processor executes computer-executable instructions stored in the memory to implement the method of layout of components on a printed circuit board as claimed in any one of claims 1-6.
10. A storage medium having stored therein computer-executable instructions which, when executed by a processor, are adapted to carry out the method of layout of components on a printed circuit board as claimed in any one of claims 1 to 6.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311219379.0A CN117408212A (en) | 2023-09-20 | 2023-09-20 | Layout method, device, equipment and storage medium for elements on printed circuit board |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311219379.0A CN117408212A (en) | 2023-09-20 | 2023-09-20 | Layout method, device, equipment and storage medium for elements on printed circuit board |
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| CN117408212A true CN117408212A (en) | 2024-01-16 |
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| CN202311219379.0A Pending CN117408212A (en) | 2023-09-20 | 2023-09-20 | Layout method, device, equipment and storage medium for elements on printed circuit board |
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| CN (1) | CN117408212A (en) |
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- 2023-09-20 CN CN202311219379.0A patent/CN117408212A/en active Pending
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