CN117407322A - Method and device for realizing dual updating of mapping table of DRAM-less solid state disk - Google Patents
Method and device for realizing dual updating of mapping table of DRAM-less solid state disk Download PDFInfo
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- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0871—Allocation or management of cache space
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- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0873—Mapping of cache memory to specific storage devices or parts thereof
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- G06F2212/2022—Flash memory
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- G06F2212/21—Employing a record carrier using a specific recording technology
- G06F2212/214—Solid state disk
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Abstract
The application relates to a method, a device, computer equipment and a storage medium for realizing dual updating of a mapping table of a DRAM-less solid state disk, wherein the method comprises the following steps: acquiring a write request, distributing a physical address for the write request, and judging whether a mapping table corresponding to the write request is loaded or not; if the mapping table is loaded, the newly generated mapping table is recorded into a mapping temporary cache and updated into a mapping table, but the mapping table is not marked as dirty, and if the mapping table is not loaded, the mapping table is recorded into the temporary mapping cache and whether the temporary mapping cache is full is judged; triggering the temporary mapping buffer memory to merge and then write data into the NAND if the temporary mapping buffer memory is full, and directly writing the data into the NAND if the temporary mapping buffer memory is not full; acquiring a read request, and judging whether a mapping table corresponding to the read request is loaded; if not, the mapping table fragment is loaded from the NAND and checked if the temporary mapping cache is empty. The invention improves the random mixed read-write performance of the DRAM-less SSD in a large range.
Description
Technical Field
The invention relates to the technical field of solid state disks, in particular to a method, a device, computer equipment and a storage medium for realizing dual updating of a mapping table of a DRAM-less solid state disk.
Background
The DRAM-less SSD has a smaller mapping table that can be cached, and when the dirty mapping table cache exceeds a threshold, the dirty mapping needs to be written into NAND to ensure that the system has enough clean mapping cache available. For a large-range random writing scene, the mapping table to be accessed cannot be fully loaded into the RAM, and for the situation that the mapping table is not loaded, the mapping table is usually newly generated in the writing process to be used as a temporary cache, then mapping fragments are loaded from the NAND in batches and combined with the temporary mapping cache, and then written back to the NAND, so that the writing quantity of the mapping table is reduced, and the large-range random writing performance is improved.
However, for a mixed scenario of random read and write in a large range in the prior art, the read command may trigger merging of the mapping tables and generate a dirty mapping table in advance, which may further result in policy failure that is expected to write back NAND through batch mapping to reduce the writing amount of the mapping table.
Disclosure of Invention
Based on the above, it is necessary to provide a method, a device, a computer device and a storage medium for implementing dual updating of the mapping table of the DRAM-less solid state disk.
A method for realizing dual updating of a mapping table of a DRAM-less solid state disk comprises the following steps:
acquiring a write request, distributing a physical address for the write request, and judging whether a mapping table corresponding to the write request is loaded or not;
if the mapping table is loaded, the newly generated mapping table is recorded into a mapping temporary cache and updated into a mapping table, but the mapping table is not marked as dirty, and if the mapping table is not loaded, the mapping table is recorded into the temporary mapping cache and whether the temporary mapping cache is full is judged;
triggering the temporary mapping buffer memory to merge and then write data into the NAND if the temporary mapping buffer memory is full, and directly writing the data into the NAND if the temporary mapping buffer memory is not full;
acquiring a read request, and judging whether a mapping table corresponding to the read request is loaded;
if not, loading the mapping table fragments from the NAND and checking whether the temporary mapping buffer is empty;
and if the temporary mapping cache is empty, traversing the temporary mapping, merging the temporary mappings belonging to the current mapping table fragments, and simultaneously, not deleting the temporary mapping and marking the mapping fragments as dirty.
In one embodiment, after traversing the temporary mapping if the temporary mapping cache is empty, merging the temporary mappings belonging to the current mapping table fragment, and not deleting the temporary mapping nor marking the mapping fragment as dirty, the method further includes:
the mapping table is queried to obtain the physical address and data is read from the NAND.
In one embodiment, the method further comprises:
traversing all temporary mappings, and judging whether mapping fragments corresponding to the temporary mappings are loaded or not;
if the corresponding mapping fragment is loaded, marking the mapping fragment as dirty, and deleting all temporary mappings corresponding to the mapping fragment;
if the corresponding mapping fragment is not loaded, loading the corresponding mapping fragment from the NAND, merging all temporary mappings belonging to the mapping fragment into the mapping fragment, deleting the temporary mappings of the mapping fragment after merging is completed, and marking the mapping fragment as dirty.
In one embodiment, the method further comprises:
if all map slices are dirty, then the dirty map slices need to be stored to the NAND to free up clean map slices.
A device for realizing double updating of a mapping table of a DRAM-less solid state disk comprises:
the write request processing module is used for acquiring a write request and distributing a physical address for the write request, and judging whether a mapping table corresponding to the write request is loaded or not; if loaded, the newly generated map is recorded into a temporary map cache and updated into a map table, but the map table is not marked as dirty; if not, recording the mapping table to the temporary mapping cache and judging whether the temporary mapping cache is full; triggering the temporary mapping buffer memory to merge and then write data into the NAND if the temporary mapping buffer memory is full, and directly writing the data into the NAND if the temporary mapping buffer memory is not full;
the read request processing module is used for acquiring a read request and judging whether a mapping table corresponding to the read request is loaded or not; if not, loading the mapping table fragments from the NAND and checking whether the temporary mapping buffer is empty; and if the temporary mapping cache is empty, traversing the temporary mapping, merging the temporary mappings belonging to the current mapping table fragments, and simultaneously, not deleting the temporary mapping and marking the mapping fragments as dirty.
In one embodiment, the read request processing module is further configured to:
the mapping table is queried to obtain the physical address and data is read from the NAND.
In one embodiment, the apparatus further comprises a map merging module for:
traversing all temporary mappings, and judging whether mapping fragments corresponding to the temporary mappings are loaded or not;
if the corresponding mapping fragment is loaded, marking the mapping fragment as dirty, and deleting all temporary mappings corresponding to the mapping fragment;
if the corresponding mapping fragment is not loaded, loading the corresponding mapping fragment from the NAND, merging all temporary mappings belonging to the mapping fragment into the mapping fragment, deleting the temporary mappings of the mapping fragment after merging is completed, and marking the mapping fragment as dirty.
In one embodiment, the apparatus further comprises a map release module for:
if all map slices are dirty, then the dirty map slices need to be stored to the NAND to free up clean map slices.
A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of any one of the methods described above when the computer program is executed.
A computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of any of the methods described above.
The method, the device, the computer equipment and the storage medium for realizing double updating of the mapping table of the DRAM-less solid state disk can effectively avoid the situation that the mapping table is combined with temporary mapping in advance to generate a dirty mapping table in a read-write mixed scene. For the loaded scene of the mapping table, the newly generated mapping is recorded into a temporary cache and updated into the mapping table, but the mapping table is not marked as dirty; only after the temporary mapping buffer is full, a complete mapping table merging operation is performed, dirty mapping table fragments are generated in the merging process, and all temporary mappings are deleted after merging is completed. Therefore, the storage of the mapping table can be greatly reduced, and the mixing performance of large-range random reading and writing is greatly improved.
Drawings
FIG. 1 is a flow chart of a method for implementing dual updating of a mapping table of a DRAM-less solid state disk in one embodiment;
FIG. 2 is a flow diagram of a large-scale random write process flow in one embodiment;
FIG. 3 is a flow diagram of a large-scale random read process in one embodiment;
FIG. 4 is a flow diagram of a temporary map merge process in one embodiment;
FIG. 5 is a block diagram of a dual update implementation device for a mapping table of a DRAM-less solid state disk in one embodiment;
FIG. 6 is a block diagram of a dual update implementation device for a mapping table of a DRAM-less solid state disk in another embodiment;
FIG. 7 is a block diagram illustrating a dual update implementation of a mapping table for a DRAM-less solid state disk according to yet another embodiment;
fig. 8 is an internal structural diagram of a computer device in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
At present, the mapping table which can be cached by the DRAM-less SSD is smaller, for a large-range random writing scene, the mapping table which needs to be accessed cannot be fully loaded into the RAM, for a situation that the mapping table is not loaded, the mapping table is newly generated in the writing process and is used for temporary caching, then the mapping table is divided from the NAND loading mapping table in batches and combined with the temporary mapping table, and then written back into the NAND, so that the writing amount of the mapping table is reduced, and the large-range random writing performance is improved. However, for a mixed scenario of random read and write over a large area, the read command may trigger the merging of temporary mappings and generate dirty mapping table fragments in advance, resulting in policy failure that expects to write back NAND through batch merging of mapping fragments to reduce the amount of mapping table writing.
Based on the method, the invention provides a dual updating realization method of the mapping table of the DRAM-less solid state disk, which aims to improve the random mixed read-write performance of the DRAM-less SSD in a large range.
In one embodiment, as shown in fig. 1, a method for implementing dual updating of a mapping table of a DRAM-less solid state disk is provided, where the method includes:
102, acquiring a write request, distributing a physical address for the write request, and judging whether a mapping table corresponding to the write request is loaded or not;
104, if the mapping table is loaded, the newly generated mapping table is recorded into a mapping temporary cache and updated into a mapping table, but the mapping table is not marked as dirty, if the mapping table is not loaded, the mapping table is recorded into the temporary mapping cache, and whether the temporary mapping cache is full is judged;
step 106, triggering the temporary mapping buffer to merge and then write the data into the NAND if the temporary mapping buffer is full, and directly writing the data into the NAND if the temporary mapping buffer is not full;
step 108, acquiring a read request, and judging whether a mapping table corresponding to the read request is loaded;
step 110, if not, loading the mapping table fragments from the NAND and checking whether the temporary mapping buffer is empty;
and step 112, traversing the temporary mapping if the temporary mapping cache is empty, merging the temporary mapping belonging to the current mapping table fragments, and not deleting the temporary mapping nor marking the mapping fragments as dirty.
In this embodiment, a dual updating implementation method for a mapping table of a DRAM-less solid state disk is provided, where in a large-scale random mixed read-write scenario, for a scenario in which the mapping table is loaded, a newly generated mapping is recorded into a mapping temporary cache or updated into the mapping table, but the mapping table is not marked as dirty.
And for the scene needing to load the mapping table, after the mapping table is loaded and combined with the temporary buffer, the mapping temporary buffer is not deleted, and the combined mapping fragments are not marked as dirty.
In addition, for the mapping table fragments combined with the temporary mapping in advance, because one part of mapping information is also stored in the temporary mapping, the mapping table fragments can be kept in a clean state and can be directly reassigned for use without writing NAND.
Only after the temporary mapping buffer is full, a complete mapping table merging operation is performed, dirty mapping table fragments are generated and written into NAND after the merging operation is performed, and all temporary mapping is deleted after the merging operation is completed. And when the mixed scene of large-range random reading and writing is fully written in the temporary mapping buffer, the situation that the mapping table is frequently written in the NAND is avoided because of too many dirty mapping tables, so that the mixed performance of large-range random reading and writing is greatly improved.
Specifically, the method comprises a large-range random writing processing flow and a large-range random reading processing flow: referring to the flow diagram of the large-scale random write process flow shown in fig. 2, the method comprises the following steps:
and 2.1, distributing physical addresses.
Step 2.2, checking whether the mapping fragment corresponding to the logical address is loaded, and if not, go step 2.4.
Step 2.3, updating the mapping table (without marking dirty).
And 2.4, mapping the record to a temporary mapping cache.
And 2.5, triggering the temporary mapping cache merging if the temporary mapping cache is full.
Step 2.6, writing data into the NAND.
In one embodiment, after traversing the temporary map if the temporary map cache is empty, merging the temporary maps belonging to the current mapping table fragment, and not deleting the temporary map and not marking the mapping fragment as dirty, the method further comprises: the mapping table is queried to obtain the physical address and data is read from the NAND.
Specifically, referring to the flow chart of the large-scale random read processing flow shown in fig. 3, the method includes the following steps:
step 3.1, checking whether the mapping fragment corresponding to the logical address is loaded, and if so, loading goto step 3.5.
Step 3.2, loading the mapping slices from the NAND.
And 3.3, checking whether the temporary mapping buffer is empty, and if so, performing a goto step 3.5.
Step 3.4, merging the temporary mappings belonging to the mapping fragment (but not deleting the temporary mappings and marking the mapping fragment as dirty).
And 3.5, inquiring the mapping table to acquire the NAND address.
Step 3.6, reading data from the NAND.
In the above embodiment, the situation that the mapping table is combined with the temporary mapping in advance to generate the dirty mapping table in the read-write mixed scene can be effectively avoided. For the loaded scene of the mapping table, the newly generated mapping is recorded into a temporary cache and updated into the mapping table, but the mapping table is not marked as dirty; only after the temporary mapping buffer is full, a complete mapping table merging operation is performed, dirty mapping table fragments are generated in the merging process, and all temporary mappings are deleted after merging is completed. Therefore, the storage of the mapping table can be greatly reduced, and the mixing performance of large-range random reading and writing is greatly improved.
In one embodiment, a method for implementing dual updating of a mapping table of a DRAM-less solid state disk is provided, and the method further includes:
traversing all temporary mappings, and judging whether mapping fragments corresponding to the temporary mappings are loaded or not;
if the corresponding mapping fragment is loaded, marking the mapping fragment as dirty, and deleting all temporary mappings corresponding to the mapping fragment;
if the corresponding mapping fragment is not loaded, loading the corresponding mapping fragment from the NAND, merging all temporary mappings belonging to the mapping fragment into the mapping fragment, deleting the temporary mappings of the mapping fragment after merging is completed, and marking the mapping fragment as dirty;
if all map slices are dirty, then the dirty map slices need to be stored to the NAND to free up clean map slices.
Specifically, reference may be made to a flow chart of the temporary mapping merging flow shown in fig. 4, which includes the following implementation steps:
traversing all temporary mappings, if the corresponding mapping fragment is loaded, marking the mapping fragment as dirty, and deleting all temporary mappings corresponding to the mapping fragment; otherwise, loading the corresponding mapping fragment, deleting the corresponding temporary mapping after merging with all temporary mapping belonging to the mapping fragment, and marking the mapping fragment as dirty.
If all mapping slices are dirty in the process, the dirty mapping is required to be kept to NAND first, and clean mapping slices are released.
In this embodiment, only after the temporary mapping buffer is full, the complete mapping table merging operation is performed once, dirty mapping table fragments are generated in the merging process, and all temporary mapping is deleted after merging is completed, so that the large-scale random hybrid read-write performance of the DRAM-less SSD is improved.
It should be understood that, although the steps in the flowcharts of fig. 1-4 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in fig. 1-4 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the sub-steps or stages are performed necessarily occur in sequence, but may be performed alternately or alternately with at least a portion of the other steps or sub-steps or stages of other steps.
In one embodiment, as shown in fig. 5, there is provided a dual update implementation apparatus 500 for mapping tables of a DRAM-less solid state disk, the apparatus including:
the write request processing module 501 is configured to obtain a write request and allocate a physical address to the write request, and determine whether a mapping table corresponding to the write request is loaded; if loaded, the newly generated map is recorded into a temporary map cache and updated into a map table, but the map table is not marked as dirty; if not, recording the mapping table to the temporary mapping cache and judging whether the temporary mapping cache is full; triggering the temporary mapping buffer memory to merge and then write data into the NAND if the temporary mapping buffer memory is full, and directly writing the data into the NAND if the temporary mapping buffer memory is not full;
the read request processing module 502 is configured to obtain a read request, and determine whether a mapping table corresponding to the read request is loaded; if not, loading the mapping table fragments from the NAND and checking whether the temporary mapping buffer is empty; and if the temporary mapping cache is empty, traversing the temporary mapping, merging the temporary mappings belonging to the current mapping table fragments, and simultaneously, not deleting the temporary mapping and marking the mapping fragments as dirty.
In one embodiment, the read request processing module 502 is further configured to:
the mapping table is queried to obtain the physical address and data is read from the NAND.
In one embodiment, as shown in fig. 6, a dual update implementation apparatus 500 of a mapping table of a DRAM-less solid state disk is provided, where the apparatus further includes a mapping merging module 503, configured to:
traversing all temporary mappings, and judging whether mapping fragments corresponding to the temporary mappings are loaded or not;
if the corresponding mapping fragment is loaded, marking the mapping fragment as dirty, and deleting all temporary mappings corresponding to the mapping fragment;
if the corresponding mapping fragment is not loaded, loading the corresponding mapping fragment from the NAND, merging all temporary mappings belonging to the mapping fragment into the mapping fragment, deleting the temporary mappings of the mapping fragment after merging is completed, and marking the mapping fragment as dirty.
In one embodiment, as shown in fig. 7, a dual update implementation apparatus 500 for a mapping table of a DRAM-less solid state disk is provided, where the apparatus further includes a mapping release module 504 configured to:
if all map slices are dirty, then the dirty map slices need to be stored to the NAND to free up clean map slices.
The specific limitation of the device for implementing the dual updating of the mapping table of the DRAM-less solid state disk can be referred to the limitation of the method for implementing the dual updating of the mapping table of the DRAM-less solid state disk, and is not repeated herein.
In one embodiment, a computer device is provided, the internal structure of which may be as shown in FIG. 8. The computer device includes a processor, a memory, and a network interface connected by a device bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The nonvolatile storage medium stores an operating device, a computer program, and a database. The internal memory provides an environment for the operation of the operating device and the computer program in the non-volatile storage medium. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to realize a dual updating realization method of the mapping table of the DRAM-less solid state disk.
It will be appreciated by those skilled in the art that the structure shown in fig. 8 is merely a block diagram of some of the structures associated with the present application and is not limiting of the computer device to which the present application may be applied, and that a particular computer device may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided that includes a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the steps in the method embodiments above when executing the computer program.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when executed by a processor, carries out the steps of the above method embodiments.
Those skilled in the art will appreciate that implementing all or part of the above described embodiment methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the various embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A method for realizing dual updating of a mapping table of a DRAM-less solid state disk comprises the following steps:
acquiring a write request, distributing a physical address for the write request, and judging whether a mapping table corresponding to the write request is loaded or not;
if the mapping table is loaded, the newly generated mapping table is recorded into a mapping temporary cache and updated into a mapping table, but the mapping table is not marked as dirty, and if the mapping table is not loaded, the mapping table is recorded into the temporary mapping cache and whether the temporary mapping cache is full is judged;
triggering the temporary mapping buffer memory to merge and then write data into the NAND if the temporary mapping buffer memory is full, and directly writing the data into the NAND if the temporary mapping buffer memory is not full;
acquiring a read request, and judging whether a mapping table corresponding to the read request is loaded;
if not, loading the mapping table fragments from the NAND and checking whether the temporary mapping buffer is empty;
and if the temporary mapping cache is empty, traversing the temporary mapping, merging the temporary mappings belonging to the current mapping table fragments, and simultaneously, not deleting the temporary mapping and marking the mapping fragments as dirty.
2. The method for implementing dual updating of mapping table of DRAM-less solid state disk according to claim 1, wherein after traversing temporary mapping if temporary mapping buffer is empty, merging temporary mapping belonging to current mapping table fragments, and simultaneously not deleting temporary mapping nor marking mapping fragments as dirty, further comprising:
the mapping table is queried to obtain the physical address and data is read from the NAND.
3. The method for implementing dual updating of the mapping table of the DRAM-less solid state disk according to claim 2, further comprising:
traversing all temporary mappings, and judging whether mapping fragments corresponding to the temporary mappings are loaded or not;
if the corresponding mapping fragment is loaded, marking the mapping fragment as dirty, and deleting all temporary mappings corresponding to the mapping fragment;
if the corresponding mapping fragment is not loaded, loading the corresponding mapping fragment from the NAND, merging all temporary mappings belonging to the mapping fragment into the mapping fragment, deleting the temporary mappings of the mapping fragment after merging is completed, and marking the mapping fragment as dirty.
4. The method for implementing dual updating of the mapping table of the DRAM-less solid state disk of claim 3, further comprising:
if all map slices are dirty, then the dirty map slices need to be stored to the NAND to free up clean map slices.
5. The utility model provides a dual realization device that updates of mapping table of DRAM-less solid state hard disk which characterized in that, the device includes:
the write request processing module is used for acquiring a write request and distributing a physical address for the write request, and judging whether a mapping table corresponding to the write request is loaded or not; if loaded, the newly generated map is recorded into a temporary map cache and updated into a map table, but the map table is not marked as dirty; if not, recording the mapping table to the temporary mapping cache and judging whether the temporary mapping cache is full; triggering the temporary mapping buffer memory to merge and then write data into the NAND if the temporary mapping buffer memory is full, and directly writing the data into the NAND if the temporary mapping buffer memory is not full;
the read request processing module is used for acquiring a read request and judging whether a mapping table corresponding to the read request is loaded or not; if not, loading the mapping table fragments from the NAND and checking whether the temporary mapping buffer is empty; and if the temporary mapping cache is empty, traversing the temporary mapping, merging the temporary mappings belonging to the current mapping table fragments, and simultaneously, not deleting the temporary mapping and marking the mapping fragments as dirty.
6. The apparatus for implementing dual updating of mapping table of DRAM-less solid state disk of claim 5, wherein said read request processing module is further configured to:
the mapping table is queried to obtain the physical address and data is read from the NAND.
7. The apparatus for implementing dual updating of the mapping table of the DRAM-less solid state disk according to claim 6, further comprising a mapping merging module, wherein the mapping merging module is configured to:
traversing all temporary mappings, and judging whether mapping fragments corresponding to the temporary mappings are loaded or not;
if the corresponding mapping fragment is loaded, marking the mapping fragment as dirty, and deleting all temporary mappings corresponding to the mapping fragment;
if the corresponding mapping fragment is not loaded, loading the corresponding mapping fragment from the NAND, merging all temporary mappings belonging to the mapping fragment into the mapping fragment, deleting the temporary mappings of the mapping fragment after merging is completed, and marking the mapping fragment as dirty.
8. The apparatus for implementing dual updating of the mapping table of the DRAM-less solid state disk according to claim 7, further comprising a mapping release module, wherein the mapping release module is configured to:
if all map slices are dirty, then the dirty map slices need to be stored to the NAND to free up clean map slices.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any one of claims 1 to 4 when the computer program is executed.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 4.
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